From 0926eab9f54f141785f4898864985ed36b16f8a1 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 22 Jun 2020 12:55:18 -0700 Subject: [PATCH] PEP8 formatting --- compiler/modules/col_cap_array.py | 24 +++++++-------------- compiler/modules/row_cap_array.py | 35 +++++++++++-------------------- 2 files changed, 19 insertions(+), 40 deletions(-) diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py index d74ab80a..ee9302d8 100644 --- a/compiler/modules/col_cap_array.py +++ b/compiler/modules/col_cap_array.py @@ -17,6 +17,7 @@ class col_cap_array(bitcell_base_array): super().__init__(cols, rows, name, column_offset) self.mirror = mirror + self.no_instances = True self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -47,8 +48,8 @@ class col_cap_array(bitcell_base_array): for col in range(self.column_size): for row in range(self.row_size): name = "bit_r{0}_c{1}".format(row, col) - self.cell_inst[row,col]=self.add_inst(name=name, - mod=self.dummy_cell) + self.cell_inst[row, col]=self.add_inst(name=name, + mod=self.dummy_cell) self.connect_inst(self.get_bitcell_pins(col, row)) def get_bitcell_pins(self, col, row): @@ -73,31 +74,20 @@ class col_cap_array(bitcell_base_array): for col in range(self.column_size): for cell_column in column_list: - bl_pin = self.cell_inst[0,col].get_pin(cell_column) - self.add_layout_pin(text=cell_column+"_{0}".format(col), + bl_pin = self.cell_inst[0, col].get_pin(cell_column) + self.add_layout_pin(text=cell_column + "_{0}".format(col), layer=bl_pin.layer, - offset=bl_pin.ll().scale(1,0), + offset=bl_pin.ll().scale(1, 0), width=bl_pin.width(), height=self.height) # Add vdd/gnd via stacks for row in range(self.row_size): for col in range(self.column_size): - inst = self.cell_inst[row,col] + inst = self.cell_inst[row, col] for pin_name in ["vdd", "gnd"]: for pin in inst.get_pins(pin_name): self.add_power_pin(name=pin.name, loc=pin.center(), start_layer=pin.layer) - - # def input_load(self): - # wl_wire = self.gen_wl_wire() - # return wl_wire.return_input_cap() - # - # def get_wordline_cin(self): - # """Get the relative input capacitance from the wordline connections in all the bitcell""" - # #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns - # bitcell_wl_cin = self.cell.get_wl_cin() - # total_cin = bitcell_wl_cin * self.column_size - # return total_cin diff --git a/compiler/modules/row_cap_array.py b/compiler/modules/row_cap_array.py index 2c7d4677..f108d86e 100644 --- a/compiler/modules/row_cap_array.py +++ b/compiler/modules/row_cap_array.py @@ -8,6 +8,7 @@ from sram_factory import factory from globals import OPTS from tech import cell_properties + class row_cap_array(bitcell_base_array): """ Generate a dummy row/column for the replica array. @@ -15,7 +16,7 @@ class row_cap_array(bitcell_base_array): def __init__(self, cols, rows, column_offset=0, mirror=0, name=""): super().__init__(cols, rows, name, column_offset) self.mirror = mirror - + self.no_instances = True self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -46,8 +47,8 @@ class row_cap_array(bitcell_base_array): for col in range(self.column_size): for row in range(1, self.row_size - 1): name = "bit_r{0}_c{1}".format(row, col) - self.cell_inst[row,col]=self.add_inst(name=name, - mod=self.dummy_cell) + self.cell_inst[row, col]=self.add_inst(name=name, + mod=self.dummy_cell) self.connect_inst(self.get_bitcell_pins(col, row)) def get_bitcell_pins(self, col, row): @@ -65,8 +66,8 @@ class row_cap_array(bitcell_base_array): def place_array(self, name_template, row_offset=0): # We increase it by a well enclosure so the precharges don't overlap our wells - self.height = self.row_size*self.cell.height - self.width = self.column_size*self.cell.width + self.height = self.row_size * self.cell.height + self.width = self.column_size * self.cell.width xoffset = 0.0 for col in range(self.column_size): @@ -74,7 +75,6 @@ class row_cap_array(bitcell_base_array): tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset) for row in range(1, self.row_size - 1): - name = name_template.format(row, col) tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset) if dir_x and dir_y: @@ -86,8 +86,8 @@ class row_cap_array(bitcell_base_array): else: dir_key = "" - self.cell_inst[row,col].place(offset=[tempx, tempy], - mirror=dir_key) + self.cell_inst[row, col].place(offset=[tempx, tempy], + mirror=dir_key) yoffset += self.cell.height xoffset += self.cell.width @@ -98,31 +98,20 @@ class row_cap_array(bitcell_base_array): for row in range(1, self.row_size - 1): for cell_row in row_list: - wl_pin = self.cell_inst[row,0].get_pin(cell_row) - self.add_layout_pin(text=cell_row+"_{0}".format(row), + wl_pin = self.cell_inst[row, 0].get_pin(cell_row) + self.add_layout_pin(text=cell_row + "_{0}".format(row), layer=wl_pin.layer, - offset=wl_pin.ll().scale(0,1), + offset=wl_pin.ll().scale(0, 1), width=self.width, height=wl_pin.height()) # Add vdd/gnd via stacks for row in range(1, self.row_size - 1): for col in range(self.column_size): - inst = self.cell_inst[row,col] + inst = self.cell_inst[row, col] for pin_name in ["vdd", "gnd"]: for pin in inst.get_pins(pin_name): self.add_power_pin(name=pin.name, loc=pin.center(), start_layer=pin.layer) - - # def input_load(self): - # wl_wire = self.gen_wl_wire() - # return wl_wire.return_input_cap() - # - # def get_wordline_cin(self): - # """Get the relative input capacitance from the wordline connections in all the bitcell""" - # #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns - # bitcell_wl_cin = self.cell.get_wl_cin() - # total_cin = bitcell_wl_cin * self.column_size - # return total_cin