From 06254fae724387e376a633a6a05c6cf64331a422 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Thu, 16 Jun 2022 11:38:20 -0700 Subject: [PATCH] forgot to multiply all delay chain pinouts by 2 because of previous design that only exposed pins for even numbered inverters in delay chain... oops --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 5feee7fe..b7077726 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -152,7 +152,7 @@ class control_logic_delay(design.design): "Must use odd number of delay chain stages for inverting delay chain.") self.multi_delay_chain=factory.create(module_type = "multi_delay_chain", fanout_list = 14 * [ OPTS.delay_chain_fanout_per_stage ], - pinout_list = [1, 6, 7, 14]) # TODO: generate this list programatically + pinout_list = [2, 12, 14, 28]) # TODO: generate this list programatically # not being used def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout):