From 05f9e809b403a363812394bae22f08645e1fcfe2 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 5 Mar 2020 16:27:35 -0800 Subject: [PATCH] PEP8 Formatting --- compiler/sram/sram_base.py | 150 ++++++++++++++++--------------------- 1 file changed, 66 insertions(+), 84 deletions(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index c7c91e90..d2fbe9fc 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -5,20 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import sys import datetime -import getpass import debug -from datetime import datetime from importlib import reload from vector import vector from globals import OPTS, print_time -import logical_effort from design import design from verilog import verilog from lef import lef from sram_factory import factory -import logical_effort + class sram_base(design, verilog, lef): """ @@ -36,11 +32,11 @@ class sram_base(design, verilog, lef): self.bank_insts = [] if self.write_size: - self.num_wmasks = int(self.word_size/self.write_size) + self.num_wmasks = int(self.word_size / self.write_size) else: self.num_wmasks = 0 - #For logical effort delay calculations. + # For logical effort delay calculations. self.all_mods_except_control_done = False def add_pins(self): @@ -48,11 +44,11 @@ class sram_base(design, verilog, lef): for port in self.write_ports: for bit in range(self.word_size): - self.add_pin("din{0}[{1}]".format(port,bit),"INPUT") + self.add_pin("din{0}[{1}]".format(port, bit), "INPUT") for port in self.all_ports: for bit in range(self.addr_size): - self.add_pin("addr{0}[{1}]".format(port,bit),"INPUT") + self.add_pin("addr{0}[{1}]".format(port, bit), "INPUT") # These are used to create the physical pins self.control_logic_inputs = [] @@ -69,22 +65,21 @@ class sram_base(design, verilog, lef): self.control_logic_outputs.append(self.control_logic_r.get_outputs()) for port in self.all_ports: - self.add_pin("csb{}".format(port),"INPUT") + self.add_pin("csb{}".format(port), "INPUT") for port in self.readwrite_ports: - self.add_pin("web{}".format(port),"INPUT") + self.add_pin("web{}".format(port), "INPUT") for port in self.all_ports: - self.add_pin("clk{}".format(port),"INPUT") + self.add_pin("clk{}".format(port), "INPUT") # add the optional write mask pins for port in self.write_ports: for bit in range(self.num_wmasks): - self.add_pin("wmask{0}[{1}]".format(port,bit),"INPUT") + self.add_pin("wmask{0}[{1}]".format(port, bit), "INPUT") for port in self.read_ports: for bit in range(self.word_size): - self.add_pin("dout{0}[{1}]".format(port,bit),"OUTPUT") + self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT") - self.add_pin("vdd","POWER") - self.add_pin("gnd","GROUND") - + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def create_netlist(self): """ Netlist creation """ @@ -100,23 +95,21 @@ class sram_base(design, verilog, lef): self.width=0 self.height=0 - if not OPTS.is_unit_test: - print_time("Submodules",datetime.now(), start_time) - + print_time("Submodules", datetime.now(), start_time) def create_layout(self): - """ Layout creation """ + """ Layout creation """ start_time = datetime.now() self.place_instances() if not OPTS.is_unit_test: - print_time("Placement",datetime.now(), start_time) + print_time("Placement", datetime.now(), start_time) start_time = datetime.now() self.route_layout() self.route_supplies() if not OPTS.is_unit_test: - print_time("Routing",datetime.now(), start_time) + print_time("Routing", datetime.now(), start_time) self.add_lvs_correspondence_points() @@ -130,10 +123,10 @@ class sram_base(design, verilog, lef): # We only enable final verification if we have routed the design self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True) if not OPTS.is_unit_test: - print_time("Verification",datetime.now(), start_time) + print_time("Verification", datetime.now(), start_time) def create_modules(self): - debug.error("Must override pure virtual function.",-1) + debug.error("Must override pure virtual function.", -1) def route_supplies(self): """ Route the supply grid and connect the pins to them. """ @@ -141,8 +134,8 @@ class sram_base(design, verilog, lef): # Copy the pins to the top level # This will either be used to route or left unconnected. for inst in self.insts: - self.copy_power_pins(inst,"vdd") - self.copy_power_pins(inst,"gnd") + self.copy_power_pins(inst, "vdd") + self.copy_power_pins(inst, "gnd") import tech if not OPTS.route_supplies: @@ -164,33 +157,31 @@ class sram_base(design, verilog, lef): from supply_grid_router import supply_grid_router as router rtr=router(grid_stack, self) rtr.route() - def compute_bus_sizes(self): """ Compute the independent bus widths shared between two and four bank SRAMs """ # address size + control signals + one-hot bank select signals - self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks,2) + 1 + self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks, 2) + 1 # data bus size self.num_horizontal_line = self.word_size - self.vertical_bus_width = self.m2_pitch*self.num_vertical_line + self.vertical_bus_width = self.m2_pitch * self.num_vertical_line # vertical bus height depends on 2 or 4 banks - self.data_bus_height = self.m3_pitch*self.num_horizontal_line - self.data_bus_width = 2*(self.bank.width + self.bank_to_bus_distance) + self.vertical_bus_width + self.data_bus_height = self.m3_pitch * self.num_horizontal_line + self.data_bus_width = 2 * (self.bank.width + self.bank_to_bus_distance) + self.vertical_bus_width - self.control_bus_height = self.m1_pitch*(self.control_size+2) + self.control_bus_height = self.m1_pitch * (self.control_size + 2) self.control_bus_width = self.bank.width + self.bank_to_bus_distance + self.vertical_bus_width - self.supply_bus_height = self.m1_pitch*2 # 2 for vdd/gnd placed with control bus + self.supply_bus_height = self.m1_pitch * 2 # 2 for vdd/gnd placed with control bus self.supply_bus_width = self.data_bus_width # Sanity check to ensure we can fit the control logic above a single bank (0.9 is a hack really) - debug.check(self.bank.width + self.vertical_bus_width > 0.9*self.control_logic.width, + debug.check(self.bank.width + self.vertical_bus_width > 0.9 * self.control_logic.width, "Bank is too small compared to control logic.") - def add_busses(self): """ Add the horizontal and vertical busses """ # Vertical bus @@ -213,24 +204,22 @@ class sram_base(design, verilog, lef): names=self.control_bus_names[port], length=self.vertical_bus_height) - self.addr_bus_names=["A{0}[{1}]".format(port,i) for i in range(self.addr_size)] + self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.addr_size)] self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2", pitch=self.m2_pitch, offset=self.addr_bus_offset, names=self.addr_bus_names, length=self.addr_bus_height)) - - self.bank_sel_bus_names = ["bank_sel{0}_{1}".format(port,i) for i in range(self.num_banks)] + self.bank_sel_bus_names = ["bank_sel{0}_{1}".format(port, i) for i in range(self.num_banks)] self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2", pitch=self.m2_pitch, offset=self.bank_sel_bus_offset, names=self.bank_sel_bus_names, length=self.vertical_bus_height)) - # Horizontal data bus - self.data_bus_names = ["DATA{0}[{1}]".format(port,i) for i in range(self.word_size)] + self.data_bus_names = ["DATA{0}[{1}]".format(port, i) for i in range(self.word_size)] self.data_bus_positions = self.create_horizontal_pin_bus(layer="m3", pitch=self.m3_pitch, offset=self.data_bus_offset, @@ -249,7 +238,7 @@ class sram_base(design, verilog, lef): # the decoder in 4-bank SRAMs self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="m1", pitch=self.m1_pitch, - offset=self.supply_bus_offset+vector(0,self.m1_pitch), + offset=self.supply_bus_offset + vector(0, self.m1_pitch), names=["gnd"], length=self.supply_bus_width)) self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="m1", @@ -258,20 +247,17 @@ class sram_base(design, verilog, lef): names=self.control_bus_names[port], length=self.control_bus_width)) - - def add_multi_bank_modules(self): """ Create the multibank address flops and bank decoder """ from dff_buf_array import dff_buf_array self.msb_address = dff_buf_array(name="msb_address", rows=1, - columns=self.num_banks/2) + columns=self.num_banks / 2) self.add_mod(self.msb_address) if self.num_banks>2: self.msb_decoder = self.bank.decoder.pre2_4 self.add_mod(self.msb_decoder) - def add_modules(self): self.bitcell = factory.create(module_type=OPTS.bitcell) @@ -293,7 +279,6 @@ class sram_base(design, verilog, lef): if self.write_size: self.wmask_dff = factory.create("dff_array", module_name="wmask_dff", rows=1, columns=self.num_wmasks) self.add_mod(self.wmask_dff) - # Create the bank module (up to four are instantiated) self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") @@ -305,7 +290,8 @@ class sram_base(design, verilog, lef): self.bank_count = 0 - #The control logic can resize itself based on the other modules. Requires all other modules added before control logic. + # The control logic can resize itself based on the other modules. + # Requires all other modules added before control logic. self.all_mods_except_control_done = True c = reload(__import__(OPTS.control_logic)) @@ -320,40 +306,40 @@ class sram_base(design, verilog, lef): port_type="rw") self.add_mod(self.control_logic_rw) if len(self.writeonly_ports)>0: - self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows, + self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, sram=self, port_type="w") self.add_mod(self.control_logic_w) if len(self.readonly_ports)>0: - self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, + self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, sram=self, port_type="r") self.add_mod(self.control_logic_r) - def create_bank(self,bank_num): - """ Create a bank """ + def create_bank(self, bank_num): + """ Create a bank """ self.bank_insts.append(self.add_inst(name="bank{0}".format(bank_num), mod=self.bank)) temp = [] for port in self.read_ports: for bit in range(self.word_size): - temp.append("dout{0}[{1}]".format(port,bit)) + temp.append("dout{0}[{1}]".format(port, bit)) for port in self.all_ports: temp.append("rbl_bl{0}".format(port)) for port in self.write_ports: for bit in range(self.word_size): - temp.append("bank_din{0}[{1}]".format(port,bit)) + temp.append("bank_din{0}[{1}]".format(port, bit)) for port in self.all_ports: for bit in range(self.bank_addr_size): - temp.append("a{0}[{1}]".format(port,bit)) + temp.append("a{0}[{1}]".format(port, bit)) if(self.num_banks > 1): for port in self.all_ports: - temp.append("bank_sel{0}[{1}]".format(port,bank_num)) + temp.append("bank_sel{0}[{1}]".format(port, bank_num)) for port in self.read_ports: temp.append("s_en{0}".format(port)) for port in self.all_ports: @@ -369,7 +355,6 @@ class sram_base(design, verilog, lef): return self.bank_insts[-1] - def place_bank(self, bank_inst, position, x_flip, y_flip): """ Place a bank at the given position with orientations """ @@ -400,7 +385,6 @@ class sram_base(design, verilog, lef): return bank_inst - def create_row_addr_dff(self): """ Add all address flops for the main decoder """ insts = [] @@ -412,13 +396,12 @@ class sram_base(design, verilog, lef): inputs = [] outputs = [] for bit in range(self.row_addr_size): - inputs.append("addr{}[{}]".format(port,bit+self.col_addr_size)) - outputs.append("a{}[{}]".format(port,bit+self.col_addr_size)) + inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size)) + outputs.append("a{}[{}]".format(port, bit + self.col_addr_size)) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) return insts - def create_col_addr_dff(self): """ Add and place all address flops for the column decoder """ @@ -431,14 +414,13 @@ class sram_base(design, verilog, lef): inputs = [] outputs = [] for bit in range(self.col_addr_size): - inputs.append("addr{}[{}]".format(port,bit)) - outputs.append("a{}[{}]".format(port,bit)) + inputs.append("addr{}[{}]".format(port, bit)) + outputs.append("a{}[{}]".format(port, bit)) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) return insts - def create_data_dff(self): """ Add and place all data flops """ insts = [] @@ -454,8 +436,8 @@ class sram_base(design, verilog, lef): inputs = [] outputs = [] for bit in range(self.word_size): - inputs.append("din{}[{}]".format(port,bit)) - outputs.append("bank_din{}[{}]".format(port,bit)) + inputs.append("din{}[{}]".format(port, bit)) + outputs.append("bank_din{}[{}]".format(port, bit)) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) @@ -483,7 +465,6 @@ class sram_base(design, verilog, lef): return insts - def create_control_logic(self): """ Add control logic instances """ @@ -516,12 +497,13 @@ class sram_base(design, verilog, lef): return insts - def connect_vbus_m2m3(self, src_pin, dest_pin): - """ Helper routine to connect an instance to a vertical bus. + """ + Helper routine to connect an instance to a vertical bus. Routes horizontal then vertical L shape. Dest pin is assumed to be on M2. - Src pin can be on M1/M2/M3.""" + Src pin can be on M1/M2/M3. + """ if src_pin.cx()