diff --git a/.gitattributes b/.gitattributes index 2e6daefb..23fcc05d 100644 --- a/.gitattributes +++ b/.gitattributes @@ -1 +1,2 @@ -*.sp linguist-vendored +*.sp linguist-language=Spice +*.tf linquist-language=Tech File diff --git a/README.md b/README.md index 674d13f2..48b15766 100644 --- a/README.md +++ b/README.md @@ -29,7 +29,7 @@ things that need to be fixed. ## Dependencies The OpenRAM compiler has very few dependencies: -+ [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) ++ [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) or [Xyce] 7.2 (or later) + Python 3.5 or higher + Various Python packages (pip install -r requirements.txt) @@ -214,6 +214,7 @@ If I forgot to add you, please let me know! [Netgen]: http://opencircuitdesign.com/netgen/ [Qflow]: http://opencircuitdesign.com/qflow/history.html [Ngspice]: http://ngspice.sourceforge.net/ +[Xyce]: http://xyce.sandia.gov/ [OSUPDK]: https://vlsiarch.ecen.okstate.edu/flow/ [FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents diff --git a/compiler/Makefile b/compiler/Makefile index a547b6ed..171c1a10 100644 --- a/compiler/Makefile +++ b/compiler/Makefile @@ -2,7 +2,7 @@ TECH = scn4m_subm CUR_DIR = $(shell pwd) TEST_DIR = ${CUR_DIR}/tests -MAKEFLAGS += -j 1 +#MAKEFLAGS += -j 1 # Library test LIBRARY_TESTS = $(shell find ${TEST_DIR} -name 0[1-2]*_test.py) @@ -64,7 +64,43 @@ usage: ${USAGE_TESTS} $(ALL_TESTS): python3 $@ -t ${TECH} + + +OPENRAM_TECHS = $(subst :, ,$(OPENRAM_TECH)) +TECH_DIR := $(word 1, $(foreach dir,$(OPENRAM_TECHS),$(wildcard $(dir)/$(TECH)))) +CONFIG_DIR = $(OPENRAM_HOME)/model_configs +MODEL_CONFIGS = $(wildcard $(CONFIG_DIR)/*.py) +SIM_DIR = $(OPENRAM_HOME)/model_data/$(TECH) +CSV_DIR = $(TECH_DIR)/sim_data +# Creates names of technology specific okay files for the configs +STAMPS=$(addprefix $(SIM_DIR)/, $(addsuffix .ok, $(notdir $(basename $(MODEL_CONFIGS))))) +OPTS = +# Characterize and perform DRC/LVS +OPTS += -c +# Do not characterize or perform DRC/LVS +OPTS += -n +# Verbosity +#OPTS += -v +# Spice +OPTS += -s hspice + +.PHONY: model + +model: $(STAMPS) + mkdir -p $(CSV_DIR) + python3 $(OPENRAM_HOME)/model_data_util.py $(SIM_DIR) $(CSV_DIR) + +%.ok: + $(eval bname=$(basename $(notdir $@))) + $(eval config_path=$(CONFIG_DIR)/$(addsuffix .py, $(notdir $(basename $@)))) + mkdir -p $(SIM_DIR)/$(bname) + -python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_DIR)/$(bname) -o $(bname) -t $(TECH) $(config_path) 2>&1 > /dev/null + touch $@ + +clean_model: + rm -f -r $(SIM_DIR)/*.ok + clean: find . -name \*.pyc -exec rm {} \; find . -name \*~ -exec rm {} \; diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index bb211842..b2697472 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -93,9 +93,9 @@ class cell: # It is assumed it is [nwell, pwell] self._body_bias = body_bias self._port_map['vnb'] = body_bias[0] - self._port_types['vnb'] = "POWER" + self._port_types['vnb'] = "GROUND" self._port_map['vpb'] = body_bias[1] - self._port_types['vpb'] = "GROUND" + self._port_types['vpb'] = "POWER" @property def port_types(self): @@ -176,7 +176,7 @@ class cell_properties(): self.names["col_cap_bitcell_2port"] = "col_cap_cell_2rw" self.names["row_cap_bitcell_1port"] = "row_cap_cell_1rw" self.names["row_cap_bitcell_2port"] = "row_cap_cell_2rw" - + self.use_strap = False self._ptx = _ptx(model_is_subckt=False, bin_spice_models=False) diff --git a/compiler/base/custom_layer_properties.py b/compiler/base/custom_layer_properties.py index eff24f82..8e20d031 100644 --- a/compiler/base/custom_layer_properties.py +++ b/compiler/base/custom_layer_properties.py @@ -45,7 +45,8 @@ class _hierarchical_predecode: bus_space_factor, input_layer, output_layer, - vertical_supply): + vertical_supply, + force_horizontal_input_contact): # hierarchical_predecode # bus_layer, bus_directions, bus_pitch, bus_space, input_layer, output_layer, output_layer_pitch # m2, pref, m2_pitch, m2_space, m1, m1, m1_pitch @@ -59,6 +60,7 @@ class _hierarchical_predecode: self.input_layer = input_layer self.output_layer = output_layer self.vertical_supply = vertical_supply + self.force_horizontal_input_contact = force_horizontal_input_contact class _column_mux_array: @@ -152,7 +154,8 @@ class layer_properties(): bus_space_factor=1, input_layer="m1", output_layer="m1", - vertical_supply=False) + vertical_supply=False, + force_horizontal_input_contact=False) self._column_mux_array = _column_mux_array(select_layer="m1", select_pitch="m2_pitch", diff --git a/compiler/base/design.py b/compiler/base/design.py index 8c621742..70a9047b 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -48,11 +48,11 @@ class design(hierarchy_design): self.add_pin_indices(prop.port_indices) self.add_pin_names(prop.port_map) self.add_pin_types(prop.port_types) - + + (width, height) = utils.get_libcell_size(self.cell_name, GDS["unit"], layer[prop.boundary_layer]) - self.pin_map = utils.get_libcell_pins(self.pins, self.cell_name, GDS["unit"]) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index d99c7363..fe295273 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -132,7 +132,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): for subinst, conns in zip(self.insts, self.conns): if subinst in self.graph_inst_exclude: continue - subinst_name = inst_name + '.X' + subinst.name + subinst_name = inst_name + "{}x".format(OPTS.hier_seperator) + subinst.name subinst_ports = self.translate_nets(conns, port_dict, inst_name) subinst.mod.build_graph(graph, subinst_name, subinst_ports) @@ -148,7 +148,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): port_dict = {pin: port for pin, port in zip(self.pins, port_nets)} debug.info(3, "Instance name={}".format(inst_name)) for subinst, conns in zip(self.insts, self.conns): - subinst_name = inst_name + '.X' + subinst.name + subinst_name = inst_name + "{}x".format(OPTS.hier_seperator) + subinst.name subinst_ports = self.translate_nets(conns, port_dict, inst_name) for si_port, conn in zip(subinst_ports, conns): # Only add for first occurrence @@ -166,7 +166,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): if conn in port_dict: converted_conns.append(port_dict[conn]) else: - converted_conns.append("{}.{}".format(inst_name, conn)) + converted_conns.append("{0}{2}{1}".format(inst_name, conn, OPTS.hier_seperator)) return converted_conns def add_graph_edges(self, graph, port_nets): diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 1e2add8d..8bbc72c7 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -20,6 +20,10 @@ from globals import OPTS from vector import vector from pin_layout import pin_layout from utils import round_to_grid +try: + from tech import special_purposes +except ImportError: + special_purposes = {} class layout(): @@ -36,12 +40,13 @@ class layout(): # This gets set in both spice and layout so either can be called first. self.name = name self.cell_name = cell_name - + self.gds_file = OPTS.openram_tech + "gds_lib/" + cell_name + ".gds" - + self.width = None self.height = None - self.bounding_box = None + self.bounding_box = None # The rectangle shape + self.bbox = None # The ll, ur coords # Holds module/cell layout instances self.insts = [] # Set of names to check for duplicates @@ -57,7 +62,7 @@ class layout(): self.visited = [] # Flag for library cells self.is_library_cell = False - + self.gds_read() try: @@ -65,7 +70,7 @@ class layout(): self.pwr_grid_layer = power_grid[0] except ImportError: self.pwr_grid_layer = "m3" - + ############################################################ # GDS layout ############################################################ @@ -117,7 +122,7 @@ class layout(): if len(self.objs) > 0: lowestx = min(min(obj.lx() for obj in self.objs if obj.name != "label"), lowestx) lowesty = min(min(obj.by() for obj in self.objs if obj.name != "label"), lowesty) - + if len(self.insts) > 0: lowestx = min(min(inst.lx() for inst in self.insts), lowestx) lowesty = min(min(inst.by() for inst in self.insts), lowesty) @@ -128,7 +133,7 @@ class layout(): continue lowestx = min(min(pin.lx() for pin in pin_set), lowestx) lowesty = min(min(pin.by() for pin in pin_set), lowesty) - + return vector(lowestx, lowesty) def find_highest_coords(self): @@ -137,7 +142,7 @@ class layout(): this layout """ highestx = highesty = -sys.maxsize - 1 - + if len(self.objs) > 0: highestx = max(max(obj.rx() for obj in self.objs if obj.name != "label"), highestx) highesty = max(max(obj.uy() for obj in self.objs if obj.name != "label"), highesty) @@ -152,7 +157,7 @@ class layout(): continue highestx = max(max(pin.rx() for pin in pin_set), highestx) highesty = max(max(pin.uy() for pin in pin_set), highesty) - + return vector(highestx, highesty) def find_highest_layer_coords(self, layer): @@ -233,7 +238,7 @@ class layout(): # This is commented out for runtime reasons # debug.info(4, "instance list: " + ",".join(x.name for x in self.insts)) return self.insts[-1] - + def get_inst(self, name): """ Retrieve an instance by name """ for inst in self.insts: @@ -331,7 +336,7 @@ class layout(): Return the pin or list of pins """ name = self.get_pin_name(text) - + try: if len(self.pin_map[name]) > 1: debug.error("Should use a pin iterator since more than one pin {}".format(text), -1) @@ -348,7 +353,7 @@ class layout(): Return a pin list (instead of a single pin) """ name = self.get_pin_name(text) - + if name in self.pin_map.keys(): return self.pin_map[name] else: @@ -359,12 +364,12 @@ class layout(): Create a mapping from internal pin names to external pin names. """ self.pin_names = pin_dict - + self.original_pin_names = {y: x for (x, y) in self.pin_names.items()} def get_pin_name(self, text): """ Return the custom cell pin name """ - + if text in self.pin_names: return self.pin_names[text] else: @@ -372,7 +377,7 @@ class layout(): def get_original_pin_names(self): """ Return the internal cell pin name """ - + # This uses the hierarchy_spice pins (in order) return [self.get_original_pin_name(x) for x in self.pins] @@ -382,7 +387,7 @@ class layout(): return self.original_pin_names[text] else: return text - + def get_pin_names(self): """ Return a pin list of all pins @@ -479,7 +484,7 @@ class layout(): offset=s.ll(), width=s.width(), height=s.height()) - + def replace_layout_pin(self, text, pin): """ Remove the old pin and replace with a new one @@ -494,7 +499,7 @@ class layout(): offset=pin.ll(), width=pin.width(), height=pin.height()) - + def add_layout_pin(self, text, layer, offset, width=None, height=None): """ Create a labeled pin @@ -776,7 +781,7 @@ class layout(): debug.info(3, "opening {}".format(self.gds_file)) self.gds = gdsMill.VlsiLayout(units=GDS["unit"]) reader = gdsMill.Gds2reader(self.gds) - reader.loadFromFile(self.gds_file) + reader.loadFromFile(self.gds_file, special_purposes) else: debug.info(3, "Creating layout structure {}".format(self.name)) self.gds = gdsMill.VlsiLayout(name=self.name, units=GDS["unit"]) @@ -788,7 +793,7 @@ class layout(): debug.info(4, "Printing {}".format(gds_file)) arrayCellLayout = gdsMill.VlsiLayout(units=GDS["unit"]) reader = gdsMill.Gds2reader(arrayCellLayout, debugToTerminal=1) - reader.loadFromFile(gds_file) + reader.loadFromFile(gds_file, special_purposes) def clear_visited(self): """ Recursively clear the visited flag """ @@ -1125,7 +1130,7 @@ class layout(): # self.add_inst(cr.name, cr) # self.connect_inst([]) self.add_flat_inst(cr.name, cr) - + def create_horizontal_channel_route(self, netlist, offset, layer_stack, directions=None): """ Wrapper to create a horizontal channel route @@ -1137,7 +1142,7 @@ class layout(): # self.add_inst(cr.name, cr) # self.connect_inst([]) self.add_flat_inst(cr.name, cr) - + def add_boundary(self, ll=vector(0, 0), ur=None): """ Add boundary for debugging dimensions """ if OPTS.netlist_only: @@ -1161,6 +1166,59 @@ class layout(): height=ur.y - ll.y, width=ur.x - ll.x) + self.bbox = [self.bounding_box.ll(), self.bounding_box.ur()] + + def get_bbox(self, side="all", big_margin=0, little_margin=0): + """ + Get the bounding box from the GDS + """ + gds_filename = OPTS.openram_temp + "temp.gds" + # If didn't specify a gds blockage file, write it out to read the gds + # This isn't efficient, but easy for now + # Load the gds file and read in all the shapes + self.gds_write(gds_filename) + layout = gdsMill.VlsiLayout(units=GDS["unit"]) + reader = gdsMill.Gds2reader(layout) + reader.loadFromFile(gds_filename) + top_name = layout.rootStructureName + + if not self.bbox: + # The boundary will determine the limits to the size + # of the routing grid + boundary = layout.measureBoundary(top_name) + # These must be un-indexed to get rid of the matrix type + ll = vector(boundary[0][0], boundary[0][1]) + ur = vector(boundary[1][0], boundary[1][1]) + else: + ll, ur = self.bbox + + ll_offset = vector(0, 0) + ur_offset = vector(0, 0) + if side in ["ring", "top", "all"]: + ur_offset += vector(0, big_margin) + else: + ur_offset += vector(0, little_margin) + if side in ["ring", "bottom", "all"]: + ll_offset += vector(0, big_margin) + else: + ll_offset += vector(0, little_margin) + if side in ["ring", "left", "all"]: + ll_offset += vector(big_margin, 0) + else: + ll_offset += vector(little_margin, 0) + if side in ["ring", "right", "all"]: + ur_offset += vector(big_margin, 0) + else: + ur_offset += vector(little_margin, 0) + bbox = (ll - ll_offset, ur + ur_offset) + size = ur - ll + debug.info(1, "Size: {0} x {1} with perimeter big margin {2} little margin {3}".format(size.x, + size.y, + big_margin, + little_margin)) + + return bbox + def add_enclosure(self, insts, layer="nwell", extend=0, leftx=None, rightx=None, topy=None, boty=None): """ Add a layer that surrounds the given instances. Useful @@ -1203,22 +1261,24 @@ class layout(): height=ymax - ymin) return rect - def copy_power_pins(self, inst, name, add_vias=True): + def copy_power_pins(self, inst, name, add_vias=True, new_name=""): """ This will copy a power pin if it is on the lowest power_grid layer. If it is on M1, it will add a power via too. """ pins = inst.get_pins(name) for pin in pins: + if new_name == "": + new_name = pin.name if pin.layer == self.pwr_grid_layer: - self.add_layout_pin(name, + self.add_layout_pin(new_name, pin.layer, pin.ll(), pin.width(), pin.height()) elif add_vias: - self.copy_power_pin(pin) + self.copy_power_pin(pin, new_name=new_name) def add_io_pin(self, instance, pin_name, new_name, start_layer=None): """ @@ -1264,16 +1324,18 @@ class layout(): width=width, height=height) - def copy_power_pin(self, pin, loc=None, directions=None): + def copy_power_pin(self, pin, loc=None, directions=None, new_name=""): """ Add a single power pin from the lowest power_grid layer down to M1 (or li) at the given center location. The starting layer is specified to determine which vias are needed. """ + if new_name == "": + new_name = pin.name if not loc: loc = pin.center() - + # Hack for min area if OPTS.tech_name == "sky130": min_area = drc["minarea_{}".format(self.pwr_grid_layer)] @@ -1282,9 +1344,9 @@ class layout(): else: width = None height = None - + if pin.layer == self.pwr_grid_layer: - self.add_layout_pin_rect_center(text=pin.name, + self.add_layout_pin_rect_center(text=new_name, layer=self.pwr_grid_layer, offset=loc, width=width, @@ -1299,7 +1361,7 @@ class layout(): width = via.width if not height: height = via.height - self.add_layout_pin_rect_center(text=pin.name, + self.add_layout_pin_rect_center(text=new_name, layer=self.pwr_grid_layer, offset=loc, width=width, @@ -1341,7 +1403,182 @@ class layout(): layer=layer, offset=peri_pin_loc) - def add_power_ring(self, bbox): + def add_dnwell(self, bbox=None, inflate=1): + """ Create a dnwell, along with nwell moat at border. """ + + if "dnwell" not in techlayer: + return + + if not bbox: + bbox = [self.find_lowest_coords(), + self.find_highest_coords()] + + # Find the corners + [ll, ur] = bbox + + # Possibly inflate the bbox + nwell_offset = vector(2 * self.nwell_width, 2 * self.nwell_width) + ll -= nwell_offset.scale(inflate, inflate) + ur += nwell_offset.scale(inflate, inflate) + + # Other corners + ul = vector(ll.x, ur.y) + lr = vector(ur.x, ll.y) + + # Add the dnwell + self.add_rect("dnwell", + offset=ll, + height=ur.y - ll.y, + width=ur.x - ll.x) + + # Add the moat + self.add_path("nwell", [ll, lr, ur, ul, ll - vector(0, 0.5 * self.nwell_width)]) + + # Add the taps + layer_stack = self.active_stack + tap_spacing = 2 + nwell_offset = vector(self.nwell_width, self.nwell_width) + + # Every nth tap is connected to gnd + period = 5 + + # BOTTOM + count = 0 + loc = ll + nwell_offset.scale(tap_spacing, 0) + end_loc = lr - nwell_offset.scale(tap_spacing, 0) + while loc.x < end_loc.x: + self.add_via_center(layers=layer_stack, + offset=loc, + implant_type="n", + well_type="n") + if count % period: + self.add_via_stack_center(from_layer="li", + to_layer="m1", + offset=loc) + else: + self.add_power_pin(name="vdd", + loc=loc, + start_layer="li") + count += 1 + loc += nwell_offset.scale(tap_spacing, 0) + + # TOP + count = 0 + loc = ul + nwell_offset.scale(tap_spacing, 0) + end_loc = ur - nwell_offset.scale(tap_spacing, 0) + while loc.x < end_loc.x: + self.add_via_center(layers=layer_stack, + offset=loc, + implant_type="n", + well_type="n") + if count % period: + self.add_via_stack_center(from_layer="li", + to_layer="m1", + offset=loc) + else: + self.add_power_pin(name="vdd", + loc=loc, + start_layer="li") + count += 1 + loc += nwell_offset.scale(tap_spacing, 0) + + # LEFT + count = 0 + loc = ll + nwell_offset.scale(0, tap_spacing) + end_loc = ul - nwell_offset.scale(0, tap_spacing) + while loc.y < end_loc.y: + self.add_via_center(layers=layer_stack, + offset=loc, + implant_type="n", + well_type="n") + if count % period: + self.add_via_stack_center(from_layer="li", + to_layer="m2", + offset=loc) + else: + self.add_power_pin(name="vdd", + loc=loc, + start_layer="li") + count += 1 + loc += nwell_offset.scale(0, tap_spacing) + + # RIGHT + count = 0 + loc = lr + nwell_offset.scale(0, tap_spacing) + end_loc = ur - nwell_offset.scale(0, tap_spacing) + while loc.y < end_loc.y: + self.add_via_center(layers=layer_stack, + offset=loc, + implant_type="n", + well_type="n") + if count % period: + self.add_via_stack_center(from_layer="li", + to_layer="m2", + offset=loc) + else: + self.add_power_pin(name="vdd", + loc=loc, + start_layer="li") + count += 1 + loc += nwell_offset.scale(0, tap_spacing) + + # Add the gnd ring + self.add_ring([ll, ur]) + + def add_ring(self, bbox=None, width_mult=8, offset=0): + """ + Add a ring around the bbox + """ + # Ring size/space/pitch + wire_width = self.m2_width * width_mult + half_width = 0.5 * wire_width + wire_space = self.m2_space + wire_pitch = wire_width + wire_space + + # Find the corners + if not bbox: + bbox = [self.find_lowest_coords(), + self.find_highest_coords()] + + [ll, ur] = bbox + ul = vector(ll.x, ur.y) + lr = vector(ur.x, ll.y) + ll += vector(-offset * wire_pitch, + -offset * wire_pitch) + lr += vector(offset * wire_pitch, + -offset * wire_pitch) + ur += vector(offset * wire_pitch, + offset * wire_pitch) + ul += vector(-offset * wire_pitch, + offset * wire_pitch) + + half_offset = vector(half_width, half_width) + self.add_path("m1", [ll - half_offset.scale(1, 0), lr + half_offset.scale(1, 0)], width=wire_width) + self.add_path("m1", [ul - half_offset.scale(1, 0), ur + half_offset.scale(1, 0)], width=wire_width) + self.add_path("m2", [ll - half_offset.scale(0, 1), ul + half_offset.scale(0, 1)], width=wire_width) + self.add_path("m2", [lr - half_offset.scale(0, 1), ur + half_offset.scale(0, 1)], width=wire_width) + + # Find the number of vias for this pitch + supply_vias = 1 + from sram_factory import factory + while True: + c = factory.create(module_type="contact", + layer_stack=self.m1_stack, + dimensions=(supply_vias, supply_vias)) + if c.second_layer_width < wire_width and c.second_layer_height < wire_width: + supply_vias += 1 + else: + supply_vias -= 1 + break + + via_points = [ll, lr, ur, ul] + for pt in via_points: + self.add_via_center(layers=self.m1_stack, + offset=pt, + size=(supply_vias, + supply_vias)) + + def add_power_ring(self): """ Create vdd and gnd power rings around an area of the bounding box argument. Must have a supply_rail_width and supply_rail_pitch @@ -1350,7 +1587,7 @@ class layout(): modules.. """ - [ll, ur] = bbox + [ll, ur] = self.bbox supply_rail_spacing = self.supply_rail_pitch - self.supply_rail_width height = (ur.y - ll.y) + 3 * self.supply_rail_pitch - supply_rail_spacing diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 2f2d3ec9..eca98eaf 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -32,7 +32,6 @@ class spice(): # This gets set in both spice and layout so either can be called first. self.name = name self.cell_name = cell_name - self.sp_file = OPTS.openram_tech + "sp_lib/" + cell_name + ".sp" # If we have a separate lvs directory, then all the lvs files @@ -570,6 +569,7 @@ class spice(): net = net.lower() int_net = self.name_dict[net]['int_net'] int_mod = self.name_dict[net]['mod'] + if int_mod.is_net_alias(int_net, alias, alias_mod, exclusion_set): aliases.append(net) return aliases diff --git a/compiler/base/lef.py b/compiler/base/lef.py index 9ff02816..1d86a63e 100644 --- a/compiler/base/lef.py +++ b/compiler/base/lef.py @@ -69,25 +69,31 @@ class lef: def lef_write(self, lef_name): """ Write the entire lef of the object to the file. """ + # Can possibly use magic lef write to create the LEF + # if OPTS.drc_exe and OPTS.drc_exe[0] == "magic": + # self.magic_lef_write(lef_name) + # return + + # To maintain the indent level easily + self.indent = "" if OPTS.detailed_lef: debug.info(3, "Writing detailed LEF to {0}".format(lef_name)) - self.detailed_lef_write(lef_name) else: debug.info(3, "Writing abstract LEF to {0}".format(lef_name)) - # Can possibly use magic lef write to create the LEF - # if OPTS.drc_exe and OPTS.drc_exe[0] == "magic": - # self.magic_lef_write(lef_name) - # return - self.abstract_lef_write(lef_name) - - def abstract_lef_write(self, lef_name): - # To maintain the indent level easily - self.indent = "" + self.compute_abstract_blockages() self.lef = open(lef_name, "w") self.lef_write_header() + for pin_name in self.pins: + self.lef_write_pin(pin_name) + + self.lef_write_obstructions(OPTS.detailed_lef) + self.lef_write_footer() + self.lef.close() + + def compute_abstract_blockages(self): # Start with blockages on all layers the size of the block # minus the pin escape margin (hard coded to 4 x m3 pitch) # These are a pin_layout to use their geometric functions @@ -104,37 +110,27 @@ class lef: # For each pin, remove the blockage and add the pin for pin_name in self.pins: - pin = self.get_pin(pin_name) - inflated_pin = pin.inflated_pin(multiple=1) - for blockage in self.blockages[pin.layer]: - if blockage.overlaps(inflated_pin): - intersection_shape = blockage.intersection(inflated_pin) - # If it is zero area, don't add the pin - if intersection_shape[0][0]==intersection_shape[1][0] or intersection_shape[0][1]==intersection_shape[1][1]: - continue - # Remove the old blockage and add the new ones - self.blockages[pin.layer].remove(blockage) - intersection_pin = pin_layout("", intersection_shape, inflated_pin.layer) - new_blockages = blockage.cut(intersection_pin) - self.blockages[pin.layer].extend(new_blockages) + pins = self.get_pins(pin_name) + for pin in pins: + inflated_pin = pin.inflated_pin(multiple=2) + continue_fragmenting = True + while continue_fragmenting: + continue_fragmenting = False + old_blockages = list(self.blockages[pin.layer]) + for blockage in old_blockages: + if blockage.overlaps(inflated_pin): + intersection_shape = blockage.intersection(inflated_pin) + # If it is zero area, don't split the blockage + if intersection_shape[0][0]==intersection_shape[1][0] or intersection_shape[0][1]==intersection_shape[1][1]: + continue - self.lef_write_pin(pin_name) - - self.lef_write_obstructions(abstracted=True) - self.lef_write_footer() - self.lef.close() - - def detailed_lef_write(self, lef_name): - # To maintain the indent level easily - self.indent = "" - - self.lef = open(lef_name, "w") - self.lef_write_header() - for pin in self.pins: - self.lef_write_pin(pin) - self.lef_write_obstructions() - self.lef_write_footer() - self.lef.close() + # Remove the old blockage and add the new ones + self.blockages[pin.layer].remove(blockage) + intersection_pin = pin_layout("", intersection_shape, inflated_pin.layer) + new_blockages = blockage.cut(intersection_pin) + self.blockages[pin.layer].extend(new_blockages) + # We split something so make another pass + continue_fragmenting = True def lef_write_header(self): """ Header of LEF file """ @@ -155,8 +151,8 @@ class lef: self.lef.write("{0}SYMMETRY X Y R90 ;\n".format(self.indent)) def lef_write_footer(self): - self.lef.write("{0}END {1}\n".format(self.indent, self.name)) self.indent = self.indent[:-3] + self.lef.write("{0}END {1}\n".format(self.indent, self.name)) self.lef.write("END LIBRARY\n") def lef_write_pin(self, name): @@ -188,20 +184,20 @@ class lef: self.indent = self.indent[:-3] self.lef.write("{0}END {1}\n".format(self.indent, name)) - def lef_write_obstructions(self, abstracted=False): + def lef_write_obstructions(self, detailed=False): """ Write all the obstructions on each layer """ self.lef.write("{0}OBS\n".format(self.indent)) for layer in self.lef_layers: self.lef.write("{0}LAYER {1} ;\n".format(self.indent, layer_names[layer])) self.indent += " " - if abstracted: - blockages = self.blockages[layer] - for b in blockages: - self.lef_write_shape(b.rect) - else: + if detailed: blockages = self.get_blockages(layer, True) for b in blockages: self.lef_write_shape(b) + else: + blockages = self.blockages[layer] + for b in blockages: + self.lef_write_shape(b.rect) self.indent = self.indent[:-3] self.lef.write("{0}END\n".format(self.indent)) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index e6baa4fc..cc13e049 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -45,9 +45,19 @@ class pin_layout: if self.same_lpp(layer_name_pp, lpp): self._layer = layer_name break + else: - debug.error("Layer {} is not a valid routing layer in the tech file.".format(layer_name_pp), -1) - + try: + from tech import layer_override + from tech import layer_override_name + if layer_override[name]: + self.lpp = layer_override[name] + self.layer = "pwellp" + self._recompute_hash() + return + except: + debug.error("Layer {} is not a valid routing layer in the tech file.".format(layer_name_pp), -1) + self.lpp = layer[self.layer] self._recompute_hash() @@ -396,6 +406,13 @@ class pin_layout: try: from tech import label_purpose + try: + from tech import layer_override_purpose + if pin_layer_num in layer_override_purpose: + layer_num = layer_override_purpose[pin_layer_num][0] + label_purpose = layer_override_purpose[pin_layer_num][1] + except: + pass except ImportError: label_purpose = purpose @@ -606,7 +623,9 @@ class pin_layout: # Don't add the existing shape in if it overlaps the pin shape if new_shape.contains(shape): continue - new_shapes.append(new_shape) + # Only add non-zero shapes + if new_shape.area() > 0: + new_shapes.append(new_shape) return new_shapes diff --git a/compiler/base/utils.py b/compiler/base/utils.py index 2b6ef888..fe27c9c0 100644 --- a/compiler/base/utils.py +++ b/compiler/base/utils.py @@ -14,7 +14,10 @@ import globals import debug from vector import vector from pin_layout import pin_layout - +try: + from tech import special_purposes +except ImportError: + special_purposes = {} OPTS = globals.OPTS @@ -88,7 +91,7 @@ def _get_gds_reader(units, gds_filename): debug.info(4, "Creating VLSI layout from {}".format(gds_absname)) cell_vlsi = gdsMill.VlsiLayout(units=units) reader = gdsMill.Gds2reader(cell_vlsi) - reader.loadFromFile(gds_absname) + reader.loadFromFile(gds_absname, special_purposes) _GDS_READER_CACHE[k] = cell_vlsi return cell_vlsi @@ -148,12 +151,21 @@ def get_gds_pins(pin_names, name, gds_filename, units): cell[str(pin_name)] = [] pin_list = cell_vlsi.getPinShape(str(pin_name)) for pin_shape in pin_list: - (lpp, boundary) = pin_shape - rect = [vector(boundary[0], boundary[1]), - vector(boundary[2], boundary[3])] - # this is a list because other cells/designs - # may have must-connect pins - cell[str(pin_name)].append(pin_layout(pin_name, rect, lpp)) + if pin_shape != None: + (lpp, boundary) = pin_shape + rect = [vector(boundary[0], boundary[1]), + vector(boundary[2], boundary[3])] + # this is a list because other cells/designs + # may have must-connect pins + if isinstance(lpp[1], list): + try: + from tech import layer_override + if layer_override[pin_name]: + lpp = layer_override[pin_name.textString] + except: + pass + lpp = (lpp[0], None) + cell[str(pin_name)].append(pin_layout(pin_name, rect, lpp)) _GDS_PINS_CACHE[k] = cell return dict(cell) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 0405649d..205baeb7 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -6,6 +6,7 @@ # All rights reserved. # import math +from tech import spice class verilog: @@ -28,7 +29,21 @@ class verilog: else: self.vf.write("\n") + try: + self.vdd_name = spice["power"] + except KeyError: + self.vdd_name = "vdd" + try: + self.gnd_name = spice["ground"] + except KeyError: + self.gnd_name = "gnd" + self.vf.write("module {0}(\n".format(self.name)) + self.vf.write("`ifdef USE_POWER_PINS\n") + self.vf.write(" {},\n".format(self.vdd_name)) + self.vf.write(" {},\n".format(self.gnd_name)) + self.vf.write("`endif\n") + for port in self.all_ports: if port in self.readwrite_ports: self.vf.write("// Port {0}: RW\n".format(port)) @@ -40,11 +55,15 @@ class verilog: self.vf.write(" clk{0},csb{0},web{0},".format(port)) if self.write_size: self.vf.write("wmask{},".format(port)) + if self.num_spare_cols > 0: + self.vf.write("spare_wen{0},".format(port)) self.vf.write("addr{0},din{0},dout{0}".format(port)) elif port in self.write_ports: self.vf.write(" clk{0},csb{0},".format(port)) if self.write_size: self.vf.write("wmask{},".format(port)) + if self.num_spare_cols > 0: + self.vf.write("spare_wen{0},".format(port)) self.vf.write("addr{0},din{0}".format(port)) elif port in self.read_ports: self.vf.write(" clk{0},csb{0},addr{0},dout{0}".format(port)) @@ -56,7 +75,7 @@ class verilog: if self.write_size: self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) self.vf.write(" parameter NUM_WMASKS = {0} ;\n".format(self.num_wmasks)) - self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size)) + self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size + self.num_spare_cols)) self.vf.write(" parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size)) self.vf.write(" parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n") self.vf.write(" // FIXME: This delay is arbitrary.\n") @@ -65,6 +84,11 @@ class verilog: self.vf.write(" parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary\n") self.vf.write("\n") + self.vf.write("`ifdef USE_POWER_PINS\n") + self.vf.write(" inout {};\n".format(self.vdd_name)) + self.vf.write(" inout {};\n".format(self.gnd_name)) + self.vf.write("`endif\n") + for port in self.all_ports: self.add_inputs_outputs(port) @@ -103,6 +127,10 @@ class verilog: if port in self.write_ports: if self.write_size: self.vf.write(" reg [NUM_WMASKS-1:0] wmask{0}_reg;\n".format(port)) + if self.num_spare_cols > 1: + self.vf.write(" reg [{1}:0] spare_wen{0}_reg;".format(port, self.num_spare_cols - 1)) + elif self.num_spare_cols == 1: + self.vf.write(" reg spare_wen{0}_reg;\n".format(port)) self.vf.write(" reg [ADDR_WIDTH-1:0] addr{0}_reg;\n".format(port)) if port in self.write_ports: self.vf.write(" reg [DATA_WIDTH-1:0] din{0}_reg;\n".format(port)) @@ -123,7 +151,9 @@ class verilog: if port in self.write_ports: if self.write_size: self.vf.write(" wmask{0}_reg = wmask{0};\n".format(port)) - self.vf.write(" addr{0}_reg = addr{0};\n".format(port)) + if self.num_spare_cols: + self.vf.write(" spare_wen{0}_reg = spare_wen{0};\n".format(port)) + self.vf.write(" addr{0}_reg = addr{0};\n".format(port)) if port in self.read_ports: self.add_write_read_checks(port) @@ -162,6 +192,11 @@ class verilog: self.vf.write(" input web{0}; // active low write control\n".format(port)) if self.write_size: self.vf.write(" input [NUM_WMASKS-1:0] wmask{0}; // write mask\n".format(port)) + if self.num_spare_cols == 1: + self.vf.write(" input spare_wen{0}; // spare mask\n".format(port)) + elif self.num_spare_cols > 1: + self.vf.write(" input [{1}:0] spare_wen{0}; // spare mask\n".format(port, self.num_spare_cols-1)) + self.vf.write(" input [ADDR_WIDTH-1:0] addr{0};\n".format(port)) if port in self.write_ports: self.vf.write(" input [DATA_WIDTH-1:0] din{0};\n".format(port)) @@ -179,29 +214,29 @@ class verilog: self.vf.write(" always @ (negedge clk{0})\n".format(port)) self.vf.write(" begin : MEM_WRITE{0}\n".format(port)) if port in self.readwrite_ports: - if self.write_size: - self.vf.write(" if ( !csb{0}_reg && !web{0}_reg ) begin\n".format(port)) - else: - self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port)) + self.vf.write(" if ( !csb{0}_reg && !web{0}_reg ) begin\n".format(port)) else: - if self.write_size: - self.vf.write(" if (!csb{0}_reg) begin\n".format(port)) - else: - self.vf.write(" if (!csb{0}_reg)\n".format(port)) + self.vf.write(" if (!csb{0}_reg) begin\n".format(port)) if self.write_size: - remainder_bits = self.word_size % self.write_size for mask in range(0, self.num_wmasks): lower = mask * self.write_size - if (remainder_bits and mask == self.num_wmasks - 1): - upper = lower + remainder_bits - 1 - else: - upper = lower + self.write_size - 1 + upper = lower + self.write_size - 1 self.vf.write(" if (wmask{0}_reg[{1}])\n".format(port, mask)) self.vf.write(" mem[addr{0}_reg][{1}:{2}] = din{0}_reg[{1}:{2}];\n".format(port, upper, lower)) - self.vf.write(" end\n") else: - self.vf.write(" mem[addr{0}_reg] = din{0}_reg;\n".format(port)) + upper = self.word_size - self.num_spare_cols - 1 + self.vf.write(" mem[addr{0}_reg][{1}:0] = din{0}_reg[{1}:0];\n".format(port, upper)) + + if self.num_spare_cols == 1: + self.vf.write(" if (spare_wen{0}_reg)\n".format(port)) + self.vf.write(" mem[addr{0}_reg][{1}] = din{0}_reg[{1}];\n".format(port, self.word_size)) + else: + for num in range(self.num_spare_cols): + self.vf.write(" if (spare_wen{0}_reg[{1}])\n".format(port, num)) + self.vf.write(" mem[addr{0}_reg][{1}] = din{0}_reg[{1}];\n".format(port, self.word_size + num)) + + self.vf.write(" end\n") self.vf.write(" end\n") def add_read_block(self, port): diff --git a/compiler/bitcells/bitcell_2port.py b/compiler/bitcells/bitcell_2port.py index fcba7a38..75d654c0 100644 --- a/compiler/bitcells/bitcell_2port.py +++ b/compiler/bitcells/bitcell_2port.py @@ -99,3 +99,8 @@ class bitcell_2port(bitcell_base.bitcell_base): # Port 1 edges graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self) graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self) + + def is_non_inverting(self): + """Return input to output polarity for module""" + + return False \ No newline at end of file diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 5112642e..1161fec8 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -26,7 +26,6 @@ class bitcell_base(design.design): self.nets_match = self.do_nets_exist(prop.storage_nets) self.mirror = prop.mirror self.end_caps = prop.end_caps - def get_stage_effort(self, load): parasitic_delay = 1 # This accounts for bitline being drained @@ -84,7 +83,7 @@ class bitcell_base(design.design): return self.storage_nets else: fmt_str = "Storage nodes={} not found in spice file." - debug.info(1, fmt_str.format(self.storage_nets)) + debug.warning(fmt_str.format(self.storage_nets)) return None def get_storage_net_offset(self): diff --git a/compiler/bitcells/replica_bitcell_2port.py b/compiler/bitcells/replica_bitcell_2port.py index f75d514f..8d113805 100644 --- a/compiler/bitcells/replica_bitcell_2port.py +++ b/compiler/bitcells/replica_bitcell_2port.py @@ -49,3 +49,8 @@ class replica_bitcell_2port(bitcell_base.bitcell_base): # Port 1 edges graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self) graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self) + + def is_non_inverting(self): + """Return input to output polarity for module""" + + return False \ No newline at end of file diff --git a/compiler/characterizer/__init__.py b/compiler/characterizer/__init__.py index 0d9fbe83..c052a0a0 100644 --- a/compiler/characterizer/__init__.py +++ b/compiler/characterizer/__init__.py @@ -12,33 +12,47 @@ from .lib import * from .delay import * from .elmore import * from .linear_regression import * +from .neural_network import * from .setup_hold import * from .functional import * from .simulation import * from .measurements import * from .model_check import * from .analytical_util import * -from .regression_model import * debug.info(1, "Initializing characterizer...") OPTS.spice_exe = "" if not OPTS.analytical_delay: - debug.info(1, "Finding spice simulator.") - - if OPTS.spice_name != "": + if OPTS.spice_name: + # Capitalize Xyce + if OPTS.spice_name == "xyce": + OPTS.spice_name = "Xyce" OPTS.spice_exe=find_exe(OPTS.spice_name) if OPTS.spice_exe=="" or OPTS.spice_exe==None: debug.error("{0} not found. Unable to perform characterization.".format(OPTS.spice_name), 1) else: - (OPTS.spice_name, OPTS.spice_exe) = get_tool("spice", ["ngspice", "ngspice.exe", "hspice", "xa"]) + (OPTS.spice_name, OPTS.spice_exe) = get_tool("spice", ["Xyce", "ngspice", "ngspice.exe", "hspice", "xa"]) + + if OPTS.spice_name in ["Xyce", "xyce"]: + (OPTS.mpi_name, OPTS.mpi_exe) = get_tool("mpi", ["mpirun"]) + OPTS.hier_seperator = ":" + else: + OPTS.mpi_name = None + OPTS.mpi_exe = "" # set the input dir for spice files if using ngspice if OPTS.spice_name == "ngspice": os.environ["NGSPICE_INPUT_DIR"] = "{0}".format(OPTS.openram_temp) - if OPTS.spice_exe == "": + if not OPTS.spice_exe: debug.error("No recognizable spice version found. Unable to perform characterization.", 1) + else: + debug.info(1, "Finding spice simulator: {} ({})".format(OPTS.spice_name, OPTS.spice_exe)) + if OPTS.mpi_name: + debug.info(1, "MPI for spice simulator: {} ({})".format(OPTS.mpi_name, OPTS.mpi_exe)) + debug.info(1, "Simulation threads: {}".format(OPTS.num_sim_threads)) + else: debug.info(1, "Analytical model enabled.") diff --git a/compiler/characterizer/analytical_util.py b/compiler/characterizer/analytical_util.py index 43435667..41120982 100644 --- a/compiler/characterizer/analytical_util.py +++ b/compiler/characterizer/analytical_util.py @@ -14,7 +14,7 @@ import os process_transform = {'SS':0.0, 'TT': 0.5, 'FF':1.0} -def get_data_names(file_name): +def get_data_names(file_name, exclude_area=True): """ Returns just the data names in the first row of the CSV """ @@ -25,8 +25,18 @@ def get_data_names(file_name): # reader is iterable not a list, probably a better way to do this for row in csv_reader: # Return names from first row - return row[0].split(',') - + names = row[0].split(',') + break + if exclude_area: + try: + area_ind = names.index('area') + except ValueError: + area_ind = -1 + + if area_ind != -1: + names = names[:area_ind] + names[area_ind+1:] + return names + def get_data(file_name): """ Returns data in CSV as lists of features @@ -35,24 +45,33 @@ def get_data(file_name): with open(file_name, newline='') as csvfile: csv_reader = csv.reader(csvfile, delimiter=' ', quotechar='|') row_iter = 0 + removed_items = 1 for row in csv_reader: row_iter += 1 if row_iter == 1: feature_names = row[0].split(',') - input_list = [[] for _ in feature_names] - scaled_list = [[] for _ in feature_names] - + input_list = [[] for _ in range(len(feature_names)-removed_items)] + try: + # Save to remove area + area_ind = feature_names.index('area') + except ValueError: + area_ind = -1 + try: process_ind = feature_names.index('process') except: debug.error('Process not included as a feature.') continue + + data = [] split_str = row[0].split(',') for i in range(len(split_str)): if i == process_ind: data.append(process_transform[split_str[i]]) + elif i == area_ind: + continue else: data.append(float(split_str[i])) @@ -227,9 +246,8 @@ def get_scaled_data(file_name): # Data is scaled by max/min and data format is changed to points vs feature lists self_scaled_data = scale_data_and_transform(all_data) - samples = np.asarray(self_scaled_data) - features, labels = samples[:, :-1], samples[:,-1:] - return features, labels + data_np = np.asarray(self_scaled_data) + return data_np def scale_data_and_transform(data): """ @@ -275,16 +293,13 @@ def unscale_data(data, file_path, pos=None): # Hard coded to only convert the last max/min (i.e. the label of the data) if pos == None: - maxs,mins,avgs = [maxs[-1]],[mins[-1]],[avgs[-1]] + maxs,mins,avgs = maxs[-1],mins[-1],avgs[-1] else: - maxs,mins,avgs = [maxs[pos]],[mins[pos]],[avgs[pos]] + maxs,mins,avgs = maxs[pos],mins[pos],avgs[pos] unscaled_data = [] for data_row in data: - unscaled_row = [] - for val, cur_max, cur_min in zip(data_row, maxs, mins): - unscaled_val = val*(cur_max-cur_min) + cur_min - unscaled_row.append(unscaled_val) - unscaled_data.append(unscaled_row) + unscaled_val = data_row*(maxs-mins) + mins + unscaled_data.append(unscaled_val) return unscaled_data diff --git a/compiler/characterizer/charutils.py b/compiler/characterizer/charutils.py index 8f33c279..59ef3177 100644 --- a/compiler/characterizer/charutils.py +++ b/compiler/characterizer/charutils.py @@ -11,21 +11,26 @@ import debug from globals import OPTS -def relative_compare(value1,value2,error_tolerance=0.001): +def relative_compare(value1, value2, error_tolerance=0.001): """ This is used to compare relative values for convergence. """ - return (abs(value1 - value2) / abs(max(value1,value2)) <= error_tolerance) + return (abs(value1 - value2) / abs(max(value1, value2)) <= error_tolerance) def parse_spice_list(filename, key): """Parses a hspice output.lis file for a key value""" + + lower_key = key.lower() + if OPTS.spice_name == "xa" : # customsim has a different output file name full_filename="{0}xa.meas".format(OPTS.openram_temp) elif OPTS.spice_name == "spectre": full_filename = os.path.join(OPTS.openram_temp, "delay_stim.measure") + elif OPTS.spice_name in ["Xyce", "xyce"]: + full_filename = os.path.join(OPTS.openram_temp, "spice_stdout.log") else: # ngspice/hspice using a .lis file - full_filename="{0}{1}.lis".format(OPTS.openram_temp, filename) + full_filename = "{0}{1}.lis".format(OPTS.openram_temp, filename) try: f = open(full_filename, "r") @@ -33,31 +38,34 @@ def parse_spice_list(filename, key): debug.error("Unable to open spice output file: {0}".format(full_filename),1) debug.archive() - contents = f.read() + contents = f.read().lower() f.close() # val = re.search(r"{0}\s*=\s*(-?\d+.?\d*\S*)\s+.*".format(key), contents) - val = re.search(r"{0}\s*=\s*(-?\d+.?\d*[e]?[-+]?[0-9]*\S*)\s+.*".format(key), contents) + val = re.search(r"{0}\s*=\s*(-?\d+.?\d*[e]?[-+]?[0-9]*\S*)\s+.*".format(lower_key), contents) if val != None: - debug.info(4, "Key = " + key + " Val = " + val.group(1)) + debug.info(4, "Key = " + lower_key + " Val = " + val.group(1)) return convert_to_float(val.group(1)) else: return "Failed" -def round_time(time,time_precision=3): + +def round_time(time, time_precision=3): # times are in ns, so this is how many digits of precision # 3 digits = 1ps # 4 digits = 0.1ps # etc. - return round(time,time_precision) + return round(time, time_precision) -def round_voltage(voltage,voltag_precision=5): + +def round_voltage(voltage, voltage_precision=5): # voltages are in volts # 3 digits = 1mv # 4 digits = 0.1mv # 5 digits = 0.01mv # 6 digits = 1uv # etc - return round(voltage,voltage_precision) + return round(voltage, voltage_precision) + def convert_to_float(number): """Converts a string into a (float) number; also converts units(m,u,n,p)""" @@ -84,7 +92,7 @@ def convert_to_float(number): 'n': lambda x: x * 0.000000001, # nano 'p': lambda x: x * 0.000000000001, # pico 'f': lambda x: x * 0.000000000000001 # femto - }[unit.group(2)](float(unit.group(1))) + }[unit.group(2)](float(unit.group(1))) # if we weren't able to convert it to a float then error out if not type(float_value)==float: @@ -92,9 +100,10 @@ def convert_to_float(number): return float_value + def check_dict_values_is_float(dict): """Checks if all the values are floats. Useful for checking failed Spice measurements.""" for key, value in dict.items(): - if type(value)!=float: - return False + if type(value)!=float: + return False return True diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 168a73e9..27d72195 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -69,7 +69,7 @@ class delay(simulation): for meas in meas_list: name = meas.name.lower() debug.check(name not in name_set, ("SPICE measurements must have unique names. " - "Duplicate name={}").format(name)) + "Duplicate name={0}").format(name)) name_set.add(name) def create_read_port_measurement_objects(self): @@ -77,7 +77,7 @@ class delay(simulation): self.read_lib_meas = [] self.clk_frmt = "clk{0}" # Unformatted clock name - targ_name = "{0}{1}_{2}".format(self.dout_name, "{}", self.probe_data) # Empty values are the port and probe data bit + targ_name = "{0}{{}}_{1}".format(self.dout_name, self.probe_data) # Empty values are the port and probe data bit self.delay_meas = [] self.delay_meas.append(delay_measure("delay_lh", self.clk_frmt, targ_name, "RISE", "RISE", measure_scale=1e9)) self.delay_meas[-1].meta_str = sram_op.READ_ONE # Used to index time delay values when measurements written to spice file. @@ -166,7 +166,7 @@ class delay(simulation): self.dout_volt_meas = [] for meas in self.delay_meas: # Output voltage measures - self.dout_volt_meas.append(voltage_at_measure("v_{}".format(meas.name), + self.dout_volt_meas.append(voltage_at_measure("v_{0}".format(meas.name), meas.targ_name_no_port)) self.dout_volt_meas[-1].meta_str = meas.meta_str @@ -186,7 +186,7 @@ class delay(simulation): self.read_bit_meas = {bit_polarity.NONINVERTING: [], bit_polarity.INVERTING: []} meas_cycles = (sram_op.READ_ZERO, sram_op.READ_ONE) for cycle in meas_cycles: - meas_tag = "a{}_b{}_{}".format(self.probe_address, self.probe_data, cycle.name) + meas_tag = "a{0}_b{1}_{2}".format(self.probe_address, self.probe_data, cycle.name) single_bit_meas = self.get_bit_measures(meas_tag, self.probe_address, self.probe_data) for polarity, meas in single_bit_meas.items(): meas.meta_str = cycle @@ -200,7 +200,7 @@ class delay(simulation): self.write_bit_meas = {bit_polarity.NONINVERTING: [], bit_polarity.INVERTING: []} meas_cycles = (sram_op.WRITE_ZERO, sram_op.WRITE_ONE) for cycle in meas_cycles: - meas_tag = "a{}_b{}_{}".format(self.probe_address, self.probe_data, cycle.name) + meas_tag = "a{0}_b{1}_{2}".format(self.probe_address, self.probe_data, cycle.name) single_bit_meas = self.get_bit_measures(meas_tag, self.probe_address, self.probe_data) for polarity, meas in single_bit_meas.items(): meas.meta_str = cycle @@ -219,20 +219,20 @@ class delay(simulation): (cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, bit_row, bit_col) storage_names = cell_inst.mod.get_storage_net_names() debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" - "supported for characterization. Storage nets={}").format(storage_names)) + "supported for characterization. Storage nets={0}").format(storage_names)) if OPTS.use_pex and OPTS.pex_exe[0] != "calibre": bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col) q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) qbar_name = "bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) else: - q_name = cell_name + '.' + str(storage_names[0]) - qbar_name = cell_name + '.' + str(storage_names[1]) + q_name = cell_name + OPTS.hier_seperator + str(storage_names[0]) + qbar_name = cell_name + OPTS.hier_seperator + str(storage_names[1]) # Bit measures, measurements times to be defined later. The measurement names must be unique # but they is enforced externally. {} added to names to differentiate between ports allow the # measurements are independent of the ports - q_meas = voltage_at_measure("v_q_{}".format(meas_tag), q_name) - qbar_meas = voltage_at_measure("v_qbar_{}".format(meas_tag), qbar_name) + q_meas = voltage_at_measure("v_q_{0}".format(meas_tag), q_name) + qbar_meas = voltage_at_measure("v_qbar_{0}".format(meas_tag), qbar_name) return {bit_polarity.NONINVERTING: q_meas, bit_polarity.INVERTING: qbar_meas} @@ -242,15 +242,15 @@ class delay(simulation): # FIXME: There should be a default_read_port variable in this case, pathing is done with this # but is never mentioned otherwise port = self.read_ports[0] - sen_and_port = self.sen_name+str(port) + sen_and_port = self.sen_name + str(port) bl_and_port = self.bl_name.format(port) # bl_name contains a '{}' for the port # Isolate the s_en and bitline paths - debug.info(1, "self.bl_name = {}".format(self.bl_name)) - debug.info(1, "self.graph.all_paths = {}".format(self.graph.all_paths)) + debug.info(1, "self.bl_name = {0}".format(self.bl_name)) + debug.info(2, "self.graph.all_paths = {0}".format(self.graph.all_paths)) sen_paths = [path for path in self.graph.all_paths if sen_and_port in path] bl_paths = [path for path in self.graph.all_paths if bl_and_port in path] - debug.check(len(sen_paths)==1, 'Found {} paths which contain the s_en net.'.format(len(sen_paths))) - debug.check(len(bl_paths)==1, 'Found {} paths which contain the bitline net.'.format(len(bl_paths))) + debug.check(len(sen_paths)==1, 'Found {0} paths which contain the s_en net.'.format(len(sen_paths))) + debug.check(len(bl_paths)==1, 'Found {0} paths which contain the bitline net.'.format(len(bl_paths))) sen_path = sen_paths[0] bitline_path = bl_paths[0] @@ -286,11 +286,11 @@ class delay(simulation): # Create the measurements path_meas = [] - for i in range(len(path)-1): - cur_net, next_net = path[i], path[i+1] - cur_dir, next_dir = path_dirs[i], path_dirs[i+1] - meas_name = "delay_{}_to_{}".format(cur_net, next_net) - if i+1 != len(path)-1: + for i in range(len(path) - 1): + cur_net, next_net = path[i], path[i + 1] + cur_dir, next_dir = path_dirs[i], path_dirs[i + 1] + meas_name = "delay_{0}_to_{1}".format(cur_net, next_net) + if i + 1 != len(path) - 1: path_meas.append(delay_measure(meas_name, cur_net, next_net, cur_dir, next_dir, measure_scale=1e9, has_port=False)) else: # Make the last measurement always measure on FALL because is a read 0 path_meas.append(delay_measure(meas_name, cur_net, next_net, cur_dir, "FALL", measure_scale=1e9, has_port=False)) @@ -309,13 +309,13 @@ class delay(simulation): # Convert to booleans based on function of modules (inverting/non-inverting) mod_type_bools = [mod.is_non_inverting() for mod in edge_mods] - #FIXME: obtuse hack to differentiate s_en input from bitline in sense amps + # FIXME: obtuse hack to differentiate s_en input from bitline in sense amps if self.sen_name in path: # Force the sense amp to be inverting for s_en->DOUT. # bitline->DOUT is non-inverting, but the module cannot differentiate inputs. s_en_index = path.index(self.sen_name) mod_type_bools[s_en_index] = False - debug.info(2,'Forcing sen->dout to be inverting.') + debug.info(2, 'Forcing sen->dout to be inverting.') # Use these to determine direction list assuming delay start on neg. edge of clock (FALL) # Also, use shorthand that 'FALL' == False, 'RISE' == True to simplify logic @@ -493,7 +493,7 @@ class delay(simulation): elif meas_type is voltage_at_measure: variant_tuple = self.get_volt_at_measure_variants(port, measure_obj) else: - debug.error("Input function not defined for measurement type={}".format(meas_type)) + debug.error("Input function not defined for measurement type={0}".format(meas_type)) # Removes port input from any object which does not use it. This shorthand only works if # the measurement has port as the last input. Could be implemented by measurement type or # remove entirely from measurement classes. @@ -515,7 +515,7 @@ class delay(simulation): elif delay_obj.meta_str == sram_op.READ_ONE: meas_cycle_delay = self.cycle_times[self.measure_cycles[port][delay_obj.meta_str]] else: - debug.error("Unrecognized delay Index={}".format(delay_obj.meta_str),1) + debug.error("Unrecognized delay Index={0}".format(delay_obj.meta_str), 1) # These measurements have there time further delayed to the neg. edge of the clock. if delay_obj.meta_add_delay: @@ -587,20 +587,20 @@ class delay(simulation): # Output some comments to aid where cycles start and # what is happening for comment in self.cycle_comments: - self.sf.write("* {}\n".format(comment)) + self.sf.write("* {0}\n".format(comment)) self.sf.write("\n") for read_port in self.targ_read_ports: - self.sf.write("* Read ports {}\n".format(read_port)) + self.sf.write("* Read ports {0}\n".format(read_port)) self.write_delay_measures_read_port(read_port) for write_port in self.targ_write_ports: - self.sf.write("* Write ports {}\n".format(write_port)) + self.sf.write("* Write ports {0}\n".format(write_port)) self.write_delay_measures_write_port(write_port) def load_pex_net(self, net: str): from subprocess import check_output, CalledProcessError - prefix = (self.sram_instance_name + ".").lower() + prefix = (self.sram_instance_name + OPTS.hier_seperator).lower() if not net.lower().startswith(prefix) or not OPTS.use_pex or not OPTS.calibre_pex: return net original_net = net @@ -640,26 +640,41 @@ class delay(simulation): col = self.bitline_column row = self.wordline_row for port in set(self.targ_read_ports + self.targ_write_ports): - probe_nets.add("WEB{}".format(port)) - probe_nets.add("{}.w_en{}".format(self.sram_instance_name, port)) - probe_nets.add("{0}.Xbank0.Xport_data{1}.Xwrite_driver_array{1}.Xwrite_driver{2}.en_bar".format( - self.sram_instance_name, port, self.bitline_column)) - probe_nets.add("{}.Xbank0.br_{}_{}".format(self.sram_instance_name, port, - self.bitline_column)) + probe_nets.add("WEB{0}".format(port)) + probe_nets.add("{0}{2}w_en{1}".format(self.sram_instance_name, port, OPTS.hier_seperator)) + probe_nets.add("{0}{3}Xbank0{3}Xport_data{1}{3}Xwrite_driver_array{1}{3}Xwrite_driver{2}{3}en_bar".format(self.sram_instance_name, + port, + self.bitline_column, + OPTS.hier_seperator)) + probe_nets.add("{0}{3}Xbank0{3}br_{1}_{2}".format(self.sram_instance_name, + port, + self.bitline_column, + OPTS.hier_seperator)) if not OPTS.use_pex: continue probe_nets.add( - "{0}.vdd_Xbank0_Xbitcell_array_xbitcell_array_xbit_r{1}_c{2}".format(sram_name, row, col - 1)) + "{0}{3}vdd_Xbank0_Xbitcell_array_xbitcell_array_xbit_r{1}_c{2}".format(sram_name, + row, + col - 1, + OPTS.hier_seperator)) probe_nets.add( - "{0}.p_en_bar{1}_Xbank0_Xport_data{1}_Xprecharge_array{1}_Xpre_column_{2}".format(sram_name, port, col)) + "{0}{3}p_en_bar{1}_Xbank0_Xport_data{1}_Xprecharge_array{1}_Xpre_column_{2}".format(sram_name, + port, + col, + OPTS.hier_seperator)) probe_nets.add( - "{0}.vdd_Xbank0_Xport_data{1}_Xprecharge_array{1}_xpre_column_{2}".format(sram_name, port, col)) - probe_nets.add("{0}.vdd_Xbank0_Xport_data{1}_Xwrite_driver_array{1}_xwrite_driver{2}".format(sram_name, - port, col)) + "{0}{3}vdd_Xbank0_Xport_data{1}_Xprecharge_array{1}_xpre_column_{2}".format(sram_name, + port, + col, + OPTS.hier_seperator)) + probe_nets.add("{0}{3}vdd_Xbank0_Xport_data{1}_Xwrite_driver_array{1}_xwrite_driver{2}".format(sram_name, + port, + col, + OPTS.hier_seperator)) probe_nets.update(self.measurement_nets) for net in probe_nets: - debug.info(2, "Probe: {}".format(net)) - self.sf.write(".plot V({}) \n".format(self.load_pex_net(net))) + debug.info(2, "Probe: {0}".format(net)) + self.sf.write(".plot V({0}) \n".format(self.load_pex_net(net))) def write_power_measures(self): """ @@ -778,7 +793,7 @@ class delay(simulation): if not self.check_bit_measures(self.write_bit_meas, port): return(False, {}) - debug.info(2, "Checking write values for port {}".format(port)) + debug.info(2, "Checking write values for port {0}".format(port)) write_port_dict = {} for measure in self.write_lib_meas: write_port_dict[measure.name] = measure.retrieve_measure(port=port) @@ -792,7 +807,7 @@ class delay(simulation): if not self.check_bit_measures(self.read_bit_meas, port): return(False, {}) - debug.info(2, "Checking read delay values for port {}".format(port)) + debug.info(2, "Checking read delay values for port {0}".format(port)) # Check sen timing, then bitlines, then general measurements. if not self.check_sen_measure(port): return (False, {}) @@ -813,7 +828,7 @@ class delay(simulation): result[port].update(read_port_dict) - self.check_path_measures() + self.path_delays = self.check_path_measures() return (True, result) @@ -821,7 +836,7 @@ class delay(simulation): """Checks that the sen occurred within a half-period""" sen_val = self.sen_meas.retrieve_measure(port=port) - debug.info(2, "s_en delay={}ns".format(sen_val)) + debug.info(2, "s_en delay={0}ns".format(sen_val)) if self.sen_meas.meta_add_delay: max_delay = self.period / 2 else: @@ -843,22 +858,22 @@ class delay(simulation): elif self.br_name == meas.targ_name_no_port: br_vals[meas.meta_str] = val - debug.info(2, "{}={}".format(meas.name, val)) + debug.info(2, "{0}={1}".format(meas.name, val)) dout_success = True bl_success = False for meas in self.dout_volt_meas: val = meas.retrieve_measure(port=port) - debug.info(2, "{}={}".format(meas.name, val)) + debug.info(2, "{0}={1}".format(meas.name, val)) debug.check(type(val)==float, "Error retrieving numeric measurement: {0} {1}".format(meas.name, val)) if meas.meta_str == sram_op.READ_ONE and val < self.vdd_voltage * 0.1: dout_success = False - debug.info(1, "Debug measurement failed. Value {}V was read on read 1 cycle.".format(val)) + debug.info(1, "Debug measurement failed. Value {0}V was read on read 1 cycle.".format(val)) bl_success = self.check_bitline_meas(bl_vals[sram_op.READ_ONE], br_vals[sram_op.READ_ONE]) elif meas.meta_str == sram_op.READ_ZERO and val > self.vdd_voltage * 0.9: dout_success = False - debug.info(1, "Debug measurement failed. Value {}V was read on read 0 cycle.".format(val)) + debug.info(1, "Debug measurement failed. Value {0}V was read on read 0 cycle.".format(val)) bl_success = self.check_bitline_meas(br_vals[sram_op.READ_ONE], bl_vals[sram_op.READ_ONE]) # If the bitlines have a correct value while the output does not then that is a @@ -877,7 +892,7 @@ class delay(simulation): for polarity, meas_list in bit_measures.items(): for meas in meas_list: val = meas.retrieve_measure(port=port) - debug.info(2, "{}={}".format(meas.name, val)) + debug.info(2, "{0}={1}".format(meas.name, val)) if type(val) != float: continue meas_cycle = meas.meta_str @@ -896,8 +911,8 @@ class delay(simulation): success = val < self.vdd_voltage / 2 if not success: debug.info(1, ("Wrong value detected on probe bit during read/write cycle. " - "Check writes and control logic for bugs.\n measure={}, op={}, " - "bit_storage={}, V(bit)={}").format(meas.name, meas_cycle.name, polarity.name, val)) + "Check writes and control logic for bugs.\n measure={0}, op={1}, " + "bit_storage={2}, V(bit)={3}").format(meas.name, meas_cycle.name, polarity.name, val)) return success @@ -912,7 +927,7 @@ class delay(simulation): min_dicharge = v_discharged_bl < self.vdd_voltage * 0.9 min_diff = (v_charged_bl - v_discharged_bl) > self.vdd_voltage * 0.1 - debug.info(1, "min_dicharge={}, min_diff={}".format(min_dicharge, min_diff)) + debug.info(1, "min_dicharge={0}, min_diff={1}".format(min_dicharge, min_diff)) return (min_dicharge and min_diff) def check_path_measures(self): @@ -921,13 +936,13 @@ class delay(simulation): # Get and set measurement, no error checking done other than prints. debug.info(2, "Checking measures in Delay Path") value_dict = {} - for meas in self.sen_path_meas+self.bl_path_meas: + for meas in self.sen_path_meas + self.bl_path_meas: val = meas.retrieve_measure() - debug.info(2, '{}={}'.format(meas.name, val)) - if type(val) != float or val > self.period/2: - debug.info(1,'Failed measurement:{}={}'.format(meas.name, val)) + debug.info(2, '{0}={1}'.format(meas.name, val)) + if type(val) != float or val > self.period / 2: + debug.info(1, 'Failed measurement:{}={}'.format(meas.name, val)) value_dict[meas.name] = val - + #debug.info(0, "value_dict={}".format(value_dict)) return value_dict def run_power_simulation(self): @@ -1100,14 +1115,14 @@ class delay(simulation): # Set up to trim the netlist here if that is enabled if OPTS.trim_netlist: - self.trim_sp_file = "{}trimmed.sp".format(OPTS.openram_temp) + self.trim_sp_file = "{0}trimmed.sp".format(OPTS.openram_temp) self.sram.sp_write(self.trim_sp_file, lvs=False, trim=True) else: # The non-reduced netlist file when it is disabled - self.trim_sp_file = "{}sram.sp".format(OPTS.openram_temp) + self.trim_sp_file = "{0}sram.sp".format(OPTS.openram_temp) # The non-reduced netlist file for power simulation - self.sim_sp_file = "{}sram.sp".format(OPTS.openram_temp) + self.sim_sp_file = "{0}sram.sp".format(OPTS.openram_temp) # Make a copy in temp for debugging shutil.copy(self.sp_file, self.sim_sp_file) @@ -1120,7 +1135,7 @@ class delay(simulation): self.create_measurement_names() self.create_measurement_objects() - def analyze(self, probe_address, probe_data, slews, loads): + def analyze(self, probe_address, probe_data, load_slews): """ Main function to characterize an SRAM for a table. Computes both delay and power characterization. """ @@ -1128,7 +1143,11 @@ class delay(simulation): # Dict to hold all characterization values char_sram_data = {} self.analysis_init(probe_address, probe_data) - + loads = [] + slews = [] + for load,slew in load_slews: + loads.append(load) + slews.append(slew) self.load=max(loads) self.slew=max(slews) @@ -1148,11 +1167,19 @@ class delay(simulation): leakage_offset = full_array_leakage - trim_array_leakage # 4) At the minimum period, measure the delay, slew and power for all slew/load pairs. self.period = min_period - char_port_data = self.simulate_loads_and_slews(slews, loads, leakage_offset) - + char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset) + if OPTS.use_specified_load_slew != None and len(load_slews) > 1: + debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew") + # Get and save the path delays + bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays) + # Removed from characterization output temporarily + #char_sram_data["bl_path_measures"] = bl_delays + #char_sram_data["sen_path_measures"] = sen_delays + #char_sram_data["bl_path_names"] = bl_names + #char_sram_data["sen_path_names"] = sen_names # FIXME: low-to-high delays are altered to be independent of the period. This makes the lib results less accurate. self.alter_lh_char_data(char_port_data) - + return (char_sram_data, char_port_data) def alter_lh_char_data(self, char_port_data): @@ -1163,30 +1190,47 @@ class delay(simulation): char_port_data[port]['delay_lh'] = char_port_data[port]['delay_hl'] char_port_data[port]['slew_lh'] = char_port_data[port]['slew_hl'] - def simulate_loads_and_slews(self, slews, loads, leakage_offset): + def simulate_loads_and_slews(self, load_slews, leakage_offset): """Simulate all specified output loads and input slews pairs of all ports""" measure_data = self.get_empty_measure_data_dict() + path_dict = {} # Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways. self.targ_read_ports = self.read_ports self.targ_write_ports = self.write_ports - for slew in slews: - for load in loads: - self.set_load_slew(load, slew) - # Find the delay, dynamic power, and leakage power of the trimmed array. - (success, delay_results) = self.run_delay_simulation() - debug.check(success, "Couldn't run a simulation. slew={0} load={1}\n".format(self.slew, self.load)) - debug.info(1, "Simulation Passed: Port {0} slew={1} load={2}".format("All", self.slew, self.load)) - # The results has a dict for every port but dicts can be empty (e.g. ports were not targeted). - for port in self.all_ports: - for mname, value in delay_results[port].items(): - if "power" in mname: - # Subtract partial array leakage and add full array leakage for the power measures - measure_data[port][mname].append(value + leakage_offset) - else: - measure_data[port][mname].append(value) + for load, slew in load_slews: + self.set_load_slew(load, slew) + # Find the delay, dynamic power, and leakage power of the trimmed array. + (success, delay_results) = self.run_delay_simulation() + debug.check(success, "Couldn't run a simulation. slew={0} load={1}\n".format(self.slew, self.load)) + debug.info(1, "Simulation Passed: Port {0} slew={1} load={2}".format("All", self.slew, self.load)) + # The results has a dict for every port but dicts can be empty (e.g. ports were not targeted). + for port in self.all_ports: + for mname, value in delay_results[port].items(): + if "power" in mname: + # Subtract partial array leakage and add full array leakage for the power measures + debug.info(1, "Adding leakage offset to {0} {1} + {2} = {3}".format(mname, value, leakage_offset, value + leakage_offset)) + measure_data[port][mname].append(value + leakage_offset) + else: + measure_data[port][mname].append(value) return measure_data + def get_delay_lists(self, value_dict): + """Returns dicts for path measures of bitline and sen paths""" + sen_name_list = [] + sen_delay_list = [] + for meas in self.sen_path_meas: + sen_name_list.append(meas.name) + sen_delay_list.append(value_dict[meas.name]) + + bl_name_list = [] + bl_delay_list = [] + for meas in self.bl_path_meas: + bl_name_list.append(meas.name) + bl_delay_list.append(value_dict[meas.name]) + + return sen_name_list, sen_delay_list, bl_name_list, bl_delay_list + def calculate_inverse_address(self): """Determine dummy test address based on probe address and column mux size.""" @@ -1218,13 +1262,13 @@ class delay(simulation): if self.t_current == 0: self.add_noop_all_ports("Idle cycle (no positive clock edge)") - self.add_write("W data 1 address {}".format(inverse_address), + self.add_write("W data 1 address {0}".format(inverse_address), inverse_address, data_ones, wmask_ones, write_port) - self.add_write("W data 0 address {} to write value".format(self.probe_address), + self.add_write("W data 0 address {0} to write value".format(self.probe_address), self.probe_address, data_zeros, wmask_ones, @@ -1235,11 +1279,11 @@ class delay(simulation): self.measure_cycles[write_port]["disabled_write0"] = len(self.cycle_times) - 1 # This also ensures we will have a H->L transition on the next read - self.add_read("R data 1 address {} to set dout caps".format(inverse_address), + self.add_read("R data 1 address {0} to set dout caps".format(inverse_address), inverse_address, read_port) - self.add_read("R data 0 address {} to check W0 worked".format(self.probe_address), + self.add_read("R data 0 address {0} to check W0 worked".format(self.probe_address), self.probe_address, read_port) self.measure_cycles[read_port][sram_op.READ_ZERO] = len(self.cycle_times) - 1 @@ -1249,7 +1293,7 @@ class delay(simulation): self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)") - self.add_write("W data 1 address {} to write value".format(self.probe_address), + self.add_write("W data 1 address {0} to write value".format(self.probe_address), self.probe_address, data_ones, wmask_ones, @@ -1259,7 +1303,7 @@ class delay(simulation): self.add_noop_clock_one_port(write_port) self.measure_cycles[write_port]["disabled_write1"] = len(self.cycle_times) - 1 - self.add_write("W data 0 address {} to clear din caps".format(inverse_address), + self.add_write("W data 0 address {0} to clear din caps".format(inverse_address), inverse_address, data_zeros, wmask_ones, @@ -1269,11 +1313,11 @@ class delay(simulation): self.measure_cycles[read_port]["disabled_read1"] = len(self.cycle_times) - 1 # This also ensures we will have a L->H transition on the next read - self.add_read("R data 0 address {} to clear dout caps".format(inverse_address), + self.add_read("R data 0 address {0} to clear dout caps".format(inverse_address), inverse_address, read_port) - self.add_read("R data 1 address {} to check W1 worked".format(self.probe_address), + self.add_read("R data 1 address {0} to check W1 worked".format(self.probe_address), self.probe_address, read_port) self.measure_cycles[read_port][sram_op.READ_ONE] = len(self.cycle_times) - 1 diff --git a/compiler/characterizer/elmore.py b/compiler/characterizer/elmore.py index b9f99f02..262b35ad 100644 --- a/compiler/characterizer/elmore.py +++ b/compiler/characterizer/elmore.py @@ -30,7 +30,7 @@ class elmore(simulation): self.create_signal_names() self.add_graph_exclusions() - def get_lib_values(self, slews, loads): + def get_lib_values(self, load_slews): """ Return the analytical model results for the SRAM. """ @@ -53,33 +53,29 @@ class elmore(simulation): # Set delay/power for slews and loads port_data = self.get_empty_measure_data_dict() - power = self.analytical_power(slews, loads) + power = self.analytical_power(load_slews) debug.info(1, 'Slew, Load, Delay(ns), Slew(ns)') max_delay = 0.0 - for slew in slews: - for load in loads: - # Calculate delay based on slew and load - path_delays = self.graph.get_timing(bl_path, self.corner, slew, load) + for load,slew in load_slews: + # Calculate delay based on slew and load + path_delays = self.graph.get_timing(bl_path, self.corner, slew, load) - total_delay = self.sum_delays(path_delays) - max_delay = max(max_delay, total_delay.delay) - debug.info(1, - '{}, {}, {}, {}'.format(slew, - load, - total_delay.delay / 1e3, - total_delay.slew / 1e3)) - - # Delay is only calculated on a single port and replicated for now. - for port in self.all_ports: - for mname in self.delay_meas_names + self.power_meas_names: - if "power" in mname: - port_data[port][mname].append(power.dynamic) - elif "delay" in mname and port in self.read_ports: - port_data[port][mname].append(total_delay.delay / 1e3) - elif "slew" in mname and port in self.read_ports: - port_data[port][mname].append(total_delay.slew / 1e3) - else: - debug.error("Measurement name not recognized: {}".format(mname), 1) + total_delay = self.sum_delays(path_delays) + max_delay = max(max_delay, total_delay.delay) + debug.info(1, + '{}, {}, {}, {}'.format(slew, + load, + total_delay.delay / 1e3, + total_delay.slew / 1e3)) + # Delay is only calculated on a single port and replicated for now. + for port in self.all_ports: + for mname in self.delay_meas_names + self.power_meas_names: + if "power" in mname: + port_data[port][mname].append(power.dynamic) + elif "delay" in mname and port in self.read_ports: + port_data[port][mname].append(total_delay.delay / 1e3) + elif "slew" in mname and port in self.read_ports: + port_data[port][mname].append(total_delay.slew / 1e3) # Margin for error in period. Calculated by averaging required margin for a small and large # memory. FIXME: margin is quite large, should be looked into. @@ -92,11 +88,11 @@ class elmore(simulation): return (sram_data, port_data) - def analytical_power(self, slews, loads): + def analytical_power(self, load_slews): """Get the dynamic and leakage power from the SRAM""" # slews unused, only last load is used - load = loads[-1] + load = load_slews[-1][0] power = self.sram.analytical_power(self.corner, load) # convert from nW to mW power.dynamic /= 1e6 diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index f93de85c..e7d03f25 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -32,13 +32,13 @@ class functional(simulation): if not spfile: # self.sp_file is assigned in base class sram.sp_write(self.sp_file, trim=OPTS.trim_netlist) - + if not corner: corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) if period: self.period = period - + if not output_path: self.output_path = OPTS.openram_temp else: @@ -54,7 +54,7 @@ class functional(simulation): self.max_data = 2 ** self.word_size - 1 self.max_col_data = 2 ** self.num_spare_cols - 1 - if self.words_per_row>1: + if self.words_per_row > 1: # This will truncate bits for word addressing in a row_addr_dff # This makes one set of spares per row by using top bits of the address self.addr_spare_index = -int(math.log(self.words_per_row) / math.log(2)) @@ -63,11 +63,11 @@ class functional(simulation): self.addr_spare_index = self.addr_size # If trim is set, specify the valid addresses self.valid_addresses = set() - self.max_address = 2**self.addr_size - 1 + (self.num_spare_rows * self.words_per_row) + self.max_address = self.num_rows * self.words_per_row - 1 if OPTS.trim_netlist: for i in range(self.words_per_row): self.valid_addresses.add(i) - self.valid_addresses.add(self.max_address - i) + self.valid_addresses.add(self.max_address - i - 1) self.probe_address, self.probe_data = '0' * self.addr_size, 0 self.set_corner(corner) self.set_spice_constants() @@ -81,13 +81,17 @@ class functional(simulation): self.create_graph() self.set_internal_spice_names() self.q_name, self.qbar_name = self.get_bit_name() - debug.info(2, "q name={}\nqbar name={}".format(self.q_name, self.qbar_name)) + debug.info(2, "q:\t\t{0}".format(self.q_name)) + debug.info(2, "qbar:\t{0}".format(self.qbar_name)) + debug.info(2, "s_en:\t{0}".format(self.sen_name)) + debug.info(2, "bl:\t{0}".format(self.bl_name)) + debug.info(2, "br:\t{0}".format(self.br_name)) # Number of checks can be changed self.num_cycles = cycles # This is to have ordered keys for random selection self.stored_words = collections.OrderedDict() - self.stored_spares = collections.OrderedDict() + self.stored_spares = collections.OrderedDict() self.read_check = [] self.read_results = [] @@ -128,11 +132,12 @@ class functional(simulation): name)) def create_random_memory_sequence(self): + # Select randomly, but have 3x more reads to increase probability if self.write_size: - rw_ops = ["noop", "write", "partial_write", "read"] + rw_ops = ["noop", "write", "partial_write", "read", "read"] w_ops = ["noop", "write", "partial_write"] else: - rw_ops = ["noop", "write", "read"] + rw_ops = ["noop", "write", "read", "read"] w_ops = ["noop", "write"] r_ops = ["noop", "read"] @@ -140,37 +145,39 @@ class functional(simulation): comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.addr_size, "0" * self.num_wmasks, 0, self.t_current) self.add_noop_all_ports(comment) - # 1. Write all the write ports first to seed a bunch of locations. - for port in self.write_ports: - addr = self.gen_addr() - (word, spare) = self.gen_data() - combined_word = "{}+{}".format(word, spare) - comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current) - self.add_write_one_port(comment, addr, word + spare, "1" * self.num_wmasks, port) - self.stored_words[addr] = word - self.stored_spares[addr[:self.addr_spare_index]] = spare - # All other read-only ports are noops. - for port in self.read_ports: - if port not in self.write_ports: - self.add_noop_one_port(port) - self.cycle_times.append(self.t_current) - self.t_current += self.period - self.check_lengths() + # 1. Write all the write ports 2x to seed a bunch of locations. + for i in range(3): + for port in self.write_ports: + addr = self.gen_addr() + (word, spare) = self.gen_data() + combined_word = self.combine_word(spare, word) + comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current) + self.add_write_one_port(comment, addr, spare + word, "1" * self.num_wmasks, port) + self.stored_words[addr] = word + self.stored_spares[addr[:self.addr_spare_index]] = spare + + # All other read-only ports are noops. + for port in self.read_ports: + if port not in self.write_ports: + self.add_noop_one_port(port) + self.cycle_times.append(self.t_current) + self.t_current += self.period + self.check_lengths() # 2. Read at least once. For multiport, it is important that one # read cycle uses all RW and R port to read from the same # address simultaniously. This will test the viablilty of the # transistor sizing in the bitcell. for port in self.all_ports: - if port in self.write_ports: + if port in self.write_ports and port not in self.read_ports: self.add_noop_one_port(port) else: (addr, word, spare) = self.get_data() - combined_word = "{}+{}".format(word, spare) + combined_word = self.combine_word(spare, word) comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current) self.add_read_one_port(comment, addr, port) - self.add_read_check(word, port) + self.add_read_check(spare + word, port) self.cycle_times.append(self.t_current) self.t_current += self.period self.check_lengths() @@ -197,9 +204,9 @@ class functional(simulation): self.add_noop_one_port(port) else: (word, spare) = self.gen_data() - combined_word = "{}+{}".format(word, spare) + combined_word = self.combine_word(spare, word) comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current) - self.add_write_one_port(comment, addr, word + spare, "1" * self.num_wmasks, port) + self.add_write_one_port(comment, addr, spare + word, "1" * self.num_wmasks, port) self.stored_words[addr] = word self.stored_spares[addr[:self.addr_spare_index]] = spare w_addrs.append(addr) @@ -213,16 +220,16 @@ class functional(simulation): (word, spare) = self.gen_data() wmask = self.gen_wmask() new_word = self.gen_masked_data(old_word, word, wmask) - combined_word = "{}+{}".format(word, spare) + combined_word = self.combine_word(spare, word) comment = self.gen_cycle_comment("partial_write", combined_word, addr, wmask, port, self.t_current) - self.add_write_one_port(comment, addr, word + spare, wmask, port) + self.add_write_one_port(comment, addr, spare + word, wmask, port) self.stored_words[addr] = new_word self.stored_spares[addr[:self.addr_spare_index]] = spare w_addrs.append(addr) else: (addr, word) = random.choice(list(self.stored_words.items())) spare = self.stored_spares[addr[:self.addr_spare_index]] - combined_word = "{}+{}".format(word, spare) + combined_word = self.combine_word(spare, word) # The write driver is not sized sufficiently to drive through the two # bitcell access transistors to the read port. So, for now, we do not allow # a simultaneous write and read to the same address on different ports. This @@ -232,8 +239,7 @@ class functional(simulation): else: comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current) self.add_read_one_port(comment, addr, port) - self.add_read_check(word + spare, port) - + self.add_read_check(spare + word, port) self.cycle_times.append(self.t_current) self.t_current += self.period @@ -258,19 +264,22 @@ class functional(simulation): def add_read_check(self, word, port): """ Add to the check array to ensure a read works. """ - try: - self.check_count - except: - self.check_count = 0 - self.read_check.append([word, "{0}{1}".format(self.dout_name, port), self.t_current + self.period, self.check_count]) - self.check_count += 1 + self.read_check.append([word, + "{0}{1}".format(self.dout_name, port), + self.t_current + self.period, + int(self.t_current/self.period)]) def read_stim_results(self): # Extract dout values from spice timing.lis - for (word, dout_port, eo_period, check_count) in self.read_check: + for (word, dout_port, eo_period, cycle) in self.read_check: sp_read_value = "" for bit in range(self.word_size + self.num_spare_cols): - value = parse_spice_list("timing", "v{0}.{1}ck{2}".format(dout_port.lower(), bit, check_count)) + measure_name = "v{0}_{1}ck{2}".format(dout_port.lower(), bit, cycle) + value = parse_spice_list("timing", measure_name) + # FIXME: Ignore the spare columns for now + if bit >= self.word_size: + value = 0 + try: value = float(value) if value > self.v_high: @@ -291,19 +300,24 @@ class functional(simulation): eo_period) return (0, error) - - self.read_results.append([sp_read_value, dout_port, eo_period, check_count]) + self.read_results.append([sp_read_value, dout_port, eo_period, cycle]) return (1, "SUCCESS") def check_stim_results(self): for i in range(len(self.read_check)): if self.read_check[i][0] != self.read_results[i][0]: - str = "FAILED: {0} read value {1} does not match written value {2} during cycle {3} at time {4}n" - error = str.format(self.read_results[i][1], - self.read_results[i][0], - self.read_check[i][0], - int((self.read_results[i][2] - self.period) / self.period), - self.read_results[i][2]) + output_name = self.read_check[i][1] + cycle = self.read_check[i][3] + read_val = self.format_value(self.read_results[i][0]) + correct_val = self.format_value(self.read_check[i][0]) + check_name = "v{0}_Xck{1}".format(output_name, cycle) + str = "FAILED: {0} read value {1} during cycle {3} at time {4}n ({5}) does not match written value ({2})" + error = str.format(output_name, + read_val, + correct_val, + cycle, + self.read_results[i][2], + check_name) return(0, error) return(1, "SUCCESS") @@ -332,13 +346,18 @@ class functional(simulation): def gen_data(self): """ Generates a random word to write. """ - random_value = random.randint(0, self.max_data) + # Don't use 0 or max value + random_value = random.randint(1, self.max_data - 1) data_bits = binary_repr(random_value, self.word_size) if self.num_spare_cols>0: random_value = random.randint(0, self.max_col_data) spare_bits = binary_repr(random_value, self.num_spare_cols) else: spare_bits = "" + + # FIXME: Set these to 0 for now... + spare_bits = "0" * len(spare_bits) + return data_bits, spare_bits def gen_addr(self): @@ -363,7 +382,7 @@ class functional(simulation): self.stim_sp = "functional_stim.sp" temp_stim = "{0}/{1}".format(self.output_path, self.stim_sp) self.sf = open(temp_stim, "w") - self.sf.write("* Functional test stimulus file for {}ns period\n\n".format(self.period)) + self.sf.write("* Functional test stimulus file for {0}ns period\n\n".format(self.period)) self.stim = stimuli(self.sf, self.corner) # Write include statements @@ -387,16 +406,16 @@ class functional(simulation): # Write important signals to stim file self.sf.write("\n\n* Important signals for debug\n") - self.sf.write("* bl: {}\n".format(self.bl_name.format(port))) - self.sf.write("* br: {}\n".format(self.br_name.format(port))) - self.sf.write("* s_en: {}\n".format(self.sen_name)) - self.sf.write("* q: {}\n".format(self.q_name)) - self.sf.write("* qbar: {}\n".format(self.qbar_name)) + self.sf.write("* bl:\t{0}\n".format(self.bl_name.format(port))) + self.sf.write("* br:\t{0}\n".format(self.br_name.format(port))) + self.sf.write("* s_en:\t{0}\n".format(self.sen_name)) + self.sf.write("* q:\t{0}\n".format(self.q_name)) + self.sf.write("* qbar:\t{0}\n".format(self.qbar_name)) # Write debug comments to stim file self.sf.write("\n\n* Sequence of operations\n") for comment in self.fn_cycle_comments: - self.sf.write("*{}\n".format(comment)) + self.sf.write("*{0}\n".format(comment)) # Generate data input bits self.sf.write("\n* Generation of data and address signals\n") @@ -414,10 +433,10 @@ class functional(simulation): # Generate control signals self.sf.write("\n * Generation of control signals\n") for port in self.all_ports: - self.stim.gen_pwl("CSB{}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05) + self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05) for port in self.readwrite_ports: - self.stim.gen_pwl("WEB{}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05) + self.stim.gen_pwl("WEB{0}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05) # Generate wmask bits for port in self.write_ports: @@ -444,20 +463,21 @@ class functional(simulation): self.stim.gen_pulse(sig_name="{0}{1}".format("clk", port), v1=self.gnd_voltage, v2=self.vdd_voltage, - offset=self.period, + offset=self.period - 0.5 * self.slew, period=self.period, t_rise=self.slew, t_fall=self.slew) # Generate dout value measurements self.sf.write("\n * Generation of dout measurements\n") - for (word, dout_port, eo_period, check) in self.read_check: - t_initial = eo_period - 0.01 * self.period + + for (word, dout_port, eo_period, cycle) in self.read_check: + t_initial = eo_period t_final = eo_period + 0.01 * self.period num_bits = self.word_size + self.num_spare_cols for bit in range(num_bits): - measure_name = "V{0}_{1}ck{2}".format(dout_port, bit, check) signal_name = "{0}_{1}".format(dout_port, bit) + measure_name = "V{0}ck{1}".format(signal_name, cycle) voltage_value = self.stim.get_voltage(word[num_bits - bit - 1]) self.stim.add_comment("* CHECK {0} {1} = {2} time = {3}".format(signal_name, @@ -472,16 +492,14 @@ class functional(simulation): self.stim.write_control(self.cycle_times[-1] + self.period) self.sf.close() - #FIXME: Similar function to delay.py, refactor this + # FIXME: Similar function to delay.py, refactor this def get_bit_name(self): """ Get a bit cell name """ (cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, 0, 0) storage_names = cell_inst.mod.get_storage_net_names() debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" - "supported for characterization. Storage nets={}").format(storage_names)) - q_name = cell_name + '.' + str(storage_names[0]) - qbar_name = cell_name + '.' + str(storage_names[1]) + "supported for characterization. Storage nets={0}").format(storage_names)) + q_name = cell_name + OPTS.hier_seperator + str(storage_names[0]) + qbar_name = cell_name + OPTS.hier_seperator + str(storage_names[1]) return (q_name, qbar_name) - - diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index aa892b3d..6138c479 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -5,7 +5,8 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import os +import os,sys,re +import time import debug import datetime from .setup_hold import * @@ -14,6 +15,7 @@ from .charutils import * import tech import numpy as np from globals import OPTS +from tech import spice class lib: @@ -21,10 +23,20 @@ class lib: def __init__(self, out_dir, sram, sp_file, use_model=OPTS.analytical_delay): + try: + self.vdd_name = spice["power"] + except KeyError: + self.vdd_name = "vdd" + try: + self.gnd_name = spice["ground"] + except KeyError: + self.gnd_name = "gnd" + self.out_dir = out_dir self.sram = sram self.sp_file = sp_file self.use_model = use_model + self.pred_time = None self.set_port_indices() self.prepare_tables() @@ -44,16 +56,32 @@ class lib: def prepare_tables(self): """ Determine the load/slews if they aren't specified in the config file. """ # These are the parameters to determine the table sizes - self.load_scales = np.array(OPTS.load_scales) - self.load = tech.spice["dff_in_cap"] - self.loads = self.load_scales * self.load - debug.info(1, "Loads: {0}".format(self.loads)) + if OPTS.use_specified_load_slew == None: + self.load_scales = np.array(OPTS.load_scales) + self.load = tech.spice["dff_in_cap"] + self.loads = self.load_scales * self.load - self.slew_scales = np.array(OPTS.slew_scales) - self.slew = tech.spice["rise_time"] - self.slews = self.slew_scales * self.slew + + self.slew_scales = np.array(OPTS.slew_scales) + self.slew = tech.spice["rise_time"] + self.slews = self.slew_scales * self.slew + self.load_slews = [] + for slew in self.slews: + for load in self.loads: + self.load_slews.append((load, slew)) + else: + debug.warning("Using the option \"use_specified_load_slew\" will make load slew,data in lib file inaccurate.") + self.load_slews = OPTS.use_specified_load_slew + self.loads = [] + self.slews = [] + for load,slew in self.load_slews: + self.loads.append(load) + self.slews.append(slew) + self.loads = np.array(self.loads) + self.slews = np.array(self.slews) debug.info(1, "Slews: {0}".format(self.slews)) - + debug.info(1, "Loads: {0}".format(self.loads)) + debug.info(1, "self.load_slews : {0}".format(self.load_slews)) def create_corners(self): """ Create corners for characterization. """ # Get the corners from the options file @@ -74,7 +102,7 @@ class lib: self.corners = [] self.lib_files = [] - + if OPTS.use_specified_corners == None: # Nominal corner corner_tuples = set() @@ -86,7 +114,7 @@ class lib: for v in self.supply_voltages: for t in self.temperatures: corner_tuples.add((p, v, t)) - else: + else: nom_corner = (nom_process, nom_supply, nom_temperature) corner_tuples.add(nom_corner) if not OPTS.nominal_corner_only: @@ -104,7 +132,7 @@ class lib: corner_tuples.remove(nom_corner) else: corner_tuples = OPTS.use_specified_corners - + for corner_tuple in corner_tuples: self.add_corner(*corner_tuple) @@ -124,7 +152,9 @@ class lib: def characterize_corners(self): """ Characterize the list of corners. """ debug.info(1,"Characterizing corners: " + str(self.corners)) + is_first_corner = True for (self.corner,lib_name) in zip(self.corners,self.lib_files): + run_start = time.time() debug.info(1,"Corner: " + str(self.corner)) (self.process, self.voltage, self.temperature) = self.corner self.lib = open(lib_name, "w") @@ -132,7 +162,12 @@ class lib: self.corner_name = lib_name.replace(self.out_dir,"").replace(".lib","") self.characterize() self.lib.close() - self.parse_info(self.corner,lib_name) + if self.pred_time == None: + total_time = time.time()-run_start + else: + total_time = self.pred_time + self.parse_info(self.corner,lib_name, is_first_corner, total_time) + is_first_corner = False def characterize(self): """ Characterize the current corner. """ @@ -249,8 +284,8 @@ class lib: self.lib.write(" default_max_fanout : 4.0 ;\n") self.lib.write(" default_connection_class : universal ;\n\n") - self.lib.write(" voltage_map ( VDD, {} );\n".format(self.voltage)) - self.lib.write(" voltage_map ( GND, 0 );\n\n") + self.lib.write(" voltage_map ( {0}, {1} );\n".format(self.vdd_name.upper(), self.voltage)) + self.lib.write(" voltage_map ( {0}, 0 );\n\n".format(self.gnd_name.upper())) def create_list(self,values): """ Helper function to create quoted, line wrapped list """ @@ -331,16 +366,16 @@ class lib: self.lib.write(" base_type : array;\n") self.lib.write(" data_type : bit;\n") self.lib.write(" bit_width : {0};\n".format(self.sram.word_size)) - self.lib.write(" bit_from : 0;\n") - self.lib.write(" bit_to : {0};\n".format(self.sram.word_size - 1)) + self.lib.write(" bit_from : {0};\n".format(self.sram.word_size - 1)) + self.lib.write(" bit_to : 0;\n") self.lib.write(" }\n\n") self.lib.write(" type (addr){\n") self.lib.write(" base_type : array;\n") self.lib.write(" data_type : bit;\n") self.lib.write(" bit_width : {0};\n".format(self.sram.addr_size)) - self.lib.write(" bit_from : 0;\n") - self.lib.write(" bit_to : {0};\n".format(self.sram.addr_size - 1)) + self.lib.write(" bit_from : {0};\n".format(self.sram.addr_size - 1)) + self.lib.write(" bit_to : 0;\n") self.lib.write(" }\n\n") if self.sram.write_size: @@ -348,8 +383,8 @@ class lib: self.lib.write(" base_type : array;\n") self.lib.write(" data_type : bit;\n") self.lib.write(" bit_width : {0};\n".format(self.sram.num_wmasks)) - self.lib.write(" bit_from : 0;\n") - self.lib.write(" bit_to : {0};\n".format(self.sram.num_wmasks - 1)) + self.lib.write(" bit_from : {0};\n".format(self.sram.num_wmasks - 1)) + self.lib.write(" bit_to : 0;\n") self.lib.write(" }\n\n") @@ -582,12 +617,12 @@ class lib: self.lib.write(" }\n") def write_pg_pin(self): - self.lib.write(" pg_pin(vdd) {\n") - self.lib.write(" voltage_name : VDD;\n") + self.lib.write(" pg_pin({0}) ".format(self.vdd_name) + "{\n") + self.lib.write(" voltage_name : {};\n".format(self.vdd_name.upper())) self.lib.write(" pg_type : primary_power;\n") self.lib.write(" }\n\n") - self.lib.write(" pg_pin(gnd) {\n") - self.lib.write(" voltage_name : GND;\n") + self.lib.write(" pg_pin({0}) ".format(self.gnd_name) + "{\n") + self.lib.write(" voltage_name : {};\n".format(self.gnd_name.upper())) self.lib.write(" pg_type : primary_ground;\n") self.lib.write(" }\n\n") @@ -599,11 +634,13 @@ class lib: from .linear_regression import linear_regression as model elif model_name_lc == "elmore": from .elmore import elmore as model + elif model_name_lc == "neural_network": + from .neural_network import neural_network as model else: debug.error("{} model not recognized. See options.py for available models.".format(OPTS.model_name)) m = model(self.sram, self.sp_file, self.corner) - char_results = m.get_lib_values(self.slews,self.loads) + char_results = m.get_lib_values(self.load_slews) else: self.d = delay(self.sram, self.sp_file, self.corner) @@ -612,8 +649,21 @@ class lib: else: probe_address = "0" + "1" * (self.sram.addr_size - 1) probe_data = self.sram.word_size - 1 - char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads) + char_results = self.d.analyze(probe_address, probe_data, self.load_slews) + + + self.char_sram_results, self.char_port_results = char_results + if 'sim_time' in self.char_sram_results: + self.pred_time = self.char_sram_results['sim_time'] + # Add to the OPTS to be written out as part of the extended OPTS file + # FIXME: Temporarily removed from characterization output + # if not self.use_model: + # OPTS.sen_path_delays = self.char_sram_results["sen_path_measures"] + # OPTS.sen_path_names = self.char_sram_results["sen_path_names"] + # OPTS.bl_path_delays = self.char_sram_results["bl_path_measures"] + # OPTS.bl_path_names = self.char_sram_results["bl_path_names"] + def compute_setup_hold(self): """ Do the analysis if we haven't characterized a FF yet """ @@ -621,35 +671,39 @@ class lib: if not hasattr(self,"sh"): self.sh = setup_hold(self.corner) if self.use_model: - self.times = self.sh.analytical_setuphold(self.slews,self.loads) + self.times = self.sh.analytical_setuphold(self.slews,self.slews) else: self.times = self.sh.analyze(self.slews,self.slews) - def parse_info(self,corner,lib_name): + def parse_info(self,corner,lib_name, is_first_corner, time): """ Copies important characterization data to datasheet.info to be added to datasheet """ if OPTS.output_datasheet_info: datasheet_path = OPTS.output_path else: datasheet_path = OPTS.openram_temp - datasheet = open(datasheet_path +'/datasheet.info', 'a+') - + # Open for write and truncate to not conflict with a previous run using the same name + if is_first_corner: + datasheet = open(datasheet_path +'/datasheet.info', 'w') + else: + datasheet = open(datasheet_path +'/datasheet.info', 'a+') + self.write_inp_params_datasheet(datasheet, corner, lib_name) self.write_signal_from_ports(datasheet, - "din{1}[{0}:0]".format(self.sram.word_size - 1, '{}'), - self.write_ports, + "din{1}[{0}:0]".format(self.sram.word_size - 1, '{}'), + self.write_ports, "setup_times_LH", - "setup_times_HL", + "setup_times_HL", "hold_times_LH", "hold_times_HL") - + # self.write_signal_from_ports(datasheet, - # "dout{1}[{0}:0]".format(self.sram.word_size - 1, '{}'), - # self.read_ports, + # "dout{1}[{0}:0]".format(self.sram.word_size - 1, '{}'), + # self.read_ports, # "delay_lh", - # "delay_hl", + # "delay_hl", # "slew_lh", - # "slew_hl") + # "slew_hl") for port in self.all_ports: #dout timing if port in self.read_ports: @@ -666,41 +720,41 @@ class lib: min(list(map(round_time,self.char_port_results[port]["slew_hl"]))), max(list(map(round_time,self.char_port_results[port]["slew_hl"]))) - )) + )) self.write_signal_from_ports(datasheet, - "csb{}", - self.all_ports, + "csb{}", + self.all_ports, "setup_times_LH", - "setup_times_HL", + "setup_times_HL", "hold_times_LH", "hold_times_HL") - - self.write_signal_from_ports(datasheet, - "addr{1}[{0}:0]".format(self.sram.addr_size - 1, '{}'), - self.all_ports, - "setup_times_LH", - "setup_times_HL", - "hold_times_LH", - "hold_times_HL") self.write_signal_from_ports(datasheet, - "web{}", - self.readwrite_ports, + "addr{1}[{0}:0]".format(self.sram.addr_size - 1, '{}'), + self.all_ports, "setup_times_LH", - "setup_times_HL", + "setup_times_HL", "hold_times_LH", - "hold_times_HL") + "hold_times_HL") + + self.write_signal_from_ports(datasheet, + "web{}", + self.readwrite_ports, + "setup_times_LH", + "setup_times_HL", + "hold_times_LH", + "hold_times_HL") self.write_power_datasheet(datasheet) - self.write_model_params(datasheet) - + self.write_model_params(datasheet, time) + datasheet.write("END\n") datasheet.close() def write_inp_params_datasheet(self, datasheet, corner, lib_name): - + if OPTS.is_unit_test: git_id = 'FFFFFFFFFFFFFFFFFFFF' @@ -720,7 +774,7 @@ class lib: debug.warning("Failed to retrieve git id") git_id = 'Failed to retrieve' current_time = datetime.date.today() - + # write static information to be parser later datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12},{13},{14},{15},{16},".format( OPTS.output_name, @@ -748,8 +802,8 @@ class lib: # write area datasheet.write(str(self.sram.width * self.sram.height) + ',') - - def write_signal_from_ports(self, datasheet, signal, ports, time_pos_1, time_pos_2, time_pos_3, time_pos_4): + + def write_signal_from_ports(self, datasheet, signal, ports, time_pos_1, time_pos_2, time_pos_3, time_pos_4): for port in ports: datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( signal.format(port), @@ -766,8 +820,8 @@ class lib: max(list(map(round_time,self.times[time_pos_4]))) )) - - def write_power_datasheet(self, datasheet): + + def write_power_datasheet(self, datasheet): # write power information for port in self.all_ports: name = '' @@ -806,31 +860,30 @@ class lib: control_str += ' & csb{0}'.format(i) datasheet.write("{0},{1},{2},".format('leak', control_str, self.char_sram_results["leakage_power"])) - - def write_model_params(self, datasheet): + + def write_model_params(self, datasheet, time): """Write values which will be used in the analytical model as inputs""" + datasheet.write("{0},{1},".format('sim_time', time)) datasheet.write("{0},{1},".format('words_per_row', OPTS.words_per_row)) datasheet.write("{0},{1},".format('slews', list(self.slews))) datasheet.write("{0},{1},".format('loads', list(self.loads))) - + for port in self.read_ports: datasheet.write("{0},{1},".format('cell_rise_{}'.format(port), self.char_port_results[port]["delay_lh"])) datasheet.write("{0},{1},".format('cell_fall_{}'.format(port), self.char_port_results[port]["delay_hl"])) datasheet.write("{0},{1},".format('rise_transition_{}'.format(port), self.char_port_results[port]["slew_lh"])) datasheet.write("{0},{1},".format('fall_transition_{}'.format(port), self.char_port_results[port]["slew_hl"])) - + for port in self.write_ports: write1_power = np.mean(self.char_port_results[port]["write1_power"]) write0_power = np.mean(self.char_port_results[port]["write0_power"]) datasheet.write("{0},{1},".format('write_rise_power_{}'.format(port), write1_power)) #FIXME: should be write_fall_power - datasheet.write("{0},{1},".format('read_fall_power_{}'.format(port), write0_power)) - + datasheet.write("{0},{1},".format('write_fall_power_{}'.format(port), write0_power)) + for port in self.read_ports: read1_power = np.mean(self.char_port_results[port]["read1_power"]) read0_power = np.mean(self.char_port_results[port]["read0_power"]) datasheet.write("{0},{1},".format('read_rise_power_{}'.format(port), read1_power)) #FIXME: should be read_fall_power - datasheet.write("{0},{1},".format('write_fall_power_{}'.format(port), read0_power)) - - + datasheet.write("{0},{1},".format('read_fall_power_{}'.format(port), read0_power)) diff --git a/compiler/characterizer/linear_regression.py b/compiler/characterizer/linear_regression.py index fac7a170..f12e607a 100644 --- a/compiler/characterizer/linear_regression.py +++ b/compiler/characterizer/linear_regression.py @@ -7,6 +7,7 @@ # from .regression_model import regression_model +from sklearn.linear_model import Ridge from globals import OPTS import debug @@ -18,12 +19,16 @@ class linear_regression(regression_model): def __init__(self, sram, spfile, corner): super().__init__(sram, spfile, corner) + def get_model(self): + return Ridge() + def generate_model(self, features, labels): """ Supervised training of model. """ - model = LinearRegression() + #model = LinearRegression() + model = self.get_model() model.fit(features, labels) return model diff --git a/compiler/characterizer/measurements.py b/compiler/characterizer/measurements.py index b1896880..448dee36 100644 --- a/compiler/characterizer/measurements.py +++ b/compiler/characterizer/measurements.py @@ -53,11 +53,20 @@ class spice_measurement(ABC): elif not self.has_port and port != None: debug.error("Unexpected port input received during measure retrieval.",1) + class delay_measure(spice_measurement): """Generates a spice measurement for the delay of 50%-to-50% points of two signals.""" - def __init__(self, measure_name, trig_name, targ_name, trig_dir_str, targ_dir_str,\ - trig_vdd=0.5, targ_vdd=0.5, measure_scale=None, has_port=True): + def __init__(self, + measure_name, + trig_name, + targ_name, + trig_dir_str, + targ_dir_str, + trig_vdd=0.5, + targ_vdd=0.5, + measure_scale=None, + has_port=True): spice_measurement.__init__(self, measure_name, measure_scale, has_port) self.set_meas_constants(trig_name, targ_name, trig_dir_str, targ_dir_str, trig_vdd, targ_vdd) @@ -73,7 +82,7 @@ class delay_measure(spice_measurement): self.trig_name_no_port = trig_name self.targ_name_no_port = targ_name - #Time delays and ports are variant and needed as inputs when writing the measurement + # Time delays and ports are variant and needed as inputs when writing the measurement def get_measure_values(self, trig_td, targ_td, vdd_voltage, port=None): """Constructs inputs to stimulus measurement function. Variant values are inputs here.""" @@ -82,7 +91,7 @@ class delay_measure(spice_measurement): targ_val = self.targ_val_of_vdd * vdd_voltage if port != None: - #For dictionary indexing reasons, the name is formatted differently than the signals + # For dictionary indexing reasons, the name is formatted differently than the signals meas_name = "{}{}".format(self.name, port) trig_name = self.trig_name_no_port.format(port) targ_name = self.targ_name_no_port.format(port) @@ -90,7 +99,8 @@ class delay_measure(spice_measurement): meas_name = self.name trig_name = self.trig_name_no_port targ_name = self.targ_name_no_port - return (meas_name,trig_name,targ_name,trig_val,targ_val,self.trig_dir_str,self.targ_dir_str,trig_td,targ_td) + return (meas_name, trig_name, targ_name, trig_val, targ_val, self.trig_dir_str, self.targ_dir_str, trig_td, targ_td) + class slew_measure(delay_measure): @@ -114,7 +124,8 @@ class slew_measure(delay_measure): self.trig_name_no_port = signal_name self.targ_name_no_port = signal_name - #Time delays and ports are variant and needed as inputs when writing the measurement + # Time delays and ports are variant and needed as inputs when writing the measurement + class power_measure(spice_measurement): """Generates a spice measurement for the average power between two time points.""" @@ -128,8 +139,8 @@ class power_measure(spice_measurement): def set_meas_constants(self, power_type): """Sets values useful for power simulations. This value is only meta related to the lib file (rise/fall)""" - #Not needed for power simulation - self.power_type = power_type #Expected to be "RISE"/"FALL" + # Not needed for power simulation + self.power_type = power_type # Expected to be "RISE"/"FALL" def get_measure_values(self, t_initial, t_final, port=None): """Constructs inputs to stimulus measurement function. Variant values are inputs here.""" @@ -138,7 +149,8 @@ class power_measure(spice_measurement): meas_name = "{}{}".format(self.name, port) else: meas_name = self.name - return (meas_name,t_initial,t_final) + return (meas_name, t_initial, t_final) + class voltage_when_measure(spice_measurement): """Generates a spice measurement to measure the voltage of a signal based on the voltage of another.""" @@ -161,7 +173,7 @@ class voltage_when_measure(spice_measurement): """Constructs inputs to stimulus measurement function. Variant values are inputs here.""" self.port_error_check(port) if port != None: - #For dictionary indexing reasons, the name is formatted differently than the signals + # For dictionary indexing reasons, the name is formatted differently than the signals meas_name = "{}{}".format(self.name, port) trig_name = self.trig_name_no_port.format(port) targ_name = self.targ_name_no_port.format(port) @@ -169,9 +181,10 @@ class voltage_when_measure(spice_measurement): meas_name = self.name trig_name = self.trig_name_no_port targ_name = self.targ_name_no_port - trig_voltage = self.trig_val_of_vdd*vdd_voltage - return (meas_name,trig_name,targ_name,trig_voltage,self.trig_dir_str,trig_td) + trig_voltage = self.trig_val_of_vdd * vdd_voltage + return (meas_name, trig_name, targ_name, trig_voltage, self.trig_dir_str, trig_td) + class voltage_at_measure(spice_measurement): """Generates a spice measurement to measure the voltage at a specific time. The time is considered variant with different periods.""" @@ -191,11 +204,11 @@ class voltage_at_measure(spice_measurement): """Constructs inputs to stimulus measurement function. Variant values are inputs here.""" self.port_error_check(port) if port != None: - #For dictionary indexing reasons, the name is formatted differently than the signals + # For dictionary indexing reasons, the name is formatted differently than the signals meas_name = "{}{}".format(self.name, port) targ_name = self.targ_name_no_port.format(port) else: meas_name = self.name targ_name = self.targ_name_no_port - return (meas_name,targ_name,time_at) + return (meas_name, targ_name, time_at) diff --git a/compiler/characterizer/model_check.py b/compiler/characterizer/model_check.py index f72c3211..fcbc51c2 100644 --- a/compiler/characterizer/model_check.py +++ b/compiler/characterizer/model_check.py @@ -5,18 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import sys,re,shutil import debug import tech -import math from .stimuli import * from .trim_spice import * from .charutils import * -import utils from globals import OPTS from .delay import delay from .measurements import * + class model_check(delay): """Functions to test for the worst case delay in a target SRAM @@ -39,43 +37,44 @@ class model_check(delay): self.power_name = "total_power" def create_measurement_names(self, port): - """Create measurement names. The names themselves currently define the type of measurement""" - #Create delay measurement names - wl_en_driver_delay_names = ["delay_wl_en_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_en_driver_stages())] - wl_driver_delay_names = ["delay_wl_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_driver_stages())] - sen_driver_delay_names = ["delay_sen_dvr_{}".format(stage) for stage in range(1,self.get_num_sen_driver_stages())] + """ + Create measurement names. The names themselves currently define the type of measurement + """ + wl_en_driver_delay_names = ["delay_wl_en_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_en_driver_stages())] + wl_driver_delay_names = ["delay_wl_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_driver_stages())] + sen_driver_delay_names = ["delay_sen_dvr_{0}".format(stage) for stage in range(1, self.get_num_sen_driver_stages())] if self.custom_delaychain: - dc_delay_names = ['delay_dc_out_final'] + dc_delay_names = ["delay_dc_out_final"] else: - dc_delay_names = ["delay_delay_chain_stage_{}".format(stage) for stage in range(1,self.get_num_delay_stages()+1)] - self.wl_delay_meas_names = wl_en_driver_delay_names+["delay_wl_en", "delay_wl_bar"]+wl_driver_delay_names+["delay_wl"] + dc_delay_names = ["delay_delay_chain_stage_{0}".format(stage) for stage in range(1, self.get_num_delay_stages() + 1)] + self.wl_delay_meas_names = wl_en_driver_delay_names + ["delay_wl_en", "delay_wl_bar"] + wl_driver_delay_names + ["delay_wl"] if port not in self.sram.readonly_ports: - self.rbl_delay_meas_names = ["delay_gated_clk_nand", "delay_delay_chain_in"]+dc_delay_names + self.rbl_delay_meas_names = ["delay_gated_clk_nand", "delay_delay_chain_in"] + dc_delay_names else: - self.rbl_delay_meas_names = ["delay_gated_clk_nand"]+dc_delay_names - self.sae_delay_meas_names = ["delay_pre_sen"]+sen_driver_delay_names+["delay_sen"] + self.rbl_delay_meas_names = ["delay_gated_clk_nand"] + dc_delay_names + self.sae_delay_meas_names = ["delay_pre_sen"] + sen_driver_delay_names + ["delay_sen"] # if self.custom_delaychain: - # self.delay_chain_indices = (len(self.rbl_delay_meas_names), len(self.rbl_delay_meas_names)+1) + # self.delay_chain_indices = (len(self.rbl_delay_meas_names), len(self.rbl_delay_meas_names)+1) # else: - self.delay_chain_indices = (len(self.rbl_delay_meas_names)-len(dc_delay_names), len(self.rbl_delay_meas_names)) - #Create slew measurement names - wl_en_driver_slew_names = ["slew_wl_en_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_en_driver_stages())] - wl_driver_slew_names = ["slew_wl_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_driver_stages())] - sen_driver_slew_names = ["slew_sen_dvr_{}".format(stage) for stage in range(1,self.get_num_sen_driver_stages())] + self.delay_chain_indices = (len(self.rbl_delay_meas_names) - len(dc_delay_names), len(self.rbl_delay_meas_names)) + # Create slew measurement names + wl_en_driver_slew_names = ["slew_wl_en_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_en_driver_stages())] + wl_driver_slew_names = ["slew_wl_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_driver_stages())] + sen_driver_slew_names = ["slew_sen_dvr_{0}".format(stage) for stage in range(1, self.get_num_sen_driver_stages())] if self.custom_delaychain: - dc_slew_names = ['slew_dc_out_final'] + dc_slew_names = ["slew_dc_out_final"] else: - dc_slew_names = ["slew_delay_chain_stage_{}".format(stage) for stage in range(1,self.get_num_delay_stages()+1)] - self.wl_slew_meas_names = ["slew_wl_gated_clk_bar"]+wl_en_driver_slew_names+["slew_wl_en", "slew_wl_bar"]+wl_driver_slew_names+["slew_wl"] + dc_slew_names = ["slew_delay_chain_stage_{0}".format(stage) for stage in range(1, self.get_num_delay_stages() + 1)] + self.wl_slew_meas_names = ["slew_wl_gated_clk_bar"] + wl_en_driver_slew_names + ["slew_wl_en", "slew_wl_bar"] + wl_driver_slew_names + ["slew_wl"] if port not in self.sram.readonly_ports: - self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar","slew_gated_clk_nand", "slew_delay_chain_in"]+dc_slew_names + self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar", "slew_gated_clk_nand", "slew_delay_chain_in"] + dc_slew_names else: - self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar"]+dc_slew_names - self.sae_slew_meas_names = ["slew_replica_bl0", "slew_pre_sen"]+sen_driver_slew_names+["slew_sen"] + self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar"] + dc_slew_names + self.sae_slew_meas_names = ["slew_replica_bl0", "slew_pre_sen"] + sen_driver_slew_names + ["slew_sen"] self.bitline_meas_names = ["delay_wl_to_bl", "delay_bl_to_dout"] - self.power_meas_names = ['read0_power'] + self.power_meas_names = ["read0_power"] def create_signal_names(self, port): """Creates list of the signal names used in the spice file along the wl and sen paths. @@ -83,40 +82,45 @@ class model_check(delay): replicated here. """ delay.create_signal_names(self) - #Signal names are all hardcoded, need to update to make it work for probe address and different configurations. - wl_en_driver_signals = ["Xsram.Xcontrol{}.Xbuf_wl_en.Zb{}_int".format('{}', stage) for stage in range(1,self.get_num_wl_en_driver_stages())] - wl_driver_signals = ["Xsram.Xbank0.Xwordline_driver{}.Xwl_driver_inv{}.Zb{}_int".format('{}', self.wordline_row, stage) for stage in range(1,self.get_num_wl_driver_stages())] - sen_driver_signals = ["Xsram.Xcontrol{}.Xbuf_s_en.Zb{}_int".format('{}',stage) for stage in range(1,self.get_num_sen_driver_stages())] + + # Signal names are all hardcoded, need to update to make it work for probe address and different configurations. + wl_en_driver_signals = ["Xsram{1}Xcontrol{{}}.Xbuf_wl_en.Zb{0}_int".format(stage, OPTS.hier_seperator) for stage in range(1, self.get_num_wl_en_driver_stages())] + wl_driver_signals = ["Xsram{2}Xbank0{2}Xwordline_driver{{}}{2}Xwl_driver_inv{0}{2}Zb{1}_int".format(self.wordline_row, stage, OPTS.hier_seperator) for stage in range(1, self.get_num_wl_driver_stages())] + sen_driver_signals = ["Xsram{1}Xcontrol{{}}{1}Xbuf_s_en{1}Zb{0}_int".format(stage, OPTS.hier_seperator) for stage in range(1, self.get_num_sen_driver_stages())] if self.custom_delaychain: delay_chain_signal_names = [] else: - delay_chain_signal_names = ["Xsram.Xcontrol{}.Xreplica_bitline.Xdelay_chain.dout_{}".format('{}', stage) for stage in range(1,self.get_num_delay_stages())] + delay_chain_signal_names = ["Xsram{1}Xcontrol{{}}{1}Xreplica_bitline{1}Xdelay_chain{1}dout_{0}".format(stage, OPTS.hier_seperator) for stage in range(1, self.get_num_delay_stages())] if len(self.sram.all_ports) > 1: port_format = '{}' else: port_format = '' - self.wl_signal_names = ["Xsram.Xcontrol{}.gated_clk_bar".format('{}')]+\ - wl_en_driver_signals+\ - ["Xsram.wl_en{}".format('{}'), "Xsram.Xbank0.Xwordline_driver{}.wl_bar_{}".format('{}',self.wordline_row)]+\ - wl_driver_signals+\ - ["Xsram.Xbank0.wl{}_{}".format(port_format, self.wordline_row)] - pre_delay_chain_names = ["Xsram.Xcontrol{}.gated_clk_bar".format('{}')] + self.wl_signal_names = ["Xsram{0}Xcontrol{{}}{0}gated_clk_bar".format(OPTS.hier_seperator)] + \ + wl_en_driver_signals + \ + ["Xsram{0}wl_en{{}}".format(OPTS.hier_seperator), + "Xsram{1}Xbank0{1}Xwordline_driver{{}}{1}wl_bar_{0}".format(self.wordline_row, + OPTS.hier_seperator)] + \ + wl_driver_signals + \ + ["Xsram{2}Xbank0{2}wl{0}_{1}".format(port_format, + self.wordline_row, + OPTS.hier_seperator)] + pre_delay_chain_names = ["Xsram.Xcontrol{{}}{0}gated_clk_bar".format(OPTS.hier_seperator)] if port not in self.sram.readonly_ports: - pre_delay_chain_names+= ["Xsram.Xcontrol{}.Xand2_rbl_in.zb_int".format('{}'), "Xsram.Xcontrol{}.rbl_in".format('{}')] + pre_delay_chain_names+= ["Xsram{0}Xcontrol{{}}{0}Xand2_rbl_in{0}zb_int".format(OPTS.hier_seperator), + "Xsram{0}Xcontrol{{}}{0}rbl_in".format(OPTS.hier_seperator)] - self.rbl_en_signal_names = pre_delay_chain_names+\ - delay_chain_signal_names+\ - ["Xsram.Xcontrol{}.Xreplica_bitline.delayed_en".format('{}')] + self.rbl_en_signal_names = pre_delay_chain_names + \ + delay_chain_signal_names + \ + ["Xsram{0}Xcontrol{{}}{0}Xreplica_bitline{0}delayed_en".format(OPTS.hier_seperator)] + self.sae_signal_names = ["Xsram{0}Xcontrol{{}}{0}Xreplica_bitline{0}bl0_0".format(OPTS.hier_seperator), + "Xsram{0}Xcontrol{{}}{0}pre_s_en".format(OPTS.hier_seperator)] + \ + sen_driver_signals + \ + ["Xsram{0}s_en{{}}".format(OPTS.hier_seperator)] - self.sae_signal_names = ["Xsram.Xcontrol{}.Xreplica_bitline.bl0_0".format('{}'), "Xsram.Xcontrol{}.pre_s_en".format('{}')]+\ - sen_driver_signals+\ - ["Xsram.s_en{}".format('{}')] - - dout_name = "{0}{1}_{2}".format(self.dout_name,"{}",self.probe_data) #Empty values are the port and probe data bit - self.bl_signal_names = ["Xsram.Xbank0.wl{}_{}".format(port_format, self.wordline_row),\ - "Xsram.Xbank0.bl{}_{}".format(port_format, self.bitline_column),\ - dout_name] + self.bl_signal_names = ["Xsram{2}Xbank0{2}wl{0}_{1}".format(port_format, self.wordline_row, OPTS.hier_seperator), + "Xsram{2}Xbank0{2}bl{0}_{1}".format(port_format, self.bitline_column, OPTS.hier_seperator), + "{0}{{}}_{1}".format(self.dout_name, self.probe_data)] # Empty values are the port and probe data bit def create_measurement_objects(self): """Create the measurements used for read and write ports""" @@ -124,7 +128,7 @@ class model_check(delay): self.create_sae_meas_objs() self.create_bl_meas_objs() self.create_power_meas_objs() - self.all_measures = self.wl_meas_objs+self.sae_meas_objs+self.bl_meas_objs+self.power_meas_objs + self.all_measures = self.wl_meas_objs + self.sae_meas_objs + self.bl_meas_objs + self.power_meas_objs def create_power_meas_objs(self): """Create power measurement object. Only one.""" @@ -138,14 +142,14 @@ class model_check(delay): targ_dir = "FALL" for i in range(1, len(self.wl_signal_names)): - self.wl_meas_objs.append(delay_measure(self.wl_delay_meas_names[i-1], - self.wl_signal_names[i-1], + self.wl_meas_objs.append(delay_measure(self.wl_delay_meas_names[i - 1], + self.wl_signal_names[i - 1], self.wl_signal_names[i], trig_dir, targ_dir, measure_scale=1e9)) - self.wl_meas_objs.append(slew_measure(self.wl_slew_meas_names[i-1], - self.wl_signal_names[i-1], + self.wl_meas_objs.append(slew_measure(self.wl_slew_meas_names[i - 1], + self.wl_signal_names[i - 1], trig_dir, measure_scale=1e9)) temp_dir = trig_dir @@ -155,9 +159,9 @@ class model_check(delay): def create_bl_meas_objs(self): """Create the measurements to measure the bitline to dout, static stages""" - #Bitline has slightly different measurements, objects appends hardcoded. + # Bitline has slightly different measurements, objects appends hardcoded. self.bl_meas_objs = [] - trig_dir, targ_dir = "RISE", "FALL" #Only check read 0 + trig_dir, targ_dir = "RISE", "FALL" # Only check read 0 self.bl_meas_objs.append(delay_measure(self.bitline_meas_names[0], self.bl_signal_names[0], self.bl_signal_names[-1], @@ -171,22 +175,22 @@ class model_check(delay): self.sae_meas_objs = [] trig_dir = "RISE" targ_dir = "FALL" - #Add measurements from gated_clk_bar to RBL + # Add measurements from gated_clk_bar to RBL for i in range(1, len(self.rbl_en_signal_names)): - self.sae_meas_objs.append(delay_measure(self.rbl_delay_meas_names[i-1], - self.rbl_en_signal_names[i-1], + self.sae_meas_objs.append(delay_measure(self.rbl_delay_meas_names[i - 1], + self.rbl_en_signal_names[i - 1], self.rbl_en_signal_names[i], trig_dir, targ_dir, measure_scale=1e9)) - self.sae_meas_objs.append(slew_measure(self.rbl_slew_meas_names[i-1], - self.rbl_en_signal_names[i-1], + self.sae_meas_objs.append(slew_measure(self.rbl_slew_meas_names[i - 1], + self.rbl_en_signal_names[i - 1], trig_dir, measure_scale=1e9)) temp_dir = trig_dir trig_dir = targ_dir targ_dir = temp_dir - if self.custom_delaychain: #Hack for custom delay chains + if self.custom_delaychain: # Hack for custom delay chains self.sae_meas_objs[-2] = delay_measure(self.rbl_delay_meas_names[-1], self.rbl_en_signal_names[-2], self.rbl_en_signal_names[-1], @@ -198,18 +202,18 @@ class model_check(delay): trig_dir, measure_scale=1e9)) - #Add measurements from rbl_out to sae. Trigger directions do not invert from previous stage due to RBL. + # Add measurements from rbl_out to sae. Trigger directions do not invert from previous stage due to RBL. trig_dir = "FALL" targ_dir = "RISE" for i in range(1, len(self.sae_signal_names)): - self.sae_meas_objs.append(delay_measure(self.sae_delay_meas_names[i-1], - self.sae_signal_names[i-1], + self.sae_meas_objs.append(delay_measure(self.sae_delay_meas_names[i - 1], + self.sae_signal_names[i - 1], self.sae_signal_names[i], trig_dir, targ_dir, measure_scale=1e9)) - self.sae_meas_objs.append(slew_measure(self.sae_slew_meas_names[i-1], - self.sae_signal_names[i-1], + self.sae_meas_objs.append(slew_measure(self.sae_slew_meas_names[i - 1], + self.sae_signal_names[i - 1], trig_dir, measure_scale=1e9)) temp_dir = trig_dir @@ -231,16 +235,16 @@ class model_check(delay): self.sf.write("* {}\n".format(comment)) for read_port in self.targ_read_ports: - self.write_measures_read_port(read_port) + self.write_measures_read_port(read_port) def get_delay_measure_variants(self, port, measure_obj): """Get the measurement values that can either vary from simulation to simulation (vdd, address) or port to port (time delays)""" - #Return value is intended to match the delay measure format: trig_td, targ_td, vdd, port - #Assuming only read 0 for now - debug.info(3,"Power measurement={}".format(measure_obj)) + # Return value is intended to match the delay measure format: trig_td, targ_td, vdd, port + # Assuming only read 0 for now + debug.info(3, "Power measurement={}".format(measure_obj)) if (type(measure_obj) is delay_measure or type(measure_obj) is slew_measure): - meas_cycle_delay = self.cycle_times[self.measure_cycles[port]["read0"]] + self.period/2 + meas_cycle_delay = self.cycle_times[self.measure_cycles[port]["read0"]] + self.period / 2 return (meas_cycle_delay, meas_cycle_delay, self.vdd_voltage, port) elif type(measure_obj) is power_measure: return self.get_power_measure_variants(port, measure_obj, "read") @@ -249,9 +253,9 @@ class model_check(delay): def get_power_measure_variants(self, port, power_obj, operation): """Get the measurement values that can either vary port to port (time delays)""" - #Return value is intended to match the power measure format: t_initial, t_final, port + # Return value is intended to match the power measure format: t_initial, t_final, port t_initial = self.cycle_times[self.measure_cycles[port]["read0"]] - t_final = self.cycle_times[self.measure_cycles[port]["read0"]+1] + t_final = self.cycle_times[self.measure_cycles[port]["read0"] + 1] return (t_initial, t_final, port) @@ -280,8 +284,8 @@ class model_check(delay): elif type(measure)is power_measure: power_meas_list.append(measure_value) else: - debug.error("Measurement object not recognized.",1) - return delay_meas_list, slew_meas_list,power_meas_list + debug.error("Measurement object not recognized.", 1) + return delay_meas_list, slew_meas_list, power_meas_list def run_delay_simulation(self): """ @@ -290,7 +294,7 @@ class model_check(delay): works on the trimmed netlist by default, so powers do not include leakage of all cells. """ - #Sanity Check + # Sanity Check debug.check(self.period > 0, "Target simulation period non-positive") wl_delay_result = [[] for i in self.all_ports] @@ -303,16 +307,16 @@ class model_check(delay): # Checking from not data_value to data_value self.write_delay_stimulus() - self.stim.run_sim() #running sim prodoces spice output file. + self.stim.run_sim() # running sim prodoces spice output file. - #Retrieve the results from the output file + # Retrieve the results from the output file for port in self.targ_read_ports: - #Parse and check the voltage measurements - wl_delay_result[port], wl_slew_result[port],_ = self.get_measurement_values(self.wl_meas_objs, port) - sae_delay_result[port], sae_slew_result[port],_ = self.get_measurement_values(self.sae_meas_objs, port) - bl_delay_result[port], bl_slew_result[port],_ = self.get_measurement_values(self.bl_meas_objs, port) - _,__,power_result[port] = self.get_measurement_values(self.power_meas_objs, port) - return (True,wl_delay_result, sae_delay_result, wl_slew_result, sae_slew_result, bl_delay_result, bl_slew_result, power_result) + # Parse and check the voltage measurements + wl_delay_result[port], wl_slew_result[port], _ = self.get_measurement_values(self.wl_meas_objs, port) + sae_delay_result[port], sae_slew_result[port], _ = self.get_measurement_values(self.sae_meas_objs, port) + bl_delay_result[port], bl_slew_result[port], _ = self.get_measurement_values(self.bl_meas_objs, port) + _, __, power_result[port] = self.get_measurement_values(self.power_meas_objs, port) + return (True, wl_delay_result, sae_delay_result, wl_slew_result, sae_slew_result, bl_delay_result, bl_slew_result, power_result) def get_model_delays(self, port): """Get model delays based on port. Currently assumes single RW port.""" @@ -345,41 +349,41 @@ class model_check(delay): def scale_delays(self, delay_list): """Takes in a list of measured delays and convert it to simple units to easily compare to model values.""" converted_values = [] - #Calculate average + # Calculate average total = 0 for meas_value in delay_list: total+=meas_value - average = total/len(delay_list) + average = total / len(delay_list) - #Convert values + # Convert values for meas_value in delay_list: - converted_values.append(meas_value/average) + converted_values.append(meas_value / average) return converted_values def min_max_normalization(self, value_list): """Re-scales input values on a range from 0-1 where min(list)=0, max(list)=1""" scaled_values = [] min_max_diff = max(value_list) - min(value_list) - average = sum(value_list)/len(value_list) + average = sum(value_list) / len(value_list) for value in value_list: - scaled_values.append((value-average)/(min_max_diff)) + scaled_values.append((value - average) / (min_max_diff)) return scaled_values def calculate_error_l2_norm(self, list_a, list_b): """Calculates error between two lists using the l2 norm""" error_list = [] for val_a, val_b in zip(list_a, list_b): - error_list.append((val_a-val_b)**2) + error_list.append((val_a - val_b)**2) return error_list def compare_measured_and_model(self, measured_vals, model_vals): """First scales both inputs into similar ranges and then compares the error between both.""" scaled_meas = self.min_max_normalization(measured_vals) - debug.info(1, "Scaled measurements:\n{}".format(scaled_meas)) + debug.info(1, "Scaled measurements:\n{0}".format(scaled_meas)) scaled_model = self.min_max_normalization(model_vals) - debug.info(1, "Scaled model:\n{}".format(scaled_model)) + debug.info(1, "Scaled model:\n{0}".format(scaled_model)) errors = self.calculate_error_l2_norm(scaled_meas, scaled_model) - debug.info(1, "Errors:\n{}\n".format(errors)) + debug.info(1, "Errors:\n{0}\n".format(errors)) def analyze(self, probe_address, probe_data, slews, loads, port): """Measures entire delay path along the wordline and sense amp enable and compare it to the model delays.""" @@ -391,19 +395,19 @@ class model_check(delay): self.create_measurement_objects() data_dict = {} - read_port = self.read_ports[0] #only test the first read port + read_port = self.read_ports[0] # only test the first read port read_port = port self.targ_read_ports = [read_port] self.targ_write_ports = [self.write_ports[0]] - debug.info(1,"Model test: corner {}".format(self.corner)) + debug.info(1, "Model test: corner {0}".format(self.corner)) (success, wl_delays, sae_delays, wl_slews, sae_slews, bl_delays, bl_slews, powers)=self.run_delay_simulation() - debug.check(success, "Model measurements Failed: period={}".format(self.period)) + debug.check(success, "Model measurements Failed: period={0}".format(self.period)) - debug.info(1,"Measured Wordline delays (ns):\n\t {}".format(wl_delays[read_port])) - debug.info(1,"Measured Wordline slews:\n\t {}".format(wl_slews[read_port])) - debug.info(1,"Measured SAE delays (ns):\n\t {}".format(sae_delays[read_port])) - debug.info(1,"Measured SAE slews:\n\t {}".format(sae_slews[read_port])) - debug.info(1,"Measured Bitline delays (ns):\n\t {}".format(bl_delays[read_port])) + debug.info(1, "Measured Wordline delays (ns):\n\t {0}".format(wl_delays[read_port])) + debug.info(1, "Measured Wordline slews:\n\t {0}".format(wl_slews[read_port])) + debug.info(1, "Measured SAE delays (ns):\n\t {0}".format(sae_delays[read_port])) + debug.info(1, "Measured SAE slews:\n\t {0}".format(sae_slews[read_port])) + debug.info(1, "Measured Bitline delays (ns):\n\t {0}".format(bl_delays[read_port])) data_dict[self.wl_meas_name] = wl_delays[read_port] data_dict[self.sae_meas_name] = sae_delays[read_port] @@ -412,14 +416,14 @@ class model_check(delay): data_dict[self.bl_meas_name] = bl_delays[read_port] data_dict[self.power_name] = powers[read_port] - if OPTS.auto_delay_chain_sizing: #Model is not used in this case + if OPTS.auto_delay_chain_sizing: # Model is not used in this case wl_model_delays, sae_model_delays = self.get_model_delays(read_port) - debug.info(1,"Wordline model delays:\n\t {}".format(wl_model_delays)) - debug.info(1,"SAE model delays:\n\t {}".format(sae_model_delays)) + debug.info(1, "Wordline model delays:\n\t {0}".format(wl_model_delays)) + debug.info(1, "SAE model delays:\n\t {0}".format(sae_model_delays)) data_dict[self.wl_model_name] = wl_model_delays data_dict[self.sae_model_name] = sae_model_delays - #Some evaluations of the model and measured values + # Some evaluations of the model and measured values # debug.info(1, "Comparing wordline measurements and model.") # self.compare_measured_and_model(wl_delays[read_port], wl_model_delays) # debug.info(1, "Comparing SAE measurements and model") @@ -430,17 +434,17 @@ class model_check(delay): def get_all_signal_names(self): """Returns all signals names as a dict indexed by hardcoded names. Useful for writing the head of the CSV.""" name_dict = {} - #Signal names are more descriptive than the measurement names, first value trimmed to match size of measurements names. + # Signal names are more descriptive than the measurement names, first value trimmed to match size of measurements names. name_dict[self.wl_meas_name] = self.wl_signal_names[1:] - name_dict[self.sae_meas_name] = self.rbl_en_signal_names[1:]+self.sae_signal_names[1:] + name_dict[self.sae_meas_name] = self.rbl_en_signal_names[1:] + self.sae_signal_names[1:] name_dict[self.wl_slew_name] = self.wl_slew_meas_names - name_dict[self.sae_slew_name] = self.rbl_slew_meas_names+self.sae_slew_meas_names + name_dict[self.sae_slew_name] = self.rbl_slew_meas_names + self.sae_slew_meas_names name_dict[self.bl_meas_name] = self.bitline_meas_names[0:1] name_dict[self.power_name] = self.power_meas_names - #name_dict[self.wl_slew_name] = self.wl_slew_meas_names + # pname_dict[self.wl_slew_name] = self.wl_slew_meas_names if OPTS.auto_delay_chain_sizing: - name_dict[self.wl_model_name] = name_dict["wl_measures"] #model uses same names as measured. + name_dict[self.wl_model_name] = name_dict["wl_measures"] # model uses same names as measured. name_dict[self.sae_model_name] = name_dict["sae_measures"] return name_dict diff --git a/compiler/characterizer/neural_network.py b/compiler/characterizer/neural_network.py index 57db4580..6f1aa7c1 100644 --- a/compiler/characterizer/neural_network.py +++ b/compiler/characterizer/neural_network.py @@ -9,10 +9,7 @@ from .regression_model import regression_model from globals import OPTS import debug - -from tensorflow import keras -from tensorflow.keras import layers -import tensorflow as tf +from sklearn.neural_network import MLPRegressor class neural_network(regression_model): @@ -20,21 +17,19 @@ class neural_network(regression_model): def __init__(self, sram, spfile, corner): super().__init__(sram, spfile, corner) + def get_model(self): + return MLPRegressor(solver='lbfgs', alpha=1e-5, + hidden_layer_sizes=(40, 40, 40, 40), random_state=1) + def generate_model(self, features, labels): """ - Supervised training of model. + Training multilayer model """ - model = keras.Sequential([ - layers.Dense(32, activation=tf.nn.relu, input_shape=[features.shape[1]]), - layers.Dense(32, activation=tf.nn.relu), - layers.Dense(32, activation=tf.nn.relu), - layers.Dense(1) - ]) - - optimizer = keras.optimizers.RMSprop(0.0099) - model.compile(loss='mean_squared_error', optimizer=optimizer) - model.fit(features, labels, epochs=100, verbose=0) + flat_labels = np.ravel(labels) + model = self.get_model() + model.fit(features, flat_labels) + return model def model_prediction(self, model, features): @@ -44,5 +39,6 @@ class neural_network(regression_model): """ pred = model.predict(features) - return pred + reshape_pred = np.reshape(pred, (len(pred),1)) + return reshape_pred \ No newline at end of file diff --git a/compiler/characterizer/regression_model.py b/compiler/characterizer/regression_model.py index d9c2359d..69f00485 100644 --- a/compiler/characterizer/regression_model.py +++ b/compiler/characterizer/regression_model.py @@ -13,7 +13,8 @@ import debug import math -relative_data_path = "/sim_data" +relative_data_path = "sim_data" +data_file = "sim_data.csv" data_fnames = ["rise_delay.csv", "fall_delay.csv", "rise_slew.csv", @@ -22,7 +23,8 @@ data_fnames = ["rise_delay.csv", "write0_power.csv", "read1_power.csv", "read0_power.csv", - "leakage_data.csv"] + "leakage_data.csv", + "sim_time.csv"] # Positions must correspond to data_fname list lib_dnames = ["delay_lh", "delay_hl", @@ -32,14 +34,15 @@ lib_dnames = ["delay_lh", "write0_power", "read1_power", "read0_power", - "leakage_power"] + "leakage_power", + "sim_time"] # Check if another data dir was specified if OPTS.sim_data_path == None: data_dir = OPTS.openram_tech+relative_data_path else: data_dir = OPTS.sim_data_path -data_paths = {dname:data_dir +'/'+fname for dname, fname in zip(lib_dnames, data_fnames)} +data_path = data_dir + '/' + data_file class regression_model(simulation): @@ -47,21 +50,25 @@ class regression_model(simulation): super().__init__(sram, spfile, corner) self.set_corner(corner) - def get_lib_values(self, slews, loads): + def get_lib_values(self, load_slews): """ A model and prediction is created for each output needed for the LIB """ - debug.info(1, "Characterizing SRAM using linear regression models.") + debug.info(1, "Characterizing SRAM using regression models.") log_num_words = math.log(OPTS.num_words, 2) model_inputs = [log_num_words, OPTS.word_size, - OPTS.words_per_row, - self.sram.width * self.sram.height, + OPTS.words_per_row, + OPTS.local_array_size, process_transform[self.process], self.vdd_voltage, self.temperature] - + # Area removed for now + # self.sram.width * self.sram.height, + # Include above inputs, plus load and slew which are added below + self.num_inputs = len(model_inputs)+2 + self.create_measurement_names() models = self.train_models() @@ -69,36 +76,35 @@ class regression_model(simulation): port_data = self.get_empty_measure_data_dict() debug.info(1, 'Slew, Load, Port, Delay(ns), Slew(ns)') max_delay = 0.0 - for slew in slews: - for load in loads: - # List returned with value order being delay, power, leakage, slew - sram_vals = self.get_predictions(model_inputs+[slew, load], models) - # Delay is only calculated on a single port and replicated for now. - for port in self.all_ports: - port_data[port]['delay_lh'].append(sram_vals['delay_lh']) - port_data[port]['delay_hl'].append(sram_vals['delay_hl']) - port_data[port]['slew_lh'].append(sram_vals['slew_lh']) - port_data[port]['slew_hl'].append(sram_vals['slew_hl']) + for load, slew in load_slews: + # List returned with value order being delay, power, leakage, slew + sram_vals = self.get_predictions(model_inputs+[slew, load], models) + # Delay is only calculated on a single port and replicated for now. + for port in self.all_ports: + port_data[port]['delay_lh'].append(sram_vals['rise_delay']) + port_data[port]['delay_hl'].append(sram_vals['fall_delay']) + port_data[port]['slew_lh'].append(sram_vals['rise_slew']) + port_data[port]['slew_hl'].append(sram_vals['fall_slew']) + + port_data[port]['write1_power'].append(sram_vals['write1_power']) + port_data[port]['write0_power'].append(sram_vals['write0_power']) + port_data[port]['read1_power'].append(sram_vals['read1_power']) + port_data[port]['read0_power'].append(sram_vals['read0_power']) + + # Disabled power not modeled. Copied from other power predictions + port_data[port]['disabled_write1_power'].append(sram_vals['write1_power']) + port_data[port]['disabled_write0_power'].append(sram_vals['write0_power']) + port_data[port]['disabled_read1_power'].append(sram_vals['read1_power']) + port_data[port]['disabled_read0_power'].append(sram_vals['read0_power']) - port_data[port]['write1_power'].append(sram_vals['write1_power']) - port_data[port]['write0_power'].append(sram_vals['write0_power']) - port_data[port]['read1_power'].append(sram_vals['read1_power']) - port_data[port]['read0_power'].append(sram_vals['read0_power']) - - # Disabled power not modeled. Copied from other power predictions - port_data[port]['disabled_write1_power'].append(sram_vals['write1_power']) - port_data[port]['disabled_write0_power'].append(sram_vals['write0_power']) - port_data[port]['disabled_read1_power'].append(sram_vals['read1_power']) - port_data[port]['disabled_read0_power'].append(sram_vals['read0_power']) - - debug.info(1, '{}, {}, {}, {}, {}'.format(slew, - load, - port, - sram_vals['delay_lh'], - sram_vals['slew_lh'])) + debug.info(1, '{}, {}, {}, {}, {}'.format(slew, + load, + port, + sram_vals['rise_delay'], + sram_vals['rise_slew'])) # Estimate the period as double the delay with margin period_margin = 0.1 - sram_data = {"min_period": sram_vals['delay_lh'] * 2, + sram_data = {"min_period": sram_vals['rise_delay'] * 2, "leakage_power": sram_vals["leakage_power"]} debug.info(2, "SRAM Data:\n{}".format(sram_data)) @@ -111,30 +117,92 @@ class regression_model(simulation): Generate a model and prediction for LIB output """ - #Scaled the inputs using first data file as a reference - data_name = lib_dnames[0] - scaled_inputs = np.asarray([scale_input_datapoint(model_inputs, data_paths[data_name])]) + #Scaled the inputs using first data file as a reference + scaled_inputs = np.asarray([scale_input_datapoint(model_inputs, data_path)]) predictions = {} - for dname in data_paths.keys(): - path = data_paths[dname] + out_pos = 0 + for dname in self.output_names: m = models[dname] - features, labels = get_scaled_data(path) scaled_pred = self.model_prediction(m, scaled_inputs) - pred = unscale_data(scaled_pred.tolist(), path) + pred = unscale_data(scaled_pred.tolist(), data_path, pos=self.num_inputs+out_pos) debug.info(2,"Unscaled Prediction = {}".format(pred)) - predictions[dname] = pred[0][0] + predictions[dname] = pred[0] + out_pos+=1 return predictions def train_models(self): """ Generate and return models """ + self.output_names = get_data_names(data_path)[self.num_inputs:] + data = get_scaled_data(data_path) + features, labels = data[:, :self.num_inputs], data[:,self.num_inputs:] + + output_num = 0 models = {} - for dname, dpath in data_paths.items(): - features, labels = get_scaled_data(dpath) - model = self.generate_model(features, labels) - models[dname] = model + for o_name in self.output_names: + output_label = labels[:,output_num] + model = self.generate_model(features, output_label) + models[o_name] = model + output_num+=1 + return models + + def score_model(self): + num_inputs = 9 #FIXME - should be defined somewhere else + self.output_names = get_data_names(data_path)[num_inputs:] + data = get_scaled_data(data_path) + features, labels = data[:, :num_inputs], data[:,num_inputs:] + + output_num = 0 + models = {} + debug.info(1, "Output name, score") + for o_name in self.output_names: + output_label = labels[:,output_num] + model = self.generate_model(features, output_label) + scr = model.score(features, output_label) + debug.info(1, "{}, {}".format(o_name, scr)) + output_num+=1 + + + def cross_validation(self, test_only=None): + """Wrapper for sklean cross validation function for OpenRAM regression models. + Returns the mean accuracy for each model/output.""" + + from sklearn.model_selection import cross_val_score + untrained_model = self.get_model() + + num_inputs = 9 #FIXME - should be defined somewhere else + self.output_names = get_data_names(data_path)[num_inputs:] + data = get_scaled_data(data_path) + features, labels = data[:, :num_inputs], data[:,num_inputs:] + + output_num = 0 + models = {} + debug.info(1, "Output name, mean_accuracy, std_dev") + model_scores = {} + if test_only != None: + test_outputs = test_only + else: + test_outputs = self.output_names + for o_name in test_outputs: + output_label = labels[:,output_num] + scores = cross_val_score(untrained_model, features, output_label, cv=10) + debug.info(1, "{}, {}, {}".format(o_name, scores.mean(), scores.std())) + model_scores[o_name] = scores.mean() + output_num+=1 + + return model_scores + + # Fixme - only will work for sklearn regression models + def save_model(self, model_name, model): + try: + OPTS.model_dict + except AttributeError: + OPTS.model_dict = {} + OPTS.model_dict[model_name+"_coef"] = list(model.coef_[0]) + debug.info(1,"Coefs of {}:{}".format(model_name,OPTS.model_dict[model_name+"_coef"])) + OPTS.model_dict[model_name+"_intercept"] = float(model.intercept_) \ No newline at end of file diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index b323078a..72e973d5 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -76,10 +76,10 @@ class setup_hold(): self.stim.write_supply() def write_data(self, mode, target_time, correct_value): - """Create the data signals for setup/hold analysis. First period is to + """ + Create the data signals for setup/hold analysis. First period is to initialize it to the opposite polarity. Second period is used for characterization. - """ self.sf.write("\n* Generation of the data and clk signals\n") if correct_value == 1: @@ -106,8 +106,11 @@ class setup_hold(): setup=0) def write_clock(self): - """ Create the clock signal for setup/hold analysis. First period initializes the FF - while the second is used for characterization.""" + """ + Create the clock signal for setup/hold analysis. + First period initializes the FF + while the second is used for characterization. + """ self.stim.gen_pwl(sig_name="clk", # initial clk edge is right after the 0 time to initialize a flop @@ -128,16 +131,6 @@ class setup_hold(): else: dout_rise_or_fall = "FALL" - # in SETUP mode, the input mirrors what the output should be - if mode == "SETUP": - din_rise_or_fall = dout_rise_or_fall - else: - # in HOLD mode, however, the input should be opposite of the output - if correct_value == 1: - din_rise_or_fall = "FALL" - else: - din_rise_or_fall = "RISE" - self.sf.write("\n* Measure statements for pass/fail verification\n") trig_name = "clk" targ_name = "Q" @@ -153,19 +146,6 @@ class setup_hold(): trig_td=1.9 * self.period, targ_td=1.9 * self.period) - targ_name = "D" - # Start triggers right after initialize value is returned to normal - # at one period - self.stim.gen_meas_delay(meas_name="setup_hold_time", - trig_name=trig_name, - targ_name=targ_name, - trig_val=trig_val, - targ_val=targ_val, - trig_dir="RISE", - targ_dir=din_rise_or_fall, - trig_td=1.2 * self.period, - targ_td=1.2 * self.period) - def bidir_search(self, correct_value, mode): """ This will perform a bidirectional search for either setup or hold times. It starts with the feasible priod and looks a half period beyond or before it @@ -189,26 +169,28 @@ class setup_hold(): correct_value=correct_value) self.stim.run_sim(self.stim_sp) ideal_clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay")) - setuphold_time = convert_to_float(parse_spice_list("timing", "setup_hold_time")) - debug.info(2,"*** {0} CHECK: {1} Ideal Clk-to-Q: {2} Setup/Hold: {3}".format(mode, correct_value,ideal_clk_to_q,setuphold_time)) + # We use a 1/2 speed clock for some reason... + setuphold_time = (feasible_bound - 2 * self.period) + if mode == "SETUP": # SETUP is clk-din, not din-clk + passing_setuphold_time = -1 * setuphold_time + else: + passing_setuphold_time = setuphold_time + debug.info(2, "*** {0} CHECK: {1} Ideal Clk-to-Q: {2} Setup/Hold: {3}".format(mode, + correct_value, + ideal_clk_to_q, + setuphold_time)) - if type(ideal_clk_to_q)!=float or type(setuphold_time)!=float: - debug.error("Initial hold time fails for data value feasible bound {0} Clk-to-Q {1} Setup/Hold {2}".format(feasible_bound, - ideal_clk_to_q, - setuphold_time), + if type(ideal_clk_to_q)!=float: + debug.error("Initial hold time fails for data value feasible " + "bound {0} Clk-to-Q {1} Setup/Hold {2}".format(feasible_bound, + ideal_clk_to_q, + setuphold_time), 2) - if mode == "SETUP": # SETUP is clk-din, not din-clk - setuphold_time *= -1e9 - else: - setuphold_time *= 1e9 - - passing_setuphold_time = setuphold_time debug.info(2, "Checked initial {0} time {1}, data at {2}, clock at {3} ".format(mode, setuphold_time, feasible_bound, 2 * self.period)) - #raw_input("Press Enter to continue...") while True: target_time = (feasible_bound + infeasible_bound) / 2 @@ -224,15 +206,14 @@ class setup_hold(): self.stim.run_sim(self.stim_sp) clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay")) - setuphold_time = convert_to_float(parse_spice_list("timing", "setup_hold_time")) - if type(clk_to_q) == float and (clk_to_q < 1.1 * ideal_clk_to_q) and type(setuphold_time)==float: - if mode == "SETUP": # SETUP is clk-din, not din-clk - setuphold_time *= -1e9 - else: - setuphold_time *= 1e9 - - debug.info(2, "PASS Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time)) + # We use a 1/2 speed clock for some reason... + setuphold_time = (target_time - 2 * self.period) + if mode == "SETUP": # SETUP is clk-din, not din-clk + passing_setuphold_time = -1 * setuphold_time + else: passing_setuphold_time = setuphold_time + if type(clk_to_q) == float and (clk_to_q < 1.1 * ideal_clk_to_q): + debug.info(2, "PASS Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time)) feasible_bound = target_time else: debug.info(2, "FAIL Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time)) @@ -242,7 +223,6 @@ class setup_hold(): debug.info(3, "CONVERGE {0} vs {1}".format(feasible_bound, infeasible_bound)) break - debug.info(2, "Converged on {0} time {1}.".format(mode, passing_setuphold_time)) return passing_setuphold_time diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 5becbacf..98729bba 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -37,6 +37,8 @@ class simulation(): self.read_ports = self.sram.read_ports self.write_ports = self.sram.write_ports self.words_per_row = self.sram.words_per_row + self.num_rows = self.sram.num_rows + self.num_cols = self.sram.num_cols if self.write_size: self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: @@ -294,7 +296,8 @@ class simulation(): self.add_data(data, port) self.add_address(address, port) self.add_wmask(wmask, port) - self.add_spare_wen("1" * self.num_spare_cols, port) + # Disable spare writes for now + self.add_spare_wen("0" * self.num_spare_cols, port) def add_read_one_port(self, comment, address, port): """ Add the control values for a read cycle. Does not increment the period. """ @@ -369,6 +372,38 @@ class simulation(): time_spacing, comment)) + def combine_word(self, spare, word): + if len(spare) > 0: + return spare + "+" + word + + return word + + def format_value(self, value): + """ Format in better readable manner """ + + def delineate(word): + # Create list of chars in reverse order + split_word = list(reversed([x for x in word])) + # Add underscore every 4th char + split_word2 = [x + '_' * (n != 0 and n % 4 == 0) for n, x in enumerate(split_word)] + # Join the word unreversed back together + new_word = ''.join(reversed(split_word2)) + return(new_word) + + # Split extra cols + if self.num_spare_cols > 0: + vals = value[self.num_spare_cols:] + spare_vals = value[:self.num_spare_cols] + else: + vals = value + spare_vals = "" + + # Insert underscores + vals = delineate(vals) + spare_vals = delineate(spare_vals) + + return self.combine_word(spare_vals, vals) + def gen_cycle_comment(self, op, word, addr, wmask, port, t_current): if op == "noop": str = "\tIdle during cycle {0} ({1}ns - {2}ns)" @@ -473,7 +508,6 @@ class simulation(): if not OPTS.use_pex or (OPTS.use_pex and OPTS.pex_exe[0] == "calibre"): self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) - sen_with_port = self.get_sen_name(self.graph.all_paths) if sen_with_port.endswith(str(port)): self.sen_name = sen_with_port[:-len(str(port))] @@ -481,38 +515,32 @@ class simulation(): self.sen_name = sen_with_port debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.") - debug.info(2, "s_en name = {}".format(self.sen_name)) - column_addr = self.get_column_addr() bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port) port_pos = -1 - len(str(column_addr)) - len(str(port)) - if bl_name_port.endswith(str(port) + "_" + str(column_addr)): - self.bl_name = bl_name_port[:port_pos] + "{}" + bl_name_port[port_pos + len(str(port)):] - elif not bl_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0 + if bl_name_port.endswith(str(port) + "_" + str(self.bitline_column)): # single port SRAM case, bl will not be numbered eg bl_0 self.bl_name = bl_name_port else: self.bl_name = bl_name_port debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.") - if br_name_port.endswith(str(port) + "_" + str(column_addr)): - self.br_name = br_name_port[:port_pos] + "{}" + br_name_port[port_pos + len(str(port)):] - elif not br_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0 + if br_name_port.endswith(str(port) + "_" + str(self.bitline_column)): # single port SRAM case, bl will not be numbered eg bl_0 self.br_name = br_name_port else: self.br_name = br_name_port debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.") - debug.info(2, "bl name={}, br name={}".format(self.bl_name, self.br_name)) else: self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) self.sen_name = self.get_sen_name(self.graph.all_paths) - debug.info(2, "s_en name = {}".format(self.sen_name)) + #debug.info(2, "s_en {}".format(self.sen_name)) self.bl_name = "bl{0}_{1}".format(port, OPTS.word_size - 1) self.br_name = "br{0}_{1}".format(port, OPTS.word_size - 1) - debug.info(2, "bl name={}, br name={}".format(self.bl_name, self.br_name)) + # debug.info(2, "bl name={0}".format(self.bl_name)) + # debug.info(2, "br name={0}".format(self.br_name)) def get_sen_name(self, paths, assumed_port=None): """ @@ -535,8 +563,13 @@ class simulation(): Creates timing graph to generate the timing paths for the SRAM output. """ + #Make exclusions dependent on the bit being tested. self.sram.clear_exclude_bits() # Removes previous bit exclusions self.sram.graph_exclude_bits(self.wordline_row, self.bitline_column) + port=self.read_ports[0] #FIXME, port_data requires a port specification, assuming single port for now + if self.words_per_row > 1: + self.sram.graph_clear_column_mux(port) + self.sram.graph_exclude_column_mux(self.bitline_column, port) # Generate new graph every analysis as edges might change depending on test bit self.graph = graph_util.timing_graph() @@ -576,7 +609,11 @@ class simulation(): """ Gets the signal name associated with the bitlines in the bank. """ - cell_mod = factory.create(module_type=OPTS.bitcell) + # FIXME: change to a solution that does not depend on the technology + if OPTS.tech_name == "sky130" and len(self.all_ports) == 1: + cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1") + else: + cell_mod = factory.create(module_type=OPTS.bitcell) cell_bl = cell_mod.get_bl_name(port) cell_br = cell_mod.get_br_name(port) @@ -586,16 +623,16 @@ class simulation(): bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) if OPTS.use_pex and OPTS.pex_exe[0] != "calibre": for i in range(len(bl_names)): - bl_names[i] = bl_names[i].split('.')[-1] + bl_names[i] = bl_names[i].split(OPTS.hier_seperator)[-1] return bl_names[0], bl_names[1] - + def get_empty_measure_data_dict(self): """Make a dict of lists for each type of delay and power measurement to append results to""" measure_names = self.delay_meas_names + self.power_meas_names # Create list of dicts. List lengths is # of ports. Each dict maps the measurement names to lists. measure_data = [{mname: [] for mname in measure_names} for i in self.all_ports] - return measure_data + return measure_data def sum_delays(self, delays): """Adds the delays (delay_data objects) so the correct slew is maintained""" @@ -604,5 +641,3 @@ class simulation(): for i in range(1, len(delays)): delay+=delays[i] return delay - - diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index d60cab85..b9e4b3c7 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -146,7 +146,7 @@ class stimuli(): edge. The first clk_time should be 0 and is the initial time that corresponds to the initial value. """ - # the initial value is not a clock time + str = "Clock and data value lengths don't match. {0} clock values, {1} data values for {2}" debug.check(len(clk_times)==len(data_values), str.format(len(clk_times), @@ -169,7 +169,7 @@ class stimuli(): def gen_constant(self, sig_name, v_val): """ Generates a constant signal with reference voltage and the voltage value """ self.sf.write("V{0} {0} 0 DC {1}\n".format(sig_name, v_val)) - + def get_voltage(self, value): if value == "0" or value == 0: return 0 @@ -181,7 +181,7 @@ class stimuli(): def gen_meas_delay(self, meas_name, trig_name, targ_name, trig_val, targ_val, trig_dir, targ_dir, trig_td, targ_td): """ Creates the .meas statement for the measurement of delay """ measure_string=".meas tran {0} TRIG v({1}) VAL={2} {3}=1 TD={4}n TARG v({5}) VAL={6} {7}=1 TD={8}n\n\n" - self.sf.write(measure_string.format(meas_name, + self.sf.write(measure_string.format(meas_name.lower(), trig_name, trig_val, trig_dir, @@ -194,7 +194,7 @@ class stimuli(): def gen_meas_find_voltage(self, meas_name, trig_name, targ_name, trig_val, trig_dir, trig_td): """ Creates the .meas statement for the measurement of delay """ measure_string=".meas tran {0} FIND v({1}) WHEN v({2})={3}v {4}=1 TD={5}n \n\n" - self.sf.write(measure_string.format(meas_name, + self.sf.write(measure_string.format(meas_name.lower(), targ_name, trig_name, trig_val, @@ -204,7 +204,7 @@ class stimuli(): def gen_meas_find_voltage_at_time(self, meas_name, targ_name, time_at): """ Creates the .meas statement for voltage at time""" measure_string=".meas tran {0} FIND v({1}) AT={2}n \n\n" - self.sf.write(measure_string.format(meas_name, + self.sf.write(measure_string.format(meas_name.lower(), targ_name, time_at)) @@ -215,13 +215,14 @@ class stimuli(): power_exp = "power" else: power_exp = "par('(-1*v(" + str(self.vdd_name) + ")*I(v" + str(self.vdd_name) + "))')" - self.sf.write(".meas tran {0} avg {1} from={2}n to={3}n\n\n".format(meas_name, + self.sf.write(".meas tran {0} avg {1} from={2}n to={3}n\n\n".format(meas_name.lower(), power_exp, t_initial, t_final)) def gen_meas_value(self, meas_name, dout, t_initial, t_final): - measure_string=".meas tran {0} AVG v({1}) FROM={2}n TO={3}n\n\n".format(meas_name, dout, t_initial, t_final) + measure_string=".meas tran {0} FIND v({1}) AT={2}n\n\n".format(meas_name.lower(), dout, (t_initial + t_final) / 2) + #measure_string=".meas tran {0} AVG v({1}) FROM={2}n TO={3}n\n\n".format(meas_name.lower(), dout, t_initial, t_final) self.sf.write(measure_string) def write_control(self, end_time, runlvl=4): @@ -236,18 +237,20 @@ class stimuli(): reltol = 0.005 # 0.5% else: reltol = 0.001 # 0.1% - timestep = 10 # ps, was 5ps but ngspice was complaining the timestep was too small in certain tests. + timestep = 10 # ps - self.sf.write(".TEMP {}\n".format(self.temperature)) if OPTS.spice_name == "ngspice": + self.sf.write(".TEMP {}\n".format(self.temperature)) # UIC is needed for ngspice to converge - self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) + # Format: .tran tstep tstop < tstart < tmax >> + self.sf.write(".TRAN {0}p {1}n 0n {0}p UIC\n".format(timestep, end_time)) # ngspice sometimes has convergence problems if not using gear method # which is more accurate, but slower than the default trapezoid method # Do not remove this or it may not converge due to some "pa_00" nodes # unless you figure out what these are. self.sf.write(".OPTIONS POST=1 RELTOL={0} PROBE method=gear ACCT\n".format(reltol)) elif OPTS.spice_name == "spectre": + self.sf.write(".TEMP {}\n".format(self.temperature)) self.sf.write("simulator lang=spectre\n") if OPTS.use_pex: nestlvl = 1 @@ -255,8 +258,7 @@ class stimuli(): else: nestlvl = 10 spectre_save = "lvlpub" - self.sf.write('saveOptions options save={} nestlvl={} pwr=total \n'.format( - spectre_save, nestlvl)) + self.sf.write('saveOptions options save={} nestlvl={} pwr=total \n'.format(spectre_save, nestlvl)) self.sf.write("simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp={0} try_fast_op=no " "rforce=10m maxnotes=10 maxwarns=10 " " preservenode=all topcheck=fixall " @@ -265,12 +267,22 @@ class stimuli(): self.sf.write('tran tran step={} stop={}n ic=node write=spectre.dc errpreset=moderate ' ' annotate=status maxiters=5 \n'.format("5p", end_time)) self.sf.write("simulator lang=spice\n") - else: - self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) + elif OPTS.spice_name in ["hspice", "xa"]: + self.sf.write(".TEMP {}\n".format(self.temperature)) + # Format: .tran tstep tstop < tstart < tmax >> + self.sf.write(".TRAN {0}p {1}n 0n {0}p UIC\n".format(timestep, end_time)) self.sf.write(".OPTIONS POST=1 RUNLVL={0} PROBE\n".format(runlvl)) - if OPTS.spice_name == "hspice": # for cadence plots - self.sf.write(".OPTIONS PSF=1 \n") - self.sf.write(".OPTIONS HIER_DELIM=1 \n") + self.sf.write(".OPTIONS PSF=1 \n") + self.sf.write(".OPTIONS HIER_DELIM=1 \n") + elif OPTS.spice_name in ["Xyce", "xyce"]: + self.sf.write(".OPTIONS DEVICE TEMP={}\n".format(self.temperature)) + self.sf.write(".OPTIONS MEASURE MEASFAIL=1\n") + self.sf.write(".OPTIONS LINSOL type=klu\n") + self.sf.write(".OPTIONS TIMEINT RELTOL=1e-6 ABSTOL=1e-10 method=gear minorder=2\n") + # Format: .TRAN + self.sf.write(".TRAN {0}p {1}n 0n {0}p\n".format(timestep, end_time)) + elif OPTS.spice_name: + debug.error("Unkown spice simulator {}".format(OPTS.spice_name), -1) # create plots for all signals if not OPTS.use_pex: # Don't save all for extracted simulations @@ -278,7 +290,7 @@ class stimuli(): if OPTS.verbose_level>0: if OPTS.spice_name in ["hspice", "xa"]: self.sf.write(".probe V(*)\n") - else: + elif OPTS.spice_name != "Xyce": self.sf.write(".plot V(*)\n") else: self.sf.write("*.probe V(*)\n") @@ -292,19 +304,27 @@ class stimuli(): self.sf.write("* {} process corner\n".format(self.process)) for item in self.device_libraries: + if OPTS.spice_name: + item[0] = item[0].replace("SIMULATOR", OPTS.spice_name.lower()) + else: + item[0] = item[0].replace("SIMULATOR", "ngspice") if os.path.isfile(item[0]): self.sf.write(".lib \"{0}\" {1}\n".format(item[0], item[1])) else: - debug.error("Could not find spice library: {0}\nSet SPICE_MODEL_DIR to over-ride path.\n".format(item[0])) + debug.error("Could not find spice library: {0}\nSet SPICE_MODEL_DIR to over-ride path.\n".format(item[0]), -1) includes = self.device_models + [circuit] for item in list(includes): + if OPTS.spice_name: + item = item.replace("SIMULATOR", OPTS.spice_name.lower()) + else: + item = item.replace("SIMULATOR", "ngspice") self.sf.write(".include \"{0}\"\n".format(item)) def add_comment(self, msg): self.sf.write(msg + "\n") - + def write_supply(self): """ Writes supply voltage statements """ gnd_node_name = "0" @@ -312,7 +332,10 @@ class stimuli(): # Adding a commented out supply for simulators where gnd and 0 are not global grounds. self.sf.write("\n*Nodes gnd and 0 are the same global ground node in ngspice/hspice/xa. Otherwise, this source may be needed.\n") - self.sf.write("*V{0} {0} {1} {2}\n".format(self.gnd_name, gnd_node_name, 0.0)) + if OPTS.spice_name in ["Xyce", "xyce"]: + self.sf.write("V{0} {0} {1} {2}\n".format(self.gnd_name, gnd_node_name, 0.0)) + else: + self.sf.write("*V{0} {0} {1} {2}\n".format(self.gnd_name, gnd_node_name, 0.0)) def run_sim(self, name): """ Run hspice in batch mode and output rawfile to parse. """ @@ -349,6 +372,20 @@ class stimuli(): temp_stim, OPTS.openram_temp) valid_retcode=0 + elif OPTS.spice_name in ["Xyce", "xyce"]: + if OPTS.num_sim_threads > 1 and OPTS.mpi_name: + mpi_cmd = "{0} -np {1}".format(OPTS.mpi_exe, + OPTS.num_sim_threads) + else: + mpi_cmd = "" + + # Xyce can save a raw file while doing timing, so keep it around + cmd = "{0} {1} -r {3}timing.raw -o {3}timing.lis {2}".format(mpi_cmd, + OPTS.spice_exe, + temp_stim, + OPTS.openram_temp) + + valid_retcode=0 else: # ngspice 27+ supports threading with "set num_threads=4" in the stimulus file or a .spiceinit # Measurements can't be made with a raw file set in ngspice @@ -368,7 +405,7 @@ class stimuli(): spice_stdout = open("{0}spice_stdout.log".format(OPTS.openram_temp), 'w') spice_stderr = open("{0}spice_stderr.log".format(OPTS.openram_temp), 'w') - debug.info(3, cmd) + debug.info(2, cmd) retcode = subprocess.call(cmd, stdout=spice_stdout, stderr=spice_stderr, shell=True) spice_stdout.close() @@ -380,5 +417,3 @@ class stimuli(): end_time = datetime.datetime.now() delta_time = round((end_time - start_time).total_seconds(), 1) debug.info(2, "*** Spice: {} seconds".format(delta_time)) - - diff --git a/compiler/custom/nand2_dec.py b/compiler/custom/nand2_dec.py index 98992f42..893bb34f 100644 --- a/compiler/custom/nand2_dec.py +++ b/compiler/custom/nand2_dec.py @@ -70,3 +70,7 @@ class nand2_dec(design.design): """ self.add_graph_edges(graph, port_nets) + def is_non_inverting(self): + """Return input to output polarity for module""" + + return False diff --git a/compiler/custom/nand3_dec.py b/compiler/custom/nand3_dec.py index 34890a9c..a887e38f 100644 --- a/compiler/custom/nand3_dec.py +++ b/compiler/custom/nand3_dec.py @@ -70,3 +70,7 @@ class nand3_dec(design.design): """ self.add_graph_edges(graph, port_nets) + def is_non_inverting(self): + """Return input to output polarity for module""" + + return False diff --git a/compiler/custom/nand4_dec.py b/compiler/custom/nand4_dec.py index d89dc926..d3b6491d 100644 --- a/compiler/custom/nand4_dec.py +++ b/compiler/custom/nand4_dec.py @@ -70,3 +70,7 @@ class nand4_dec(design.design): """ self.add_graph_edges(graph, port_nets) + def is_non_inverting(self): + """Return input to output polarity for module""" + + return False diff --git a/compiler/example_configs/example_config_scn4m_subm.py b/compiler/example_configs/example_config_scn4m_subm.py index d331c1fc..8fc92169 100644 --- a/compiler/example_configs/example_config_scn4m_subm.py +++ b/compiler/example_configs/example_config_scn4m_subm.py @@ -11,7 +11,7 @@ process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] -route_supplies = True +route_supplies = "side" check_lvsdrc = True output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, diff --git a/compiler/example_configs/sky130_sram_1kbyte_1r1w_8x1024_8.py b/compiler/example_configs/sky130_sram_1kbyte_1r1w_8x1024_8.py new file mode 100644 index 00000000..6462032e --- /dev/null +++ b/compiler/example_configs/sky130_sram_1kbyte_1r1w_8x1024_8.py @@ -0,0 +1,20 @@ +""" +Pseudo-dual port (independent read and write ports), 8bit word, 1 kbyte SRAM. + +Useful as a byte FIFO between two devices (the reader and the writer). +""" +word_size = 8 # Bits +num_words = 1024 +human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8) + +# Allow byte writes +#write_size = 8 # Bits + +# Dual port +num_rw_ports = 0 +num_r_ports = 1 +num_w_ports = 1 +ports_human = '1r1w' + +import os +exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read()) diff --git a/compiler/example_configs/sky130_sram_1kbyte_1rw1r_32x256_8.py b/compiler/example_configs/sky130_sram_1kbyte_1rw1r_32x256_8.py new file mode 100644 index 00000000..51d64589 --- /dev/null +++ b/compiler/example_configs/sky130_sram_1kbyte_1rw1r_32x256_8.py @@ -0,0 +1,21 @@ +""" +Dual port (1 read/write + 1 read only) 1 kbytes SRAM with byte write. + +FIXME: What is this useful for? +FIXME: Why would you want byte write on this? +""" +word_size = 32 # Bits +num_words = 256 +human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8) + +# Allow byte writes +write_size = 8 # Bits + +# Dual port +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 +ports_human = '1rw1r' + +import os +exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read()) diff --git a/compiler/example_configs/sky130_sram_1kbyte_1rw1r_8x1024_8.py b/compiler/example_configs/sky130_sram_1kbyte_1rw1r_8x1024_8.py new file mode 100644 index 00000000..ef62221c --- /dev/null +++ b/compiler/example_configs/sky130_sram_1kbyte_1rw1r_8x1024_8.py @@ -0,0 +1,21 @@ +""" +Dual port (1 read/write + 1 read only) 1 kbytes SRAM with byte write. + +FIXME: What is this useful for? +FIXME: Why would you want byte write on this? +""" +word_size = 8 # Bits +num_words = 1024 +human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8) + +# Allow byte writes +write_size = 8 # Bits + +# Dual port +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 +ports_human = '1rw1r' + +import os +exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read()) diff --git a/compiler/example_configs/sky130_sram_1kbyte_1rw_32x256_8.py b/compiler/example_configs/sky130_sram_1kbyte_1rw_32x256_8.py new file mode 100644 index 00000000..955d3959 --- /dev/null +++ b/compiler/example_configs/sky130_sram_1kbyte_1rw_32x256_8.py @@ -0,0 +1,19 @@ +""" +Single port, 1 kbytes SRAM, with byte write, useful for RISC-V processor main +memory. +""" +word_size = 32 # Bits +num_words = 256 +human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8) + +# Allow byte writes +write_size = 8 # Bits + +# Single port +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 +ports_human = '1rw' + +import os +exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read()) diff --git a/compiler/example_configs/sky130_sram_2kbyte_1rw1r_32x512_8.py b/compiler/example_configs/sky130_sram_2kbyte_1rw1r_32x512_8.py new file mode 100644 index 00000000..0492902a --- /dev/null +++ b/compiler/example_configs/sky130_sram_2kbyte_1rw1r_32x512_8.py @@ -0,0 +1,21 @@ +""" +Dual port (1 read/write + 1 read only), 2 kbytes SRAM (with byte write). + +FIXME: What is this useful for? +FIXME: Why would you want byte write on this? +""" +word_size = 32 # Bits +num_words = 512 +human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8) + +# Allow byte writes +write_size = 8 # Bits + +# Dual port +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 +ports_human = '1rw1r' + +import os +exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read()) diff --git a/compiler/example_configs/sky130_sram_2kbyte_1rw_32x512_8.py b/compiler/example_configs/sky130_sram_2kbyte_1rw_32x512_8.py new file mode 100644 index 00000000..7f64d18c --- /dev/null +++ b/compiler/example_configs/sky130_sram_2kbyte_1rw_32x512_8.py @@ -0,0 +1,19 @@ +""" +Single port, 2 kbytes SRAM, with byte write, useful for RISC-V processor main +memory. +""" +word_size = 32 # Bits +num_words = 512 +human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8) + +# Allow byte writes +write_size = 8 # Bits + +# Single port +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 +ports_human = '1rw' + +import os +exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read()) diff --git a/compiler/example_configs/sky130_sram_4kbyte_1rw1r_32x1024_8.py b/compiler/example_configs/sky130_sram_4kbyte_1rw1r_32x1024_8.py new file mode 100644 index 00000000..8d2f40e0 --- /dev/null +++ b/compiler/example_configs/sky130_sram_4kbyte_1rw1r_32x1024_8.py @@ -0,0 +1,22 @@ +""" +Dual port (1 read/write + 1 read only), 4 kbytes SRAM (with byte write). + +FIXME: What is this useful for? +FIXME: Why would you want byte write on this? +""" + +word_size = 32 # Bits +num_words = 1024 +human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8) + +# Allow byte writes +write_size = 8 # Bits + +# Dual port +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 +ports_human = '1rw1r' + +import os +exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read()) diff --git a/compiler/example_configs/sky130_sram_4kbyte_1rw_32x1024_8.py b/compiler/example_configs/sky130_sram_4kbyte_1rw_32x1024_8.py new file mode 100644 index 00000000..571ca030 --- /dev/null +++ b/compiler/example_configs/sky130_sram_4kbyte_1rw_32x1024_8.py @@ -0,0 +1,20 @@ +""" +Single port, 4 kbytes SRAM, with byte write, useful for RISC-V processor main +memory. +""" + +word_size = 32 # Bits +num_words = 1024 +human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8) + +# Allow byte writes +write_size = 8 # Bits + +# Single port +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 +ports_human = '1rw' + +import os +exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read()) diff --git a/compiler/example_configs/sky130_sram_common.py b/compiler/example_configs/sky130_sram_common.py new file mode 100644 index 00000000..445c88cc --- /dev/null +++ b/compiler/example_configs/sky130_sram_common.py @@ -0,0 +1,21 @@ +# Include with +# import os +# exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read()) + + +tech_name = "sky130" +nominal_corner_only = True + +# Local wordlines have issues with met3 power routing for now +#local_array_size = 16 + +route_supplies = "ring" +#route_supplies = "left" +check_lvsdrc = True +uniquify = True +#perimeter_pins = False +#netlist_only = True +#analytical_delay = False + +output_name = "{tech_name}_sram_{human_byte_size}_{ports_human}_{word_size}x{num_words}_{write_size}".format(**locals()) +output_path = "macro/{output_name}".format(**locals()) diff --git a/compiler/gdsMill/gdsMill/gds2reader.py b/compiler/gdsMill/gdsMill/gds2reader.py index 448355a8..94f59d3d 100644 --- a/compiler/gdsMill/gdsMill/gds2reader.py +++ b/compiler/gdsMill/gdsMill/gds2reader.py @@ -79,7 +79,7 @@ class Gds2reader: recordLength = struct.unpack(">h",recordLengthAscii) #gives us a tuple with a short int inside offset_int = int(recordLength[0]) # extract length offset += offset_int # count offset - if(self.debugToTerminal==1): + if(self.debugToTerminal==1): print("Offset: " + str(offset)) #print out the record numbers for de-bugging record = self.fileHandle.read(recordLength[0]-2) #read the rest of it (first 2 bytes were already read) return record @@ -669,11 +669,11 @@ class Gds2reader: else: print("There was an error parsing the GDS header. Aborting...") - def loadFromFile(self, fileName): + def loadFromFile(self, fileName, special_purposes={}): self.fileHandle = open(fileName,"rb") self.readGds2() self.fileHandle.close() - self.layoutObject.initialize() + self.layoutObject.initialize(special_purposes) ############################################## diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index bd9968dc..466f4be6 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -81,6 +81,42 @@ class VlsiLayout: coordinatesRotate.extend((newX,newY)) return coordinatesRotate + def uniquify(self, prefix_name=None): + new_structures = {} + if self.rootStructureName[-1] == "\x00": + prefix = self.rootStructureName[0:-1] + "_" + else: + prefix = self.rootStructureName + "_" + for name in self.structures: + if name[-1] == "\x00": + base_name = name[0:-1] + else: + base_name = name + # Don't do library cells + if prefix_name and base_name.startswith(prefix_name): + new_name = name + elif name != self.rootStructureName: + new_name = self.padText(prefix + base_name) + else: + new_name = name + #print("Structure: {0} -> {1}".format(base_name, new_name)) + + new_structures[new_name] = self.structures[name] + new_structures[new_name].name = new_name + for sref in new_structures[new_name].srefs: + if sref.sName[-1] == "\x00": + base_sref_name = sref.sName[0:-1] + else: + base_sref_name = sref.sName + # Don't do library cells + if prefix_name and base_sref_name.startswith(prefix_name): + new_sref_name = sref.sName + else: + new_sref_name = self.padText(prefix + base_sref_name) + sref.sName = new_sref_name + #print("SREF: {0} -> {1}".format(base_sref_name, new_sref_name)) + self.structures = new_structures + def rename(self,newName): # take the root structure and copy it to a new structure with the new name self.structures[newName] = self.structures[self.rootStructureName] @@ -211,13 +247,17 @@ class VlsiLayout: del transformPath[-1] return - def initialize(self): + def initialize(self, special_purposes={}): self.deduceHierarchy() # self.traverseTheHierarchy() self.populateCoordinateMap() - + # only ones with text for layerNumber in self.layerNumbersInUse: - self.processLabelPins((layerNumber, None)) + # if layerNumber not in no_pin_shape: + if layerNumber in special_purposes: + self.processLabelPins((layerNumber, special_purposes[layerNumber])) + else: + self.processLabelPins((layerNumber, None)) def populateCoordinateMap(self): def addToXyTree(startingStructureName = None,transformPath = None): @@ -422,7 +462,8 @@ class VlsiLayout: self.structures[self.rootStructureName].texts.append(textToAdd) def padText(self, text): - if(len(text)%2 == 1): + debug.check(len(text) > 0, "Cannot have zero length text string.") + if(len(text) % 2 == 1): return text + '\x00' else: return text @@ -696,7 +737,6 @@ class VlsiLayout: return max_pins - def getAllPinShapes(self, pin_name): """ Search for a pin label and return ALL the enclosing rectangles on the same layer @@ -716,6 +756,7 @@ class VlsiLayout: Find all text labels and create a map to a list of shapes that they enclose on the given layer. """ + # Get the labels on a layer in the root level labels = self.getTexts(lpp) @@ -727,16 +768,28 @@ class VlsiLayout: label_coordinate = label.coordinates[0] user_coordinate = [x*self.units[0] for x in label_coordinate] pin_shapes = [] + # Remove the padding if it exists + if label.textString[-1] == "\x00": + label_text = label.textString[0:-1] + else: + label_text = label.textString + try: + from tech import layer_override + if layer_override[label_text]: + shapes = self.getAllShapes((layer_override[label_text][0], None)) + if not shapes: + shapes = self.getAllShapes(lpp) + else: + lpp = layer_override[label_text] + + + + except: + pass for boundary in shapes: if self.labelInRectangle(user_coordinate, boundary): pin_shapes.append((lpp, boundary)) - label_text = label.textString - - # Remove the padding if it exists - if label_text[-1] == "\x00": - label_text = label_text[0:-1] - try: self.pins[label_text] except KeyError: @@ -903,6 +956,16 @@ def sameLPP(lpp1, lpp2): if lpp1[1] == None or lpp2[1] == None: return lpp1[0] == lpp2[0] + if isinstance(lpp1[1], list): + for i in range(len(lpp1[1])): + if lpp1[0] == lpp2[0] and lpp1[1][i] == lpp2[1]: + return True + + if isinstance(lpp2[1], list): + for i in range(len(lpp2[1])): + if lpp1[0] == lpp2[0] and lpp1[1] == lpp2[1][i]: + return True + return lpp1[0] == lpp2[0] and lpp1[1] == lpp2[1] diff --git a/compiler/globals.py b/compiler/globals.py index 4c5f8a00..adc4cddf 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -66,7 +66,7 @@ def parse_args(): optparse.make_option("-m", "--sim_threads", action="store", type="int", - help="Specify the number of spice simulation threads (default: 2)", + help="Specify the number of spice simulation threads (default: 3)", dest="num_sim_threads"), optparse.make_option("-v", "--verbose", @@ -238,8 +238,8 @@ def setup_bitcell(): OPTS.dummy_bitcell = "dummy_pbitcell" OPTS.replica_bitcell = "replica_pbitcell" else: - num_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports - OPTS.bitcell = "bitcell_{}port".format(num_ports) + OPTS.num_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports + OPTS.bitcell = "bitcell_{}port".format(OPTS.num_ports) OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell OPTS.replica_bitcell = "replica_" + OPTS.bitcell @@ -329,7 +329,7 @@ def read_config(config_file, is_unit_test=True): debug.info(1, "Configuration file is " + config_file + ".py") try: config = importlib.import_module(module_name) - except: + except ImportError: debug.error("Unable to read configuration file: {0}".format(config_file), 2) OPTS.overridden = {} @@ -607,14 +607,14 @@ def report_status(): # If a write mask is specified by the user, the mask write size should be the same as # the word size so that an entire word is written at once. - if OPTS.write_size is not None: + if OPTS.write_size is not None and OPTS.write_size != OPTS.word_size: if (OPTS.word_size % OPTS.write_size != 0): debug.error("Write size needs to be an integer multiple of word size.") # If write size is more than half of the word size, # then it doesn't need a write mask. It would be writing # the whole word. - if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size/2): - debug.error("Write size needs to be between 1 bit and {0} bits/2.".format(OPTS.word_size)) + if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size / 2): + debug.error("Write size needs to be between 1 bit and {0} bits.".format(int(OPTS.word_size / 2))) if not OPTS.tech_name: debug.error("Tech name must be specified in config file.") diff --git a/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py b/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py new file mode 100644 index 00000000..e343a699 --- /dev/null +++ b/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py @@ -0,0 +1,9 @@ +word_size = 10 +num_words = 64 +words_per_row = 4 +local_array_size = 21 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_128b_1024_1rw.py b/compiler/model_configs/sram_128b_1024_1rw.py new file mode 100644 index 00000000..57585e10 --- /dev/null +++ b/compiler/model_configs/sram_128b_1024_1rw.py @@ -0,0 +1,7 @@ +word_size = 128 +num_words = 1024 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py b/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py new file mode 100644 index 00000000..e0b2725e --- /dev/null +++ b/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py @@ -0,0 +1,9 @@ +word_size = 12 +num_words = 128 +words_per_row = 4 +local_array_size = 38 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py b/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py new file mode 100644 index 00000000..61ad7ef7 --- /dev/null +++ b/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py @@ -0,0 +1,9 @@ +word_size = 12 +num_words = 16 +words_per_row = 1 +local_array_size = 1 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py b/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py new file mode 100644 index 00000000..a2ddaccc --- /dev/null +++ b/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py @@ -0,0 +1,9 @@ +word_size = 12 +num_words = 256 +words_per_row = 8 +local_array_size = 17 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py b/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py new file mode 100644 index 00000000..b9f305ac --- /dev/null +++ b/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py @@ -0,0 +1,9 @@ +word_size = 15 +num_words = 512 +words_per_row = 8 +local_array_size = 85 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py b/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py new file mode 100644 index 00000000..f088f5da --- /dev/null +++ b/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py @@ -0,0 +1,9 @@ +word_size = 16 +num_words = 1024 +words_per_row = 16 +local_array_size = 40 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py b/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py new file mode 100644 index 00000000..372b9d2f --- /dev/null +++ b/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py @@ -0,0 +1,9 @@ +word_size = 17 +num_words = 1024 +words_per_row = 16 +local_array_size = 86 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py b/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py new file mode 100644 index 00000000..fdaba442 --- /dev/null +++ b/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py @@ -0,0 +1,9 @@ +word_size = 17 +num_words = 256 +words_per_row = 16 +local_array_size = 49 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py b/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py new file mode 100644 index 00000000..efea335a --- /dev/null +++ b/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py @@ -0,0 +1,9 @@ +word_size = 18 +num_words = 128 +words_per_row = 2 +local_array_size = 7 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py b/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py new file mode 100644 index 00000000..4cc1c002 --- /dev/null +++ b/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py @@ -0,0 +1,9 @@ +word_size = 18 +num_words = 32 +words_per_row = 1 +local_array_size = 18 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py b/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py new file mode 100644 index 00000000..1d41916b --- /dev/null +++ b/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py @@ -0,0 +1,9 @@ +word_size = 22 +num_words = 512 +words_per_row = 16 +local_array_size = 249 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py b/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py new file mode 100644 index 00000000..20bbdaba --- /dev/null +++ b/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py @@ -0,0 +1,9 @@ +word_size = 23 +num_words = 1024 +words_per_row = 16 +local_array_size = 118 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py b/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py new file mode 100644 index 00000000..87ca9915 --- /dev/null +++ b/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py @@ -0,0 +1,9 @@ +word_size = 26 +num_words = 64 +words_per_row = 4 +local_array_size = 23 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py b/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py new file mode 100644 index 00000000..3dc6a351 --- /dev/null +++ b/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py @@ -0,0 +1,9 @@ +word_size = 27 +num_words = 1024 +words_per_row = 4 +local_array_size = 89 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py b/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py new file mode 100644 index 00000000..ab2c084e --- /dev/null +++ b/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py @@ -0,0 +1,9 @@ +word_size = 27 +num_words = 256 +words_per_row = 8 +local_array_size = 191 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py b/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py new file mode 100644 index 00000000..1bbac3d3 --- /dev/null +++ b/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py @@ -0,0 +1,9 @@ +word_size = 27 +num_words = 512 +words_per_row = 4 +local_array_size = 60 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_32b_1024_1rw.py b/compiler/model_configs/sram_32b_1024_1rw.py new file mode 100644 index 00000000..2de1ce15 --- /dev/null +++ b/compiler/model_configs/sram_32b_1024_1rw.py @@ -0,0 +1,7 @@ +word_size = 32 +num_words = 1024 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_32b_2048_1rw.py b/compiler/model_configs/sram_32b_2048_1rw.py new file mode 100644 index 00000000..eb987e71 --- /dev/null +++ b/compiler/model_configs/sram_32b_2048_1rw.py @@ -0,0 +1,7 @@ +word_size = 32 +num_words = 2048 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_32b_256_1rw.py b/compiler/model_configs/sram_32b_256_1rw.py new file mode 100644 index 00000000..b4cfb10f --- /dev/null +++ b/compiler/model_configs/sram_32b_256_1rw.py @@ -0,0 +1,7 @@ +word_size = 32 +num_words = 256 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_32b_512_1rw.py b/compiler/model_configs/sram_32b_512_1rw.py new file mode 100644 index 00000000..f90e0460 --- /dev/null +++ b/compiler/model_configs/sram_32b_512_1rw.py @@ -0,0 +1,7 @@ +word_size = 32 +num_words = 512 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py b/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py new file mode 100644 index 00000000..b7bc521d --- /dev/null +++ b/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py @@ -0,0 +1,9 @@ +word_size = 4 +num_words = 16 +words_per_row = 1 +local_array_size = 4 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py b/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py new file mode 100644 index 00000000..6a007d48 --- /dev/null +++ b/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py @@ -0,0 +1,9 @@ +word_size = 4 +num_words = 32 +words_per_row = 2 +local_array_size = 5 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py b/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py new file mode 100644 index 00000000..c970d774 --- /dev/null +++ b/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py @@ -0,0 +1,9 @@ +word_size = 4 +num_words = 64 +words_per_row = 4 +local_array_size = 14 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_64b_1024_1rw.py b/compiler/model_configs/sram_64b_1024_1rw.py new file mode 100644 index 00000000..d73899f3 --- /dev/null +++ b/compiler/model_configs/sram_64b_1024_1rw.py @@ -0,0 +1,7 @@ +word_size = 64 +num_words = 1024 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_64b_512_1rw.py b/compiler/model_configs/sram_64b_512_1rw.py new file mode 100644 index 00000000..966bed6c --- /dev/null +++ b/compiler/model_configs/sram_64b_512_1rw.py @@ -0,0 +1,7 @@ +word_size = 64 +num_words = 512 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py b/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py new file mode 100644 index 00000000..ec0dbed6 --- /dev/null +++ b/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py @@ -0,0 +1,9 @@ +word_size = 6 +num_words = 16 +words_per_row = 1 +local_array_size = 1 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py b/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py new file mode 100644 index 00000000..c620f2bd --- /dev/null +++ b/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py @@ -0,0 +1,9 @@ +word_size = 7 +num_words = 64 +words_per_row = 2 +local_array_size = 10 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_8b_1024_1rw.py b/compiler/model_configs/sram_8b_1024_1rw.py new file mode 100644 index 00000000..5d14d509 --- /dev/null +++ b/compiler/model_configs/sram_8b_1024_1rw.py @@ -0,0 +1,7 @@ +word_size = 8 +num_words = 1024 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_8b_256_1rw.py b/compiler/model_configs/sram_8b_256_1rw.py new file mode 100644 index 00000000..1fa3f737 --- /dev/null +++ b/compiler/model_configs/sram_8b_256_1rw.py @@ -0,0 +1,7 @@ +word_size = 8 +num_words = 256 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py b/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py new file mode 100644 index 00000000..dfbf96d3 --- /dev/null +++ b/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py @@ -0,0 +1,9 @@ +word_size = 8 +num_words = 256 +words_per_row = 1 +local_array_size = 1 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_8b_512_1rw.py b/compiler/model_configs/sram_8b_512_1rw.py new file mode 100644 index 00000000..57615846 --- /dev/null +++ b/compiler/model_configs/sram_8b_512_1rw.py @@ -0,0 +1,7 @@ +word_size = 8 +num_words = 512 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py b/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py new file mode 100644 index 00000000..8c742281 --- /dev/null +++ b/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py @@ -0,0 +1,9 @@ +word_size = 9 +num_words = 1024 +words_per_row = 4 +local_array_size = 3 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py b/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py new file mode 100644 index 00000000..5df33035 --- /dev/null +++ b/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py @@ -0,0 +1,9 @@ +word_size = 9 +num_words = 256 +words_per_row = 4 +local_array_size = 15 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True diff --git a/compiler/model_data_util.py b/compiler/model_data_util.py new file mode 100644 index 00000000..96b6ab39 --- /dev/null +++ b/compiler/model_data_util.py @@ -0,0 +1,288 @@ +import os +import csv +import re +import sys +import csv +import importlib + +# Use the HTML file to extra the data. Easier to do than LIB +data_file_ext = ".html" +extended_name = "_extended" # Name addon of extended config file +DEFAULT_LAS = 0 + +def gen_regex_float_group(num, separator): + if num <= 0: + return '' + float_regex = '([-+]?[0-9]*\.?[0-9]*)' + full_regex = float_regex + for i in range(num-1): + full_regex+=separator+float_regex + return full_regex + +def import_module(mod_name, mod_path): + spec = importlib.util.spec_from_file_location(mod_name, mod_path) + mod = importlib.util.module_from_spec(spec) + spec.loader.exec_module(mod) + return mod + +def get_config_mods(openram_dir): + # Get dataset name used by all the files e.g. sram_1b_16 + files_names = [name for name in os.listdir(openram_dir) if os.path.isfile(openram_dir+'/'+name)] + log = [name for name in files_names if '.log' in name][0] + dataset_name = log[:-4] + print("Extracting dataset:{}".format(dataset_name)) + + # Check that the config files exist (including special extended config) + dir_path = openram_dir+"/" + #sys.path.append(dir_path) + imp_mod = None + imp_mod_extended = None + if not os.path.exists(openram_dir+'/'+dataset_name+".py"): + print("Python module for {} not found.".format(dataset_name)) + imp_mod = None + else: + imp_mod = import_module(dataset_name, openram_dir+"/"+dataset_name+".py") + + if not os.path.exists(openram_dir+'/'+dataset_name+extended_name+".py"): + print("Extended Python module for {} not found.".format(dataset_name)) + imp_mod_extended = None + else: + imp_mod_extended = import_module(dataset_name+extended_name, openram_dir+"/"+dataset_name+extended_name+".py") + + datasheet_fname = openram_dir+"/"+dataset_name+data_file_ext + + return dataset_name, imp_mod, imp_mod_extended, datasheet_fname + +def get_corners(datafile_contents, dataset_name, tech): + """Search through given datasheet to find all corners available""" + + corner_regex = r"{}.*{},([-+]?[0-9]*\.?[0-9]*),([-+]?[0-9]*\.?[0-9]*),([tsfTSF][tsfTSF]),".format(dataset_name, tech) + corners = re.findall(corner_regex,datafile_contents) + return corners # List of corner tuples in order (T, V, P) + +feature_names = ['num_words', + 'word_size', + 'words_per_row', + 'local_array_size', + 'area', + 'process', + 'voltage', + 'temperature', + 'slew', + 'load'] +output_names = ['rise_delay', + 'fall_delay', + 'rise_slew', + 'fall_slew', + 'write1_power', + 'write0_power', + 'read1_power', + 'read0_power', + 'leakage_power'] + +multivalue_names = ['cell_rise_0', + 'cell_fall_0', + 'rise_transition_0', + 'fall_transition_0'] +singlevalue_names = ['write_rise_power_0', + 'write_fall_power_0', + 'read_rise_power_0', + 'read_fall_power_0'] + +def write_to_csv(dataset_name, csv_file, datasheet_fname, imp_mod, imp_mod_extended, mode): + + + writer = csv.writer(csv_file,lineterminator='\n') + # If the file was opened to write and not append then we write the header + if mode == 'w': + writer.writerow(feature_names+output_names) + + try: + load_slews = imp_mod.use_specified_load_slew + except: + load_slews = None + + if load_slews != None: + num_items = len(load_slews) + num_loads_or_slews = len(load_slews) + else: + # These are the defaults for openram + num_items = 9 + num_loads_or_slews = 3 + + try: + f = open(datasheet_fname, "r") + except IOError: + print("Unable to open spice output file: {0}".format(datasheet_fname)) + return None + print("Opened file",datasheet_fname) + contents = f.read() + f.close() + + available_corners = get_corners(contents, dataset_name, imp_mod_extended.tech_name) + + # Loop through corners, adding data for each corner + for (temp, voltage, process) in available_corners: + + # Create a regex to search the datasheet for specified outputs + voltage_str = "".join(['\\'+i if i=='.' else i for i in str(voltage)]) + area_regex = r"Area \(µm2<\/sup>\)<\/td>(\d+)" + + leakage_regex = r"leakage<\/td>([-+]?[0-9]*\.?[0-9]*)" + slew_regex = r"rise transition<\/td>([-+]?[0-9]*\.?[0-9]*)" + + if load_slews == None: + float_regex = gen_regex_float_group(num_loads_or_slews, ', ') + inp_slews_regex = r"{},{}.*{},{},{},.*slews,\[{}".format( + dataset_name, + imp_mod.num_words, + str(temp), + voltage_str, + process, + float_regex) + + loads_regex = r"{},{}.*{},{},{},.*loads,\[{}".format( + dataset_name, + imp_mod.num_words, + str(temp), + voltage_str, + process, + float_regex) + + float_regex = gen_regex_float_group(num_items, ', ') + multivalue_regexs = [] + for value_identifier in multivalue_names: + regex_str = r"{},{}.*{},{},{},.*{},\[{}".format( + dataset_name, + imp_mod.num_words, + str(temp), + voltage_str, + process, + value_identifier, + float_regex) + multivalue_regexs.append(regex_str) + + singlevalue_regexs = [] + for value_identifier in singlevalue_names: + regex_str = r"{},{}.*{},{},{},.*{},([-+]?[0-9]*\.?[0-9]*)".format( + dataset_name, + imp_mod.num_words, + str(temp), + voltage_str, + process, + value_identifier, + float_regex) + singlevalue_regexs.append(regex_str) + + area_vals = re.search(area_regex,contents) + leakage_vals = re.search(leakage_regex,contents) + if load_slews == None: + inp_slew_vals = re.search(inp_slews_regex,contents) + load_vals = re.search(loads_regex,contents) + + datasheet_multivalues = [re.search(r,contents) for r in multivalue_regexs] + datasheet_singlevalues = [re.search(r,contents) for r in singlevalue_regexs] + for dval in datasheet_multivalues+datasheet_singlevalues: + if dval == None: + print("Error occurred while searching through datasheet: {}".format(datasheet_fname)) + return None + + try: + las = imp_mod.local_array_size + except: + las = DEFAULT_LAS + + # All the extracted values are delays but val[2] is the max delay + feature_vals = [imp_mod.num_words, + imp_mod.word_size, + imp_mod_extended.words_per_row, + las, + area_vals[1], + process, + voltage, + temp] + + if load_slews == None: + c = 1 + for i in range(num_loads_or_slews): + for j in range(num_loads_or_slews): + multi_values = [val[i+j+c] for val in datasheet_multivalues] + single_values = [val[1] for val in datasheet_singlevalues] + writer.writerow(feature_vals+[inp_slew_vals[i+1], load_vals[j+1]]+multi_values+single_values+[leakage_vals[1]]) + c+=2 + else: + # if num loads and num slews are not equal then this might break because of how OpenRAM formats + # the outputs + c = 1 + for load,slew in load_slews: + multi_values = [val[c] for val in datasheet_multivalues] + single_values = [val[1] for val in datasheet_singlevalues] + writer.writerow(feature_vals+[slew, load]+multi_values+single_values+[leakage_vals[1]]) + c+=1 + + +def extract_data(openram_dir, out_dir, is_first): + """Given an OpenRAM output dir, searches through datasheet files and ouputs + a CSV files with data used in model.""" + + # Get dataset name used by all the files e.g. sram_1b_16 + dataset_name, inp_mod, imp_mod_extended, datasheet_fname = get_config_mods(openram_dir) + if inp_mod == None or imp_mod_extended == None: + print("Config file(s) for this run not found. Skipping...") + return + + if is_first: + mode = 'w' + else: + mode = 'a+' + with open("{}/sim_data.csv".format(out_dir), mode, newline='\n') as data_file: + write_to_csv(dataset_name, data_file, datasheet_fname, inp_mod, imp_mod_extended, mode) + + return out_dir + +def gen_model_csv(openram_dir_path, out_dir): + if not os.path.isdir(input_dir_path): + print("Path does not exist: {}".format(input_dir_path)) + return + + if not os.path.isdir(out_path): + print("Path does not exist: {}".format(out_path)) + return + + is_first = True + oram_dirs = [openram_dir_path+'/'+name for name in os.listdir(openram_dir_path) if os.path.isdir(openram_dir_path+'/'+name)] + for dir in oram_dirs: + extract_data(dir, out_dir, is_first) + is_first = False + +if __name__ == "__main__": + if len(sys.argv) < 3: + print("Usage: python model_data_util.py path_to_openram_dirs out_dir_path") + else: + input_dir_path = sys.argv[1] + out_path = sys.argv[2] + gen_model_csv(input_dir_path, out_path) + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 9c2b2add..666458ed 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -75,6 +75,11 @@ class bank(design.design): self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1) self.bank_array_ur = self.bitcell_array_inst.ur() self.bank_array_ul = self.bitcell_array_inst.ul() + + # These are used for other placements (e.g. address flops) + self.predecoder_top = self.port_address[0].predecoder_height + self.port_address_inst[0].by() + self.predecoder_bottom = self.port_address_inst[0].by() + self.DRC_LVS() def add_pins(self): @@ -227,7 +232,6 @@ class bank(design.design): x_offset = self.m2_gap + self.port_address[port].width self.port_address_offsets[port] = vector(-x_offset, self.main_bitcell_array_bottom) - self.predecoder_height = self.port_address[port].predecoder_height + self.port_address_offsets[port].y # LOWER LEFT QUADRANT # Place the col decoder left aligned with wordline driver @@ -362,18 +366,13 @@ class bank(design.design): # A space for wells or jogging m2 self.m2_gap = max(2 * drc("pwell_to_nwell") + drc("nwell_enclose_active"), - 3 * self.m2_pitch) + 3 * self.m2_pitch, + drc("nwell_to_nwell")) + def add_modules(self): """ Add all the modules using the class loader """ - self.port_address = [] - for port in self.all_ports: - self.port_address.append(factory.create(module_type="port_address", - cols=self.num_cols + self.num_spare_cols, - rows=self.num_rows, - port=port)) - self.add_mod(self.port_address[port]) local_array_size = OPTS.local_array_size @@ -394,6 +393,14 @@ class bank(design.design): rows=self.num_rows) self.add_mod(self.bitcell_array) + self.port_address = [] + for port in self.all_ports: + self.port_address.append(factory.create(module_type="port_address", + cols=self.num_cols + self.num_spare_cols, + rows=self.num_rows, + port=port)) + self.add_mod(self.port_address[port]) + self.port_data = [] self.bit_offsets = self.get_column_offsets() for port in self.all_ports: @@ -426,7 +433,9 @@ class bank(design.design): temp.append("vdd") temp.append("gnd") - + if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins: + temp.append('vpb') + temp.append('vnb') self.connect_inst(temp) def place_bitcell_array(self, offset): @@ -610,6 +619,10 @@ class bank(design.design): self.copy_power_pins(inst, "vdd", add_vias=False) self.copy_power_pins(inst, "gnd", add_vias=False) + if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins: + for pin_name, supply_name in zip(['vnb','vpb'],['gnd','vdd']): + self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name) + # If we use the pinvbuf as the decoder, we need to add power pins. # Other decoders already have them. if self.col_addr_size == 1: @@ -1058,7 +1071,6 @@ class bank(design.design): to_layer="m2", offset=control_pos) - def graph_exclude_precharge(self): """ Precharge adds a loop between bitlines, can be excluded to reduce complexity @@ -1071,7 +1083,7 @@ class bank(design.design): """ Gets the spice name of the target bitcell. """ - return self.bitcell_array_inst.mod.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, + return self.bitcell_array_inst.mod.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col) @@ -1087,3 +1099,14 @@ class bank(design.design): """ self.bitcell_array.clear_exclude_bits() + def graph_exclude_column_mux(self, column_include_num, port): + """ + Excludes all columns muxes unrelated to the target bit being simulated. + """ + self.port_data[port].graph_exclude_column_mux(column_include_num) + + def graph_clear_column_mux(self, port): + """ + Clear mux exclusions to allow different bit tests. + """ + self.port_data[port].graph_clear_column_mux() diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 9d1cc0de..238d499f 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -121,4 +121,4 @@ class bitcell_array(bitcell_base_array): def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" - return inst_name + '.x' + self.cell_inst[row, col].name, self.cell_inst[row, col] + return inst_name + "{}x".format(OPTS.hier_seperator) + self.cell_inst[row, col].name, self.cell_inst[row, col] diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 196f9868..f9eeaeb7 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -128,9 +128,8 @@ class bitcell_base_array(design.design): if len(self.all_ports) > 1: temp.extend(self.get_rbl_wordline_names(1)) return temp - - def add_layout_pins(self): - """ Add the layout pins """ + + def add_bitline_pins(self): bitline_names = self.cell.get_all_bitline_names() for col in range(self.column_size): for port in self.all_ports: @@ -146,7 +145,7 @@ class bitcell_base_array(design.design): offset=br_pin.ll().scale(1, 0), width=br_pin.width(), height=self.height) - + def add_wl_pins(self): wl_names = self.cell.get_all_wl_names() for row in range(self.row_size): for port in self.all_ports: @@ -157,13 +156,19 @@ class bitcell_base_array(design.design): width=self.width, height=wl_pin.height()) - # Copy a vdd/gnd layout pin from every cell + def add_supply_pins(self): for row in range(self.row_size): for col in range(self.column_size): inst = self.cell_inst[row, col] for pin_name in ["vdd", "gnd"]: self.copy_layout_pin(inst, pin_name) + def add_layout_pins(self): + """ Add the layout pins """ + self.add_bitline_pins() + self.add_wl_pins() + self.add_supply_pins() + def _adjust_x_offset(self, xoffset, col, col_offset): tempx = xoffset dir_y = False diff --git a/compiler/modules/column_mux_array.py b/compiler/modules/column_mux_array.py index 4aa23dfe..544b37e1 100644 --- a/compiler/modules/column_mux_array.py +++ b/compiler/modules/column_mux_array.py @@ -230,3 +230,12 @@ class column_mux_array(design.design): to_layer=self.sel_layer, offset=br_out_offset_begin, directions=self.via_directions) + + def graph_exclude_columns(self, column_include_num): + """ + Excludes all columns muxes unrelated to the target bit being simulated. + Each mux in mux_inst corresponds to respective column in bitcell array. + """ + for i in range(len(self.mux_inst)): + if i != column_include_num: + self.graph_inst_exclude.add(self.mux_inst[i]) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index eb9a21ed..52c1dd87 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -346,9 +346,12 @@ class control_logic(design.design): row += 1 self.place_wlen_row(row) row += 1 - self.place_delay(row) + + control_center_y = self.wl_en_inst.uy() + self.m3_pitch + + # Delay chain always gets placed at row 4 + self.place_delay(4) height = self.delay_inst.uy() - control_center_y = self.delay_inst.by() # This offset is used for placement of the control logic in the SRAM level. self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y) @@ -387,19 +390,22 @@ class control_logic(design.design): def place_delay(self, row): """ Place the replica bitline """ - y_off = row * self.and2.height + 2 * self.m1_pitch + debug.check(row % 2 == 0, "Must place delay chain at even row for supply alignment.") + + # It is flipped on X axis + y_off = row * self.and2.height + self.delay_chain.height # Add the RBL above the rows # Add to the right of the control rows and routing channel - offset = vector(self.delay_chain.width, y_off) - self.delay_inst.place(offset, mirror="MY") + offset = vector(0, y_off) + self.delay_inst.place(offset, mirror="MX") def route_delay(self): - out_pos = self.delay_inst.get_pin("out").bc() + out_pos = self.delay_inst.get_pin("out").center() # Connect to the rail level with the vdd rail - # Use pen since it is in every type of control logic - vdd_ypos = self.p_en_bar_nand_inst.get_pin("vdd").by() + # Use gated clock since it is in every type of control logic + vdd_ypos = self.gated_clk_buf_inst.get_pin("vdd").cy() + self.m1_pitch in_pos = vector(self.input_bus["rbl_bl_delay"].cx(), vdd_ypos) mid1 = vector(out_pos.x, in_pos.y) self.add_wire(self.m1_stack, [out_pos, mid1, in_pos]) @@ -676,7 +682,7 @@ class control_logic(design.design): # Connect the clock rail to the other clock rail # by routing in the supply rail track to avoid channel conflicts in_pos = self.ctrl_dff_inst.get_pin("clk").uc() - mid_pos = in_pos + vector(0, self.and2.height) + mid_pos = vector(in_pos.x, self.gated_clk_buf_inst.get_pin("vdd").cy() - self.m1_pitch) rail_pos = vector(self.input_bus["clk_buf"].cx(), mid_pos.y) self.add_wire(self.m1_stack, [in_pos, mid_pos, rail_pos]) self.add_via_center(layers=self.m1_stack, @@ -794,3 +800,8 @@ class control_logic(design.design): to_layer="m2", offset=out_pos) + def get_left_pins(self, name): + """ + Return the left side supply pins to connect to a vertical stripe. + """ + return(self.cntrl_dff_inst.get_pins(name) + self.delay_inst.get_pins(name)) diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index d7e9c2d0..7e4830c9 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -31,6 +31,7 @@ class delay_chain(design.design): # number of inverters including any fanout loads. self.fanout_list = fanout_list + self.rows = len(self.fanout_list) self.create_netlist() if not OPTS.netlist_only: @@ -43,10 +44,10 @@ class delay_chain(design.design): def create_layout(self): # Each stage is a a row - self.height = len(self.fanout_list) * self.inv.height + self.height = self.rows * self.inv.height # The width is determined by the largest fanout plus the driver self.width = (max(self.fanout_list) + 1) * self.inv.width - + self.place_inverters() self.route_inverters() self.route_supplies() @@ -62,14 +63,19 @@ class delay_chain(design.design): self.add_pin("gnd", "GROUND") def add_modules(self): - self.inv = factory.create(module_type="pinv") + + self.dff = factory.create(module_type="dff_buf") + dff_height = self.dff.height + + self.inv = factory.create(module_type="pinv", + height=dff_height) self.add_mod(self.inv) def create_inverters(self): """ Create the inverters and connect them based on the stage list """ self.driver_inst_list = [] self.load_inst_map = {} - for stage_num, fanout_size in zip(range(len(self.fanout_list)), self.fanout_list): + for stage_num, fanout_size in zip(range(self.rows), self.fanout_list): # Add the inverter cur_driver=self.add_inst(name="dinv{}".format(stage_num), mod=self.inv) @@ -77,7 +83,7 @@ class delay_chain(design.design): self.driver_inst_list.append(cur_driver) # Hook up the driver - if stage_num + 1 == len(self.fanout_list): + if stage_num + 1 == self.rows: stageout_name = "out" else: stageout_name = "dout_{}".format(stage_num + 1) @@ -101,7 +107,7 @@ class delay_chain(design.design): def place_inverters(self): """ Place the inverters and connect them based on the stage list """ - for stage_num, fanout_size in zip(range(len(self.fanout_list)), self.fanout_list): + for stage_num, fanout_size in zip(range(self.rows), self.fanout_list): if stage_num % 2: inv_mirror = "MX" inv_offset = vector(0, (stage_num + 1) * self.inv.height) @@ -185,24 +191,26 @@ class delay_chain(design.design): def add_layout_pins(self): # input is A pin of first inverter + # It gets routed to the left a bit to prevent pin access errors + # due to the output pin when going up to M3 a_pin = self.driver_inst_list[0].get_pin("A") + mid_loc = vector(a_pin.cx() - self.m3_pitch, a_pin.cy()) self.add_via_stack_center(from_layer=a_pin.layer, - to_layer="m2", - offset=a_pin.center()) - self.add_layout_pin(text="in", - layer="m2", - offset=a_pin.ll().scale(1, 0), - height=a_pin.cy()) + to_layer="m2", + offset=mid_loc) + self.add_path(a_pin.layer, [a_pin.center(), mid_loc]) + + self.add_layout_pin_rect_center(text="in", + layer="m2", + offset=mid_loc) - # output is A pin of last load inverter + # output is A pin of last load/fanout inverter last_driver_inst = self.driver_inst_list[-1] a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A") self.add_via_stack_center(from_layer=a_pin.layer, - to_layer="m2", + to_layer="m1", offset=a_pin.center()) - mid_point = vector(a_pin.cx() + 3 * self.m2_width, a_pin.cy()) - self.add_path("m2", [a_pin.center(), mid_point, mid_point.scale(1, 0)]) - self.add_layout_pin_segment_center(text="out", - layer="m2", - start=mid_point, - end=mid_point.scale(1, 0)) + self.add_layout_pin_rect_center(text="out", + layer="m1", + offset=a_pin.center()) + diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index e8474fed..d979c0fe 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -109,7 +109,7 @@ class dff_buf(design.design): except AttributeError: pass - well_spacing += self.well_extend_active + well_spacing += 2 * self.well_extend_active self.inv1_inst.place(vector(self.dff_inst.rx() + well_spacing, 0)) diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py index 8eb527d2..bd1c243b 100644 --- a/compiler/modules/global_bitcell_array.py +++ b/compiler/modules/global_bitcell_array.py @@ -296,12 +296,12 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): # We must also translate the global array column number to the local array column number local_col = targ_col - self.col_offsets[i - 1] - for mod in self.local_mods: + for mod, inst in zip(self.local_mods, self.local_insts): if mod == local_array: mod.graph_exclude_bits(targ_row, local_col) else: - # Otherwise, we exclude ALL of the rows/columns - mod.graph_exclude_bits() + # Otherwise, exclude the local array inst + self.graph_inst_exclude.add(inst) def graph_exclude_replica_col_bits(self): """ @@ -330,7 +330,7 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): # We must also translate the global array column number to the local array column number local_col = col - self.col_offsets[i - 1] - return local_array.get_cell_name(inst_name + '.x' + local_inst.name, row, local_col) + return local_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + local_inst.name, row, local_col) def clear_exclude_bits(self): """ @@ -338,6 +338,7 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): """ for mod in self.local_mods: mod.clear_exclude_bits() + self.init_graph_params() def graph_exclude_dffs(self): """Exclude dffs from graph as they do not represent critical path""" diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 141e717a..24267719 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -11,8 +11,10 @@ import math from sram_factory import factory from vector import vector from globals import OPTS +from tech import layer_indices +from tech import layer_stacks from tech import layer_properties as layer_props - +from tech import drc class hierarchical_decoder(design.design): """ @@ -29,7 +31,7 @@ class hierarchical_decoder(design.design): b = factory.create(module_type=OPTS.bitcell) self.cell_height = b.height - + self.predecode_bus_rail_pos = [] self.num_outputs = num_outputs self.num_inputs = math.ceil(math.log(self.num_outputs, 2)) (self.no_of_pre2x4, self.no_of_pre3x8, self.no_of_pre4x16)=self.determine_predecodes(self.num_inputs) @@ -504,9 +506,9 @@ class hierarchical_decoder(design.design): offset=vector(self.bus_pitch, 0), names=input_bus_names, length=self.height) - - self.route_predecodes_to_bus() self.route_bus_to_decoder() + self.route_predecodes_to_bus() + def route_predecodes_to_bus(self): """ @@ -521,7 +523,7 @@ class hierarchical_decoder(design.design): pin = self.pre2x4_inst[pre_num].get_pin(out_name) x_offset = self.pre2x4_inst[pre_num].rx() + self.output_layer_pitch y_offset = self.pre2x4_inst[pre_num].by() + i * self.cell_height - self.route_predecode_bus_inputs(predecode_name, pin, x_offset, y_offset) + self.route_predecode_bus_inputs(predecode_name, pin, x_offset, y_offset, "pre2x4") # FIXME: convert to connect_bus for pre_num in range(self.no_of_pre3x8): @@ -531,7 +533,7 @@ class hierarchical_decoder(design.design): pin = self.pre3x8_inst[pre_num].get_pin(out_name) x_offset = self.pre3x8_inst[pre_num].rx() + self.output_layer_pitch y_offset = self.pre3x8_inst[pre_num].by() + i * self.cell_height - self.route_predecode_bus_inputs(predecode_name, pin, x_offset, y_offset) + self.route_predecode_bus_inputs(predecode_name, pin, x_offset, y_offset, "pre3x8") # FIXME: convert to connect_bus for pre_num in range(self.no_of_pre4x16): @@ -541,7 +543,7 @@ class hierarchical_decoder(design.design): pin = self.pre4x16_inst[pre_num].get_pin(out_name) x_offset = self.pre4x16_inst[pre_num].rx() + self.output_layer_pitch y_offset = self.pre4x16_inst[pre_num].by() + i * self.cell_height - self.route_predecode_bus_inputs(predecode_name, pin, x_offset, y_offset) + self.route_predecode_bus_inputs(predecode_name, pin, x_offset, y_offset, "pre4x16") def route_bus_to_decoder(self): """ @@ -649,8 +651,9 @@ class hierarchical_decoder(design.design): to_layer=self.input_layer, offset=pin_pos, directions=("H", "H")) + self.predecode_bus_rail_pos.append(rail_pos) - def route_predecode_bus_inputs(self, rail_name, pin, x_offset, y_offset): + def route_predecode_bus_inputs(self, rail_name, pin, x_offset, y_offset, predecode_type): """ Connect the routing rail to the given metal1 pin using a jog to the right of the cell at the given x_offset. @@ -661,14 +664,58 @@ class hierarchical_decoder(design.design): mid_point1 = vector(x_offset, pin_pos.y) mid_point2 = vector(x_offset, y_offset) rail_pos = vector(self.predecode_bus[rail_name].cx(), mid_point2.y) - self.add_path(self.output_layer, [pin_pos, mid_point1, mid_point2, rail_pos]) - if layer_props.hierarchical_decoder.vertical_supply: - above_rail = vector(self.predecode_bus[rail_name].cx(), mid_point2.y + (self.cell_height / 2)) - self.add_path(self.bus_layer, [rail_pos, above_rail], width=self.li_width + self.m1_enclose_mcon * 2) + #self.add_path(self.output_layer, [pin_pos, mid_point1, mid_point2, rail_pos]) + #if layer_props.hierarchical_decoder.vertical_supply: + # above_rail = vector(self.predecode_bus[rail_name].cx(), mid_point2.y + (self.cell_height / 2)) + # self.add_path(self.bus_layer, [rail_pos, above_rail], width=self.li_width + self.m1_enclose_mcon * 2) + + #pin_pos = pin.center() + #rail_pos = vector(self.predecode_bus[rail_name].cx(), pin_pos.y) + #self.add_path(self.output_layer, [pin_pos, rail_pos]) + + # create via for dimensions + from_layer = self.output_layer + to_layer = self.bus_layer + + cur_layer = from_layer + from_id = layer_indices[cur_layer] + to_id = layer_indices[to_layer] + + if from_id < to_id: # grow the stack up + search_id = 0 + next_id = 2 + else: # grow the stack down + search_id = 2 + next_id = 0 + curr_stack = next(filter(lambda stack: stack[search_id] == cur_layer, layer_stacks), None) + via = factory.create(module_type="contact", + layer_stack=curr_stack, + dimensions=[1, 1], + directions=self.bus_directions) + overlapping_pin_space = getattr(self, "{}_space".format(self.output_layer)) + total_buffer_space = (overlapping_pin_space + via.height) + while(True): + drc_error = 0 + for and_input in self.predecode_bus_rail_pos: + if and_input.x == rail_pos.x: + if (abs(y_offset - and_input.y) < total_buffer_space) or (abs(y_offset - and_input.y) < via.height): + drc_error = 1 + if drc_error == 0: + break + else: + y_offset += drc["grid"] + rail_pos.y = y_offset + + if predecode_type == "pre2x4": + right_pos = pin_pos + elif predecode_type =="pre3x8": + right_pos = pin_pos + elif predecode_type == "pre4x16": + right_pos = pin_pos + # else: + # error("invalid predcoder type {}".format(predecode_type)) + self.add_path(self.output_layer, [pin_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) - # pin_pos = pin.center() - # rail_pos = vector(self.predecode_bus[rail_name].cx(), pin_pos.y) - # self.add_path(self.output_layer, [pin_pos, rail_pos]) self.add_via_stack_center(from_layer=pin.layer, to_layer=self.output_layer, offset=pin_pos) diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index f83516d2..30908c4c 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -12,6 +12,10 @@ from vector import vector from sram_factory import factory from globals import OPTS from tech import layer_properties as layer_props +from tech import layer_indices +from tech import layer_stacks +from tech import preferred_directions +from tech import drc class hierarchical_predecode(design.design): @@ -29,7 +33,7 @@ class hierarchical_predecode(design.design): self.cell_height = height self.column_decoder = column_decoder - + self.input_and_rail_pos = [] self.number_of_outputs = int(math.pow(2, self.number_of_inputs)) super().__init__(name) @@ -118,7 +122,7 @@ class hierarchical_predecode(design.design): self.input_rails = self.create_vertical_bus(layer=self.bus_layer, offset=offset, names=input_names, - length=self.height - 2 * self.bus_pitch, + length=self.height - self.bus_pitch, pitch=self.bus_pitch) invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)] @@ -128,7 +132,7 @@ class hierarchical_predecode(design.design): self.decode_rails = self.create_vertical_bus(layer=self.bus_layer, offset=offset, names=decode_names, - length=self.height - 2 * self.bus_pitch, + length=self.height - self.bus_pitch, pitch=self.bus_pitch) def create_input_inverters(self): @@ -183,15 +187,15 @@ class hierarchical_predecode(design.design): def route(self): self.route_input_inverters() - self.route_output_inverters() - self.route_inputs_to_rails() self.route_input_ands() + self.route_output_inverters() + self.route_inputs_to_rails() self.route_output_ands() self.route_vdd_gnd() def route_inputs_to_rails(self): """ Route the uninverted inputs to the second set of rails """ - + top_and_gate = self.and_inst[-1] for num in range(self.number_of_inputs): if num == 0: @@ -211,13 +215,25 @@ class hierarchical_predecode(design.design): in_pos = vector(self.input_rails[in_pin].cx(), y_offset) a_pos = vector(self.decode_rails[a_pin].cx(), y_offset) self.add_path(self.input_layer, [in_pos, a_pos]) - self.add_via_stack_center(from_layer=self.input_layer, - to_layer=self.bus_layer, - offset=[self.input_rails[in_pin].cx(), y_offset]) - self.add_via_stack_center(from_layer=self.input_layer, - to_layer=self.bus_layer, - offset=[self.decode_rails[a_pin].cx(), y_offset]) + if(layer_props.hierarchical_predecode.force_horizontal_input_contact): + self.add_via_stack_center(from_layer=self.input_layer, + to_layer=self.bus_layer, + offset=[self.input_rails[in_pin].cx(), y_offset], + directions= ("H", "H")) + + self.add_via_stack_center(from_layer=self.input_layer, + to_layer=self.bus_layer, + offset=[self.decode_rails[a_pin].cx(), y_offset], + directions=("H", "H")) + else: + self.add_via_stack_center(from_layer=self.input_layer, + to_layer=self.bus_layer, + offset=[self.input_rails[in_pin].cx(), y_offset]) + + self.add_via_stack_center(from_layer=self.input_layer, + to_layer=self.bus_layer, + offset=[self.decode_rails[a_pin].cx(), y_offset]) def route_output_ands(self): """ Route all conections of the outputs and gates @@ -274,8 +290,45 @@ class hierarchical_predecode(design.design): # pins in the and gates. inv_out_pos = inv_out_pin.rc() y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch - right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0) rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset) + + # create via for dimensions + from_layer = self.output_layer + to_layer = self.bus_layer + + cur_layer = from_layer + from_id = layer_indices[cur_layer] + to_id = layer_indices[to_layer] + + if from_id < to_id: # grow the stack up + search_id = 0 + next_id = 2 + else: # grow the stack down + search_id = 2 + next_id = 0 + + curr_stack = next(filter(lambda stack: stack[search_id] == cur_layer, layer_stacks), None) + + via = factory.create(module_type="contact", + layer_stack=curr_stack, + dimensions=[1, 1], + directions=self.bus_directions) + + overlapping_pin_space = drc["{0}_to_{0}".format(self.output_layer)] + total_buffer_space = (overlapping_pin_space + via.height) + #FIXME: compute rail locations instead of just guessing and nudging + while(True): + drc_error = 0 + for and_input in self.input_and_rail_pos: + if and_input.x == rail_pos.x: + if (abs(y_offset - and_input.y) < total_buffer_space) and (abs(y_offset - and_input.y) > via.height): + drc_error = 1 + if drc_error == 0: + break + else: + y_offset += drc["grid"] + rail_pos.y = y_offset + right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0) self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) self.add_via_stack_center(from_layer=inv_out_pin.layer, @@ -290,7 +343,7 @@ class hierarchical_predecode(design.design): """ Route the different permutations of the NAND/AND decocer cells. """ - + # This 2D array defines the connection mapping and_input_line_combination = self.get_and_input_line_combination() for k in range(self.number_of_outputs): @@ -316,6 +369,7 @@ class hierarchical_predecode(design.design): to_layer=self.bus_layer, offset=rail_pos, directions=self.bus_directions) + self.input_and_rail_pos.append(rail_pos) if gate_pin == "A": direction = None else: diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index 30da5bf1..e48cff5c 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -217,6 +217,12 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): y_offset += global_wl_pitch_factor * global_wl_pitch mid = vector(in_pin.cx(), y_offset) + self.add_layout_pin_rect_center(text=wl_name, + layer=global_wl_layer, + offset=mid) + + self.add_path(local_wl_layer, [in_pin.center(), mid]) + # A short jog to the global line self.add_via_stack_center(from_layer=in_pin.layer, to_layer=local_wl_layer, @@ -289,7 +295,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" - return self.bitcell_array.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, row, col) + return self.bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col) def clear_exclude_bits(self): """ diff --git a/compiler/modules/orig_bitcell_array.py b/compiler/modules/orig_bitcell_array.py index 8bf498a4..42ebdc33 100644 --- a/compiler/modules/orig_bitcell_array.py +++ b/compiler/modules/orig_bitcell_array.py @@ -114,4 +114,4 @@ class bitcell_array(bitcell_base_array): def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" - return inst_name + '.x' + self.cell_inst[row, col].name, self.cell_inst[row, col] + return inst_name + "{}x".format(OPTS.hier_seperator) + self.cell_inst[row, col].name, self.cell_inst[row, col] diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 71c8449a..7b329702 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -11,6 +11,7 @@ from sram_factory import factory from collections import namedtuple from vector import vector from globals import OPTS +from tech import cell_properties from tech import layer_properties as layer_props @@ -20,7 +21,7 @@ class port_data(design.design): Port 0 always has the RBL on the left while port 1 is on the right. """ - def __init__(self, sram_config, port, bit_offsets=None, name=""): + def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="",): sram_config.set_local_config(self) self.port = port @@ -28,18 +29,23 @@ class port_data(design.design): self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 - + + if num_spare_cols is not None: + self.num_spare_cols = num_spare_cols + self.num_spare_cols if self.num_spare_cols is None: self.num_spare_cols = 0 - if not bit_offsets: bitcell = factory.create(module_type=OPTS.bitcell) + if(cell_properties.use_strap == True and OPTS.num_ports == 1): + strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) + precharge_width = bitcell.width + strap.width + else: + precharge_width = bitcell.width self.bit_offsets = [] for i in range(self.num_cols + self.num_spare_cols): - self.bit_offsets.append(i * bitcell.width) + self.bit_offsets.append(i * precharge_width) else: self.bit_offsets = bit_offsets - if name == "": name = "port_data_{0}".format(self.port) super().__init__(name) @@ -117,7 +123,6 @@ class port_data(design.design): for bit in range(self.num_spare_cols): self.add_pin("sparebl_{0}".format(bit), "INOUT") self.add_pin("sparebr_{0}".format(bit), "INOUT") - if self.port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout_{}".format(bit), "OUTPUT") @@ -191,14 +196,19 @@ class port_data(design.design): # and mirroring happens correctly # Used for names/dimensions only - self.cell = factory.create(module_type=OPTS.bitcell) - + cell = factory.create(module_type=OPTS.bitcell) + if(cell_properties.use_strap == True and OPTS.num_ports == 1): + strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) + precharge_width = cell.width + strap.width + else: + precharge_width = cell.width if self.port == 0: # Append an offset on the left - precharge_bit_offsets = [self.bit_offsets[0] - self.cell.width] + self.bit_offsets + precharge_bit_offsets = [self.bit_offsets[0] - precharge_width] + self.bit_offsets else: # Append an offset on the right - precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + self.cell.width] + precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + precharge_width] + self.precharge_array = factory.create(module_type="precharge_array", columns=self.num_cols + self.num_spare_cols + 1, offsets=precharge_bit_offsets, @@ -567,19 +577,32 @@ class port_data(design.design): off = 1 else: off = 0 + if OPTS.num_ports > 1: + self.channel_route_bitlines(inst1=self.column_mux_array_inst, + inst1_bls_template="{inst}_out_{bit}", + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) - self.channel_route_bitlines(inst1=self.column_mux_array_inst, - inst1_bls_template="{inst}_out_{bit}", - inst2=inst2, - num_bits=self.word_size, - inst1_start_bit=start_bit) + self.channel_route_bitlines(inst1=self.precharge_array_inst, + inst1_bls_template="{inst}_{bit}", + inst2=inst2, + num_bits=self.num_spare_cols, + inst1_start_bit=self.num_cols + off, + inst2_start_bit=self.word_size) + else: + self.connect_bitlines(inst1=self.column_mux_array_inst, + inst1_bls_template="{inst}_out_{bit}", + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) - self.channel_route_bitlines(inst1=self.precharge_array_inst, - inst1_bls_template="{inst}_{bit}", - inst2=inst2, - num_bits=self.num_spare_cols, - inst1_start_bit=self.num_cols + off, - inst2_start_bit=self.word_size) + self.connect_bitlines(inst1=self.precharge_array_inst, + inst1_bls_template="{inst}_{bit}", + inst2=inst2, + num_bits=self.num_spare_cols, + inst1_start_bit=self.num_cols + off, + inst2_start_bit=self.word_size) elif layer_props.port_data.channel_route_bitlines: self.channel_route_bitlines(inst1=inst1, @@ -828,3 +851,17 @@ class port_data(design.design): """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" if self.precharge_array_inst: self.graph_inst_exclude.add(self.precharge_array_inst) + + def graph_exclude_column_mux(self, column_include_num): + """ + Excludes all columns muxes unrelated to the target bit being simulated. + """ + if self.column_mux_array: + self.column_mux_array.graph_exclude_columns(column_include_num) + + def graph_clear_column_mux(self): + """ + Clear mux exclusions to allow different bit tests. + """ + if self.column_mux_array: + self.column_mux_array.init_graph_params() diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 8718dfd0..ed19b387 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -76,8 +76,8 @@ class precharge_array(design.design): size=self.size, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) + self.add_mod(self.pc_cell) - self.cell = factory.create(module_type=OPTS.bitcell) def add_layout_pins(self): diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 828941ae..baf83964 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -6,7 +6,7 @@ import debug from bitcell_base_array import bitcell_base_array -from tech import drc, spice +from tech import drc, spice, cell_properties from vector import vector from globals import OPTS from sram_factory import factory @@ -553,7 +553,7 @@ class replica_bitcell_array(bitcell_base_array): """ Gets the spice name of the target bitcell. """ - return self.bitcell_array.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, row, col) + return self.bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col) def clear_exclude_bits(self): """ diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index b890566a..d237bcc8 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -238,5 +238,4 @@ class replica_column(bitcell_base_array): for row, cell in enumerate(self.cell_inst): if row != self.replica_bit: self.graph_inst_exclude.add(cell) - - + diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 01b74c84..713f4daf 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -8,6 +8,7 @@ import design from vector import vector from sram_factory import factory +from tech import cell_properties import debug from globals import OPTS @@ -41,7 +42,6 @@ class sense_amp_array(design.design): self.en_layer = "m3" else: self.en_layer = "m1" - self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -109,15 +109,22 @@ class sense_amp_array(design.design): self.en_name, "vdd", "gnd"]) def place_sense_amp_array(self): - if self.bitcell.width > self.amp.width: - self.amp_spacing = self.bitcell.width + cell = factory.create(module_type=OPTS.bitcell) + if(cell_properties.use_strap == True and OPTS.num_ports == 1): + strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) + precharge_width = cell.width + strap.width + else: + precharge_width = cell.width + + if precharge_width > self.amp.width: + self.amp_spacing = precharge_width else: self.amp_spacing = self.amp.width if not self.offsets: self.offsets = [] for i in range(self.num_cols + self.num_spare_cols): - self.offsets.append(i * self.bitcell.width) + self.offsets.append(i * self.amp_spacing) for i, xoffset in enumerate(self.offsets[0:self.num_cols:self.words_per_row]): if self.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2: @@ -128,13 +135,12 @@ class sense_amp_array(design.design): amp_position = vector(xoffset, 0) self.local_insts[i].place(offset=amp_position, mirror=mirror) - # place spare sense amps (will share the same enable as regular sense amps) for i, xoffset in enumerate(self.offsets[self.num_cols:]): index = self.word_size + i if self.bitcell.mirror.y and (index + self.column_offset) % 2: mirror = "MY" - xoffset = xoffset + self.amp_width + xoffset = xoffset + self.amp_spacing else: mirror = "" diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index c0bd8b84..2ccf34a1 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -117,9 +117,10 @@ class write_mask_and_array(design.design): for i in range(self.num_wmasks): # Route the A pin over to the left so that it doesn't conflict with the sense # amp output which is usually in the center - a_pin = self.and2_insts[i].get_pin("A") + inst = self.and2_insts[i] + a_pin = inst.get_pin("A") a_pos = a_pin.center() - in_pos = vector(self.and2_insts[i].lx(), + in_pos = vector(inst.lx(), a_pos.y) self.add_via_stack_center(from_layer=a_pin.layer, to_layer="m2", @@ -130,21 +131,31 @@ class write_mask_and_array(design.design): self.add_path(a_pin.layer, [in_pos, a_pos]) # Copy remaining layout pins - self.copy_layout_pin(self.and2_insts[i], "Z", "wmask_out_{0}".format(i)) + self.copy_layout_pin(inst, "Z", "wmask_out_{0}".format(i)) # Add via connections to metal3 for AND array's B pin - en_pin = self.and2_insts[i].get_pin("B") + en_pin = inst.get_pin("B") en_pos = en_pin.center() self.add_via_stack_center(from_layer=en_pin.layer, to_layer="m3", offset=en_pos) + + # Add connection to the supply + for supply_name in ["gnd", "vdd"]: + supply_pin = inst.get_pin(supply_name) + self.add_via_stack_center(from_layer=supply_pin.layer, + to_layer="m1", + offset=supply_pin.center()) for supply in ["gnd", "vdd"]: supply_pin = self.and2_insts[0].get_pin(supply) supply_pin_yoffset = supply_pin.cy() left_loc = vector(0, supply_pin_yoffset) right_loc = vector(self.width, supply_pin_yoffset) - self.add_path(supply_pin.layer, [left_loc, right_loc]) - self.copy_power_pin(supply_pin, loc=left_loc) - self.copy_power_pin(supply_pin, loc=right_loc) + self.add_path("m1", [left_loc, right_loc]) + for loc in [left_loc, right_loc]: + self.add_via_stack_center(from_layer=supply_pin.layer, + to_layer="m1", + offset=loc) + self.copy_power_pin(supply_pin, loc=loc) diff --git a/compiler/options.py b/compiler/options.py index cd54b2c6..f3c19283 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -6,9 +6,9 @@ # All rights reserved. # import optparse -import getpass import os + class options(optparse.Values): """ Class for holding all of the OpenRAM options. All @@ -60,7 +60,7 @@ class options(optparse.Values): rbl_delay_percentage = 0.5 # Allow manual adjustment of the delay chain over automatic - auto_delay_chain_sizing = False + auto_delay_chain_sizing = False delay_chain_stages = 9 delay_chain_fanout_per_stage = 4 @@ -72,10 +72,12 @@ class options(optparse.Values): # This is the temp directory where all intermediate results are stored. try: # If user defined the temporary location in their environment, use it + openram_temp = os.path.abspath(os.environ.get("OPENRAM_TMP")) + except: openram_temp = "/tmp" - + # This is the verbosity level to control debug information. 0 is none, 1 # is minimal, etc. verbose_level = 0 @@ -87,6 +89,8 @@ class options(optparse.Values): use_specified_corners = None # Allows specification of model data sim_data_path = None + # A list of load/slew tuples + use_specified_load_slew = None ################### # Run-time vs accuracy options. @@ -97,6 +101,7 @@ class options(optparse.Values): netlist_only = False # Whether we should do the final power routing route_supplies = "tree" + supply_pin_type = "ring" # This determines whether LVS and DRC is checked at all. check_lvsdrc = False # This determines whether LVS and DRC is checked for every submodule. @@ -117,13 +122,13 @@ class options(optparse.Values): # Tool options ################### # Variable to select the variant of spice - spice_name = "" + spice_name = None # The spice executable being used which is derived from the user PATH. - spice_exe = "" + spice_exe = None # Variable to select the variant of drc, lvs, pex - drc_name = "" - lvs_name = "" - pex_name = "" + drc_name = None + lvs_name = None + pex_name = None # The DRC/LVS/PEX executable being used # which is derived from the user PATH. drc_exe = None @@ -131,11 +136,14 @@ class options(optparse.Values): pex_exe = None # For sky130, we need magic for filtering. magic_exe = None - + # Number of threads to use num_threads = 1 # Number of threads to use in ngspice/hspice - num_sim_threads = 2 + num_sim_threads = 3 + + # Some tools (e.g. Xyce) use other separators like ":" + hier_seperator = "." # Should we print out the banner at startup print_banner = True @@ -158,6 +166,9 @@ class options(optparse.Values): keep_temp = False + # Add a prefix of the root cell before every structure in the GDS + # after outputting the GDS2 + uniquify = False # These are the default modules that can be over-riden bank_select = "bank_select" diff --git a/compiler/pgates/column_mux.py b/compiler/pgates/column_mux.py index 1e8c5bf8..0dd923ba 100644 --- a/compiler/pgates/column_mux.py +++ b/compiler/pgates/column_mux.py @@ -56,7 +56,13 @@ class column_mux(pgate.pgate): self.place_ptx() - self.width = self.bitcell.width + cell = factory.create(module_type=OPTS.bitcell) + if(cell_props.use_strap == True and OPTS.num_ports == 1): + strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version) + precharge_width = cell.width + strap.width + else: + precharge_width = cell.width + self.width = precharge_width self.height = self.nmos_upper.uy() + self.pin_height self.connect_poly() @@ -217,10 +223,15 @@ class column_mux(pgate.pgate): Add a well and implant over the whole cell. Also, add the pwell contact (if it exists) """ - + if(cell_props.use_strap == True and OPTS.num_ports == 1): + strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version) + rbc_width = self.bitcell.width + strap.width + else: + rbc_width = self.bitcell.width # Add it to the right, aligned in between the two tx - active_pos = vector(self.bitcell.width, + active_pos = vector(rbc_width, self.nmos_upper.by() - 0.5 * self.poly_space) + self.add_via_center(layers=self.active_stack, offset=active_pos, implant_type="p", @@ -239,5 +250,5 @@ class column_mux(pgate.pgate): if "pwell" in layer: self.add_rect(layer="pwell", offset=vector(0, 0), - width=self.bitcell.width, + width=rbc_width, height=self.height) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index d1999384..951fe834 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -30,7 +30,11 @@ class precharge(design.design): self.beta = parameter["beta"] self.ptx_width = self.beta * parameter["min_tx_size"] self.ptx_mults = 1 - self.width = self.bitcell.width + if(cell_props.use_strap == True and OPTS.num_ports == 1): + strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version) + self.width = self.bitcell.width + strap.width + else: + self.width = self.bitcell.width self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br self.bitcell_bl_pin =self.bitcell.get_pin(self.bitcell_bl) diff --git a/compiler/router/grid.py b/compiler/router/grid.py index 793e5e89..843fb3ed 100644 --- a/compiler/router/grid.py +++ b/compiler/router/grid.py @@ -37,6 +37,8 @@ class grid: # This is really lower left bottom layer and upper right top layer in 3D. self.ll = vector3d(ll.x, ll.y, 0).scale(self.track_factor).round() self.ur = vector3d(ur.x, ur.y, 0).scale(self.track_factor).round() + debug.info(1, "BBOX coords: ll=" + str(ll) + " ur=" + str(ur)) + debug.info(1, "BBOX grids: ll=" + str(self.ll) + " ur=" + str(self.ur)) # let's leave the map sparse, cells are created on demand to reduce memory self.map={} @@ -122,35 +124,59 @@ class grid: self.set_target(n) # self.set_blocked(n, False) - def add_perimeter_target(self, side="all"): - debug.info(3, "Adding perimeter target") + def get_perimeter_list(self, side="left", layers=[0, 1], width=1, margin=0, offset=0): + """ + Side specifies which side. + Layer specifies horizontal (0) or vertical (1) + Width specifies how wide the perimter "stripe" should be. + Works from the inside out from the bbox (ll, ur) + """ + if "ring" in side: + ring_width = width + else: + ring_width = 0 + + if "ring" in side: + ring_offset = offset + else: + ring_offset = 0 perimeter_list = [] # Add the left/right columns - if side=="all" or side=="left": - x = self.ll.x - for y in range(self.ll.y, self.ur.y, 1): - perimeter_list.append(vector3d(x, y, 0)) - perimeter_list.append(vector3d(x, y, 1)) + if side=="all" or "left" in side: + for x in range(self.ll.x - offset, self.ll.x - width - offset, -1): + for y in range(self.ll.y - ring_offset - margin - ring_width + 1, self.ur.y + ring_offset + margin + ring_width, 1): + for layer in layers: + perimeter_list.append(vector3d(x, y, layer)) - if side=="all" or side=="right": - x = self.ur.x - for y in range(self.ll.y, self.ur.y, 1): - perimeter_list.append(vector3d(x, y, 0)) - perimeter_list.append(vector3d(x, y, 1)) + if side=="all" or "right" in side: + for x in range(self.ur.x + offset, self.ur.x + width + offset, 1): + for y in range(self.ll.y - ring_offset - margin - ring_width + 1, self.ur.y + ring_offset + margin + ring_width, 1): + for layer in layers: + perimeter_list.append(vector3d(x, y, layer)) - if side=="all" or side=="bottom": - y = self.ll.y - for x in range(self.ll.x, self.ur.x, 1): - perimeter_list.append(vector3d(x, y, 0)) - perimeter_list.append(vector3d(x, y, 1)) + if side=="all" or "bottom" in side: + for y in range(self.ll.y - offset, self.ll.y - width - offset, -1): + for x in range(self.ll.x - ring_offset - margin - ring_width + 1, self.ur.x + ring_offset + margin + ring_width, 1): + for layer in layers: + perimeter_list.append(vector3d(x, y, layer)) - if side=="all" or side=="top": - y = self.ur.y - for x in range(self.ll.x, self.ur.x, 1): - perimeter_list.append(vector3d(x, y, 0)) - perimeter_list.append(vector3d(x, y, 1)) + if side=="all" or "top" in side: + for y in range(self.ur.y + offset, self.ur.y + width + offset, 1): + for x in range(self.ll.x - ring_offset - margin - ring_width + 1, self.ur.x + ring_offset + margin + ring_width, 1): + for layer in layers: + perimeter_list.append(vector3d(x, y, layer)) + # Add them all to the map + self.add_map(perimeter_list) + + return perimeter_list + + def add_perimeter_target(self, side="all", layers=[0, 1]): + debug.info(3, "Adding perimeter target") + + perimeter_list = self.get_perimeter_list(side, layers) + self.set_target(perimeter_list) def is_target(self, point): diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index 7a5d8817..5e6d6f89 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -155,6 +155,10 @@ class pin_group: # Now simplify the enclosure list new_pin_list = self.remove_redundant_shapes(pin_list) + # Now add the right name + for pin in new_pin_list: + pin.name = self.name + debug.check(len(new_pin_list) > 0, "Did not find any enclosures.") diff --git a/compiler/router/router.py b/compiler/router/router.py index 5213af4a..f82a6128 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -28,7 +28,7 @@ class router(router_tech): route on a given layer. This is limited to two layer routes. It populates blockages on a grid class. """ - def __init__(self, layers, design, gds_filename=None, bbox=None, margin=0, route_track_width=1): + def __init__(self, layers, design, bbox=None, margin=0, route_track_width=1): """ This will instantiate a copy of the gds file or the module at (0,0) and route on top of this. The blockages from the gds/module will be @@ -39,19 +39,7 @@ class router(router_tech): self.cell = design - # If didn't specify a gds blockage file, write it out to read the gds - # This isn't efficient, but easy for now - # start_time = datetime.now() - if not gds_filename: - gds_filename = OPTS.openram_temp+"temp.gds" - self.cell.gds_write(gds_filename) - - # Load the gds file and read in all the shapes - self.layout = gdsMill.VlsiLayout(units=GDS["unit"]) - self.reader = gdsMill.Gds2reader(self.layout) - self.reader.loadFromFile(gds_filename) - self.top_name = self.layout.rootStructureName - # print_time("GDS read",datetime.now(), start_time) + self.gds_filename = OPTS.openram_temp + "temp.gds" # The pin data structures # A map of pin names to a set of pin_layout structures @@ -87,25 +75,20 @@ class router(router_tech): self.margin = margin self.init_bbox(bbox, margin) + # New pins if we create a ring or side pins or etc. + self.new_pins = {} + def init_bbox(self, bbox=None, margin=0): """ Initialize the ll,ur values with the paramter or using the layout boundary. """ if not bbox: - # The boundary will determine the limits to the size - # of the routing grid - self.boundary = self.layout.measureBoundary(self.top_name) - # These must be un-indexed to get rid of the matrix type - self.ll = vector(self.boundary[0][0], self.boundary[0][1]) - self.ur = vector(self.boundary[1][0], self.boundary[1][1]) + self.bbox = self.cell.get_bbox(margin) else: - self.ll, self.ur = bbox + self.bbox = bbox + + (self.ll, self.ur) = self.bbox - margin_offset = vector(margin, margin) - self.bbox = (self.ll - margin_offset, self.ur + margin_offset) - size = self.ur - self.ll - debug.info(1, "Size: {0} x {1} with perimeter margin {2}".format(size.x, size.y, margin)) - def get_bbox(self): return self.bbox @@ -178,6 +161,17 @@ class router(router_tech): """ Find the pins and blockages in the design """ + + # If didn't specify a gds blockage file, write it out to read the gds + # This isn't efficient, but easy for now + # Load the gds file and read in all the shapes + self.cell.gds_write(self.gds_filename) + self.layout = gdsMill.VlsiLayout(units=GDS["unit"]) + self.reader = gdsMill.Gds2reader(self.layout) + self.reader.loadFromFile(self.gds_filename) + self.top_name = self.layout.rootStructureName + # print_time("GDS read",datetime.now(), start_time) + # This finds the pin shapes and sorts them into "groups" that # are connected. This must come before the blockages, so we # can not count the pins themselves @@ -717,6 +711,27 @@ class router(router_tech): p = pin_layout("", [ll, ur], self.get_layer(track[2])) return p + def convert_tracks_to_pin(self, tracks): + """ + Convert a list of grid point into a rectangle shape. + Must all be on the same layer. + """ + for t in tracks: + debug.check(t[2] == tracks[0][2], "Different layers used.") + + # For each shape, convert it to a pin + pins = [self.convert_track_to_pin(t) for t in tracks] + # Now find the bounding box + minx = min([p.lx() for p in pins]) + maxx = max([p.rx() for p in pins]) + miny = min([p.by() for p in pins]) + maxy = max([p.uy() for p in pins]) + ll = vector(minx, miny) + ur = vector(maxx, maxy) + + p = pin_layout("", [ll, ur], self.get_layer(tracks[0][2])) + return p + def convert_track_to_shape_pin(self, track): """ Convert a grid point into a rectangle shape @@ -881,12 +896,103 @@ class router(router_tech): # Clearing the blockage of this pin requires the inflated pins self.clear_blockages(pin_name) + def add_side_supply_pin(self, name, side="left", width=3, space=2): + """ + Adds a supply pin to the perimeter and resizes the bounding box. + """ + pg = pin_group(name, [], self) + # Offset two spaces inside and one between the rings + if name == "gnd": + offset = width + 2 * space + else: + offset = space + if side in ["left", "right"]: + layers = [1] + else: + layers = [0] + + pg.grids = set(self.rg.get_perimeter_list(side=side, + width=width, + margin=self.margin, + offset=offset, + layers=layers)) + pg.enclosures = pg.compute_enclosures() + pg.pins = set(pg.enclosures) + debug.check(len(pg.pins)==1, "Too many pins for a side supply.") + + self.cell.pin_map[name].update(pg.pins) + self.pin_groups[name].append(pg) + + self.new_pins[name] = pg.pins + + def add_ring_supply_pin(self, name, width=3, space=2): + """ + Adds a ring supply pin that goes inside the given bbox. + """ + pg = pin_group(name, [], self) + # Offset two spaces inside and one between the rings + # Units are in routing grids + if name == "gnd": + offset = width + 2 * space + else: + offset = space + + # LEFT + left_grids = set(self.rg.get_perimeter_list(side="left_ring", + width=width, + margin=self.margin, + offset=offset, + layers=[1])) + + # RIGHT + right_grids = set(self.rg.get_perimeter_list(side="right_ring", + width=width, + margin=self.margin, + offset=offset, + layers=[1])) + # TOP + top_grids = set(self.rg.get_perimeter_list(side="top_ring", + width=width, + margin=self.margin, + offset=offset, + layers=[0])) + # BOTTOM + bottom_grids = set(self.rg.get_perimeter_list(side="bottom_ring", + width=width, + margin=self.margin, + offset=offset, + layers=[0])) + + horizontal_layer_grids = left_grids | right_grids + + # Must move to the same layer to find layer 1 corner grids + vertical_layer_grids = set() + for x in top_grids | bottom_grids: + vertical_layer_grids.add(vector3d(x.x, x.y, 1)) + + # Add vias in the overlap points + horizontal_corner_grids = vertical_layer_grids & horizontal_layer_grids + for g in horizontal_corner_grids: + self.add_via(g) + + # The big pin group, but exclude the corners from the pins + pg.grids = (left_grids | right_grids | top_grids | bottom_grids) + pg.enclosures = pg.compute_enclosures() + pg.pins = set(pg.enclosures) + + self.cell.pin_map[name].update(pg.pins) + self.pin_groups[name].append(pg) + self.new_pins[name] = pg.pins + + def get_new_pins(self, name): + return self.new_pins[name] + def add_perimeter_target(self, side="all"): """ This will mark all the cells on the perimeter of the original layout as a target. """ self.rg.add_perimeter_target(side=side) - + def num_pin_components(self, pin_name): """ This returns how many disconnected pin components there are. @@ -1209,17 +1315,34 @@ class router(router_tech): def get_perimeter_pin(self): """ Return the shape of the last routed path that was on the perimeter """ - for v in self.paths[-1]: + lastpath = self.paths[-1] + for v in lastpath: if self.rg.is_target(v): + # Find neighboring grid to make double wide pin + neighbor = v + vector3d(0, 1, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + neighbor = v + vector3d(0, -1, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + neighbor = v + vector3d(1, 0, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + neighbor = v + vector3d(-1, 0, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + + # Else if we came from a different layer, we can only add + # a signle grid return self.convert_track_to_pin(v) - + return None - + def get_ll_pin(self, pin_name): """ Return the lowest, leftest pin group """ keep_pin = None - for index,pg in enumerate(self.pin_groups[pin_name]): + for index, pg in enumerate(self.pin_groups[pin_name]): for pin in pg.enclosures: if not keep_pin: keep_pin = pin @@ -1228,7 +1351,7 @@ class router(router_tech): keep_pin = pin return keep_pin - + def check_all_routed(self, pin_name): """ Check that all pin groups are routed. diff --git a/compiler/router/router_tech.py b/compiler/router/router_tech.py index b3e26f79..6cbbd422 100644 --- a/compiler/router/router_tech.py +++ b/compiler/router/router_tech.py @@ -123,7 +123,7 @@ class router_tech: min_wire_width = drc("minwidth_{0}".format(layer_name), 0, math.inf) - min_width = drc("minwidth_{0}".format(layer_name), self.route_track_width * min_wire_width, math.inf) + min_width = self.route_track_width * drc("minwidth_{0}".format(layer_name), self.route_track_width * min_wire_width, math.inf) min_spacing = drc(str(layer_name)+"_to_"+str(layer_name), self.route_track_width * min_wire_width, math.inf) return (min_width, min_spacing) diff --git a/compiler/router/signal_escape_router.py b/compiler/router/signal_escape_router.py index a9531290..7cc41d97 100644 --- a/compiler/router/signal_escape_router.py +++ b/compiler/router/signal_escape_router.py @@ -17,7 +17,7 @@ class signal_escape_router(router): A router that routes signals to perimeter and makes pins. """ - def __init__(self, layers, design, bbox=None, margin=0, gds_filename=None): + def __init__(self, layers, design, bbox=None, margin=0): """ This will route on layers in design. It will get the blockages from either the gds file name or the design itself (by saving to a gds file). @@ -25,7 +25,6 @@ class signal_escape_router(router): router.__init__(self, layers=layers, design=design, - gds_filename=gds_filename, bbox=bbox, margin=margin) diff --git a/compiler/router/signal_router.py b/compiler/router/signal_router.py index 89edcb01..9fbf871f 100644 --- a/compiler/router/signal_router.py +++ b/compiler/router/signal_router.py @@ -15,12 +15,12 @@ class signal_router(router): route on a given layer. This is limited to two layer routes. """ - def __init__(self, layers, design, gds_filename=None, bbox=None): + def __init__(self, layers, design, bbox=None): """ This will route on layers in design. It will get the blockages from either the gds file name or the design itself (by saving to a gds file). """ - router.__init__(self, layers, design, gds_filename, bbox) + router.__init__(self, layers, design, bbox) def route(self, src, dest, detour_scale=5): """ diff --git a/compiler/router/supply_grid_router.py b/compiler/router/supply_grid_router.py index 8a201474..06831299 100644 --- a/compiler/router/supply_grid_router.py +++ b/compiler/router/supply_grid_router.py @@ -21,7 +21,7 @@ class supply_grid_router(router): routes a grid to connect the supply on the two layers. """ - def __init__(self, layers, design, gds_filename=None, bbox=None): + def __init__(self, layers, design, bbox=None, pin_type=None): """ This will route on layers in design. It will get the blockages from either the gds file name or the design itself (by saving to a gds file). @@ -29,9 +29,9 @@ class supply_grid_router(router): start_time = datetime.now() # Power rail width in minimum wire widths - self.route_track_width = 2 + self.route_track_width = 1 - router.__init__(self, layers, design, gds_filename, bbox, self.route_track_width) + router.__init__(self, layers, design, bbox=bbox, margin=margin, route_track_width=self.route_track_width) # The list of supply rails (grid sets) that may be routed self.supply_rails = {} @@ -357,8 +357,9 @@ class supply_grid_router(router): # This is inefficient since it is non-incremental, but it was # easier to debug. - self.prepare_blockages(pin_name) - + self.prepare_blockages() + self.clear_blockages(self.vdd_name) + # Add the single component of the pin as the source # which unmarks it as a blockage too self.add_pin_component_source(pin_name, index) @@ -369,7 +370,7 @@ class supply_grid_router(router): # Actually run the A* router if not self.run_router(detour_scale=5): - self.write_debug_gds("debug_route.gds", False) + self.write_debug_gds("debug_route.gds") # if index==3 and pin_name=="vdd": # self.write_debug_gds("route.gds",False) diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index ba54ee39..88d02f2e 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -21,7 +21,7 @@ class supply_tree_router(router): routes a grid to connect the supply on the two layers. """ - def __init__(self, layers, design, gds_filename=None, bbox=None): + def __init__(self, layers, design, bbox=None, pin_type=None): """ This will route on layers in design. It will get the blockages from either the gds file name or the design itself (by saving to a gds file). @@ -31,11 +31,22 @@ class supply_tree_router(router): # for prettier routes. self.route_track_width = 1 - router.__init__(self, layers, design, gds_filename, bbox, self.route_track_width) + # The pin escape router already made the bounding box big enough, + # so we can use the regular bbox here. + if pin_type: + debug.check(pin_type in ["left", "right", "top", "bottom", "single", "ring"], + "Invalid pin type {}".format(pin_type)) + self.pin_type = pin_type + router.__init__(self, + layers, + design, + bbox=bbox, + route_track_width=self.route_track_width) def route(self, vdd_name="vdd", gnd_name="gnd"): """ - Route the two nets in a single layer) + Route the two nets in a single layer. + Setting pin stripe will make a power rail on the left side. """ debug.info(1, "Running supply router on {0} and {1}...".format(vdd_name, gnd_name)) self.vdd_name = vdd_name @@ -50,11 +61,20 @@ class supply_tree_router(router): # but this is simplest for now. self.create_routing_grid(signal_grid) - # Get the pin shapes start_time = datetime.now() + + # Get the pin shapes self.find_pins_and_blockages([self.vdd_name, self.gnd_name]) print_time("Finding pins and blockages", datetime.now(), start_time, 3) + # Add side pins if enabled + if self.pin_type in ["left", "right", "top", "bottom"]: + self.add_side_supply_pin(self.vdd_name, side=self.pin_type) + self.add_side_supply_pin(self.gnd_name, side=self.pin_type) + elif self.pin_type == "ring": + self.add_ring_supply_pin(self.vdd_name) + self.add_ring_supply_pin(self.gnd_name) + # Route the supply pins to the supply rails # Route vdd first since we want it to be shorter start_time = datetime.now() @@ -82,21 +102,36 @@ class supply_tree_router(router): debug.info(1, "Routing {0} with {1} pins.".format(pin_name, remaining_components)) + # Save pin center locations + if False: + debug.info(2, "Creating location file {0}_{1}.csv".format(self.cell.name, pin_name)) + f = open("{0}_{1}.csv".format(self.cell.name, pin_name), "w") + pin_size = len(self.pin_groups[pin_name]) + for index1, pg1 in enumerate(self.pin_groups[pin_name]): + location = list(pg1.grids)[0] + f.write("{0},{1},{2}\n".format(location.x, location.y, location.z)) + f.close() + # Create full graph debug.info(2, "Creating adjacency matrix") pin_size = len(self.pin_groups[pin_name]) adj_matrix = [[0] * pin_size for i in range(pin_size)] - for index1,pg1 in enumerate(self.pin_groups[pin_name]): - for index2,pg2 in enumerate(self.pin_groups[pin_name]): + for index1, pg1 in enumerate(self.pin_groups[pin_name]): + for index2, pg2 in enumerate(self.pin_groups[pin_name]): if index1>=index2: continue dist = int(grid_utils.distance_set(list(pg1.grids)[0], pg2.grids)) adj_matrix[index1][index2] = dist # Find MST - debug.info(2, "Finding MinimumSpanning Tree") + debug.info(2, "Finding Minimum Spanning Tree") X = csr_matrix(adj_matrix) + from scipy.sparse import save_npz + #print("Saving {}.npz".format(self.cell.name)) + #save_npz("{}.npz".format(self.cell.name), X) + #exit(1) + Tcsr = minimum_spanning_tree(X) mst = Tcsr.toarray().astype(int) connections = [] @@ -115,8 +150,8 @@ class supply_tree_router(router): # if pin_name == "gnd": # print("\nSRC {}: ".format(src) + str(self.pin_groups[pin_name][src].grids) + str(self.pin_groups[pin_name][src].blockages)) # print("DST {}: ".format(dest) + str(self.pin_groups[pin_name][dest].grids) + str(self.pin_groups[pin_name][dest].blockages)) - # self.write_debug_gds("post_{0}_{1}.gds".format(src, dest), False) - + # self.write_debug_gds("post_{0}_{1}.gds".format(src, dest), False) + #self.write_debug_gds("final.gds", True) #return @@ -128,7 +163,7 @@ class supply_tree_router(router): for unblock_routes in [False, True]: for detour_scale in [5 * pow(2, x) for x in range(5)]: debug.info(2, "Routing {0} to {1} with scale {2}".format(src_idx, dest_idx, detour_scale)) - + # Clear everything in the routing grid. self.rg.reinit() diff --git a/compiler/router/vector3d.py b/compiler/router/vector3d.py index 8830fc36..71709837 100644 --- a/compiler/router/vector3d.py +++ b/compiler/router/vector3d.py @@ -5,9 +5,9 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug import math + class vector3d(): """ This is the vector3d class to represent a 3D coordinate. @@ -22,20 +22,20 @@ class vector3d(): self.x = x[0] self.y = x[1] self.z = x[2] - #will take inputs as the values of a coordinate + # will take inputs as the values of a coordinate else: self.x = x self.y = y self.z = z - self._hash = hash((self.x,self.y,self.z)) + self._hash = hash((self.x, self.y, self.z)) def __str__(self): """ override print function output """ - return "v3d["+str(self.x)+", "+str(self.y)+", "+str(self.z)+"]" + return "v3d[" + str(self.x) + ", " + str(self.y) + ", " + str(self.z) + "]" def __repr__(self): """ override print function output """ - return "v3d["+str(self.x)+", "+str(self.y)+", "+str(self.z)+"]" + return "v3d[" + str(self.x) + ", " + str(self.y) + ", " + str(self.z) + "]" def __setitem__(self, index, value): """ @@ -74,7 +74,6 @@ class vector3d(): """ return vector3d(self.x + other[0], self.y + other[1], self.z + other[2]) - def __radd__(self, other): """ Override + function (right add) @@ -98,7 +97,6 @@ class vector3d(): """ return self._hash - def __rsub__(self, other): """ Override - function (right) @@ -107,7 +105,7 @@ class vector3d(): def rotate(self): """ pass a copy of rotated vector3d, without altering the vector3d! """ - return vector3d(self.y,self.x,self.z) + return vector3d(self.y, self.x, self.z) def scale(self, x_factor, y_factor=None,z_factor=None): """ pass a copy of scaled vector3d, without altering the vector3d! """ @@ -115,7 +113,7 @@ class vector3d(): z_factor=x_factor[2] y_factor=x_factor[1] x_factor=x_factor[0] - return vector3d(self.x*x_factor,self.y*y_factor,self.z*z_factor) + return vector3d(self.x * x_factor, self.y * y_factor, self.z * z_factor) def rotate_scale(self, x_factor, y_factor=None, z_factor=None): """ pass a copy of scaled vector3d, without altering the vector3d! """ @@ -123,25 +121,25 @@ class vector3d(): z_factor=x_factor[2] y_factor=x_factor[1] x_factor=x_factor[0] - return vector3d(self.y*x_factor,self.x*y_factor,self.z*z_factor) + return vector3d(self.y * x_factor, self.x * y_factor, self.z * z_factor) def floor(self): """ Override floor function """ - return vector3d(int(math.floor(self.x)),int(math.floor(self.y)), self.z) + return vector3d(int(math.floor(self.x)), int(math.floor(self.y)), self.z) def ceil(self): """ Override ceil function """ - return vector3d(int(math.ceil(self.x)),int(math.ceil(self.y)), self.z) + return vector3d(int(math.ceil(self.x)), int(math.ceil(self.y)), self.z) def round(self): """ Override round function """ - return vector3d(int(round(self.x)),int(round(self.y)), self.z) + return vector3d(int(round(self.x)), int(round(self.y)), self.z) def __eq__(self, other): """Override the default Equals behavior""" @@ -164,30 +162,29 @@ class vector3d(): def max(self, other): """ Max of both values """ - return vector3d(max(self.x,other.x),max(self.y,other.y),max(self.z,other.z)) + return vector3d(max(self.x, other.x), max(self.y, other.y), max(self.z, other.z)) def min(self, other): """ Min of both values """ - return vector3d(min(self.x,other.x),min(self.y,other.y),min(self.z,other.z)) + return vector3d(min(self.x, other.x), min(self.y, other.y), min(self.z, other.z)) def distance(self, other): """ Return the manhattan distance between two values """ - return abs(self.x-other.x)+abs(self.y-other.y) + return abs(self.x - other.x) + abs(self.y - other.y) def euclidean_distance(self, other): """ Return the euclidean distance between two values """ - return math.sqrt((self.x-other.x)**2+(self.y-other.y)**2) - + return math.sqrt((self.x - other.x)**2 + (self.y - other.y)**2) def adjacent(self, other): """ Is the one grid adjacent in any planar direction to the other """ - if self == other + vector3d(1,0,0): + if self == other + vector3d(1, 0, 0): return True - elif self == other + vector3d(-1,0,0): + elif self == other + vector3d(-1, 0, 0): return True - elif self == other + vector3d(0,1,0): + elif self == other + vector3d(0, 1, 0): return True - elif self == other + vector3d(0,-1,0): + elif self == other + vector3d(0, -1, 0): return True else: return False diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index 599ef666..90855d8e 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -11,6 +11,7 @@ import debug import verify from characterizer import functional from globals import OPTS, print_time +import shutil class sram(): @@ -23,13 +24,7 @@ class sram(): def __init__(self, sram_config, name): sram_config.set_local_config(self) - - # FIXME: adjust this to not directly change OPTS. - # Word-around to have values relevant to OPTS be displayed if not directly set. - OPTS.words_per_row = self.words_per_row - debug.info(1, "Changed OPTS wpr={}".format(self.words_per_row)) - debug.info(1, "OPTS wpr={}".format(OPTS.words_per_row)) - + # reset the static duplicate name checker for unit tests # in case we create more than one SRAM from design import design @@ -66,6 +61,26 @@ class sram(): def gds_write(self, name): self.s.gds_write(name) + # This addresses problems with flat GDS namespaces when we + # want to merge this SRAM with other SRAMs. + if OPTS.uniquify: + import gdsMill + gds = gdsMill.VlsiLayout() + reader = gdsMill.Gds2reader(gds) + reader.loadFromFile(name) + + # Uniquify but skip the library cells since they are hard coded + try: + from tech import library_prefix_name + except ImportError: + library_prefix_name = None + gds.uniquify(library_prefix_name) + + writer = gdsMill.Gds2writer(gds) + unique_name = name.replace(".gds", "_unique.gds") + writer.writeToFile(unique_name) + shutil.move(unique_name, name) + def verilog_write(self, name): self.s.verilog_write(name) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 6bc2cd43..a6abeba6 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -9,6 +9,7 @@ from vector import vector from sram_base import sram_base from contact import m2_via from channel_route import channel_route +from router_tech import router_tech from globals import OPTS @@ -101,7 +102,7 @@ class sram_1bank(sram_base): # Place with an initial wide channel (from above) self.place_dffs() - + # Route the channel and set to the new data bus size # We need to temporarily add some pins for the x offsets # but we'll remove them so that they have the right y @@ -109,7 +110,7 @@ class sram_1bank(sram_base): self.add_layout_pins(add_vias=False) self.route_dffs(add_routes=False) self.remove_layout_pins() - + # Re-place with the new channel size self.place_dffs() @@ -120,8 +121,9 @@ class sram_1bank(sram_base): port = 0 # The row address bits are placed above the control logic aligned on the right. x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width - # It is above the control logic but below the top of the bitcell array - y_offset = max(self.control_logic_insts[port].uy(), self.bank.predecoder_height) + # It is above the control logic and the predecoder array + y_offset = max(self.control_logic_insts[port].uy(), self.bank.predecoder_top) + self.row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(self.row_addr_pos[port]) @@ -130,7 +132,7 @@ class sram_1bank(sram_base): # The row address bits are placed above the control logic aligned on the left. x_offset = self.control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width # If it can be placed above the predecoder and below the control logic, do it - y_offset = self.bank.bank_array_ll.y + y_offset = self.bank.predecoder_bottom self.row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(self.row_addr_pos[port], mirror="XY") @@ -268,7 +270,7 @@ class sram_1bank(sram_base): signal, signal + "{}".format(port), start_layer=pin_layer) - + if port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): self.add_io_pin(self.data_dff_insts[port], @@ -301,15 +303,21 @@ class sram_1bank(sram_base): self.add_io_pin(self.wmask_dff_insts[port], "din_{}".format(bit), "wmask{0}[{1}]".format(port, bit), - start_layer=pin_layer) + start_layer=pin_layer) if port in self.write_ports: - for bit in range(self.num_spare_cols): + if self.num_spare_cols == 1: self.add_io_pin(self.spare_wen_dff_insts[port], - "din_{}".format(bit), - "spare_wen{0}[{1}]".format(port, bit), - start_layer=pin_layer) - + "din_{}".format(0), + "spare_wen{0}".format(port), + start_layer=pin_layer) + else: + for bit in range(self.num_spare_cols): + self.add_io_pin(self.spare_wen_dff_insts[port], + "din_{}".format(bit), + "spare_wen{0}[{1}]".format(port, bit), + start_layer=pin_layer) + def route_layout(self): """ Route a single bank SRAM """ @@ -325,14 +333,35 @@ class sram_1bank(sram_base): # they might create some blockages self.add_layout_pins() + # Some technologies have an isolation + self.add_dnwell(inflate=2.5) + + # We need the initial bbox for the supply rings later + # because the perimeter pins will change the bbox # Route the pins to the perimeter + pre_bbox = None if OPTS.perimeter_pins: - self.route_escape_pins() - + rt = router_tech(self.supply_stack, 1) + + if OPTS.supply_pin_type in ["ring", "left", "right", "top", "bottom"]: + big_margin = 12 * rt.track_width + little_margin = 2 * rt.track_width + else: + big_margin = 6 * rt.track_width + little_margin = 0 + + pre_bbox = self.get_bbox(side="ring", + big_margin=rt.track_width) + + bbox = self.get_bbox(side=OPTS.supply_pin_type, + big_margin=big_margin, + little_margin=little_margin) + self.route_escape_pins(bbox) + # Route the supplies first since the MST is not blockage aware # and signals can route to anywhere on sides (it is flexible) - self.route_supplies() - + self.route_supplies(pre_bbox) + def route_dffs(self, add_routes=True): for port in self.all_ports: @@ -348,7 +377,7 @@ class sram_1bank(sram_base): self.route_data_dffs(port, add_routes) def route_col_addr_dffs(self, port): - + route_map = [] # column mux dff is routed on it's own since it is to the far end @@ -362,6 +391,7 @@ class sram_1bank(sram_base): if len(route_map) > 0: + # This layer stack must be different than the data dff layer stack layer_stack = self.m1_stack if port == 0: @@ -371,11 +401,11 @@ class sram_1bank(sram_base): offset=offset, layer_stack=layer_stack, parent=self) - # This causes problem in magic since it sometimes cannot extract connectivity of isntances + # This causes problem in magic since it sometimes cannot extract connectivity of instances # with no active devices. self.add_inst(cr.name, cr) self.connect_inst([]) - #self.add_flat_inst(cr.name, cr) + # self.add_flat_inst(cr.name, cr) else: offset = vector(0, self.bank.height + self.m3_pitch) @@ -383,15 +413,15 @@ class sram_1bank(sram_base): offset=offset, layer_stack=layer_stack, parent=self) - # This causes problem in magic since it sometimes cannot extract connectivity of isntances + # This causes problem in magic since it sometimes cannot extract connectivity of instances # with no active devices. self.add_inst(cr.name, cr) self.connect_inst([]) - #self.add_flat_inst(cr.name, cr) - + # self.add_flat_inst(cr.name, cr) + def route_data_dffs(self, port, add_routes): route_map = [] - + # wmask dff if self.num_wmasks > 0 and port in self.write_ports: dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)] @@ -418,40 +448,48 @@ class sram_1bank(sram_base): if len(route_map) > 0: - # The write masks will have blockages on M1 - if self.num_wmasks > 0 and port in self.write_ports: - layer_stack = self.m3_stack - else: - layer_stack = self.m1_stack - + # This layer stack must be different than the column addr dff layer stack + layer_stack = self.m3_stack if port == 0: + # This is relative to the bank at 0,0 or the s_en which is routed on M3 also + if "s_en" in self.control_logic_insts[port].mod.pin_map: + y_bottom = min(0, self.control_logic_insts[port].get_pin("s_en").by()) + else: + y_bottom = 0 + + y_offset = y_bottom - self.data_bus_size[port] + 2 * self.m3_pitch offset = vector(self.control_logic_insts[port].rx() + self.dff.width, - - self.data_bus_size[port] + 2 * self.m3_pitch) + y_offset) cr = channel_route(netlist=route_map, offset=offset, layer_stack=layer_stack, parent=self) if add_routes: - # This causes problem in magic since it sometimes cannot extract connectivity of isntances + # This causes problem in magic since it sometimes cannot extract connectivity of instances # with no active devices. self.add_inst(cr.name, cr) self.connect_inst([]) - #self.add_flat_inst(cr.name, cr) + # self.add_flat_inst(cr.name, cr) else: self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap else: + if "s_en" in self.control_logic_insts[port].mod.pin_map: + y_top = max(self.bank.height, self.control_logic_insts[port].get_pin("s_en").uy()) + else: + y_top = self.bank.height + y_offset = y_top + self.m3_pitch offset = vector(0, - self.bank.height + self.m3_pitch) + y_offset) cr = channel_route(netlist=route_map, offset=offset, layer_stack=layer_stack, parent=self) if add_routes: - # This causes problem in magic since it sometimes cannot extract connectivity of isntances + # This causes problem in magic since it sometimes cannot extract connectivity of instances # with no active devices. self.add_inst(cr.name, cr) self.connect_inst([]) - #self.add_flat_inst(cr.name, cr) + # self.add_flat_inst(cr.name, cr) else: self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap @@ -527,13 +565,13 @@ class sram_1bank(sram_base): # Only input (besides pins) is the replica bitline src_pin = self.control_logic_insts[port].get_pin("rbl_bl") dest_pin = self.bank_inst.get_pin("rbl_bl_{0}_{0}".format(port)) - self.add_wire(self.m2_stack[::-1], + self.add_wire(self.m3_stack, [src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()]) self.add_via_stack_center(from_layer=src_pin.layer, - to_layer="m2", + to_layer="m4", offset=src_pin.center()) self.add_via_stack_center(from_layer=dest_pin.layer, - to_layer="m2", + to_layer="m3", offset=dest_pin.center()) def route_row_addr_dff(self): @@ -612,7 +650,7 @@ class sram_1bank(sram_base): # Sanity check in case it was forgotten if inst_name.find("x") != 0: inst_name = "x" + inst_name - return self.bank_inst.mod.get_cell_name(inst_name + ".x" + self.bank_inst.name, row, col) + return self.bank_inst.mod.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bank_inst.name, row, col) def get_bank_num(self, inst_name, row, col): return 0 diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 7621f67b..da479298 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -15,6 +15,7 @@ from design import design from verilog import verilog from lef import lef from sram_factory import factory +from tech import spice class sram_base(design, verilog, lef): @@ -40,6 +41,14 @@ class sram_base(design, verilog, lef): if not self.num_spare_cols: self.num_spare_cols = 0 + try: + from tech import power_grid + self.supply_stack = power_grid + except ImportError: + # if no power_grid is specified by tech we use sensible defaults + # Route a M3/M4 grid + self.supply_stack = self.m3_stack + def add_pins(self): """ Add pins for entire SRAM. """ @@ -75,14 +84,29 @@ class sram_base(design, verilog, lef): for port in self.write_ports: for bit in range(self.num_wmasks): self.add_pin("wmask{0}[{1}]".format(port, bit), "INPUT") - for bit in range(self.num_spare_cols): - self.add_pin("spare_wen{0}[{1}]".format(port, bit), "INPUT") + if self.num_spare_cols == 1: + self.add_pin("spare_wen{0}".format(port), "INPUT") + else: + for bit in range(self.num_spare_cols): + self.add_pin("spare_wen{0}[{1}]".format(port, bit), "INPUT") for port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT") - self.add_pin("vdd", "POWER") - self.add_pin("gnd", "GROUND") + # Standard supply and ground names + try: + self.vdd_name = spice["power"] + except KeyError: + self.vdd_name = "vdd" + try: + self.gnd_name = spice["ground"] + except KeyError: + self.gnd_name = "gnd" + + self.add_pin(self.vdd_name, "POWER") + self.add_pin(self.gnd_name, "GROUND") + self.ext_supplies = [self.vdd_name, self.gnd_name] + self.ext_supply = {"vdd" : self.vdd_name, "gnd" : self.gnd_name} def add_global_pex_labels(self): """ @@ -217,66 +241,90 @@ class sram_base(design, verilog, lef): def create_modules(self): debug.error("Must override pure virtual function.", -1) - def route_supplies(self): + def route_supplies(self, bbox=None): """ Route the supply grid and connect the pins to them. """ # Copy the pins to the top level # This will either be used to route or left unconnected. for pin_name in ["vdd", "gnd"]: for inst in self.insts: - self.copy_power_pins(inst, pin_name) + self.copy_power_pins(inst, pin_name, self.ext_supply[pin_name]) if not OPTS.route_supplies: # Do not route the power supply (leave as must-connect pins) return - - try: - from tech import power_grid - grid_stack = power_grid - except ImportError: - # if no power_grid is specified by tech we use sensible defaults - # Route a M3/M4 grid - grid_stack = self.m3_stack - - if OPTS.route_supplies == "grid": + elif OPTS.route_supplies == "grid": from supply_grid_router import supply_grid_router as router - elif OPTS.route_supplies: + else: from supply_tree_router import supply_tree_router as router - - rtr=router(grid_stack, self) + rtr=router(layers=self.supply_stack, + design=self, + bbox=bbox, + pin_type=OPTS.supply_pin_type) + rtr.route() - # Find the lowest leftest pin for vdd and gnd - for pin_name in ["vdd", "gnd"]: - # Copy the pin shape(s) to rectangles - for pin in self.get_pins(pin_name): + if OPTS.supply_pin_type in ["left", "right", "top", "bottom", "ring"]: + # Find the lowest leftest pin for vdd and gnd + for pin_name in ["vdd", "gnd"]: + # Copy the pin shape(s) to rectangles + for pin in self.get_pins(pin_name): + self.add_rect(pin.layer, + pin.ll(), + pin.width(), + pin.height()) + + # Remove the pin shape(s) + self.remove_layout_pin(pin_name) + + # Get new pins + pins = rtr.get_new_pins(pin_name) + for pin in pins: + self.add_layout_pin(self.ext_supply[pin_name], + pin.layer, + pin.ll(), + pin.width(), + pin.height()) + + elif OPTS.route_supplies and OPTS.supply_pin_type == "single": + # Update these as we may have routed outside the region (perimeter pins) + lowest_coord = self.find_lowest_coords() + + # Find the lowest leftest pin for vdd and gnd + for pin_name in ["vdd", "gnd"]: + # Copy the pin shape(s) to rectangles + for pin in self.get_pins(pin_name): + self.add_rect(pin.layer, + pin.ll(), + pin.width(), + pin.height()) + + # Remove the pin shape(s) + self.remove_layout_pin(pin_name) + + # Get the lowest, leftest pin + pin = rtr.get_ll_pin(pin_name) + + pin_width = 2 * getattr(self, "{}_width".format(pin.layer)) + + # Add it as an IO pin to the perimeter + route_width = pin.rx() - lowest_coord.x + pin_offset = vector(lowest_coord.x, pin.by()) self.add_rect(pin.layer, - pin.ll(), - pin.width(), + pin_offset, + route_width, pin.height()) - # Remove the pin shape(s) - self.remove_layout_pin(pin_name) + self.add_layout_pin(self.ext_supply[pin_name], + pin.layer, + pin_offset, + pin_width, + pin.height()) + else: + # Grid is left with many top level pins + pass - # Get the lowest, leftest pin - pin = rtr.get_ll_pin(pin_name) - - # Add it as an IO pin to the perimeter - lowest_coord = self.find_lowest_coords() - route_width = pin.rx() - lowest_coord.x - pin_width = 2 * getattr(self, "{}_width".format(pin.layer)) - pin_offset = vector(lowest_coord.x, pin.by()) - self.add_layout_pin(pin_name, - pin.layer, - pin_offset, - pin_width, - pin.height()) - self.add_rect(pin.layer, - pin_offset, - route_width, - pin.height()) - - def route_escape_pins(self): + def route_escape_pins(self, bbox): """ Add the top-level pins for a single bank SRAM with control. """ @@ -292,7 +340,7 @@ class sram_base(design, verilog, lef): pins_to_route.append("{0}{1}".format(signal, port)) else: pins_to_route.append("{0}{1}".format(signal, port)) - + if port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): pins_to_route.append("din{0}[{1}]".format(port, bit)) @@ -313,13 +361,16 @@ class sram_base(design, verilog, lef): pins_to_route.append("wmask{0}[{1}]".format(port, bit)) if port in self.write_ports: - for bit in range(self.num_spare_cols): - pins_to_route.append("spare_wen{0}[{1}]".format(port, bit)) + if self.num_spare_cols == 1: + pins_to_route.append("spare_wen{0}".format(port)) + else: + for bit in range(self.num_spare_cols): + pins_to_route.append("spare_wen{0}[{1}]".format(port, bit)) from signal_escape_router import signal_escape_router as router rtr=router(layers=self.m3_stack, design=self, - margin=4 * self.m3_pitch) + bbox=bbox) rtr.escape_route(pins_to_route) def compute_bus_sizes(self): @@ -427,6 +478,12 @@ class sram_base(design, verilog, lef): self.bitcell = factory.create(module_type=OPTS.bitcell) self.dff = factory.create(module_type="dff") + # Create the bank module (up to four are instantiated) + self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") + self.add_mod(self.bank) + + self.num_spare_cols = self.bank.num_spare_cols + # Create the address and control flops (but not the clk) self.row_addr_dff = factory.create("dff_array", module_name="row_addr_dff", rows=self.row_addr_size, columns=1) self.add_mod(self.row_addr_dff) @@ -448,10 +505,6 @@ class sram_base(design, verilog, lef): self.spare_wen_dff = factory.create("dff_array", module_name="spare_wen_dff", rows=1, columns=self.num_spare_cols) self.add_mod(self.spare_wen_dff) - # Create the bank module (up to four are instantiated) - self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") - self.add_mod(self.bank) - # Create bank decoder if(self.num_banks > 1): self.add_multi_bank_modules() @@ -500,13 +553,13 @@ class sram_base(design, verilog, lef): temp.append("rbl_bl{0}".format(port)) for port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): - temp.append("bank_din{0}[{1}]".format(port, bit)) + temp.append("bank_din{0}_{1}".format(port, bit)) for port in self.all_ports: for bit in range(self.bank_addr_size): - temp.append("a{0}[{1}]".format(port, bit)) + temp.append("a{0}_{1}".format(port, bit)) if(self.num_banks > 1): for port in self.all_ports: - temp.append("bank_sel{0}[{1}]".format(port, bank_num)) + temp.append("bank_sel{0}_{1}".format(port, bank_num)) for port in self.read_ports: temp.append("s_en{0}".format(port)) for port in self.all_ports: @@ -514,12 +567,12 @@ class sram_base(design, verilog, lef): for port in self.write_ports: temp.append("w_en{0}".format(port)) for bit in range(self.num_wmasks): - temp.append("bank_wmask{}[{}]".format(port, bit)) + temp.append("bank_wmask{0}_{1}".format(port, bit)) for bit in range(self.num_spare_cols): - temp.append("bank_spare_wen{0}[{1}]".format(port, bit)) + temp.append("bank_spare_wen{0}_{1}".format(port, bit)) for port in self.all_ports: temp.append("wl_en{0}".format(port)) - temp.extend(["vdd", "gnd"]) + temp.extend(self.ext_supplies) self.connect_inst(temp) return self.bank_insts[-1] @@ -566,9 +619,9 @@ class sram_base(design, verilog, lef): outputs = [] for bit in range(self.row_addr_size): inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size)) - outputs.append("a{}[{}]".format(port, bit + self.col_addr_size)) + outputs.append("a{}_{}".format(port, bit + self.col_addr_size)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) return insts @@ -584,9 +637,9 @@ class sram_base(design, verilog, lef): outputs = [] for bit in range(self.col_addr_size): inputs.append("addr{}[{}]".format(port, bit)) - outputs.append("a{}[{}]".format(port, bit)) + outputs.append("a{}_{}".format(port, bit)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) return insts @@ -606,9 +659,9 @@ class sram_base(design, verilog, lef): outputs = [] for bit in range(self.word_size + self.num_spare_cols): inputs.append("din{}[{}]".format(port, bit)) - outputs.append("bank_din{}[{}]".format(port, bit)) + outputs.append("bank_din{}_{}".format(port, bit)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) return insts @@ -628,9 +681,9 @@ class sram_base(design, verilog, lef): outputs = [] for bit in range(self.num_wmasks): inputs.append("wmask{}[{}]".format(port, bit)) - outputs.append("bank_wmask{}[{}]".format(port, bit)) + outputs.append("bank_wmask{}_{}".format(port, bit)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) return insts @@ -650,9 +703,9 @@ class sram_base(design, verilog, lef): outputs = [] for bit in range(self.num_spare_cols): inputs.append("spare_wen{}[{}]".format(port, bit)) - outputs.append("bank_spare_wen{}[{}]".format(port, bit)) + outputs.append("bank_spare_wen{}_{}".format(port, bit)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) return insts @@ -683,7 +736,7 @@ class sram_base(design, verilog, lef): if port in self.write_ports: temp.append("w_en{}".format(port)) temp.append("p_en_bar{}".format(port)) - temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"]) + temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port)] + self.ext_supplies) self.connect_inst(temp) return insts @@ -726,3 +779,15 @@ class sram_base(design, verilog, lef): Clears the bit exclusions """ self.bank.clear_exclude_bits() + + def graph_exclude_column_mux(self, column_include_num, port): + """ + Excludes all columns muxes unrelated to the target bit being simulated. + """ + self.bank.graph_exclude_column_mux(column_include_num, port) + + def graph_clear_column_mux(self, port): + """ + Clear mux exclusions to allow different bit tests. + """ + self.bank.graph_clear_column_mux(port) diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index c2a542b9..d28f28a8 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -17,11 +17,27 @@ class sram_config: def __init__(self, word_size, num_words, write_size=None, num_banks=1, words_per_row=None, num_spare_rows=0, num_spare_cols=0): self.word_size = word_size self.num_words = num_words - self.write_size = write_size + # Don't add a write mask if it is the same size as the data word + if write_size and write_size==word_size: + self.write_size = None + else: + self.write_size = write_size self.num_banks = num_banks self.num_spare_rows = num_spare_rows self.num_spare_cols = num_spare_cols + try: + from tech import array_row_multiple + self.array_row_multiple = array_row_multiple + except ImportError: + self.array_row_multiple = 1 + try: + from tech import array_col_multiple + self.array_col_multiple = array_col_multiple + except ImportError: + self.array_col_multiple = 1 + + # This will get over-written when we determine the organization self.words_per_row = words_per_row @@ -63,6 +79,10 @@ class sram_config: self.recompute_sizes() + # Set word_per_row in OPTS + OPTS.words_per_row = self.words_per_row + debug.info(1, "Set SRAM Words Per Row={}".format(OPTS.words_per_row)) + def recompute_sizes(self): """ Calculate the auxiliary values assuming fixed number of words per row. @@ -91,6 +111,14 @@ class sram_config: + " Col addr size: {}".format(self.col_addr_size) + " Bank addr size: {}".format(self.bank_addr_size)) + num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports + if num_ports == 1: + if ((self.num_cols + num_ports + self.num_spare_cols) % self.array_col_multiple != 0): + debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, self.array_col_multiple), -1) + + if ((self.num_rows + num_ports) % self.array_row_multiple != 0): + debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.num_rows + num_ports, self.array_row_multiple), -1) + def estimate_words_per_row(self, tentative_num_cols, word_size): """ This provides a heuristic rounded estimate for the number of words diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index e641bbdb..916a4356 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -23,7 +23,15 @@ class array_test(openram_test): globals.init_openram(config_file) debug.info(2, "Testing 8x8 array for 6t_cell") - a = factory.create(module_type="bitcell_array", cols=8, rows=8) + + if OPTS.tech_name == "sky130": + num_spare_rows = 1 + num_spare_cols = 1 + else: + num_spare_rows = 0 + num_spare_cols = 0 + + a = factory.create(module_type="bitcell_array", cols=8 + num_spare_cols, rows=8 + num_spare_rows) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index f61f365c..ae55ba3e 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -58,9 +58,9 @@ class hierarchical_decoder_test(openram_test): self.local_check(a) # Checks 3 x 4x16 and 4-input NAND decoder - # debug.info(1, "Testing 4096 row sample for hierarchical_decoder") - # a = factory.create(module_type="hierarchical_decoder", num_outputs=4096) - # self.local_check(a) + #debug.info(1, "Testing 4096 row sample for hierarchical_decoder") + #a = factory.create(module_type="hierarchical_decoder", num_outputs=4096) + #self.local_check(a) globals.end_openram() diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py index 1bd91673..c8d50a53 100755 --- a/compiler/tests/14_replica_column_test.py +++ b/compiler/tests/14_replica_column_test.py @@ -19,9 +19,19 @@ class replica_column_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) + if OPTS.tech_name == "sky130": + num_spare_rows = 1 + num_spare_cols = 1 + else: + num_spare_rows = 0 + num_spare_cols = 0 debug.info(2, "Testing replica column for single port") - a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1) + a = factory.create(module_type="replica_column", + rows=4 + num_spare_rows, + rbl=[1, 0], + replica_bit=1, + column_offset=num_spare_cols) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/20_sram_1bank_ring_test.py b/compiler/tests/20_sram_1bank_ring_test.py new file mode 100755 index 00000000..e34920c2 --- /dev/null +++ b/compiler/tests/20_sram_1bank_ring_test.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class sram_1bank_nomux_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.supply_pin_type = "ring" + from sram_config import sram_config + c = sram_config(word_size=4, + num_words=16, + num_banks=1) + + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 6a5e8f52..584e705f 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -50,7 +50,11 @@ class timing_sram_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] - data, port_data = d.analyze(probe_address, probe_data, slews, loads) + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) + data, port_data = d.analyze(probe_address, probe_data, load_slews) #Combine info about port into all data data.update(port_data[0]) diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 634b2982..9154502e 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -45,8 +45,8 @@ class timing_setup_test(openram_test): 'setup_times_HL': [0.16357419999999998], 'setup_times_LH': [0.1757812]} elif OPTS.tech_name == "sky130": - golden_data = {'hold_times_HL': [-0.05615234], - 'hold_times_LH': [-0.03173828], + golden_data = {'hold_times_HL': [-0.03173828], + 'hold_times_LH': [-0.05615234], 'setup_times_HL': [0.078125], 'setup_times_LH': [0.1025391]} else: diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index e5c4b96d..28c3def1 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -55,13 +55,17 @@ class model_delay_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) # Run a spice characterization - spice_data, port_data = d.analyze(probe_address, probe_data, slews, loads) + spice_data, port_data = d.analyze(probe_address, probe_data, load_slews) spice_data.update(port_data[0]) # Run analytical characterization - model_data, port_data = m.get_lib_values(slews, loads) + model_data, port_data = m.get_lib_values(load_slews) model_data.update(port_data[0]) # Only compare the delays @@ -79,6 +83,9 @@ class model_delay_test(openram_test): else: self.assertTrue(False) # other techs fail + print('spice_delays', spice_delays) + print('model_delays', model_delays) + # Check if no too many or too few results self.assertTrue(len(spice_delays.keys())==len(model_delays.keys())) diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py index 6d1b5567..f5bcc658 100755 --- a/compiler/tests/21_ngspice_delay_extra_rows_test.py +++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py @@ -51,7 +51,11 @@ class timing_sram_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] - data, port_data = d.analyze(probe_address, probe_data, slews, loads) + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) + data, port_data = d.analyze(probe_address, probe_data, load_slews) #Combine info about port into all data data.update(port_data[0]) diff --git a/compiler/tests/21_ngspice_delay_global_test.py b/compiler/tests/21_ngspice_delay_global_test.py index 47def503..78b764f4 100755 --- a/compiler/tests/21_ngspice_delay_global_test.py +++ b/compiler/tests/21_ngspice_delay_global_test.py @@ -58,7 +58,11 @@ class timing_sram_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] - data, port_data = d.analyze(probe_address, probe_data, slews, loads) + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) + data, port_data = d.analyze(probe_address, probe_data, load_slews) #Combine info about port into all data data.update(port_data[0]) diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 9a0d224c..15fdaca3 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -50,7 +50,11 @@ class timing_sram_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] - data, port_data = d.analyze(probe_address, probe_data, slews, loads) + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) + data, port_data = d.analyze(probe_address, probe_data, load_slews) #Combine info about port into all data data.update(port_data[0]) diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index dab02e7d..9bda2c2c 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -45,8 +45,8 @@ class timing_setup_test(openram_test): 'setup_times_HL': [0.1757812], 'setup_times_LH': [0.1879883]} elif OPTS.tech_name == "sky130": - golden_data = {'hold_times_HL': [-0.05615234], - 'hold_times_LH': [-0.03173828], + golden_data = {'hold_times_HL': [-0.03173828], + 'hold_times_LH': [-0.05615234], 'setup_times_HL': [0.078125], 'setup_times_LH': [0.1025391]} else: diff --git a/compiler/tests/21_regression_delay_test.py b/compiler/tests/21_regression_delay_test.py new file mode 100755 index 00000000..9d0c50c8 --- /dev/null +++ b/compiler/tests/21_regression_delay_test.py @@ -0,0 +1,67 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +# @unittest.skip("SKIPPING 21_regression_model_test") +class regression_model_test(openram_test): + """ Compare the accuracy of the analytical model with a spice simulation. """ + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import linear_regression + from characterizer import neural_network + from sram import sram + from sram_config import sram_config + c = sram_config(word_size=1, + num_words=16, + num_banks=1) + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") + s = factory.create(module_type="sram", sram_config=c) + + tempspice = OPTS.openram_temp + "temp.sp" + s.sp_write(tempspice) + + probe_address = "1" * s.s.addr_size + probe_data = s.s.word_size - 1 + debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data)) + + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + + #m = linear_regression(s.s, tempspice, corner) + m = neural_network(s.s, tempspice, corner) + only_test = ['rise_delay'] + scores = m.cross_validation(only_test) + accuracy_requirement = 0.75 + self.assertTrue(scores['rise_delay'] >= accuracy_requirement) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_xyce_delay_test.py b/compiler/tests/21_xyce_delay_test.py new file mode 100755 index 00000000..63798931 --- /dev/null +++ b/compiler/tests/21_xyce_delay_test.py @@ -0,0 +1,106 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class timing_sram_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.spice_name="xyce" + OPTS.analytical_delay = False + OPTS.netlist_only = True + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import delay + from sram_config import sram_config + c = sram_config(word_size=4, + num_words=16, + num_banks=1) + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") + s = factory.create(module_type="sram", sram_config=c) + + tempspice = OPTS.openram_temp + "temp.sp" + s.sp_write(tempspice) + + probe_address = "1" * s.s.addr_size + probe_data = s.s.word_size - 1 + debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data)) + + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + d = delay(s.s, tempspice, corner) + import tech + loads = [tech.spice["dff_in_cap"]*4] + slews = [tech.spice["rise_time"]*2] + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) + data, port_data = d.analyze(probe_address, probe_data, load_slews) + # Combine info about port into all data + data.update(port_data[0]) + + if OPTS.tech_name == "freepdk45": + golden_data = {'delay_hl': [0.24042560000000002], + 'delay_lh': [0.24042560000000002], + 'disabled_read0_power': [0.8981647999999998], + 'disabled_read1_power': [0.9101543999999998], + 'disabled_write0_power': [0.9270382999999998], + 'disabled_write1_power': [0.9482969999999998], + 'leakage_power': 2.9792199999999998, + 'min_period': 0.938, + 'read0_power': [1.1107930999999998], + 'read1_power': [1.1143252999999997], + 'slew_hl': [0.2800772], + 'slew_lh': [0.2800772], + 'write0_power': [1.1667769], + 'write1_power': [1.0986076999999999]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'delay_hl': [1.884186], + 'delay_lh': [1.884186], + 'disabled_read0_power': [20.86336], + 'disabled_read1_power': [22.10636], + 'disabled_write0_power': [22.62321], + 'disabled_write1_power': [23.316010000000002], + 'leakage_power': 13.351170000000002, + 'min_period': 7.188, + 'read0_power': [29.90159], + 'read1_power': [30.47858], + 'slew_hl': [2.042723], + 'slew_lh': [2.042723], + 'write0_power': [32.13199], + 'write1_power': [28.46703]} + else: + self.assertTrue(False) # other techs fail + # Check if no too many or too few results + self.assertTrue(len(data.keys())==len(golden_data.keys())) + + self.assertTrue(self.check_golden_data(data,golden_data,0.25)) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_xyce_setuphold_test.py b/compiler/tests/21_xyce_setuphold_test.py new file mode 100755 index 00000000..3aabce06 --- /dev/null +++ b/compiler/tests/21_xyce_setuphold_test.py @@ -0,0 +1,67 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS + + +class timing_setup_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.spice_name="Xyce" + OPTS.analytical_delay = False + OPTS.netlist_only = True + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import setup_hold + import tech + slews = [tech.spice["rise_time"]*2] + + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + sh = setup_hold(corner) + data = sh.analyze(slews,slews) + if OPTS.tech_name == "freepdk45": + golden_data = {'hold_times_HL': [-0.0158691], + 'hold_times_LH': [-0.0158691], + 'setup_times_HL': [0.026855499999999997], + 'setup_times_LH': [0.032959]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'hold_times_HL': [-0.0805664], + 'hold_times_LH': [-0.11718749999999999], + 'setup_times_HL': [0.16357419999999998], + 'setup_times_LH': [0.1757812]} + elif OPTS.tech_name == "sky130": + golden_data = {'hold_times_HL': [-0.03173828], + 'hold_times_LH': [-0.05615234], + 'setup_times_HL': [0.078125], + 'setup_times_LH': [0.1025391]} + else: + self.assertTrue(False) # other techs fail + + # Check if no too many or too few results + self.assertTrue(len(data.keys())==len(golden_data.keys())) + + self.assertTrue(self.check_golden_data(data,golden_data,0.25)) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py index c84c70a5..0e3a0f27 100755 --- a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py @@ -16,7 +16,7 @@ from sram_factory import factory import debug -#@unittest.skip("SKIPPING 22_sram_1bank_2mux_sparecols_func_test") +@unittest.skip("SKIPPING 22_sram_1bank_2mux_sparecols_func_test") class sram_1bank_2mux_sparecols_func_test(openram_test): def runTest(self): diff --git a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py index 0d649ace..a2fa6d88 100755 --- a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py @@ -16,7 +16,7 @@ from sram_factory import factory import debug -#@unittest.skip("SKIPPING 22_sram_func_test") +@unittest.skip("SKIPPING 22_sram_func_test") class sram_1bank_nomux_sparecols_func_test(openram_test): def runTest(self): diff --git a/compiler/tests/50_riscv_1k_1rw1r_func_test.py b/compiler/tests/50_riscv_1k_1rw1r_func_test.py new file mode 100755 index 00000000..6cd494aa --- /dev/null +++ b/compiler/tests/50_riscv_1k_1rw1r_func_test.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + #OPTS.local_array_size = 16 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=256, + num_banks=1) + + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner, cycles=100) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_1k_1rw_func_test.py b/compiler/tests/50_riscv_1k_1rw_func_test.py new file mode 100755 index 00000000..a99fba03 --- /dev/null +++ b/compiler/tests/50_riscv_1k_1rw_func_test.py @@ -0,0 +1,66 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + #OPTS.local_array_size = 16 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=256, + num_banks=1, + num_spare_rows=1, + num_spare_cols=1) + + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner, cycles=3) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_func_test.py b/compiler/tests/50_riscv_1rw1r_func_test.py similarity index 94% rename from compiler/tests/50_riscv_func_test.py rename to compiler/tests/50_riscv_1rw1r_func_test.py index 5bd55e96..19609159 100755 --- a/compiler/tests/50_riscv_func_test.py +++ b/compiler/tests/50_riscv_1rw1r_func_test.py @@ -24,7 +24,8 @@ class riscv_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True - OPTS.local_array_size = 16 + OPTS.trim_netlist = False + OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 @@ -38,7 +39,7 @@ class riscv_func_test(openram_test): from sram_config import sram_config c = sram_config(word_size=32, write_size=8, - num_words=256, + num_words=32, num_banks=1) c.words_per_row=1 c.recompute_sizes() @@ -49,7 +50,7 @@ class riscv_func_test(openram_test): c.num_banks)) s = factory.create(module_type="sram", sram_config=c) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) - f = functional(s.s, corner=corner) + f = functional(s.s, corner=corner, cycles=25) (fail, error) = f.run() self.assertTrue(fail, error) diff --git a/compiler/tests/50_riscv_phys_test.py b/compiler/tests/50_riscv_1rw1r_phys_test.py similarity index 97% rename from compiler/tests/50_riscv_phys_test.py rename to compiler/tests/50_riscv_1rw1r_phys_test.py index af2e2312..40ae942f 100755 --- a/compiler/tests/50_riscv_phys_test.py +++ b/compiler/tests/50_riscv_1rw1r_phys_test.py @@ -16,7 +16,7 @@ from sram_factory import factory import debug -@unittest.skip("SKIPPING 50_riscv_phys_test") +# @unittest.skip("SKIPPING 50_riscv_phys_test") class riscv_phys_test(openram_test): def runTest(self): diff --git a/compiler/tests/50_riscv_1rw_func_test.py b/compiler/tests/50_riscv_1rw_func_test.py new file mode 100755 index 00000000..c77f21d1 --- /dev/null +++ b/compiler/tests/50_riscv_1rw_func_test.py @@ -0,0 +1,73 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + if OPTS.tech_name == "sky130": + num_spare_rows = 1 + num_spare_cols = 1 + else: + num_spare_rows = 0 + num_spare_cols = 0 + + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=64, + num_banks=1, + num_spare_cols=num_spare_cols, + num_spare_rows=num_spare_rows) + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner, cycles=25) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_1rw_phys_test.py b/compiler/tests/50_riscv_1rw_phys_test.py new file mode 100755 index 00000000..a2822b09 --- /dev/null +++ b/compiler/tests/50_riscv_1rw_phys_test.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +# @unittest.skip("SKIPPING 50_riscv_phys_test") +class riscv_phys_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + OPTS.local_array_size = 16 + globals.setup_bitcell() + OPTS.route_supplies = False + OPTS.perimeter_pins = False + + c = sram_config(word_size=32, + write_size=8, + num_words=32, + num_banks=1, + num_spare_rows=1, + num_spare_cols=1) + c.words_per_row=2 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_2k_1rw1r_func_test.py b/compiler/tests/50_riscv_2k_1rw1r_func_test.py new file mode 100755 index 00000000..2fa1ec47 --- /dev/null +++ b/compiler/tests/50_riscv_2k_1rw1r_func_test.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + #OPTS.local_array_size = 16 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=512, + num_banks=1) + + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner, cycles=100) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_2k_1rw_func_test.py b/compiler/tests/50_riscv_2k_1rw_func_test.py new file mode 100755 index 00000000..24ec2e3a --- /dev/null +++ b/compiler/tests/50_riscv_2k_1rw_func_test.py @@ -0,0 +1,66 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + #OPTS.local_array_size = 16 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=512, + num_banks=1, + num_spare_rows=1, + num_spare_cols=1) + + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner, cycles=100) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_4k_1rw1r_func_test.py b/compiler/tests/50_riscv_4k_1rw1r_func_test.py new file mode 100755 index 00000000..6b4f336e --- /dev/null +++ b/compiler/tests/50_riscv_4k_1rw1r_func_test.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + #OPTS.local_array_size = 16 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=1024, + num_banks=1) + + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_4k_1rw_func_test.py b/compiler/tests/50_riscv_4k_1rw_func_test.py new file mode 100755 index 00000000..9f2dc2f6 --- /dev/null +++ b/compiler/tests/50_riscv_4k_1rw_func_test.py @@ -0,0 +1,66 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + #OPTS.local_array_size = 16 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=1024, + num_banks=1, + num_spare_rows=1, + num_spare_cols=1) + + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_512b_1rw1r_func_test.py b/compiler/tests/50_riscv_512b_1rw1r_func_test.py new file mode 100755 index 00000000..17b3f518 --- /dev/null +++ b/compiler/tests/50_riscv_512b_1rw1r_func_test.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + #OPTS.local_array_size = 16 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=128, + num_banks=1) + + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner, cycles=100) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_512b_1rw_func_test.py b/compiler/tests/50_riscv_512b_1rw_func_test.py new file mode 100755 index 00000000..4cceefd8 --- /dev/null +++ b/compiler/tests/50_riscv_512b_1rw_func_test.py @@ -0,0 +1,66 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + #OPTS.local_array_size = 16 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=128, + num_banks=1, + num_spare_rows=1, + num_spare_cols=1) + + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner, cycles=25) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_8k_1rw1r_func_test.py b/compiler/tests/50_riscv_8k_1rw1r_func_test.py new file mode 100755 index 00000000..0783823c --- /dev/null +++ b/compiler/tests/50_riscv_8k_1rw1r_func_test.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + OPTS.local_array_size = 16 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=2048, + num_banks=1) + + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner, cycles=100) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_8k_1rw_func_test.py b/compiler/tests/50_riscv_8k_1rw_func_test.py new file mode 100755 index 00000000..7b948aad --- /dev/null +++ b/compiler/tests/50_riscv_8k_1rw_func_test.py @@ -0,0 +1,66 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.trim_netlist = False + + OPTS.local_array_size = 16 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=2048, + num_banks=1, + num_spare_rows=1, + num_spare_cols=1) + + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner, cycles=100) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/configs/config_back_end.py b/compiler/tests/configs/config_back_end.py index 884b4926..3294e979 100644 --- a/compiler/tests/configs/config_back_end.py +++ b/compiler/tests/configs/config_back_end.py @@ -6,7 +6,7 @@ # All rights reserved. # from globals import OPTS -word_size = 1 +word_size = 2 num_words = 16 tech_name = OPTS.tech_name diff --git a/compiler/tests/configs/config_front_end.py b/compiler/tests/configs/config_front_end.py index e255d7a5..4486b077 100644 --- a/compiler/tests/configs/config_front_end.py +++ b/compiler/tests/configs/config_front_end.py @@ -6,7 +6,7 @@ # All rights reserved. # from globals import OPTS -word_size = 1 +word_size = 2 num_words = 16 tech_name = OPTS.tech_name diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.v b/compiler/tests/golden/sram_2_16_1_freepdk45.v index 46f89fa5..859d1cc6 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45.v +++ b/compiler/tests/golden/sram_2_16_1_freepdk45.v @@ -3,6 +3,10 @@ // Word size: 2 module sram_2_16_1_freepdk45( +`ifdef USE_POWER_PINS + vdd, + gnd, +`endif // Port 0: RW clk0,csb0,web0,addr0,din0,dout0 ); @@ -15,6 +19,10 @@ module sram_2_16_1_freepdk45( parameter VERBOSE = 1 ; //Set to 0 to only display warnings parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary +`ifdef USE_POWER_PINS + inout vdd; + inout gnd; +`endif input clk0; // clock input csb0; // active low chip select input web0; // active low write control @@ -48,8 +56,9 @@ reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; // Write Operation : When web0 = 0, csb0 = 0 always @ (negedge clk0) begin : MEM_WRITE0 - if ( !csb0_reg && !web0_reg ) - mem[addr0_reg] = din0_reg; + if ( !csb0_reg && !web0_reg ) begin + mem[addr0_reg][1:0] = din0_reg[1:0]; + end end // Memory Read Block Port 0 diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v index cb95036b..ce3714b2 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v @@ -3,6 +3,10 @@ // Word size: 2 module sram_2_16_1_scn4m_subm( +`ifdef USE_POWER_PINS + vdd, + gnd, +`endif // Port 0: RW clk0,csb0,web0,addr0,din0,dout0 ); @@ -15,6 +19,10 @@ module sram_2_16_1_scn4m_subm( parameter VERBOSE = 1 ; //Set to 0 to only display warnings parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary +`ifdef USE_POWER_PINS + inout vdd; + inout gnd; +`endif input clk0; // clock input csb0; // active low chip select input web0; // active low write control @@ -48,8 +56,9 @@ reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; // Write Operation : When web0 = 0, csb0 = 0 always @ (negedge clk0) begin : MEM_WRITE0 - if ( !csb0_reg && !web0_reg ) - mem[addr0_reg] = din0_reg; + if ( !csb0_reg && !web0_reg ) begin + mem[addr0_reg][1:0] = din0_reg[1:0]; + end end // Memory Read Block Port 0 diff --git a/compiler/uniquifyGDS.py b/compiler/uniquifyGDS.py new file mode 100755 index 00000000..8eddce3d --- /dev/null +++ b/compiler/uniquifyGDS.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 + +import sys +from gdsMill import gdsMill + +if len(sys.argv) < 4: + print("Script to prefix every instance and structure with the root cell name to provide unique namespace, but skip cells that begin with the library prefix.") + print("Usage: {0} in.gds out.gds".format(sys.argv[0])) + sys.exit(1) + +gds_file = sys.argv[2] +gds = gdsMill.VlsiLayout() +reader = gdsMill.Gds2reader(gds) +reader.loadFromFile(gds_file) + +gds.uniquify(prefix_name=sys.argv[1]) + +writer = gdsMill.Gds2writer(gds) +writer.writeToFile(sys.argv[3]) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 3983de7c..18ba53fc 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -71,9 +71,12 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa global OPTS # Copy .magicrc file into the output directory - magic_file = OPTS.openram_tech + "tech/.magicrc" + magic_file = os.environ.get('OPENRAM_MAGICRC', None) + if not magic_file: + magic_file = OPTS.openram_tech + "tech/.magicrc" + if os.path.exists(magic_file): - shutil.copy(magic_file, output_path) + shutil.copy(magic_file, output_path + "/.magicrc") else: debug.warning("Could not locate .magicrc file: {}".format(magic_file)) @@ -86,7 +89,10 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1])) # Do not run DRC for extraction/conversion f.write("drc off\n") - f.write("gds polygon subcell true\n") + f.write("set VDD vdd\n") + f.write("set GND gnd\n") + f.write("set SUB gnd\n") + #f.write("gds polygon subcell true\n") f.write("gds warning default\n") # These two options are temporarily disabled until Tim fixes a bug in magic related # to flattening channel routes and vias (hierarchy with no devices in it). Otherwise, @@ -174,6 +180,10 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa f.write('puts "Finished drc check"\n') f.write("drc catchup\n") f.write('puts "Finished drc catchup"\n') + # This is needed instead of drc count total because it displays + # some errors that are not "DRC" errors. + # f.write("puts -nonewline \"Total DRC errors found: \"\n") + # f.write("puts stdout [drc listall count total]\n") f.write("drc count total\n") f.write("quit -noprompt\n") f.write("EOF\n") @@ -241,11 +251,14 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out if not output_path: output_path = OPTS.openram_temp - setup_file = "setup.tcl" - full_setup_file = OPTS.openram_tech + "tech/" + setup_file - if os.path.exists(full_setup_file): + # Copy setup.tcl file into the output directory + setup_file = os.environ.get('OPENRAM_NETGENRC', None) + if not setup_file: + setup_file = OPTS.openram_tech + "tech/setup.tcl" + + if os.path.exists(setup_file): # Copy setup.tcl file into temp dir - shutil.copy(full_setup_file, output_path) + shutil.copy(setup_file, output_path) else: setup_file = 'nosetup' diff --git a/technology/freepdk45/sim_data/fall_delay.csv b/technology/freepdk45/sim_data/fall_delay.csv deleted file mode 100644 index 3f71e58d..00000000 --- a/technology/freepdk45/sim_data/fall_delay.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,fall_delay -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.25498 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.25622 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.26145999999999997 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.25553 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.25679 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.26204 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.26091 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.26221 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.26743 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.31658000000000003 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.31839 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.32593 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.31714 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.31899 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.32621 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.32362 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.32575 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.33302 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.28139 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.2828 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.28887999999999997 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.28178 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.28296000000000004 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.28944 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.28772000000000003 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.28927 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.29542 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.25365 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.25494 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.26016 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.25412999999999997 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.25533 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.26065000000000005 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.25889 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.26022 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.26556 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.31452 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.3165 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.32376 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.31516 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.31709 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.32435 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.32149999999999995 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.32315 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.33074 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.27948999999999996 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.28136999999999995 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.28725 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.28032 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.28179000000000004 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.28813 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.28549 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.28752 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.29366 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.23641 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.23782999999999999 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.24323999999999998 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.23717000000000002 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.23853 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.2437 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.24194 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.2432 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.2486 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.29381 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.29564 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.30294 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.2943 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.29651999999999995 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.30362 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.30057 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.30256 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.30998 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.26071 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.26230000000000003 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.26844999999999997 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.26130000000000003 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.26276 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.26908000000000004 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.26691000000000004 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.26833 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.27488 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.23962999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.24112 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.24631 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.24009999999999998 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.24160000000000004 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.24684 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.24514999999999998 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.24680000000000002 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.2518 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.298 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.29993000000000003 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.30740999999999996 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.29886 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.30074 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.30826 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.30518 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.30701 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.3144 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.26469 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.26608 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.27228 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.26508 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.26661 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.27302 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.27074 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.27229 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.27856000000000003 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.20774 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.20883 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.21308 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.20826 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.20935 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.21361 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.21305000000000002 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.21434999999999998 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.21861999999999998 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.25171 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.25345 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.25919000000000003 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.25259 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.25406 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.26003 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.2589 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.26036000000000004 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.26641000000000004 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.22749999999999998 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.22874 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.23365000000000002 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.22791 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.22928 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.23424 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.23372999999999997 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.23488000000000003 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.23993000000000003 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.2099 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.21104 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.21528 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.21069 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.21178 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.21605 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.21550999999999998 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.21662 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.22065 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.25471 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.25597 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.2622 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.25558000000000003 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.25673 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.26284 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.26176 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.26276 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.26884 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.2299 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.2311 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.23639 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.23051 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.23177999999999999 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.23668 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.23592 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.23736999999999997 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.24238999999999997 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.24361999999999998 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.24481 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.25027 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.24414 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.24541 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.25079 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.24897000000000002 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.25027 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.25566 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.30235 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.30436 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.31167 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.30313 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.30508 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.31239 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.30959000000000003 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.31098 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.31853 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.26874 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.27017 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.27657 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.26937 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.27088 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.27708 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.2749 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.27648 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.28285 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.21178 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.21289 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.21739999999999998 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.21234 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.21344 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.21807 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.21609 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.21733 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.22167 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.25711999999999996 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.25864 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.26446 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.25783 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.25905999999999996 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.26514 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.26306 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.26462 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.27044999999999997 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.23172 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.23336 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.23824 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.23241 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.23397 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.23889 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.23715 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.2385 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.24325000000000002 diff --git a/technology/freepdk45/sim_data/fall_slew.csv b/technology/freepdk45/sim_data/fall_slew.csv deleted file mode 100644 index 35cc666c..00000000 --- a/technology/freepdk45/sim_data/fall_slew.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,fall_slew -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.22674999999999998 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.22697 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.22827 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.22672 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.22709 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.22804 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.22672 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.22705 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.22846 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.27583 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.27593 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.27729 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.27573 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.27598 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.27741 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.27579 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.27622 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.27759 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.24922 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.24954 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.25093 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.24912 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.24960999999999997 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.2506 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.24927000000000002 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.24956 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.25087 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.22310000000000002 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.22333 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.22433 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.22287 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.22319 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.22444 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.22305 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.22338 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.22451000000000002 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.27102000000000004 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.27135 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.27273 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.27105999999999997 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.27127 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.27282999999999996 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.27105 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.2713 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.27285 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.24507 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.24528999999999998 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.24652999999999997 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.24494 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.24531 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.24655 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.24504 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.24564 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.24654 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.22154 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.22174 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.22285000000000002 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.22133 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.22172999999999998 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.22272 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.22146 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.22181 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.22283 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.26865 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.26902000000000004 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.27041 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.26871 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.26911 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.27043 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.26875 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.26904 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.27055 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.24329 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.24347 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.2447 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.24322000000000002 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.24357 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.24477000000000002 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.24329 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.24358999999999997 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.24467999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.22533999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.22555 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.22665 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.22537 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.22542 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.22643 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.22558999999999998 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.22558999999999998 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.22674999999999998 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.27363000000000004 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.27408 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.27523 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.27340000000000003 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.27366 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.27528 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.27339 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.27398 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.2752 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.24745999999999999 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.24766999999999997 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.24877000000000002 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.24738 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.24769 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.24877000000000002 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.24742 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.24786999999999998 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.24909 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.24514999999999998 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.24546 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.24648 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.24517999999999998 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.24543 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.24646999999999997 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.24536000000000002 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.24561 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.24656000000000003 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.29841 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.29889 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.29997999999999997 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.29843000000000003 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.2987 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.30012999999999995 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.29830999999999996 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.29874 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.30011 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.26954 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.26983 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.27093 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.26944999999999997 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.26990000000000003 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.27093 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.26973 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.26999 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.27142 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.24907999999999997 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.24947000000000003 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.25053000000000003 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.24922999999999998 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.24939 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.2505 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.24939 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.24963999999999997 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.25067 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.30352999999999997 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.30381 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.30519999999999997 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.30346999999999996 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.30373999999999995 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.30509 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.30369999999999997 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.30395 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.30522 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.27411 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.27423 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.27543 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.27395 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.27429 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.27555999999999997 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.27455999999999997 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.27428 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.27565 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.22893 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.22913 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.23035 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.22876 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.22889 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.23018 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.22888 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.22907 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.23024 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.27804 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.27853 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.27971999999999997 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.27799 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.27854999999999996 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.27982 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.27827999999999997 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.27878 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.28027 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.25155000000000005 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.25172 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.2531 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.25128 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.25178 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.25283 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.25175 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.25175 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.25299000000000005 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.24119000000000002 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.24160000000000004 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.24266000000000001 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.24132 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.24153 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.24263 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.24134000000000003 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.24184000000000003 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.24273999999999998 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.29352 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.29379 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.29528 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.29344000000000003 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.29385 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.29532 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.29348 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.29385 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.29524 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.26513 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.26541000000000003 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.2666 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.26519 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.26541000000000003 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.26646 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.26518 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.26582 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.26681 diff --git a/technology/freepdk45/sim_data/read0_power.csv b/technology/freepdk45/sim_data/read0_power.csv deleted file mode 100644 index 86f7a27e..00000000 --- a/technology/freepdk45/sim_data/read0_power.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,read0_power -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.5530577777777778 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.4157033333333333 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.4849055555555555 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.4980888888888889 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.37430555555555556 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.43683 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.43683 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.43683 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.43683 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.43683 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.43683 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.43683 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.43683 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.43683 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.41289444444444445 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.3072488888888889 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.3452 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.3452 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.3452 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.3452 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.3452 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.3452 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.3452 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.3452 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.3452 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.43302222222222225 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.33773888888888887 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.3793722222222222 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.39631555555555553 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.3082988888888889 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.34673 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.34673 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.34673 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.34673 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.34673 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.34673 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.34673 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.34673 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.34673 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.42707555555555554 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.3208011111111111 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.37415 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.37415 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.37415 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.37415 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.37415 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.37415 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.37415 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.37415 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.37415 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.48461444444444446 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.36542555555555556 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.4254733333333333 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.3644511111111111 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.2822922222222222 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.31802888888888886 diff --git a/technology/freepdk45/sim_data/read1_power.csv b/technology/freepdk45/sim_data/read1_power.csv deleted file mode 100644 index ca1bef87..00000000 --- a/technology/freepdk45/sim_data/read1_power.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,read1_power -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.5523799999999999 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.4153288888888889 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.48412777777777777 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.49752777777777774 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.37363111111111114 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.43609 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.43609 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.43609 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.43609 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.43609 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.43609 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.43609 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.43609 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.43609 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.41303 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.41303 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.41303 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.41303 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.41303 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.41303 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.41303 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.41303 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.41303 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.30725222222222226 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.3453111111111111 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.43318 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.43318 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.43318 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.43318 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.43318 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.43318 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.43318 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.43318 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.43318 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.33794555555555555 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.37956999999999996 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.3962455555555555 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.3082555555555555 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.3466588888888889 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.4269344444444444 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.32067333333333337 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.3741288888888889 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.4844888888888889 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.3652088888888889 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.4253611111111111 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.36431555555555556 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.28226222222222225 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.31788666666666665 diff --git a/technology/freepdk45/sim_data/rise_delay.csv b/technology/freepdk45/sim_data/rise_delay.csv deleted file mode 100644 index bcc8f9dc..00000000 --- a/technology/freepdk45/sim_data/rise_delay.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,rise_delay -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.25498 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.25622 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.26145999999999997 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.25553 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.25679 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.26204 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.26091 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.26221 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.26743 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.31658000000000003 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.31839 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.32593 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.31714 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.31899 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.32621 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.32362 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.32575 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.33302 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.28139 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.2828 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.28887999999999997 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.28178 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.28296000000000004 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.28944 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.28772000000000003 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.28927 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.29542 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.25365 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.25494 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.26016 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.25412999999999997 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.25533 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.26065000000000005 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.25889 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.26022 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.26556 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.31452 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.3165 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.32376 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.31516 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.31709 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.32435 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.32149999999999995 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.32315 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.33074 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.27948999999999996 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.28136999999999995 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.28725 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.28032 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.28179000000000004 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.28813 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.28549 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.28752 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.29366 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.23641 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.23782999999999999 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.24323999999999998 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.23717000000000002 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.23853 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.2437 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.24194 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.2432 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.2486 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.29381 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.29564 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.30294 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.2943 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.29651999999999995 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.30362 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.30057 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.30256 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.30998 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.26071 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.26230000000000003 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.26844999999999997 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.26130000000000003 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.26276 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.26908000000000004 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.26691000000000004 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.26833 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.27488 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.23962999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.24112 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.24631 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.24009999999999998 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.24160000000000004 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.24684 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.24514999999999998 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.24680000000000002 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.2518 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.298 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.29993000000000003 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.30740999999999996 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.29886 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.30074 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.30826 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.30518 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.30701 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.3144 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.26469 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.26608 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.27228 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.26508 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.26661 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.27302 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.27074 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.27229 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.27856000000000003 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.20774 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.20883 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.21308 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.20826 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.20935 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.21361 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.21305000000000002 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.21434999999999998 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.21861999999999998 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.25171 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.25345 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.25919000000000003 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.25259 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.25406 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.26003 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.2589 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.26036000000000004 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.26641000000000004 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.22749999999999998 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.22874 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.23365000000000002 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.22791 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.22928 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.23424 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.23372999999999997 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.23488000000000003 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.23993000000000003 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.2099 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.21104 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.21528 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.21069 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.21178 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.21605 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.21550999999999998 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.21662 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.22065 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.25471 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.25597 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.2622 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.25558000000000003 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.25673 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.26284 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.26176 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.26276 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.26884 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.2299 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.2311 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.23639 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.23051 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.23177999999999999 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.23668 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.23592 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.23736999999999997 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.24238999999999997 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.24361999999999998 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.24481 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.25027 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.24414 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.24541 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.25079 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.24897000000000002 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.25027 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.25566 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.30235 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.30436 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.31167 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.30313 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.30508 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.31239 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.30959000000000003 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.31098 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.31853 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.26874 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.27017 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.27657 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.26937 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.27088 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.27708 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.2749 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.27648 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.28285 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.21178 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.21289 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.21739999999999998 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.21234 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.21344 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.21807 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.21609 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.21733 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.22167 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.25711999999999996 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.25864 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.26446 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.25783 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.25905999999999996 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.26514 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.26306 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.26462 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.27044999999999997 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.23172 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.23336 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.23824 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.23241 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.23397 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.23889 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.23715 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.2385 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.24325000000000002 diff --git a/technology/freepdk45/sim_data/rise_slew.csv b/technology/freepdk45/sim_data/rise_slew.csv deleted file mode 100644 index 384f6715..00000000 --- a/technology/freepdk45/sim_data/rise_slew.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,rise_slew -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.22674999999999998 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.22697 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.22827 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.22672 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.22709 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.22804 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.22672 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.22705 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.22846 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.27583 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.27593 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.27729 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.27573 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.27598 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.27741 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.27579 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.27622 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.27759 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.24922 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.24954 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.25093 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.24912 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.24960999999999997 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.2506 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.24927000000000002 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.24956 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.25087 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.22310000000000002 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.22333 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.22433 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.22287 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.22319 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.22444 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.22305 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.22338 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.22451000000000002 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.27102000000000004 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.27135 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.27273 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.27105999999999997 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.27127 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.27282999999999996 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.27105 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.2713 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.27285 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.24507 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.24528999999999998 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.24652999999999997 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.24494 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.24531 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.24655 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.24504 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.24564 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.24654 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.22154 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.22174 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.22285000000000002 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.22133 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.22172999999999998 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.22272 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.22146 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.22181 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.22283 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.26865 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.26902000000000004 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.27041 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.26871 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.26911 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.27043 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.26875 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.26904 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.27055 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.24329 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.24347 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.2447 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.24322000000000002 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.24357 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.24477000000000002 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.24329 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.24358999999999997 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.24467999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.22533999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.22555 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.22665 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.22537 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.22542 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.22643 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.22558999999999998 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.22558999999999998 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.22674999999999998 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.27363000000000004 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.27408 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.27523 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.27340000000000003 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.27366 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.27528 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.27339 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.27398 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.2752 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.24745999999999999 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.24766999999999997 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.24877000000000002 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.24738 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.24769 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.24877000000000002 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.24742 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.24786999999999998 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.24909 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.24514999999999998 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.24546 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.24648 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.24517999999999998 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.24543 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.24646999999999997 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.24536000000000002 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.24561 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.24656000000000003 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.29841 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.29889 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.29997999999999997 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.29843000000000003 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.2987 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.30012999999999995 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.29830999999999996 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.29874 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.30011 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.26954 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.26983 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.27093 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.26944999999999997 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.26990000000000003 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.27093 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.26973 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.26999 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.27142 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.24907999999999997 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.24947000000000003 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.25053000000000003 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.24922999999999998 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.24939 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.2505 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.24939 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.24963999999999997 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.25067 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.30352999999999997 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.30381 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.30519999999999997 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.30346999999999996 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.30373999999999995 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.30509 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.30369999999999997 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.30395 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.30522 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.27411 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.27423 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.27543 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.27395 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.27429 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.27555999999999997 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.27455999999999997 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.27428 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.27565 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.22893 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.22913 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.23035 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.22876 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.22889 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.23018 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.22888 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.22907 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.23024 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.27804 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.27853 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.27971999999999997 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.27799 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.27854999999999996 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.27982 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.27827999999999997 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.27878 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.28027 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.25155000000000005 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.25172 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.2531 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.25128 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.25178 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.25283 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.25175 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.25175 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.25299000000000005 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.24119000000000002 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.24160000000000004 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.24266000000000001 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.24132 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.24153 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.24263 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.24134000000000003 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.24184000000000003 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.24273999999999998 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.29352 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.29379 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.29528 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.29344000000000003 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.29385 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.29532 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.29348 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.29385 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.29524 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.26513 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.26541000000000003 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.2666 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.26519 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.26541000000000003 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.26646 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.26518 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.26582 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.26681 diff --git a/technology/freepdk45/sim_data/sim_data.csv b/technology/freepdk45/sim_data/sim_data.csv new file mode 100644 index 00000000..6771d59b --- /dev/null +++ b/technology/freepdk45/sim_data/sim_data.csv @@ -0,0 +1,325 @@ +num_words,word_size,words_per_row,local_array_size,area,process,voltage,temperature,slew,load,rise_delay,fall_delay,rise_slew,fall_slew,write1_power,write0_power,read1_power,read0_power,leakage_power +1024,23,16,118,0,TT,1.0,25,0.00125,0.052275,0.85234,0.85234,0.27117,0.27117,4.091554666666666,8.445465777777779,8.360854666666668,8.360021333333334,0.182 +1024,23,16,118,0,TT,1.0,25,0.00125,0.2091,0.85418,0.85418,0.27031,0.27031,4.091554666666666,8.445465777777779,8.360854666666668,8.360021333333334,0.182 +1024,23,16,118,0,TT,1.0,25,0.00125,0.8364,0.8604499999999999,0.8604499999999999,0.27264,0.27264,4.091554666666666,8.445465777777779,8.360854666666668,8.360021333333334,0.182 +1024,23,16,118,0,TT,1.0,25,0.005,0.052275,0.85316,0.85316,0.27098,0.27098,4.091554666666666,8.445465777777779,8.360854666666668,8.360021333333334,0.182 +1024,23,16,118,0,TT,1.0,25,0.005,0.2091,0.85477,0.85477,0.27147,0.27147,4.091554666666666,8.445465777777779,8.360854666666668,8.360021333333334,0.182 +1024,23,16,118,0,TT,1.0,25,0.005,0.8364,0.86048,0.86048,0.27293,0.27293,4.091554666666666,8.445465777777779,8.360854666666668,8.360021333333334,0.182 +1024,23,16,118,0,TT,1.0,25,0.04,0.052275,0.85768,0.85768,0.27049,0.27049,4.091554666666666,8.445465777777779,8.360854666666668,8.360021333333334,0.182 +1024,23,16,118,0,TT,1.0,25,0.04,0.2091,0.8594700000000001,0.8594700000000001,0.26963,0.26963,4.091554666666666,8.445465777777779,8.360854666666668,8.360021333333334,0.182 +1024,23,16,118,0,TT,1.0,25,0.04,0.8364,0.86544,0.86544,0.27325,0.27325,4.091554666666666,8.445465777777779,8.360854666666668,8.360021333333334,0.182 +128,18,2,7,0,TT,1.0,25,0.00125,0.052275,0.37588,0.37588,0.28696,0.28696,1.0738881111111112,1.2295436666666668,1.0598547777777778,1.0586103333333332,0.025092999999999997 +128,18,2,7,0,TT,1.0,25,0.00125,0.2091,0.37765,0.37765,0.28747,0.28747,1.0738881111111112,1.2295436666666668,1.0598547777777778,1.0586103333333332,0.025092999999999997 +128,18,2,7,0,TT,1.0,25,0.00125,0.8364,0.38401,0.38401,0.289,0.289,1.0738881111111112,1.2295436666666668,1.0598547777777778,1.0586103333333332,0.025092999999999997 +128,18,2,7,0,TT,1.0,25,0.005,0.052275,0.37664000000000003,0.37664000000000003,0.28673,0.28673,1.0738881111111112,1.2295436666666668,1.0598547777777778,1.0586103333333332,0.025092999999999997 +128,18,2,7,0,TT,1.0,25,0.005,0.2091,0.37813,0.37813,0.28726,0.28726,1.0738881111111112,1.2295436666666668,1.0598547777777778,1.0586103333333332,0.025092999999999997 +128,18,2,7,0,TT,1.0,25,0.005,0.8364,0.38448,0.38448,0.28884,0.28884,1.0738881111111112,1.2295436666666668,1.0598547777777778,1.0586103333333332,0.025092999999999997 +128,18,2,7,0,TT,1.0,25,0.04,0.052275,0.38083,0.38083,0.28731,0.28731,1.0738881111111112,1.2295436666666668,1.0598547777777778,1.0586103333333332,0.025092999999999997 +128,18,2,7,0,TT,1.0,25,0.04,0.2091,0.38227,0.38227,0.28787,0.28787,1.0738881111111112,1.2295436666666668,1.0598547777777778,1.0586103333333332,0.025092999999999997 +128,18,2,7,0,TT,1.0,25,0.04,0.8364,0.38874,0.38874,0.28899,0.28899,1.0738881111111112,1.2295436666666668,1.0598547777777778,1.0586103333333332,0.025092999999999997 +128,12,4,38,0,TT,1.0,25,0.00125,0.052275,0.50365,0.50365,0.2647,0.2647,0.8532664888888889,1.3061720444444442,1.203938711111111,1.2031831555555557,0.015184999999999999 +128,12,4,38,0,TT,1.0,25,0.00125,0.2091,0.50549,0.50549,0.26520000000000005,0.26520000000000005,0.8532664888888889,1.3061720444444442,1.203938711111111,1.2031831555555557,0.015184999999999999 +128,12,4,38,0,TT,1.0,25,0.00125,0.8364,0.5114500000000001,0.5114500000000001,0.26664000000000004,0.26664000000000004,0.8532664888888889,1.3061720444444442,1.203938711111111,1.2031831555555557,0.015184999999999999 +128,12,4,38,0,TT,1.0,25,0.005,0.052275,0.50464,0.50464,0.26481,0.26481,0.8532664888888889,1.3061720444444442,1.203938711111111,1.2031831555555557,0.015184999999999999 +128,12,4,38,0,TT,1.0,25,0.005,0.2091,0.5059800000000001,0.5059800000000001,0.26507,0.26507,0.8532664888888889,1.3061720444444442,1.203938711111111,1.2031831555555557,0.015184999999999999 +128,12,4,38,0,TT,1.0,25,0.005,0.8364,0.5122800000000001,0.5122800000000001,0.26648999999999995,0.26648999999999995,0.8532664888888889,1.3061720444444442,1.203938711111111,1.2031831555555557,0.015184999999999999 +128,12,4,38,0,TT,1.0,25,0.04,0.052275,0.50921,0.50921,0.26495,0.26495,0.8532664888888889,1.3061720444444442,1.203938711111111,1.2031831555555557,0.015184999999999999 +128,12,4,38,0,TT,1.0,25,0.04,0.2091,0.5108,0.5108,0.26542,0.26542,0.8532664888888889,1.3061720444444442,1.203938711111111,1.2031831555555557,0.015184999999999999 +128,12,4,38,0,TT,1.0,25,0.04,0.8364,0.51663,0.51663,0.26712,0.26712,0.8532664888888889,1.3061720444444442,1.203938711111111,1.2031831555555557,0.015184999999999999 +2048,32,8,0,0,TT,1.0,25,0.00125,0.052275,0.72804,0.72804,0.27723,0.27723,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.00125,0.2091,0.72938,0.72938,0.27716,0.27716,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.00125,0.8364,0.73548,0.73548,0.27867,0.27867,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.005,0.052275,0.7283,0.7283,0.27621,0.27621,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.005,0.2091,0.73001,0.73001,0.27708,0.27708,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.005,0.8364,0.73619,0.73619,0.278,0.278,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.04,0.052275,0.7329899999999999,0.7329899999999999,0.27509,0.27509,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.04,0.2091,0.73472,0.73472,0.27569,0.27569,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.04,0.8364,0.74073,0.74073,0.27765,0.27765,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +16,4,1,4,0,TT,1.0,25,0.00125,0.052275,0.25400999999999996,0.25400999999999996,0.26805,0.26805,0.3716818888888889,0.45269522222222225,0.39135077777777777,0.3916741111111111,0.0021831 +16,4,1,4,0,TT,1.0,25,0.00125,0.2091,0.25522,0.25522,0.26838,0.26838,0.3716818888888889,0.45269522222222225,0.39135077777777777,0.3916741111111111,0.0021831 +16,4,1,4,0,TT,1.0,25,0.00125,0.8364,0.26011,0.26011,0.26957,0.26957,0.3716818888888889,0.45269522222222225,0.39135077777777777,0.3916741111111111,0.0021831 +16,4,1,4,0,TT,1.0,25,0.005,0.052275,0.25468999999999997,0.25468999999999997,0.26817,0.26817,0.3716818888888889,0.45269522222222225,0.39135077777777777,0.3916741111111111,0.0021831 +16,4,1,4,0,TT,1.0,25,0.005,0.2091,0.25582,0.25582,0.26844,0.26844,0.3716818888888889,0.45269522222222225,0.39135077777777777,0.3916741111111111,0.0021831 +16,4,1,4,0,TT,1.0,25,0.005,0.8364,0.26049999999999995,0.26049999999999995,0.26965,0.26965,0.3716818888888889,0.45269522222222225,0.39135077777777777,0.3916741111111111,0.0021831 +16,4,1,4,0,TT,1.0,25,0.04,0.052275,0.25988,0.25988,0.26833,0.26833,0.3716818888888889,0.45269522222222225,0.39135077777777777,0.3916741111111111,0.0021831 +16,4,1,4,0,TT,1.0,25,0.04,0.2091,0.26134999999999997,0.26134999999999997,0.26854,0.26854,0.3716818888888889,0.45269522222222225,0.39135077777777777,0.3916741111111111,0.0021831 +16,4,1,4,0,TT,1.0,25,0.04,0.8364,0.26609,0.26609,0.26984,0.26984,0.3716818888888889,0.45269522222222225,0.39135077777777777,0.3916741111111111,0.0021831 +256,9,4,15,0,TT,1.0,25,0.00125,0.052275,0.41859999999999997,0.41859999999999997,0.2505,0.2505,0.7577922222222222,1.0025177777777778,0.9412322222222222,0.94063,0.021991999999999998 +256,9,4,15,0,TT,1.0,25,0.00125,0.2091,0.42011,0.42011,0.25124,0.25124,0.7577922222222222,1.0025177777777778,0.9412322222222222,0.94063,0.021991999999999998 +256,9,4,15,0,TT,1.0,25,0.00125,0.8364,0.42629,0.42629,0.25256999999999996,0.25256999999999996,0.7577922222222222,1.0025177777777778,0.9412322222222222,0.94063,0.021991999999999998 +256,9,4,15,0,TT,1.0,25,0.005,0.052275,0.41933,0.41933,0.25063,0.25063,0.7577922222222222,1.0025177777777778,0.9412322222222222,0.94063,0.021991999999999998 +256,9,4,15,0,TT,1.0,25,0.005,0.2091,0.4208,0.4208,0.25076000000000004,0.25076000000000004,0.7577922222222222,1.0025177777777778,0.9412322222222222,0.94063,0.021991999999999998 +256,9,4,15,0,TT,1.0,25,0.005,0.8364,0.42707999999999996,0.42707999999999996,0.25241,0.25241,0.7577922222222222,1.0025177777777778,0.9412322222222222,0.94063,0.021991999999999998 +256,9,4,15,0,TT,1.0,25,0.04,0.052275,0.42373,0.42373,0.25072,0.25072,0.7577922222222222,1.0025177777777778,0.9412322222222222,0.94063,0.021991999999999998 +256,9,4,15,0,TT,1.0,25,0.04,0.2091,0.42548,0.42548,0.25092,0.25092,0.7577922222222222,1.0025177777777778,0.9412322222222222,0.94063,0.021991999999999998 +256,9,4,15,0,TT,1.0,25,0.04,0.8364,0.43151,0.43151,0.25275,0.25275,0.7577922222222222,1.0025177777777778,0.9412322222222222,0.94063,0.021991999999999998 +64,7,2,10,0,TT,1.0,25,0.00125,0.052275,0.34562,0.34562,0.25544999999999995,0.25544999999999995,0.5341884111111113,0.6900539666666667,0.6045984111111111,0.6039550777777778,0.0062749 +64,7,2,10,0,TT,1.0,25,0.00125,0.2091,0.34704,0.34704,0.25564000000000003,0.25564000000000003,0.5341884111111113,0.6900539666666667,0.6045984111111111,0.6039550777777778,0.0062749 +64,7,2,10,0,TT,1.0,25,0.00125,0.8364,0.35318,0.35318,0.25702,0.25702,0.5341884111111113,0.6900539666666667,0.6045984111111111,0.6039550777777778,0.0062749 +64,7,2,10,0,TT,1.0,25,0.005,0.052275,0.34617,0.34617,0.25527,0.25527,0.5341884111111113,0.6900539666666667,0.6045984111111111,0.6039550777777778,0.0062749 +64,7,2,10,0,TT,1.0,25,0.005,0.2091,0.34763,0.34763,0.25561,0.25561,0.5341884111111113,0.6900539666666667,0.6045984111111111,0.6039550777777778,0.0062749 +64,7,2,10,0,TT,1.0,25,0.005,0.8364,0.35381,0.35381,0.25709,0.25709,0.5341884111111113,0.6900539666666667,0.6045984111111111,0.6039550777777778,0.0062749 +64,7,2,10,0,TT,1.0,25,0.04,0.052275,0.35229,0.35229,0.25562999999999997,0.25562999999999997,0.5341884111111113,0.6900539666666667,0.6045984111111111,0.6039550777777778,0.0062749 +64,7,2,10,0,TT,1.0,25,0.04,0.2091,0.35359,0.35359,0.25606999999999996,0.25606999999999996,0.5341884111111113,0.6900539666666667,0.6045984111111111,0.6039550777777778,0.0062749 +64,7,2,10,0,TT,1.0,25,0.04,0.8364,0.36012,0.36012,0.25693,0.25693,0.5341884111111113,0.6900539666666667,0.6045984111111111,0.6039550777777778,0.0062749 +1024,27,4,89,0,TT,1.0,25,0.00125,0.052275,0.90703,0.90703,0.25694999999999996,0.25694999999999996,1.7577155555555555,3.104271111111111,3.005037777777778,3.0044155555555556,0.21148999999999998 +1024,27,4,89,0,TT,1.0,25,0.00125,0.2091,0.9084,0.9084,0.25723999999999997,0.25723999999999997,1.7577155555555555,3.104271111111111,3.005037777777778,3.0044155555555556,0.21148999999999998 +1024,27,4,89,0,TT,1.0,25,0.00125,0.8364,0.9153899999999999,0.9153899999999999,0.25769000000000003,0.25769000000000003,1.7577155555555555,3.104271111111111,3.005037777777778,3.0044155555555556,0.21148999999999998 +1024,27,4,89,0,TT,1.0,25,0.005,0.052275,0.90752,0.90752,0.25662,0.25662,1.7577155555555555,3.104271111111111,3.005037777777778,3.0044155555555556,0.21148999999999998 +1024,27,4,89,0,TT,1.0,25,0.005,0.2091,0.90938,0.90938,0.25679,0.25679,1.7577155555555555,3.104271111111111,3.005037777777778,3.0044155555555556,0.21148999999999998 +1024,27,4,89,0,TT,1.0,25,0.005,0.8364,0.91578,0.91578,0.25822,0.25822,1.7577155555555555,3.104271111111111,3.005037777777778,3.0044155555555556,0.21148999999999998 +1024,27,4,89,0,TT,1.0,25,0.04,0.052275,0.91227,0.91227,0.25771,0.25771,1.7577155555555555,3.104271111111111,3.005037777777778,3.0044155555555556,0.21148999999999998 +1024,27,4,89,0,TT,1.0,25,0.04,0.2091,0.9138799999999999,0.9138799999999999,0.25757,0.25757,1.7577155555555555,3.104271111111111,3.005037777777778,3.0044155555555556,0.21148999999999998 +1024,27,4,89,0,TT,1.0,25,0.04,0.8364,0.92033,0.92033,0.2585,0.2585,1.7577155555555555,3.104271111111111,3.005037777777778,3.0044155555555556,0.21148999999999998 +1024,17,16,86,0,TT,1.0,25,0.00125,0.052275,0.74048,0.74048,0.25687,0.25687,2.9444091111111113,5.9905535555555565,5.916342444444445,5.915775777777778,0.13595 +1024,17,16,86,0,TT,1.0,25,0.00125,0.2091,0.74195,0.74195,0.25744999999999996,0.25744999999999996,2.9444091111111113,5.9905535555555565,5.916342444444445,5.915775777777778,0.13595 +1024,17,16,86,0,TT,1.0,25,0.00125,0.8364,0.7482,0.7482,0.25879,0.25879,2.9444091111111113,5.9905535555555565,5.916342444444445,5.915775777777778,0.13595 +1024,17,16,86,0,TT,1.0,25,0.005,0.052275,0.74078,0.74078,0.25626,0.25626,2.9444091111111113,5.9905535555555565,5.916342444444445,5.915775777777778,0.13595 +1024,17,16,86,0,TT,1.0,25,0.005,0.2091,0.74265,0.74265,0.25615,0.25615,2.9444091111111113,5.9905535555555565,5.916342444444445,5.915775777777778,0.13595 +1024,17,16,86,0,TT,1.0,25,0.005,0.8364,0.74908,0.74908,0.25773999999999997,0.25773999999999997,2.9444091111111113,5.9905535555555565,5.916342444444445,5.915775777777778,0.13595 +1024,17,16,86,0,TT,1.0,25,0.04,0.052275,0.74514,0.74514,0.25593,0.25593,2.9444091111111113,5.9905535555555565,5.916342444444445,5.915775777777778,0.13595 +1024,17,16,86,0,TT,1.0,25,0.04,0.2091,0.74711,0.74711,0.25631000000000004,0.25631000000000004,2.9444091111111113,5.9905535555555565,5.916342444444445,5.915775777777778,0.13595 +1024,17,16,86,0,TT,1.0,25,0.04,0.8364,0.7533099999999999,0.7533099999999999,0.25807,0.25807,2.9444091111111113,5.9905535555555565,5.916342444444445,5.915775777777778,0.13595 +64,26,4,23,0,TT,1.0,25,0.00125,0.052275,0.41342,0.41342,0.31986000000000003,0.31986000000000003,1.601789222222222,1.8642003333333337,1.7103781111111112,1.709867,0.019089 +64,26,4,23,0,TT,1.0,25,0.00125,0.2091,0.41485,0.41485,0.32014,0.32014,1.601789222222222,1.8642003333333337,1.7103781111111112,1.709867,0.019089 +64,26,4,23,0,TT,1.0,25,0.00125,0.8364,0.42079,0.42079,0.32178999999999996,0.32178999999999996,1.601789222222222,1.8642003333333337,1.7103781111111112,1.709867,0.019089 +64,26,4,23,0,TT,1.0,25,0.005,0.052275,0.41369,0.41369,0.31972,0.31972,1.601789222222222,1.8642003333333337,1.7103781111111112,1.709867,0.019089 +64,26,4,23,0,TT,1.0,25,0.005,0.2091,0.41546,0.41546,0.32,0.32,1.601789222222222,1.8642003333333337,1.7103781111111112,1.709867,0.019089 +64,26,4,23,0,TT,1.0,25,0.005,0.8364,0.42108999999999996,0.42108999999999996,0.32167,0.32167,1.601789222222222,1.8642003333333337,1.7103781111111112,1.709867,0.019089 +64,26,4,23,0,TT,1.0,25,0.04,0.052275,0.41859,0.41859,0.31999,0.31999,1.601789222222222,1.8642003333333337,1.7103781111111112,1.709867,0.019089 +64,26,4,23,0,TT,1.0,25,0.04,0.2091,0.4201,0.4201,0.32038,0.32038,1.601789222222222,1.8642003333333337,1.7103781111111112,1.709867,0.019089 +64,26,4,23,0,TT,1.0,25,0.04,0.8364,0.42583000000000004,0.42583000000000004,0.32176,0.32176,1.601789222222222,1.8642003333333337,1.7103781111111112,1.709867,0.019089 +256,8,1,1,0,TT,1.0,25,0.00125,0.052275,0.44856,0.44856,0.33908,0.33908,0.8436666666666667,1.1422777777777777,0.9599111111111109,0.9614677777777777,0.047965 +256,8,1,1,0,TT,1.0,25,0.00125,0.2091,0.44982,0.44982,0.33948999999999996,0.33948999999999996,0.8436666666666667,1.1422777777777777,0.9599111111111109,0.9614677777777777,0.047965 +256,8,1,1,0,TT,1.0,25,0.00125,0.8364,0.45516,0.45516,0.34109,0.34109,0.8436666666666667,1.1422777777777777,0.9599111111111109,0.9614677777777777,0.047965 +256,8,1,1,0,TT,1.0,25,0.005,0.052275,0.44912,0.44912,0.33914,0.33914,0.8436666666666667,1.1422777777777777,0.9599111111111109,0.9614677777777777,0.047965 +256,8,1,1,0,TT,1.0,25,0.005,0.2091,0.45050999999999997,0.45050999999999997,0.33939,0.33939,0.8436666666666667,1.1422777777777777,0.9599111111111109,0.9614677777777777,0.047965 +256,8,1,1,0,TT,1.0,25,0.005,0.8364,0.45592,0.45592,0.34074,0.34074,0.8436666666666667,1.1422777777777777,0.9599111111111109,0.9614677777777777,0.047965 +256,8,1,1,0,TT,1.0,25,0.04,0.052275,0.45376,0.45376,0.33902,0.33902,0.8436666666666667,1.1422777777777777,0.9599111111111109,0.9614677777777777,0.047965 +256,8,1,1,0,TT,1.0,25,0.04,0.2091,0.45496,0.45496,0.33996,0.33996,0.8436666666666667,1.1422777777777777,0.9599111111111109,0.9614677777777777,0.047965 +256,8,1,1,0,TT,1.0,25,0.04,0.8364,0.4601,0.4601,0.34103,0.34103,0.8436666666666667,1.1422777777777777,0.9599111111111109,0.9614677777777777,0.047965 +256,12,16,186,0,TT,1.0,25,0.00125,0.052275,1.0659,1.0659,0.21687,0.21687,2.3978811111111114,4.672447777777778,4.632525555555556,4.635481111111111,0.028530999999999997 +256,12,16,186,0,TT,1.0,25,0.00125,0.2091,1.0675000000000001,1.0675000000000001,0.21809,0.21809,2.3978811111111114,4.672447777777778,4.632525555555556,4.635481111111111,0.028530999999999997 +256,12,16,186,0,TT,1.0,25,0.00125,0.8364,1.0772,1.0772,0.2192,0.2192,2.3978811111111114,4.672447777777778,4.632525555555556,4.635481111111111,0.028530999999999997 +256,12,16,186,0,TT,1.0,25,0.005,0.052275,1.0664,1.0664,0.21708,0.21708,2.3978811111111114,4.672447777777778,4.632525555555556,4.635481111111111,0.028530999999999997 +256,12,16,186,0,TT,1.0,25,0.005,0.2091,1.0681,1.0681,0.21808000000000002,0.21808000000000002,2.3978811111111114,4.672447777777778,4.632525555555556,4.635481111111111,0.028530999999999997 +256,12,16,186,0,TT,1.0,25,0.005,0.8364,1.0774,1.0774,0.21858999999999998,0.21858999999999998,2.3978811111111114,4.672447777777778,4.632525555555556,4.635481111111111,0.028530999999999997 +256,12,16,186,0,TT,1.0,25,0.04,0.052275,1.0709000000000002,1.0709000000000002,0.21670999999999999,0.21670999999999999,2.3978811111111114,4.672447777777778,4.632525555555556,4.635481111111111,0.028530999999999997 +256,12,16,186,0,TT,1.0,25,0.04,0.2091,1.0727,1.0727,0.21869,0.21869,2.3978811111111114,4.672447777777778,4.632525555555556,4.635481111111111,0.028530999999999997 +256,12,16,186,0,TT,1.0,25,0.04,0.8364,1.0814,1.0814,0.21942,0.21942,2.3978811111111114,4.672447777777778,4.632525555555556,4.635481111111111,0.028530999999999997 +64,4,4,14,0,TT,1.0,25,0.00125,0.052275,0.34403,0.34403,0.24206,0.24206,0.4700171888888889,0.5782438555555554,0.5341883,0.5336016333333332,0.0039777 +64,4,4,14,0,TT,1.0,25,0.00125,0.2091,0.34562,0.34562,0.24231000000000003,0.24231000000000003,0.4700171888888889,0.5782438555555554,0.5341883,0.5336016333333332,0.0039777 +64,4,4,14,0,TT,1.0,25,0.00125,0.8364,0.35161,0.35161,0.24378999999999998,0.24378999999999998,0.4700171888888889,0.5782438555555554,0.5341883,0.5336016333333332,0.0039777 +64,4,4,14,0,TT,1.0,25,0.005,0.052275,0.34472,0.34472,0.24199,0.24199,0.4700171888888889,0.5782438555555554,0.5341883,0.5336016333333332,0.0039777 +64,4,4,14,0,TT,1.0,25,0.005,0.2091,0.34617,0.34617,0.24223999999999998,0.24223999999999998,0.4700171888888889,0.5782438555555554,0.5341883,0.5336016333333332,0.0039777 +64,4,4,14,0,TT,1.0,25,0.005,0.8364,0.35231999999999997,0.35231999999999997,0.24358,0.24358,0.4700171888888889,0.5782438555555554,0.5341883,0.5336016333333332,0.0039777 +64,4,4,14,0,TT,1.0,25,0.04,0.052275,0.35077,0.35077,0.24187,0.24187,0.4700171888888889,0.5782438555555554,0.5341883,0.5336016333333332,0.0039777 +64,4,4,14,0,TT,1.0,25,0.04,0.2091,0.35200000000000004,0.35200000000000004,0.24217999999999998,0.24217999999999998,0.4700171888888889,0.5782438555555554,0.5341883,0.5336016333333332,0.0039777 +64,4,4,14,0,TT,1.0,25,0.04,0.8364,0.35832,0.35832,0.24372000000000002,0.24372000000000002,0.4700171888888889,0.5782438555555554,0.5341883,0.5336016333333332,0.0039777 +256,17,16,49,0,TT,1.0,25,0.00125,0.052275,0.5776,0.5776,0.26636,0.26636,2.752683222222222,4.809016555555555,4.721416555555556,4.721149888888888,0.040664000000000006 +256,17,16,49,0,TT,1.0,25,0.00125,0.2091,0.5792999999999999,0.5792999999999999,0.26668000000000003,0.26668000000000003,2.752683222222222,4.809016555555555,4.721416555555556,4.721149888888888,0.040664000000000006 +256,17,16,49,0,TT,1.0,25,0.00125,0.8364,0.58553,0.58553,0.26821999999999996,0.26821999999999996,2.752683222222222,4.809016555555555,4.721416555555556,4.721149888888888,0.040664000000000006 +256,17,16,49,0,TT,1.0,25,0.005,0.052275,0.57848,0.57848,0.26581,0.26581,2.752683222222222,4.809016555555555,4.721416555555556,4.721149888888888,0.040664000000000006 +256,17,16,49,0,TT,1.0,25,0.005,0.2091,0.5800599999999999,0.5800599999999999,0.26658000000000004,0.26658000000000004,2.752683222222222,4.809016555555555,4.721416555555556,4.721149888888888,0.040664000000000006 +256,17,16,49,0,TT,1.0,25,0.005,0.8364,0.58597,0.58597,0.26754,0.26754,2.752683222222222,4.809016555555555,4.721416555555556,4.721149888888888,0.040664000000000006 +256,17,16,49,0,TT,1.0,25,0.04,0.052275,0.58292,0.58292,0.26671999999999996,0.26671999999999996,2.752683222222222,4.809016555555555,4.721416555555556,4.721149888888888,0.040664000000000006 +256,17,16,49,0,TT,1.0,25,0.04,0.2091,0.58372,0.58372,0.26713,0.26713,2.752683222222222,4.809016555555555,4.721416555555556,4.721149888888888,0.040664000000000006 +256,17,16,49,0,TT,1.0,25,0.04,0.8364,0.59056,0.59056,0.26844999999999997,0.26844999999999997,2.752683222222222,4.809016555555555,4.721416555555556,4.721149888888888,0.040664000000000006 +32,18,1,18,0,TT,1.0,25,0.00125,0.052275,0.34286999999999995,0.34286999999999995,0.3305,0.3305,0.7507451222222222,0.8881084555555555,0.7044717888888888,0.7042806777777777,0.0084411 +32,18,1,18,0,TT,1.0,25,0.00125,0.2091,0.34389,0.34389,0.33097,0.33097,0.7507451222222222,0.8881084555555555,0.7044717888888888,0.7042806777777777,0.0084411 +32,18,1,18,0,TT,1.0,25,0.00125,0.8364,0.34912,0.34912,0.33249,0.33249,0.7507451222222222,0.8881084555555555,0.7044717888888888,0.7042806777777777,0.0084411 +32,18,1,18,0,TT,1.0,25,0.005,0.052275,0.34353999999999996,0.34353999999999996,0.33037,0.33037,0.7507451222222222,0.8881084555555555,0.7044717888888888,0.7042806777777777,0.0084411 +32,18,1,18,0,TT,1.0,25,0.005,0.2091,0.34464,0.34464,0.33072,0.33072,0.7507451222222222,0.8881084555555555,0.7044717888888888,0.7042806777777777,0.0084411 +32,18,1,18,0,TT,1.0,25,0.005,0.8364,0.34981,0.34981,0.33209,0.33209,0.7507451222222222,0.8881084555555555,0.7044717888888888,0.7042806777777777,0.0084411 +32,18,1,18,0,TT,1.0,25,0.04,0.052275,0.34776,0.34776,0.33082999999999996,0.33082999999999996,0.7507451222222222,0.8881084555555555,0.7044717888888888,0.7042806777777777,0.0084411 +32,18,1,18,0,TT,1.0,25,0.04,0.2091,0.34893,0.34893,0.33091,0.33091,0.7507451222222222,0.8881084555555555,0.7044717888888888,0.7042806777777777,0.0084411 +32,18,1,18,0,TT,1.0,25,0.04,0.8364,0.35436,0.35436,0.33236,0.33236,0.7507451222222222,0.8881084555555555,0.7044717888888888,0.7042806777777777,0.0084411 +512,22,16,249,0,TT,1.0,25,0.00125,0.052275,1.6605,1.6605,0.22986,0.22986,3.9463950000000003,7.910672777777778,7.870661666666667,7.875750555555555,0.09105 +512,22,16,249,0,TT,1.0,25,0.00125,0.2091,1.6612,1.6612,0.23041999999999999,0.23041999999999999,3.9463950000000003,7.910672777777778,7.870661666666667,7.875750555555555,0.09105 +512,22,16,249,0,TT,1.0,25,0.00125,0.8364,1.6622999999999999,1.6622999999999999,0.23181,0.23181,3.9463950000000003,7.910672777777778,7.870661666666667,7.875750555555555,0.09105 +512,22,16,249,0,TT,1.0,25,0.005,0.052275,1.6606,1.6606,0.22952,0.22952,3.9463950000000003,7.910672777777778,7.870661666666667,7.875750555555555,0.09105 +512,22,16,249,0,TT,1.0,25,0.005,0.2091,1.6608,1.6608,0.22913,0.22913,3.9463950000000003,7.910672777777778,7.870661666666667,7.875750555555555,0.09105 +512,22,16,249,0,TT,1.0,25,0.005,0.8364,1.6597,1.6597,0.22829,0.22829,3.9463950000000003,7.910672777777778,7.870661666666667,7.875750555555555,0.09105 +512,22,16,249,0,TT,1.0,25,0.04,0.052275,1.6640000000000001,1.6640000000000001,0.22821,0.22821,3.9463950000000003,7.910672777777778,7.870661666666667,7.875750555555555,0.09105 +512,22,16,249,0,TT,1.0,25,0.04,0.2091,1.6653,1.6653,0.22913,0.22913,3.9463950000000003,7.910672777777778,7.870661666666667,7.875750555555555,0.09105 +512,22,16,249,0,TT,1.0,25,0.04,0.8364,1.6668999999999998,1.6668999999999998,0.23044,0.23044,3.9463950000000003,7.910672777777778,7.870661666666667,7.875750555555555,0.09105 +512,15,8,85,0,TT,1.0,25,0.00125,0.052275,0.81077,0.81077,0.25318999999999997,0.25318999999999997,1.6537620000000002,3.1433064444444443,3.083662,3.083550888888889,0.061834999999999994 +512,15,8,85,0,TT,1.0,25,0.00125,0.2091,0.81247,0.81247,0.25372,0.25372,1.6537620000000002,3.1433064444444443,3.083662,3.083550888888889,0.061834999999999994 +512,15,8,85,0,TT,1.0,25,0.00125,0.8364,0.81894,0.81894,0.25572,0.25572,1.6537620000000002,3.1433064444444443,3.083662,3.083550888888889,0.061834999999999994 +512,15,8,85,0,TT,1.0,25,0.005,0.052275,0.81113,0.81113,0.25397000000000003,0.25397000000000003,1.6537620000000002,3.1433064444444443,3.083662,3.083550888888889,0.061834999999999994 +512,15,8,85,0,TT,1.0,25,0.005,0.2091,0.8128500000000001,0.8128500000000001,0.25283999999999995,0.25283999999999995,1.6537620000000002,3.1433064444444443,3.083662,3.083550888888889,0.061834999999999994 +512,15,8,85,0,TT,1.0,25,0.005,0.8364,0.81927,0.81927,0.25543,0.25543,1.6537620000000002,3.1433064444444443,3.083662,3.083550888888889,0.061834999999999994 +512,15,8,85,0,TT,1.0,25,0.04,0.052275,0.81586,0.81586,0.25389,0.25389,1.6537620000000002,3.1433064444444443,3.083662,3.083550888888889,0.061834999999999994 +512,15,8,85,0,TT,1.0,25,0.04,0.2091,0.81748,0.81748,0.25489,0.25489,1.6537620000000002,3.1433064444444443,3.083662,3.083550888888889,0.061834999999999994 +512,15,8,85,0,TT,1.0,25,0.04,0.8364,0.82371,0.82371,0.25639,0.25639,1.6537620000000002,3.1433064444444443,3.083662,3.083550888888889,0.061834999999999994 +512,27,4,60,0,TT,1.0,25,0.00125,0.052275,0.8225199999999999,0.8225199999999999,0.28365999999999997,0.28365999999999997,1.6582586666666665,2.944914222222222,2.8431586666666666,2.8427920000000007,0.10886 +512,27,4,60,0,TT,1.0,25,0.00125,0.2091,0.8242400000000001,0.8242400000000001,0.28402,0.28402,1.6582586666666665,2.944914222222222,2.8431586666666666,2.8427920000000007,0.10886 +512,27,4,60,0,TT,1.0,25,0.00125,0.8364,0.8301999999999999,0.8301999999999999,0.28620999999999996,0.28620999999999996,1.6582586666666665,2.944914222222222,2.8431586666666666,2.8427920000000007,0.10886 +512,27,4,60,0,TT,1.0,25,0.005,0.052275,0.82333,0.82333,0.28382999999999997,0.28382999999999997,1.6582586666666665,2.944914222222222,2.8431586666666666,2.8427920000000007,0.10886 +512,27,4,60,0,TT,1.0,25,0.005,0.2091,0.8245300000000001,0.8245300000000001,0.2843,0.2843,1.6582586666666665,2.944914222222222,2.8431586666666666,2.8427920000000007,0.10886 +512,27,4,60,0,TT,1.0,25,0.005,0.8364,0.8310299999999999,0.8310299999999999,0.28607,0.28607,1.6582586666666665,2.944914222222222,2.8431586666666666,2.8427920000000007,0.10886 +512,27,4,60,0,TT,1.0,25,0.04,0.052275,0.82779,0.82779,0.28248,0.28248,1.6582586666666665,2.944914222222222,2.8431586666666666,2.8427920000000007,0.10886 +512,27,4,60,0,TT,1.0,25,0.04,0.2091,0.82894,0.82894,0.28298,0.28298,1.6582586666666665,2.944914222222222,2.8431586666666666,2.8427920000000007,0.10886 +512,27,4,60,0,TT,1.0,25,0.04,0.8364,0.83489,0.83489,0.28474,0.28474,1.6582586666666665,2.944914222222222,2.8431586666666666,2.8427920000000007,0.10886 +16,12,1,1,0,TT,1.0,25,0.00125,0.052275,0.28398,0.28398,0.29045000000000004,0.29045000000000004,0.6609966666666667,0.7927133333333334,0.6223755555555556,0.6238977777777779,0.0065626999999999994 +16,12,1,1,0,TT,1.0,25,0.00125,0.2091,0.28533,0.28533,0.29063,0.29063,0.6609966666666667,0.7927133333333334,0.6223755555555556,0.6238977777777779,0.0065626999999999994 +16,12,1,1,0,TT,1.0,25,0.00125,0.8364,0.29073,0.29073,0.29231,0.29231,0.6609966666666667,0.7927133333333334,0.6223755555555556,0.6238977777777779,0.0065626999999999994 +16,12,1,1,0,TT,1.0,25,0.005,0.052275,0.28465999999999997,0.28465999999999997,0.29035,0.29035,0.6609966666666667,0.7927133333333334,0.6223755555555556,0.6238977777777779,0.0065626999999999994 +16,12,1,1,0,TT,1.0,25,0.005,0.2091,0.2858,0.2858,0.29086,0.29086,0.6609966666666667,0.7927133333333334,0.6223755555555556,0.6238977777777779,0.0065626999999999994 +16,12,1,1,0,TT,1.0,25,0.005,0.8364,0.29102999999999996,0.29102999999999996,0.29207,0.29207,0.6609966666666667,0.7927133333333334,0.6223755555555556,0.6238977777777779,0.0065626999999999994 +16,12,1,1,0,TT,1.0,25,0.04,0.052275,0.28922000000000003,0.28922000000000003,0.29046,0.29046,0.6609966666666667,0.7927133333333334,0.6223755555555556,0.6238977777777779,0.0065626999999999994 +16,12,1,1,0,TT,1.0,25,0.04,0.2091,0.29036,0.29036,0.29098,0.29098,0.6609966666666667,0.7927133333333334,0.6223755555555556,0.6238977777777779,0.0065626999999999994 +16,12,1,1,0,TT,1.0,25,0.04,0.8364,0.29567000000000004,0.29567000000000004,0.29267,0.29267,0.6609966666666667,0.7927133333333334,0.6223755555555556,0.6238977777777779,0.0065626999999999994 +256,27,8,191,0,TT,1.0,25,0.00125,0.052275,1.1192,1.1192,0.28469,0.28469,2.8616455555555556,5.433612222222222,5.357312222222223,5.356867777777778,0.058220999999999995 +256,27,8,191,0,TT,1.0,25,0.00125,0.2091,1.1212,1.1212,0.286,0.286,2.8616455555555556,5.433612222222222,5.357312222222223,5.356867777777778,0.058220999999999995 +256,27,8,191,0,TT,1.0,25,0.00125,0.8364,1.1281,1.1281,0.28843,0.28843,2.8616455555555556,5.433612222222222,5.357312222222223,5.356867777777778,0.058220999999999995 +256,27,8,191,0,TT,1.0,25,0.005,0.052275,1.12,1.12,0.28461000000000003,0.28461000000000003,2.8616455555555556,5.433612222222222,5.357312222222223,5.356867777777778,0.058220999999999995 +256,27,8,191,0,TT,1.0,25,0.005,0.2091,1.1216,1.1216,0.28496,0.28496,2.8616455555555556,5.433612222222222,5.357312222222223,5.356867777777778,0.058220999999999995 +256,27,8,191,0,TT,1.0,25,0.005,0.8364,1.129,1.129,0.28575,0.28575,2.8616455555555556,5.433612222222222,5.357312222222223,5.356867777777778,0.058220999999999995 +256,27,8,191,0,TT,1.0,25,0.04,0.052275,1.1242999999999999,1.1242999999999999,0.28528000000000003,0.28528000000000003,2.8616455555555556,5.433612222222222,5.357312222222223,5.356867777777778,0.058220999999999995 +256,27,8,191,0,TT,1.0,25,0.04,0.2091,1.1262999999999999,1.1262999999999999,0.28525,0.28525,2.8616455555555556,5.433612222222222,5.357312222222223,5.356867777777778,0.058220999999999995 +256,27,8,191,0,TT,1.0,25,0.04,0.8364,1.1334,1.1334,0.28638,0.28638,2.8616455555555556,5.433612222222222,5.357312222222223,5.356867777777778,0.058220999999999995 +1024,64,4,0,0,TT,1.0,25,0.00125,0.052275,0.7484999999999999,0.7484999999999999,0.37309,0.37309,2.6633876666666665,3.3416209999999995,3.0794432222222223,3.0788321111111108,0.33807 +1024,64,4,0,0,TT,1.0,25,0.00125,0.2091,0.75021,0.75021,0.37358,0.37358,2.6633876666666665,3.3416209999999995,3.0794432222222223,3.0788321111111108,0.33807 +1024,64,4,0,0,TT,1.0,25,0.00125,0.8364,0.75676,0.75676,0.37532,0.37532,2.6633876666666665,3.3416209999999995,3.0794432222222223,3.0788321111111108,0.33807 +1024,64,4,0,0,TT,1.0,25,0.005,0.052275,0.7490199999999999,0.7490199999999999,0.37309,0.37309,2.6633876666666665,3.3416209999999995,3.0794432222222223,3.0788321111111108,0.33807 +1024,64,4,0,0,TT,1.0,25,0.005,0.2091,0.75092,0.75092,0.37370000000000003,0.37370000000000003,2.6633876666666665,3.3416209999999995,3.0794432222222223,3.0788321111111108,0.33807 +1024,64,4,0,0,TT,1.0,25,0.005,0.8364,0.75752,0.75752,0.37552,0.37552,2.6633876666666665,3.3416209999999995,3.0794432222222223,3.0788321111111108,0.33807 +1024,64,4,0,0,TT,1.0,25,0.04,0.052275,0.75399,0.75399,0.37582,0.37582,2.6633876666666665,3.3416209999999995,3.0794432222222223,3.0788321111111108,0.33807 +1024,64,4,0,0,TT,1.0,25,0.04,0.2091,0.75554,0.75554,0.37531000000000003,0.37531000000000003,2.6633876666666665,3.3416209999999995,3.0794432222222223,3.0788321111111108,0.33807 +1024,64,4,0,0,TT,1.0,25,0.04,0.8364,0.76181,0.76181,0.37611,0.37611,2.6633876666666665,3.3416209999999995,3.0794432222222223,3.0788321111111108,0.33807 +512,64,4,0,0,TT,1.0,25,0.00125,0.052275,0.65448,0.65448,0.42133,0.42133,2.2284265555555556,2.582793222222222,2.356371,2.3562598888888893,0.17347 +512,64,4,0,0,TT,1.0,25,0.00125,0.2091,0.6561600000000001,0.6561600000000001,0.42239,0.42239,2.2284265555555556,2.582793222222222,2.356371,2.3562598888888893,0.17347 +512,64,4,0,0,TT,1.0,25,0.00125,0.8364,0.66169,0.66169,0.42561,0.42561,2.2284265555555556,2.582793222222222,2.356371,2.3562598888888893,0.17347 +512,64,4,0,0,TT,1.0,25,0.005,0.052275,0.65515,0.65515,0.42155,0.42155,2.2284265555555556,2.582793222222222,2.356371,2.3562598888888893,0.17347 +512,64,4,0,0,TT,1.0,25,0.005,0.2091,0.6556799999999999,0.6556799999999999,0.42229999999999995,0.42229999999999995,2.2284265555555556,2.582793222222222,2.356371,2.3562598888888893,0.17347 +512,64,4,0,0,TT,1.0,25,0.005,0.8364,0.6625000000000001,0.6625000000000001,0.42538,0.42538,2.2284265555555556,2.582793222222222,2.356371,2.3562598888888893,0.17347 +512,64,4,0,0,TT,1.0,25,0.04,0.052275,0.65991,0.65991,0.42117,0.42117,2.2284265555555556,2.582793222222222,2.356371,2.3562598888888893,0.17347 +512,64,4,0,0,TT,1.0,25,0.04,0.2091,0.6612100000000001,0.6612100000000001,0.42212,0.42212,2.2284265555555556,2.582793222222222,2.356371,2.3562598888888893,0.17347 +512,64,4,0,0,TT,1.0,25,0.04,0.8364,0.66734,0.66734,0.42366000000000004,0.42366000000000004,2.2284265555555556,2.582793222222222,2.356371,2.3562598888888893,0.17347 +256,5,16,75,0,TT,1.0,25,0.00125,0.052275,0.66301,0.66301,0.21657,0.21657,1.0368410888888888,1.9255522,1.8943633111111113,1.8950410888888887,0.012858 +256,5,16,75,0,TT,1.0,25,0.00125,0.2091,0.66458,0.66458,0.21710000000000002,0.21710000000000002,1.0368410888888888,1.9255522,1.8943633111111113,1.8950410888888887,0.012858 +256,5,16,75,0,TT,1.0,25,0.00125,0.8364,0.67091,0.67091,0.21826,0.21826,1.0368410888888888,1.9255522,1.8943633111111113,1.8950410888888887,0.012858 +256,5,16,75,0,TT,1.0,25,0.005,0.052275,0.66364,0.66364,0.21685000000000001,0.21685000000000001,1.0368410888888888,1.9255522,1.8943633111111113,1.8950410888888887,0.012858 +256,5,16,75,0,TT,1.0,25,0.005,0.2091,0.6652499999999999,0.6652499999999999,0.21747,0.21747,1.0368410888888888,1.9255522,1.8943633111111113,1.8950410888888887,0.012858 +256,5,16,75,0,TT,1.0,25,0.005,0.8364,0.67162,0.67162,0.21839999999999998,0.21839999999999998,1.0368410888888888,1.9255522,1.8943633111111113,1.8950410888888887,0.012858 +256,5,16,75,0,TT,1.0,25,0.04,0.052275,0.66807,0.66807,0.21627,0.21627,1.0368410888888888,1.9255522,1.8943633111111113,1.8950410888888887,0.012858 +256,5,16,75,0,TT,1.0,25,0.04,0.2091,0.66976,0.66976,0.21675,0.21675,1.0368410888888888,1.9255522,1.8943633111111113,1.8950410888888887,0.012858 +256,5,16,75,0,TT,1.0,25,0.04,0.8364,0.67626,0.67626,0.21782,0.21782,1.0368410888888888,1.9255522,1.8943633111111113,1.8950410888888887,0.012858 +32,4,2,5,0,TT,1.0,25,0.00125,0.052275,0.30502999999999997,0.30502999999999997,0.24575,0.24575,0.41479390000000005,0.5094283444444445,0.44650278888888895,0.4462083444444444,0.0028599 +32,4,2,5,0,TT,1.0,25,0.00125,0.2091,0.30640999999999996,0.30640999999999996,0.24605,0.24605,0.41479390000000005,0.5094283444444445,0.44650278888888895,0.4462083444444444,0.0028599 +32,4,2,5,0,TT,1.0,25,0.00125,0.8364,0.31256,0.31256,0.24731999999999998,0.24731999999999998,0.41479390000000005,0.5094283444444445,0.44650278888888895,0.4462083444444444,0.0028599 +32,4,2,5,0,TT,1.0,25,0.005,0.052275,0.30556,0.30556,0.24584999999999999,0.24584999999999999,0.41479390000000005,0.5094283444444445,0.44650278888888895,0.4462083444444444,0.0028599 +32,4,2,5,0,TT,1.0,25,0.005,0.2091,0.30672,0.30672,0.24605999999999997,0.24605999999999997,0.41479390000000005,0.5094283444444445,0.44650278888888895,0.4462083444444444,0.0028599 +32,4,2,5,0,TT,1.0,25,0.005,0.8364,0.3134,0.3134,0.24727000000000002,0.24727000000000002,0.41479390000000005,0.5094283444444445,0.44650278888888895,0.4462083444444444,0.0028599 +32,4,2,5,0,TT,1.0,25,0.04,0.052275,0.31099,0.31099,0.24588,0.24588,0.41479390000000005,0.5094283444444445,0.44650278888888895,0.4462083444444444,0.0028599 +32,4,2,5,0,TT,1.0,25,0.04,0.2091,0.31221,0.31221,0.24651,0.24651,0.41479390000000005,0.5094283444444445,0.44650278888888895,0.4462083444444444,0.0028599 +32,4,2,5,0,TT,1.0,25,0.04,0.8364,0.31865,0.31865,0.24758,0.24758,0.41479390000000005,0.5094283444444445,0.44650278888888895,0.4462083444444444,0.0028599 +1024,32,8,0,0,TT,1.0,25,0.00125,0.052275,0.63671,0.63671,0.31766,0.31766,2.018787111111111,2.913942666666667,2.7620093333333333,2.7609426666666668,0.1718 +1024,32,8,0,0,TT,1.0,25,0.00125,0.2091,0.6386999999999999,0.6386999999999999,0.31834999999999997,0.31834999999999997,2.018787111111111,2.913942666666667,2.7620093333333333,2.7609426666666668,0.1718 +1024,32,8,0,0,TT,1.0,25,0.00125,0.8364,0.64426,0.64426,0.32078999999999996,0.32078999999999996,2.018787111111111,2.913942666666667,2.7620093333333333,2.7609426666666668,0.1718 +1024,32,8,0,0,TT,1.0,25,0.005,0.052275,0.6377200000000001,0.6377200000000001,0.31766,0.31766,2.018787111111111,2.913942666666667,2.7620093333333333,2.7609426666666668,0.1718 +1024,32,8,0,0,TT,1.0,25,0.005,0.2091,0.63897,0.63897,0.31832,0.31832,2.018787111111111,2.913942666666667,2.7620093333333333,2.7609426666666668,0.1718 +1024,32,8,0,0,TT,1.0,25,0.005,0.8364,0.64432,0.64432,0.32087,0.32087,2.018787111111111,2.913942666666667,2.7620093333333333,2.7609426666666668,0.1718 +1024,32,8,0,0,TT,1.0,25,0.04,0.052275,0.6418699999999999,0.6418699999999999,0.31814,0.31814,2.018787111111111,2.913942666666667,2.7620093333333333,2.7609426666666668,0.1718 +1024,32,8,0,0,TT,1.0,25,0.04,0.2091,0.64316,0.64316,0.31871,0.31871,2.018787111111111,2.913942666666667,2.7620093333333333,2.7609426666666668,0.1718 +1024,32,8,0,0,TT,1.0,25,0.04,0.8364,0.64915,0.64915,0.32105999999999996,0.32105999999999996,2.018787111111111,2.913942666666667,2.7620093333333333,2.7609426666666668,0.1718 +1024,16,16,40,0,TT,1.0,25,0.00125,0.052275,0.58144,0.58144,0.25797,0.25797,2.575803222222222,4.556358777777778,4.471125444444445,4.4691032222222224,0.13135 +1024,16,16,40,0,TT,1.0,25,0.00125,0.2091,0.5829399999999999,0.5829399999999999,0.25837,0.25837,2.575803222222222,4.556358777777778,4.471125444444445,4.4691032222222224,0.13135 +1024,16,16,40,0,TT,1.0,25,0.00125,0.8364,0.58911,0.58911,0.26042000000000004,0.26042000000000004,2.575803222222222,4.556358777777778,4.471125444444445,4.4691032222222224,0.13135 +1024,16,16,40,0,TT,1.0,25,0.005,0.052275,0.58187,0.58187,0.25808,0.25808,2.575803222222222,4.556358777777778,4.471125444444445,4.4691032222222224,0.13135 +1024,16,16,40,0,TT,1.0,25,0.005,0.2091,0.5836899999999999,0.5836899999999999,0.25821,0.25821,2.575803222222222,4.556358777777778,4.471125444444445,4.4691032222222224,0.13135 +1024,16,16,40,0,TT,1.0,25,0.005,0.8364,0.5898599999999999,0.5898599999999999,0.26034,0.26034,2.575803222222222,4.556358777777778,4.471125444444445,4.4691032222222224,0.13135 +1024,16,16,40,0,TT,1.0,25,0.04,0.052275,0.58653,0.58653,0.25834999999999997,0.25834999999999997,2.575803222222222,4.556358777777778,4.471125444444445,4.4691032222222224,0.13135 +1024,16,16,40,0,TT,1.0,25,0.04,0.2091,0.58827,0.58827,0.25841,0.25841,2.575803222222222,4.556358777777778,4.471125444444445,4.4691032222222224,0.13135 +1024,16,16,40,0,TT,1.0,25,0.04,0.8364,0.59409,0.59409,0.26028999999999997,0.26028999999999997,2.575803222222222,4.556358777777778,4.471125444444445,4.4691032222222224,0.13135 +32,32,1,31,0,TT,1.0,25,0.00125,0.052275,0.39809,0.39809,0.38494,0.38494,1.0239104444444445,1.2246882222222224,0.9484993333333332,0.9491537777777778,0.013528 +32,32,1,31,0,TT,1.0,25,0.00125,0.2091,0.39943,0.39943,0.38543,0.38543,1.0239104444444445,1.2246882222222224,0.9484993333333332,0.9491537777777778,0.013528 +32,32,1,31,0,TT,1.0,25,0.00125,0.8364,0.40502,0.40502,0.38669,0.38669,1.0239104444444445,1.2246882222222224,0.9484993333333332,0.9491537777777778,0.013528 +32,32,1,31,0,TT,1.0,25,0.005,0.052275,0.39864,0.39864,0.38508,0.38508,1.0239104444444445,1.2246882222222224,0.9484993333333332,0.9491537777777778,0.013528 +32,32,1,31,0,TT,1.0,25,0.005,0.2091,0.40009,0.40009,0.38528,0.38528,1.0239104444444445,1.2246882222222224,0.9484993333333332,0.9491537777777778,0.013528 +32,32,1,31,0,TT,1.0,25,0.005,0.8364,0.40516,0.40516,0.38643,0.38643,1.0239104444444445,1.2246882222222224,0.9484993333333332,0.9491537777777778,0.013528 +32,32,1,31,0,TT,1.0,25,0.04,0.052275,0.40308,0.40308,0.38532,0.38532,1.0239104444444445,1.2246882222222224,0.9484993333333332,0.9491537777777778,0.013528 +32,32,1,31,0,TT,1.0,25,0.04,0.2091,0.40458,0.40458,0.38577,0.38577,1.0239104444444445,1.2246882222222224,0.9484993333333332,0.9491537777777778,0.013528 +32,32,1,31,0,TT,1.0,25,0.04,0.8364,0.40956,0.40956,0.38703,0.38703,1.0239104444444445,1.2246882222222224,0.9484993333333332,0.9491537777777778,0.013528 +256,12,8,17,0,TT,1.0,25,0.00125,0.052275,0.42535,0.42535,0.26105999999999996,0.26105999999999996,1.2404507777777778,1.6185285555555555,1.5411507777777778,1.5407285555555557,0.028741000000000003 +256,12,8,17,0,TT,1.0,25,0.00125,0.2091,0.42707999999999996,0.42707999999999996,0.26165000000000005,0.26165000000000005,1.2404507777777778,1.6185285555555555,1.5411507777777778,1.5407285555555557,0.028741000000000003 +256,12,8,17,0,TT,1.0,25,0.00125,0.8364,0.43297,0.43297,0.26285,0.26285,1.2404507777777778,1.6185285555555555,1.5411507777777778,1.5407285555555557,0.028741000000000003 +256,12,8,17,0,TT,1.0,25,0.005,0.052275,0.42607,0.42607,0.26083,0.26083,1.2404507777777778,1.6185285555555555,1.5411507777777778,1.5407285555555557,0.028741000000000003 +256,12,8,17,0,TT,1.0,25,0.005,0.2091,0.42774,0.42774,0.26114,0.26114,1.2404507777777778,1.6185285555555555,1.5411507777777778,1.5407285555555557,0.028741000000000003 +256,12,8,17,0,TT,1.0,25,0.005,0.8364,0.43376000000000003,0.43376000000000003,0.26282,0.26282,1.2404507777777778,1.6185285555555555,1.5411507777777778,1.5407285555555557,0.028741000000000003 +256,12,8,17,0,TT,1.0,25,0.04,0.052275,0.43068999999999996,0.43068999999999996,0.26122999999999996,0.26122999999999996,1.2404507777777778,1.6185285555555555,1.5411507777777778,1.5407285555555557,0.028741000000000003 +256,12,8,17,0,TT,1.0,25,0.04,0.2091,0.43226000000000003,0.43226000000000003,0.26174000000000003,0.26174000000000003,1.2404507777777778,1.6185285555555555,1.5411507777777778,1.5407285555555557,0.028741000000000003 +256,12,8,17,0,TT,1.0,25,0.04,0.8364,0.43858,0.43858,0.26295999999999997,0.26295999999999997,1.2404507777777778,1.6185285555555555,1.5411507777777778,1.5407285555555557,0.028741000000000003 +1024,21,4,54,0,TT,1.0,25,0.00125,0.052275,0.8127099999999999,0.8127099999999999,0.24213,0.24213,1.4336077777777778,2.5185744444444444,2.4333299999999998,2.4329188888888886,0.1669 +1024,21,4,54,0,TT,1.0,25,0.00125,0.2091,0.81429,0.81429,0.24216000000000001,0.24216000000000001,1.4336077777777778,2.5185744444444444,2.4333299999999998,2.4329188888888886,0.1669 +1024,21,4,54,0,TT,1.0,25,0.00125,0.8364,0.82065,0.82065,0.2434,0.2434,1.4336077777777778,2.5185744444444444,2.4333299999999998,2.4329188888888886,0.1669 +1024,21,4,54,0,TT,1.0,25,0.005,0.052275,0.81346,0.81346,0.24179,0.24179,1.4336077777777778,2.5185744444444444,2.4333299999999998,2.4329188888888886,0.1669 +1024,21,4,54,0,TT,1.0,25,0.005,0.2091,0.81463,0.81463,0.24216000000000001,0.24216000000000001,1.4336077777777778,2.5185744444444444,2.4333299999999998,2.4329188888888886,0.1669 +1024,21,4,54,0,TT,1.0,25,0.005,0.8364,0.8213600000000001,0.8213600000000001,0.24308999999999997,0.24308999999999997,1.4336077777777778,2.5185744444444444,2.4333299999999998,2.4329188888888886,0.1669 +1024,21,4,54,0,TT,1.0,25,0.04,0.052275,0.81781,0.81781,0.24241,0.24241,1.4336077777777778,2.5185744444444444,2.4333299999999998,2.4329188888888886,0.1669 +1024,21,4,54,0,TT,1.0,25,0.04,0.2091,0.81908,0.81908,0.24293,0.24293,1.4336077777777778,2.5185744444444444,2.4333299999999998,2.4329188888888886,0.1669 +1024,21,4,54,0,TT,1.0,25,0.04,0.8364,0.82637,0.82637,0.24331,0.24331,1.4336077777777778,2.5185744444444444,2.4333299999999998,2.4329188888888886,0.1669 +16,6,1,1,0,TT,1.0,25,0.00125,0.052275,0.26095999999999997,0.26095999999999997,0.26767,0.26767,0.4605411111111111,0.5804677777777778,0.48906111111111117,0.4905355555555555,0.0037517 +16,6,1,1,0,TT,1.0,25,0.00125,0.2091,0.26216,0.26216,0.26804,0.26804,0.4605411111111111,0.5804677777777778,0.48906111111111117,0.4905355555555555,0.0037517 +16,6,1,1,0,TT,1.0,25,0.00125,0.8364,0.26697,0.26697,0.26952000000000004,0.26952000000000004,0.4605411111111111,0.5804677777777778,0.48906111111111117,0.4905355555555555,0.0037517 +16,6,1,1,0,TT,1.0,25,0.005,0.052275,0.26118,0.26118,0.26757,0.26757,0.4605411111111111,0.5804677777777778,0.48906111111111117,0.4905355555555555,0.0037517 +16,6,1,1,0,TT,1.0,25,0.005,0.2091,0.26266,0.26266,0.26805,0.26805,0.4605411111111111,0.5804677777777778,0.48906111111111117,0.4905355555555555,0.0037517 +16,6,1,1,0,TT,1.0,25,0.005,0.8364,0.26791,0.26791,0.26925,0.26925,0.4605411111111111,0.5804677777777778,0.48906111111111117,0.4905355555555555,0.0037517 +16,6,1,1,0,TT,1.0,25,0.04,0.052275,0.26682,0.26682,0.26773,0.26773,0.4605411111111111,0.5804677777777778,0.48906111111111117,0.4905355555555555,0.0037517 +16,6,1,1,0,TT,1.0,25,0.04,0.2091,0.26814,0.26814,0.2683,0.2683,0.4605411111111111,0.5804677777777778,0.48906111111111117,0.4905355555555555,0.0037517 +16,6,1,1,0,TT,1.0,25,0.04,0.8364,0.27316,0.27316,0.26947,0.26947,0.4605411111111111,0.5804677777777778,0.48906111111111117,0.4905355555555555,0.0037517 +512,8,8,0,0,TT,1.0,25,0.00125,0.052275,0.41187999999999997,0.41187999999999997,0.25485,0.25485,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.00125,0.2091,0.41344000000000003,0.41344000000000003,0.25508000000000003,0.25508000000000003,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.00125,0.8364,0.41973,0.41973,0.25621,0.25621,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.005,0.052275,0.4124,0.4124,0.25453,0.25453,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.005,0.2091,0.41421,0.41421,0.25514000000000003,0.25514000000000003,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.005,0.8364,0.4204,0.4204,0.25642,0.25642,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.04,0.052275,0.41726,0.41726,0.25458000000000003,0.25458000000000003,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.04,0.2091,0.41863,0.41863,0.25496,0.25496,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.04,0.8364,0.42510000000000003,0.42510000000000003,0.25647,0.25647,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +256,32,4,0,0,TT,1.0,25,0.00125,0.052275,0.45405,0.45405,0.34162,0.34162,1.661666777777778,1.6992112222222222,1.520577888888889,1.5201223333333334,0.049185 +256,32,4,0,0,TT,1.0,25,0.00125,0.2091,0.45528,0.45528,0.34209999999999996,0.34209999999999996,1.661666777777778,1.6992112222222222,1.520577888888889,1.5201223333333334,0.049185 +256,32,4,0,0,TT,1.0,25,0.00125,0.8364,0.46157,0.46157,0.3443,0.3443,1.661666777777778,1.6992112222222222,1.520577888888889,1.5201223333333334,0.049185 +256,32,4,0,0,TT,1.0,25,0.005,0.052275,0.45478,0.45478,0.34142,0.34142,1.661666777777778,1.6992112222222222,1.520577888888889,1.5201223333333334,0.049185 +256,32,4,0,0,TT,1.0,25,0.005,0.2091,0.45639,0.45639,0.342,0.342,1.661666777777778,1.6992112222222222,1.520577888888889,1.5201223333333334,0.049185 +256,32,4,0,0,TT,1.0,25,0.005,0.8364,0.46215999999999996,0.46215999999999996,0.34429,0.34429,1.661666777777778,1.6992112222222222,1.520577888888889,1.5201223333333334,0.049185 +256,32,4,0,0,TT,1.0,25,0.04,0.052275,0.45906,0.45906,0.34167000000000003,0.34167000000000003,1.661666777777778,1.6992112222222222,1.520577888888889,1.5201223333333334,0.049185 +256,32,4,0,0,TT,1.0,25,0.04,0.2091,0.46106,0.46106,0.34254,0.34254,1.661666777777778,1.6992112222222222,1.520577888888889,1.5201223333333334,0.049185 +256,32,4,0,0,TT,1.0,25,0.04,0.8364,0.46706000000000003,0.46706000000000003,0.34437,0.34437,1.661666777777778,1.6992112222222222,1.520577888888889,1.5201223333333334,0.049185 +1024,8,16,0,0,TT,1.0,25,0.00125,0.052275,0.5018900000000001,0.5018900000000001,0.24662000000000003,0.24662000000000003,1.1389833333333332,1.4221277777777779,1.366761111111111,1.36785,0.046667 +1024,8,16,0,0,TT,1.0,25,0.00125,0.2091,0.50374,0.50374,0.24719,0.24719,1.1389833333333332,1.4221277777777779,1.366761111111111,1.36785,0.046667 +1024,8,16,0,0,TT,1.0,25,0.00125,0.8364,0.5103,0.5103,0.24869,0.24869,1.1389833333333332,1.4221277777777779,1.366761111111111,1.36785,0.046667 +1024,8,16,0,0,TT,1.0,25,0.005,0.052275,0.50258,0.50258,0.2466,0.2466,1.1389833333333332,1.4221277777777779,1.366761111111111,1.36785,0.046667 +1024,8,16,0,0,TT,1.0,25,0.005,0.2091,0.50431,0.50431,0.24699999999999997,0.24699999999999997,1.1389833333333332,1.4221277777777779,1.366761111111111,1.36785,0.046667 +1024,8,16,0,0,TT,1.0,25,0.005,0.8364,0.5107,0.5107,0.24854,0.24854,1.1389833333333332,1.4221277777777779,1.366761111111111,1.36785,0.046667 +1024,8,16,0,0,TT,1.0,25,0.04,0.052275,0.50744,0.50744,0.24681999999999998,0.24681999999999998,1.1389833333333332,1.4221277777777779,1.366761111111111,1.36785,0.046667 +1024,8,16,0,0,TT,1.0,25,0.04,0.2091,0.50883,0.50883,0.24710000000000001,0.24710000000000001,1.1389833333333332,1.4221277777777779,1.366761111111111,1.36785,0.046667 +1024,8,16,0,0,TT,1.0,25,0.04,0.8364,0.51523,0.51523,0.2486,0.2486,1.1389833333333332,1.4221277777777779,1.366761111111111,1.36785,0.046667 +32,14,2,23,0,TT,1.0,25,0.00125,0.052275,0.40019,0.40019,0.28265,0.28265,0.7410601222222223,0.9264201222222221,0.7936212333333333,0.7924412333333333,0.0065994 +32,14,2,23,0,TT,1.0,25,0.00125,0.2091,0.40174,0.40174,0.28288,0.28288,0.7410601222222223,0.9264201222222221,0.7936212333333333,0.7924412333333333,0.0065994 +32,14,2,23,0,TT,1.0,25,0.00125,0.8364,0.40787,0.40787,0.28422,0.28422,0.7410601222222223,0.9264201222222221,0.7936212333333333,0.7924412333333333,0.0065994 +32,14,2,23,0,TT,1.0,25,0.005,0.052275,0.40075,0.40075,0.28248,0.28248,0.7410601222222223,0.9264201222222221,0.7936212333333333,0.7924412333333333,0.0065994 +32,14,2,23,0,TT,1.0,25,0.005,0.2091,0.40238999999999997,0.40238999999999997,0.28286999999999995,0.28286999999999995,0.7410601222222223,0.9264201222222221,0.7936212333333333,0.7924412333333333,0.0065994 +32,14,2,23,0,TT,1.0,25,0.005,0.8364,0.4085,0.4085,0.28432,0.28432,0.7410601222222223,0.9264201222222221,0.7936212333333333,0.7924412333333333,0.0065994 +32,14,2,23,0,TT,1.0,25,0.04,0.052275,0.40541,0.40541,0.28291,0.28291,0.7410601222222223,0.9264201222222221,0.7936212333333333,0.7924412333333333,0.0065994 +32,14,2,23,0,TT,1.0,25,0.04,0.2091,0.40645,0.40645,0.28332,0.28332,0.7410601222222223,0.9264201222222221,0.7936212333333333,0.7924412333333333,0.0065994 +32,14,2,23,0,TT,1.0,25,0.04,0.8364,0.41269999999999996,0.41269999999999996,0.28459999999999996,0.28459999999999996,0.7410601222222223,0.9264201222222221,0.7936212333333333,0.7924412333333333,0.0065994 +256,8,8,0,0,TT,1.0,25,0.00125,0.052275,0.38406,0.38406,0.2619,0.2619,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.00125,0.2091,0.38583,0.38583,0.26224000000000003,0.26224000000000003,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.00125,0.8364,0.3919,0.3919,0.26391000000000003,0.26391000000000003,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.005,0.052275,0.38477,0.38477,0.26191,0.26191,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.005,0.2091,0.38619,0.38619,0.26216,0.26216,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.005,0.8364,0.39225000000000004,0.39225000000000004,0.26381,0.26381,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.04,0.052275,0.38925000000000004,0.38925000000000004,0.2621,0.2621,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.04,0.2091,0.39111999999999997,0.39111999999999997,0.26225,0.26225,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.04,0.8364,0.39707,0.39707,0.264,0.264,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +512,32,4,0,0,TT,1.0,25,0.00125,0.052275,0.5222600000000001,0.5222600000000001,0.31686,0.31686,1.6074554444444447,1.8241554444444443,1.6588554444444445,1.6592776666666669,0.091441 +512,32,4,0,0,TT,1.0,25,0.00125,0.2091,0.52378,0.52378,0.31689,0.31689,1.6074554444444447,1.8241554444444443,1.6588554444444445,1.6592776666666669,0.091441 +512,32,4,0,0,TT,1.0,25,0.00125,0.8364,0.52941,0.52941,0.31903,0.31903,1.6074554444444447,1.8241554444444443,1.6588554444444445,1.6592776666666669,0.091441 +512,32,4,0,0,TT,1.0,25,0.005,0.052275,0.52267,0.52267,0.31698,0.31698,1.6074554444444447,1.8241554444444443,1.6588554444444445,1.6592776666666669,0.091441 +512,32,4,0,0,TT,1.0,25,0.005,0.2091,0.52425,0.52425,0.31673999999999997,0.31673999999999997,1.6074554444444447,1.8241554444444443,1.6588554444444445,1.6592776666666669,0.091441 +512,32,4,0,0,TT,1.0,25,0.005,0.8364,0.53028,0.53028,0.31927,0.31927,1.6074554444444447,1.8241554444444443,1.6588554444444445,1.6592776666666669,0.091441 +512,32,4,0,0,TT,1.0,25,0.04,0.052275,0.52742,0.52742,0.31582,0.31582,1.6074554444444447,1.8241554444444443,1.6588554444444445,1.6592776666666669,0.091441 +512,32,4,0,0,TT,1.0,25,0.04,0.2091,0.5289699999999999,0.5289699999999999,0.31623,0.31623,1.6074554444444447,1.8241554444444443,1.6588554444444445,1.6592776666666669,0.091441 +512,32,4,0,0,TT,1.0,25,0.04,0.8364,0.5341899999999999,0.5341899999999999,0.3189,0.3189,1.6074554444444447,1.8241554444444443,1.6588554444444445,1.6592776666666669,0.091441 diff --git a/technology/freepdk45/sim_data/write0_power.csv b/technology/freepdk45/sim_data/write0_power.csv deleted file mode 100644 index d1aa3786..00000000 --- a/technology/freepdk45/sim_data/write0_power.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,write0_power -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.5987044444444445 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.44650666666666666 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.5227588888888889 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.5357155555555555 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.40510666666666667 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.46823333333333333 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.4518333333333333 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.33565222222222224 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.37737333333333334 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.48253111111111113 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.3785866666666667 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.42674111111111107 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.4481144444444445 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.3461288888888889 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.39059222222222223 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.4936044444444444 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.36787222222222227 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.4307977777777778 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.5488922222222222 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.41788222222222227 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.4881888888888889 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.40128444444444444 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.3089811111111111 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.3490755555555556 diff --git a/technology/freepdk45/sim_data/write1_power.csv b/technology/freepdk45/sim_data/write1_power.csv deleted file mode 100644 index e0f52798..00000000 --- a/technology/freepdk45/sim_data/write1_power.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,write1_power -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.5261355555555556 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.40059666666666666 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.4624466666666667 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.45413222222222216 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.3441577777777778 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.39791999999999994 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.3642022222222222 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.27147333333333334 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.3076588888888889 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.40458444444444447 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.3120677777777778 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.35318999999999995 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.36643111111111115 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.28035333333333334 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.3188844444444444 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.40822222222222215 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.30674111111111113 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.35570999999999997 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.4593966666666667 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.3476077777777778 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.4021511111111111 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.3219666666666667 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.24487 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.24487 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.24487 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.24487 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.24487 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.24487 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.24487 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.24487 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.24487 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.27919111111111117 diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 794042f3..f5decd3c 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -135,6 +135,8 @@ layer["m10"] = (29, 0) layer["text"] = (239, 0) layer["boundary"]= (239, 0) +use_purpose = {} + # Layer names for external PDKs layer_names = {} layer_names["active"] = "active" diff --git a/technology/freepdk45/tf/FreePDK45.lyp b/technology/freepdk45/tf/FreePDK45.lyp index 29e8e32f..4823c15a 100644 --- a/technology/freepdk45/tf/FreePDK45.lyp +++ b/technology/freepdk45/tf/FreePDK45.lyp @@ -5,7 +5,7 @@ #ff8000 0 0 - C36 + C35 C0 true true @@ -22,7 +22,7 @@ #00cc66 0 0 - C36 + C35 C0 true true @@ -39,7 +39,7 @@ #0000ff 0 0 - C41 + C40 C1 true true @@ -56,7 +56,7 @@ #0000ff 0 0 - C42 + C41 C1 true true @@ -73,7 +73,7 @@ #00cc66 0 0 - C34 + C33 C0 true true @@ -85,6 +85,23 @@ active.drawing - 1/0 1/0@1 + + #00cc66 + #00cc66 + 0 + 0 + C34 + C0 + false + true + false + 1 + false + false + 0 + active.blockage - 1/1 + 1/1@1 + #00cc66 #00cc66 @@ -124,7 +141,7 @@ #ff0000 0 0 - C37 + C36 C0 true true @@ -136,12 +153,29 @@ poly.drawing - 9/0 9/0@1 + + #ff0000 + #ff0000 + 0 + 0 + C37 + C0 + false + true + false + 1 + false + false + 0 + poly.blockage - 9/1 + 9/1@1 + #ffff00 #ffff00 0 0 - C43 + C42 C0 true true @@ -154,21 +188,38 @@ 8/0@1 - #00cc66 - #00cc66 + #00ff00 + #000000 0 0 - C1 + I1 C0 true true false + 2 + false + true + 0 + contact.drawing - 10/0 + 10/0@1 + + + #00ff00 + #000000 + 0 + 0 + I1 + C0 + false + true + false 1 false false 0 - contact.drawing - 10/0 - 10/0@1 + contact.blockage - 10/1 + 10/1@1 #0000ff @@ -188,22 +239,73 @@ 11/0@1 - #333399 - #ff00ff + #0000ff + #0000ff 0 0 - C39 + C12 C0 - true + false true false 1 false false 0 + metal1.blockage - 11/1 + 11/1@1 + + + #0000ff + #0000ff + 0 + 0 + C12 + C0 + true + true + false + 3 + false + false + 0 + metal1.pin - 11/2 + 11/2@1 + + + #333399 + #ff00ff + 0 + 0 + C38 + C0 + true + true + false + 1 + false + true + 0 via1.drawing - 12/0 12/0@1 + + #333399 + #ff00ff + 0 + 0 + C38 + C0 + false + true + false + 1 + false + false + 0 + via1.blockage - 12/1 + 12/1@1 + #ff00ff #ff00ff @@ -222,22 +324,73 @@ 13/0@1 - #39bfff - #39bfff + #ff00ff + #ff00ff 0 0 - C39 + C2 C0 - true + false true false 1 false false 0 + metal2.blockage - 13/1 + 13/1@1 + + + #ff00ff + #ff00ff + 0 + 0 + C2 + C0 + true + true + false + 3 + false + false + 0 + metal2.pin - 13/2 + 13/2@1 + + + #39bfff + #39bfff + 0 + 0 + C38 + C0 + true + true + false + 1 + false + true + 0 via2.drawing - 14/0 14/0@1 + + #39bfff + #39bfff + 0 + 0 + C38 + C0 + false + true + false + 1 + false + false + 0 + via2.blockage - 14/1 + 14/1@1 + #00ffff #00ffff @@ -256,28 +409,79 @@ 15/0@1 - #ffe6bf - #ffe6bf + #00ffff + #00ffff 0 0 - C39 + C11 C0 - true + false true false 1 false false 0 + metal3.blockage - 15/1 + 15/1@1 + + + #00ffff + #00ffff + 0 + 0 + C11 + C0 + true + true + false + 3 + false + false + 0 + metal3.pin - 15/2 + 15/2@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C38 + C0 + true + true + false + 1 + false + true + 0 via3.drawing - 16/0 16/0@1 + + #ffe6bf + #ffe6bf + 0 + 0 + C38 + C0 + false + true + false + 1 + false + false + 0 + via3.blockage - 16/1 + 16/1@1 + #ffffcc #ffffcc 0 0 - C25 + C24 C0 true true @@ -290,28 +494,79 @@ 17/0@1 - #0000ff - #0000ff + #ffffcc + #ffffcc 0 0 - C39 + C24 C0 - true + false true false 1 false false 0 + metal4.blockage - 17/1 + 17/1@1 + + + #ffffcc + #ffffcc + 0 + 0 + C24 + C0 + true + true + false + 3 + false + false + 0 + metal4.pin - 17/2 + 17/2@1 + + + #0000ff + #0000ff + 0 + 0 + C38 + C0 + true + true + false + 1 + false + true + 0 via4.drawing - 18/0 18/0@1 + + #0000ff + #0000ff + 0 + 0 + C38 + C0 + false + true + false + 1 + false + false + 0 + via4.blockage - 18/1 + 18/1@1 + #39bfff #39bfff 0 0 - C29 + C28 C0 true true @@ -324,22 +579,73 @@ 19/0@1 - #ffff00 - #ffff00 + #39bfff + #39bfff 0 0 - C39 + C28 C0 - true + false true false 1 false false 0 + metal5.blockage - 19/1 + 19/1@1 + + + #39bfff + #39bfff + 0 + 0 + C28 + C0 + true + true + false + 3 + false + false + 0 + metal5.pin - 19/2 + 19/2@1 + + + #ffff00 + #ffff00 + 0 + 0 + C38 + C0 + true + true + false + 1 + false + true + 0 via5.drawing - 20/0 20/0@1 + + #ffff00 + #ffff00 + 0 + 0 + C38 + C0 + false + true + false + 1 + false + false + 0 + via5.blockage - 20/1 + 20/1@1 + #d9cc00 #d9cc00 @@ -358,22 +664,73 @@ 21/0@1 - #ff00ff - #ff00ff + #d9cc00 + #d9cc00 0 0 - C39 + C8 C0 - true + false true false 1 false false 0 + metal6.blockage - 21/1 + 21/1@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C8 + C0 + true + true + false + 3 + false + false + 0 + metal6.pin - 21/2 + 21/2@1 + + + #ff00ff + #ff00ff + 0 + 0 + C38 + C0 + true + true + false + 1 + false + true + 0 via6.drawing - 22/0 22/0@1 + + #ff00ff + #ff00ff + 0 + 0 + C38 + C0 + false + true + false + 1 + false + false + 0 + via6.blockage - 22/1 + 22/1@1 + #00ff00 #00ff00 @@ -392,22 +749,73 @@ 23/0@1 - #39bfff - #39bfff + #00ff00 + #00ff00 0 0 - C39 + C11 C0 - true + false true false 1 false false 0 + metal7.blockage - 23/1 + 23/1@1 + + + #00ff00 + #00ff00 + 0 + 0 + C11 + C0 + true + true + false + 3 + false + false + 0 + metal7.pin - 23/2 + 23/2@1 + + + #39bfff + #39bfff + 0 + 0 + C38 + C0 + true + true + false + 1 + false + true + 0 via7.drawing - 24/0 24/0@1 + + #39bfff + #39bfff + 0 + 0 + C38 + C0 + false + true + false + 1 + false + false + 0 + via7.blockage - 24/1 + 24/1@1 + #ffffff #ffffff @@ -426,22 +834,73 @@ 25/0@1 - #ffffcc - #ffffcc + #ffffff + #ffffff 0 0 - C39 + C4 C0 - true + false true false 1 false false 0 + metal8.blockage - 25/1 + 25/1@1 + + + #ffffff + #ffffff + 0 + 0 + C4 + C0 + true + true + false + 3 + false + false + 0 + metal8.pin - 25/2 + 25/2@1 + + + #ffffcc + #ffffcc + 0 + 0 + C38 + C0 + true + true + false + 1 + false + true + 0 via8.drawing - 26/0 26/0@1 + + #ffffcc + #ffffcc + 0 + 0 + C38 + C0 + false + true + false + 1 + false + false + 0 + via8.blockage - 26/1 + 26/1@1 + #ffe6bf #ffe6bf @@ -460,28 +919,79 @@ 27/0@1 - #0000ff - #0000ff + #ffe6bf + #ffe6bf 0 0 - C39 + C6 C0 - true + false true false 1 false false 0 + metal9.blockage - 27/1 + 27/1@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C6 + C0 + true + true + false + 3 + false + false + 0 + metal9.pin - 27/2 + 27/2@1 + + + #0000ff + #0000ff + 0 + 0 + C38 + C0 + true + true + false + 1 + false + true + 0 via9.drawing - 28/0 28/0@1 + + #0000ff + #0000ff + 0 + 0 + C38 + C0 + false + true + false + 1 + false + false + 0 + via9.blockage - 28/1 + 28/1@1 + #ff8000 #ff8000 0 0 - C29 + C28 C0 true true @@ -493,6 +1003,57 @@ metal10.drawing - 29/0 29/0@1 + + #ff8000 + #ff8000 + 0 + 0 + C28 + C0 + false + true + false + 1 + false + false + 0 + metal10.blockage - 29/1 + 29/1@1 + + + #ff8000 + #ff8000 + 0 + 0 + C28 + C0 + true + true + false + 3 + false + false + 0 + metal10.pin - 29/2 + 29/2@1 + + + #ffff00 + #ffff00 + 0 + 0 + C0 + + true + true + false + 1 + false + false + 0 + text.drawing - 230/0 + 230/0@1 + #9900e6 #9900e6 @@ -510,6 +1071,142 @@ comment.drawing - 239/0 239/0@1 + + #01ff6b + #01ff6b + 0 + 0 + I3 + I6 + true + true + false + 1 + false + false + 0 + phot_silicon.drawing + 400/0@1 + + + #808080 + #808080 + 0 + 0 + I2 + I0 + true + true + false + 1 + false + false + 0 + phot_poly.drawing + 410/0@1 + + + #ff0000 + #ff0000 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + phot_pwell.drawing + 420/0@1 + + + #0000ff + #0000ff + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + phot_nwell.drawing + 430/0@1 + + + #ff0000 + #ff0000 + 0 + 0 + I11 + + true + true + false + 1 + false + false + 0 + phot_pimplant.drawing + 440/0@1 + + + #0000ff + #0000ff + 0 + 0 + I7 + + true + true + false + 1 + false + false + 0 + phot_nimplant.drawing + 450/0@1 + + + #ddff00 + #ddff00 + 0 + 0 + I9 + + false + true + true + + false + false + 0 + IP + 63/63@1 + + + #ffffff + + 0 + 0 + I1 + I1 + true + true + false + + false + false + 0 + OUTLINE - 235/0 + 235/0@1 + @@ -973,28 +1670,6 @@ 21 triangle - - - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - - 22 - x - *............... @@ -1014,7 +1689,7 @@ ................ ................ - 23 + 22 dot1 @@ -1036,7 +1711,7 @@ ................ ................ - 24 + 23 dot2 @@ -1058,7 +1733,7 @@ ..*.....*.....*. ................ - 25 + 24 dot3 @@ -1080,7 +1755,7 @@ .*...*.....*.... ................ - 26 + 25 dot4 @@ -1102,7 +1777,7 @@ ........******** ........******** - 27 + 26 checker @@ -1124,7 +1799,7 @@ ....*...*...*... ...............* - 28 + 27 viap @@ -1146,7 +1821,7 @@ .............**. ..............** - 29 + 28 metal1S @@ -1168,7 +1843,7 @@ .....*.......... *..............* - 30 + 29 metal2S @@ -1190,7 +1865,7 @@ ....***.....***. ......*.......*. - 31 + 30 gnd2S @@ -1212,7 +1887,7 @@ .**......**..... ..*.......*..... - 32 + 31 vcc2S @@ -1234,7 +1909,7 @@ .**...*..**...*. ..*....*..*....* - 33 + 32 vcc1S @@ -1256,7 +1931,7 @@ ................ ................ - 34 + 33 poly2p @@ -1278,7 +1953,7 @@ ................ ................ - 35 + 34 contp @@ -1316,7 +1991,7 @@ ................................ ................................ - 36 + 35 pplusp @@ -1354,7 +2029,7 @@ ................................ ................................ - 37 + 36 wellp @@ -1376,7 +2051,7 @@ .*.*.*.*.*.*.*.* *.*.*.*.*.*.*.*. - 38 + 37 checker1 @@ -1398,7 +2073,7 @@ ..**..**..**..** ..**..**..**..** - 39 + 38 checker2 @@ -1420,7 +2095,7 @@ .***.***.***.*** *.*.*.*.*.*.*.*. - 40 + 39 invCross @@ -1458,7 +2133,7 @@ ................................ ................................ - 41 + 40 wellBp @@ -1496,7 +2171,7 @@ ...........*........*........... ...........**********........... - 42 + 41 wellvtg @@ -1534,7 +2209,7 @@ ...........*.......*............ ...........*.......*............ - 43 + 42 wellvth @@ -1572,7 +2247,7 @@ ...............*................ ...............*................ - 44 + 43 thickox @@ -1610,7 +2285,7 @@ ................................ ................................ - 45 + 44 cwellBp @@ -1632,7 +2307,7 @@ ................ ................ - 46 + 45 capID @@ -1654,7 +2329,7 @@ ................ ................ - 47 + 46 resID @@ -1676,7 +2351,7 @@ ................ ................ - 48 + 47 diodeID @@ -1698,9 +2373,16 @@ **.*.*.***.*.*.* **************** - 49 + 48 sgrid + + + * + + 49 + + *** 1 @@ -1737,13 +2419,13 @@ hidden - *** + 8 - thickLine + - *** - 9 - mLine + + 0 + diff --git a/technology/freepdk45/tf/FreePDK45.lyt b/technology/freepdk45/tf/FreePDK45.lyt new file mode 100644 index 00000000..98e934a3 --- /dev/null +++ b/technology/freepdk45/tf/FreePDK45.lyt @@ -0,0 +1,172 @@ + + + FreePDK45 + Free PDK 45nm + + 0.001 + $(appdata_path)/tech/FreePDK45 + .klayout/tech/FreePDK45 + FreePDK45.lyp + true + + + 1 + true + true + + + true + layer_map() + true + true + + + true + layer_map() + 0.001 + true + #1 + true + #1 + false + #1 + true + OUTLINE + true + PLACEMENT_BLK + true + REGIONS + true + + 0 + true + .PIN + 2 + true + .OBS + 3 + true + .BLK + 4 + true + .LABEL + 1 + true + + 0 + + + false + true + true + 64 + 0 + 1 + 0 + DATA + 0 + 0 + BORDER + layer_map() + true + + + 0.001 + 1 + 100 + 100 + 0 + 0 + 0 + false + false + false + true + layer_map() + + + 0 + 0.001 + layer_map() + true + false + + + 1 + 0.001 + layer_map() + true + false + true + + + + + + + true + false + false + false + false + 8000 + 32000 + LIB + + + 2 + false + false + 1 + * + false + + + 0 + + + false + false + + + 0 + + true + + + + DrainSource,contact,metal1 + poly,contact,metal1 + metal1,via1,metal2 + metal2,via2,metal3 + metal3,via3,metal4 + metal4,via4,metal5 + metal5,via5,metal6 + metal6,via6,metal7 + metal7,via7,metal8 + metal8,via8,metal9 + metal9,via9,metal10 + DrainSource='1/0 - 9/0' + poly='9/0' + contact='10/0' + metal1='11/0 + 11/1 + 11/2' + via1='12/0' + metal2='13/0 + 13/1 + 13/2' + via2='14/0' + metal3='15/0 + 15/1 + 15/2' + via3='16/0' + metal4='17/0 + 17/1 + 17/2' + via4='18/0' + metal5='19/0 + 19/1 + 19/2' + via5='20/0' + metal6='21/0 + 21/1 + 21/2' + via6='22/0' + metal7='23/0 + 23/1 + 23/2' + via7='24/0' + metal8='25/0 + 25/1 + 25/2' + via8='26/0' + metal9='27/0 + 27/1 + 27/2' + via9='28/0' + metal10='29/0 + 29/1 + 29/2' + + diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index 0bd12162..39ca0cfc 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -63,6 +63,7 @@ layer["text"] = (63, 0) layer["boundary"] = (63, 0) layer["blockage"] = (83, 0) +use_purpose = {} ################################################### ##END GDS Layer Map ################################################### @@ -304,3 +305,5 @@ pex_name = "magic" ################################################### ##END Technology Tool Preferences ################################################### +array_row_multiple = 1 +array_col_multiple = 1 \ No newline at end of file diff --git a/technology/scn4m_subm/sim_data/fall_delay.csv b/technology/scn4m_subm/sim_data/fall_delay.csv deleted file mode 100644 index 51ce4f06..00000000 --- a/technology/scn4m_subm/sim_data/fall_delay.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,fall_delay -16,2,1,46853,FF,5.0,25,0.0125,2.45605,1.4938000000000002 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,1.5326 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,1.6802000000000001 -16,2,1,46853,FF,5.0,25,0.05,2.45605,1.4975 -16,2,1,46853,FF,5.0,25,0.05,9.8242,1.5366 -16,2,1,46853,FF,5.0,25,0.05,39.2968,1.6841 -16,2,1,46853,FF,5.0,25,0.4,2.45605,1.5540000000000003 -16,2,1,46853,FF,5.0,25,0.4,9.8242,1.5933000000000002 -16,2,1,46853,FF,5.0,25,0.4,39.2968,1.7406 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,1.546 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,1.5871 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,1.7390000000000003 -16,2,1,46853,SS,5.0,25,0.05,2.45605,1.5518 -16,2,1,46853,SS,5.0,25,0.05,9.8242,1.5922 -16,2,1,46853,SS,5.0,25,0.05,39.2968,1.7441 -16,2,1,46853,SS,5.0,25,0.4,2.45605,1.6087 -16,2,1,46853,SS,5.0,25,0.4,9.8242,1.6503 -16,2,1,46853,SS,5.0,25,0.4,39.2968,1.8022 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,1.8344000000000003 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,1.8822000000000003 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,2.0635000000000003 -16,2,1,46853,TT,3.6,25,0.05,2.45605,1.8402 -16,2,1,46853,TT,3.6,25,0.05,9.8242,1.8872000000000002 -16,2,1,46853,TT,3.6,25,0.05,39.2968,2.0700000000000003 -16,2,1,46853,TT,3.6,25,0.4,2.45605,1.9033000000000002 -16,2,1,46853,TT,3.6,25,0.4,9.8242,1.9512 -16,2,1,46853,TT,3.6,25,0.4,39.2968,2.1324 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,1.8070000000000002 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,1.8492 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,2.0125 -64,2,4,66821,FF,5.0,25,0.05,2.45605,1.811 -64,2,4,66821,FF,5.0,25,0.05,9.8242,1.8535000000000001 -64,2,4,66821,FF,5.0,25,0.05,39.2968,2.016 -64,2,4,66821,FF,5.0,25,0.4,2.45605,1.8676000000000001 -64,2,4,66821,FF,5.0,25,0.4,9.8242,1.9101 -64,2,4,66821,FF,5.0,25,0.4,39.2968,2.0732000000000004 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,1.8638000000000001 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,1.9071000000000002 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,2.0763 -64,2,4,66821,SS,5.0,25,0.05,2.45605,1.8675 -64,2,4,66821,SS,5.0,25,0.05,9.8242,1.9116 -64,2,4,66821,SS,5.0,25,0.05,39.2968,2.0798 -64,2,4,66821,SS,5.0,25,0.4,2.45605,1.9269 -64,2,4,66821,SS,5.0,25,0.4,9.8242,1.9710000000000003 -64,2,4,66821,SS,5.0,25,0.4,39.2968,2.1389 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,2.2213 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,2.2757000000000005 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,2.4855 -64,2,4,66821,TT,3.6,25,0.05,2.45605,2.2262 -64,2,4,66821,TT,3.6,25,0.05,9.8242,2.281 -64,2,4,66821,TT,3.6,25,0.05,39.2968,2.4907 -64,2,4,66821,TT,3.6,25,0.4,2.45605,2.2909000000000006 -64,2,4,66821,TT,3.6,25,0.4,9.8242,2.3447 -64,2,4,66821,TT,3.6,25,0.4,39.2968,2.5554 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,1.4932 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,1.5311000000000001 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,1.6784 -16,1,1,44918,FF,5.0,25,0.05,2.45605,1.4969000000000001 -16,1,1,44918,FF,5.0,25,0.05,9.8242,1.5359 -16,1,1,44918,FF,5.0,25,0.05,39.2968,1.6818000000000002 -16,1,1,44918,FF,5.0,25,0.4,2.45605,1.5468000000000002 -16,1,1,44918,FF,5.0,25,0.4,9.8242,1.5872000000000002 -16,1,1,44918,FF,5.0,25,0.4,39.2968,1.732 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,1.5465 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,1.5855 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,1.7358000000000002 -16,1,1,44918,SS,5.0,25,0.05,2.45605,1.5502 -16,1,1,44918,SS,5.0,25,0.05,9.8242,1.5898000000000003 -16,1,1,44918,SS,5.0,25,0.05,39.2968,1.7407 -16,1,1,44918,SS,5.0,25,0.4,2.45605,1.6046000000000002 -16,1,1,44918,SS,5.0,25,0.4,9.8242,1.6447 -16,1,1,44918,SS,5.0,25,0.4,39.2968,1.7955000000000003 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,1.8358000000000003 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,1.8833 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,2.0637 -16,1,1,44918,TT,3.6,25,0.05,2.45605,1.8410000000000002 -16,1,1,44918,TT,3.6,25,0.05,9.8242,1.8883 -16,1,1,44918,TT,3.6,25,0.05,39.2968,2.0690000000000004 -16,1,1,44918,TT,3.6,25,0.4,2.45605,1.8998 -16,1,1,44918,TT,3.6,25,0.4,9.8242,1.9467000000000003 -16,1,1,44918,TT,3.6,25,0.4,39.2968,2.1277 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,1.7466 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,1.7888000000000002 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,1.951 -32,3,2,61533,FF,5.0,25,0.05,2.45605,1.7509000000000001 -32,3,2,61533,FF,5.0,25,0.05,9.8242,1.7935000000000003 -32,3,2,61533,FF,5.0,25,0.05,39.2968,1.9557000000000002 -32,3,2,61533,FF,5.0,25,0.4,2.45605,1.8069 -32,3,2,61533,FF,5.0,25,0.4,9.8242,1.8495000000000001 -32,3,2,61533,FF,5.0,25,0.4,39.2968,2.0117 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,1.8027 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,1.8469000000000002 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,2.0147 -32,3,2,61533,SS,5.0,25,0.05,2.45605,1.8072000000000001 -32,3,2,61533,SS,5.0,25,0.05,9.8242,1.8516000000000001 -32,3,2,61533,SS,5.0,25,0.05,39.2968,2.0192 -32,3,2,61533,SS,5.0,25,0.4,2.45605,1.8658 -32,3,2,61533,SS,5.0,25,0.4,9.8242,1.9107 -32,3,2,61533,SS,5.0,25,0.4,39.2968,2.079 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,2.1397 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,2.1948 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,2.4041000000000006 -32,3,2,61533,TT,3.6,25,0.05,2.45605,2.1449 -32,3,2,61533,TT,3.6,25,0.05,9.8242,2.1999000000000004 -32,3,2,61533,TT,3.6,25,0.05,39.2968,2.4093 -32,3,2,61533,TT,3.6,25,0.4,2.45605,2.2086000000000006 -32,3,2,61533,TT,3.6,25,0.4,9.8242,2.2639 -32,3,2,61533,TT,3.6,25,0.4,39.2968,2.4734000000000003 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,1.7161000000000002 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,1.7588 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,1.9199 -32,2,2,55960,FF,5.0,25,0.05,2.45605,1.72 -32,2,2,55960,FF,5.0,25,0.05,9.8242,1.7622000000000002 -32,2,2,55960,FF,5.0,25,0.05,39.2968,1.9238 -32,2,2,55960,FF,5.0,25,0.4,2.45605,1.7759000000000003 -32,2,2,55960,FF,5.0,25,0.4,9.8242,1.8184 -32,2,2,55960,FF,5.0,25,0.4,39.2968,1.9794 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,1.7713000000000003 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,1.8156000000000003 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,1.9823000000000002 -32,2,2,55960,SS,5.0,25,0.05,2.45605,1.7763000000000002 -32,2,2,55960,SS,5.0,25,0.05,9.8242,1.8201 -32,2,2,55960,SS,5.0,25,0.05,39.2968,1.9870000000000003 -32,2,2,55960,SS,5.0,25,0.4,2.45605,1.8341 -32,2,2,55960,SS,5.0,25,0.4,9.8242,1.8781000000000003 -32,2,2,55960,SS,5.0,25,0.4,39.2968,2.0451 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,2.1025 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,2.1574 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,2.366 -32,2,2,55960,TT,3.6,25,0.05,2.45605,2.1063 -32,2,2,55960,TT,3.6,25,0.05,9.8242,2.1612 -32,2,2,55960,TT,3.6,25,0.05,39.2968,2.3698 -32,2,2,55960,TT,3.6,25,0.4,2.45605,2.1703 -32,2,2,55960,TT,3.6,25,0.4,9.8242,2.2248000000000006 -32,2,2,55960,TT,3.6,25,0.4,39.2968,2.4334 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,1.5062 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,1.5456 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,1.6936 -16,3,1,49288,FF,5.0,25,0.05,2.45605,1.5117 -16,3,1,49288,FF,5.0,25,0.05,9.8242,1.5506 -16,3,1,49288,FF,5.0,25,0.05,39.2968,1.6983 -16,3,1,49288,FF,5.0,25,0.4,2.45605,1.5674 -16,3,1,49288,FF,5.0,25,0.4,9.8242,1.6067 -16,3,1,49288,FF,5.0,25,0.4,39.2968,1.7538 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,1.5613 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,1.6019000000000003 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,1.7544 -16,3,1,49288,SS,5.0,25,0.05,2.45605,1.5662000000000003 -16,3,1,49288,SS,5.0,25,0.05,9.8242,1.6061000000000003 -16,3,1,49288,SS,5.0,25,0.05,39.2968,1.7587000000000002 -16,3,1,49288,SS,5.0,25,0.4,2.45605,1.6242000000000003 -16,3,1,49288,SS,5.0,25,0.4,9.8242,1.6645 -16,3,1,49288,SS,5.0,25,0.4,39.2968,1.817 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,1.8522000000000003 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,1.9004 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,2.0833 -16,3,1,49288,TT,3.6,25,0.05,2.45605,1.8586000000000003 -16,3,1,49288,TT,3.6,25,0.05,9.8242,1.9065000000000003 -16,3,1,49288,TT,3.6,25,0.05,39.2968,2.0888 -16,3,1,49288,TT,3.6,25,0.4,2.45605,1.9209000000000003 -16,3,1,49288,TT,3.6,25,0.4,9.8242,1.9689 -16,3,1,49288,TT,3.6,25,0.4,39.2968,2.1510000000000002 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,1.7980000000000003 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,1.8410000000000002 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,2.0055 -64,1,4,56307,FF,5.0,25,0.05,2.45605,1.8018 -64,1,4,56307,FF,5.0,25,0.05,9.8242,1.8449000000000002 -64,1,4,56307,FF,5.0,25,0.05,39.2968,2.0094000000000003 -64,1,4,56307,FF,5.0,25,0.4,2.45605,1.8579 -64,1,4,56307,FF,5.0,25,0.4,9.8242,1.9013 -64,1,4,56307,FF,5.0,25,0.4,39.2968,2.0651 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,1.8547000000000002 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,1.8986 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,2.0683 -64,1,4,56307,SS,5.0,25,0.05,2.45605,1.8586000000000003 -64,1,4,56307,SS,5.0,25,0.05,9.8242,1.9023000000000003 -64,1,4,56307,SS,5.0,25,0.05,39.2968,2.0722000000000005 -64,1,4,56307,SS,5.0,25,0.4,2.45605,1.9177000000000002 -64,1,4,56307,SS,5.0,25,0.4,9.8242,1.9612000000000003 -64,1,4,56307,SS,5.0,25,0.4,39.2968,2.1309 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,2.2058 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,2.2605000000000004 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,2.4711 -64,1,4,56307,TT,3.6,25,0.05,2.45605,2.2114000000000003 -64,1,4,56307,TT,3.6,25,0.05,9.8242,2.2665 -64,1,4,56307,TT,3.6,25,0.05,39.2968,2.4763 -64,1,4,56307,TT,3.6,25,0.4,2.45605,2.275 -64,1,4,56307,TT,3.6,25,0.4,9.8242,2.3298000000000005 -64,1,4,56307,TT,3.6,25,0.4,39.2968,2.5404 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,1.6865 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,1.7291 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,1.8895000000000002 -32,1,2,50620,FF,5.0,25,0.05,2.45605,1.6914000000000002 -32,1,2,50620,FF,5.0,25,0.05,9.8242,1.7333000000000003 -32,1,2,50620,FF,5.0,25,0.05,39.2968,1.8939 -32,1,2,50620,FF,5.0,25,0.4,2.45605,1.7472 -32,1,2,50620,FF,5.0,25,0.4,9.8242,1.7880000000000003 -32,1,2,50620,FF,5.0,25,0.4,39.2968,1.9504000000000001 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,1.7409000000000001 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,1.7842 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,1.9504000000000001 -32,1,2,50620,SS,5.0,25,0.05,2.45605,1.7450000000000003 -32,1,2,50620,SS,5.0,25,0.05,9.8242,1.7885000000000002 -32,1,2,50620,SS,5.0,25,0.05,39.2968,1.9549000000000003 -32,1,2,50620,SS,5.0,25,0.4,2.45605,1.8043 -32,1,2,50620,SS,5.0,25,0.4,9.8242,1.8470000000000002 -32,1,2,50620,SS,5.0,25,0.4,39.2968,2.0142 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,2.0660000000000003 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,2.1195 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,2.3282 -32,1,2,50620,TT,3.6,25,0.05,2.45605,2.0698 -32,1,2,50620,TT,3.6,25,0.05,9.8242,2.1242 -32,1,2,50620,TT,3.6,25,0.05,39.2968,2.3331 -32,1,2,50620,TT,3.6,25,0.4,2.45605,2.1344 -32,1,2,50620,TT,3.6,25,0.4,9.8242,2.1888 -32,1,2,50620,TT,3.6,25,0.4,39.2968,2.3966000000000003 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,1.5255 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,1.5651000000000002 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,1.7136000000000002 -16,4,1,51796,FF,5.0,25,0.05,2.45605,1.5287000000000002 -16,4,1,51796,FF,5.0,25,0.05,9.8242,1.5694 -16,4,1,51796,FF,5.0,25,0.05,39.2968,1.7179 -16,4,1,51796,FF,5.0,25,0.4,2.45605,1.5851 -16,4,1,51796,FF,5.0,25,0.4,9.8242,1.6246000000000003 -16,4,1,51796,FF,5.0,25,0.4,39.2968,1.7731 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,1.5803000000000003 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,1.6209 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,1.7744 -16,4,1,51796,SS,5.0,25,0.05,2.45605,1.5839 -16,4,1,51796,SS,5.0,25,0.05,9.8242,1.6246000000000003 -16,4,1,51796,SS,5.0,25,0.05,39.2968,1.7778000000000003 -16,4,1,51796,SS,5.0,25,0.4,2.45605,1.6416 -16,4,1,51796,SS,5.0,25,0.4,9.8242,1.6837000000000002 -16,4,1,51796,SS,5.0,25,0.4,39.2968,1.8361 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,1.5574000000000001 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,1.5984000000000003 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,1.7492 -16,4,1,51796,TT,5.0,25,0.05,2.45605,1.5622 -16,4,1,51796,TT,5.0,25,0.05,9.8242,1.6025000000000003 -16,4,1,51796,TT,5.0,25,0.05,39.2968,1.7526000000000002 -16,4,1,51796,TT,5.0,25,0.4,2.45605,1.618 -16,4,1,51796,TT,5.0,25,0.4,9.8242,1.6577 -16,4,1,51796,TT,5.0,25,0.4,39.2968,1.8096000000000003 diff --git a/technology/scn4m_subm/sim_data/fall_slew.csv b/technology/scn4m_subm/sim_data/fall_slew.csv deleted file mode 100644 index 38b3dfae..00000000 --- a/technology/scn4m_subm/sim_data/fall_slew.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,fall_slew -16,2,1,46853,FF,5.0,25,0.0125,2.45605,1.7733000000000003 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,1.7797000000000003 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,1.8085000000000002 -16,2,1,46853,FF,5.0,25,0.05,2.45605,1.7736 -16,2,1,46853,FF,5.0,25,0.05,9.8242,1.7796 -16,2,1,46853,FF,5.0,25,0.05,39.2968,1.8081000000000003 -16,2,1,46853,FF,5.0,25,0.4,2.45605,1.774 -16,2,1,46853,FF,5.0,25,0.4,9.8242,1.7812000000000001 -16,2,1,46853,FF,5.0,25,0.4,39.2968,1.8084 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,1.8483 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,1.8552000000000002 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,1.8888000000000003 -16,2,1,46853,SS,5.0,25,0.05,2.45605,1.8472 -16,2,1,46853,SS,5.0,25,0.05,9.8242,1.8547000000000002 -16,2,1,46853,SS,5.0,25,0.05,39.2968,1.8883 -16,2,1,46853,SS,5.0,25,0.4,2.45605,1.8462 -16,2,1,46853,SS,5.0,25,0.4,9.8242,1.8541000000000003 -16,2,1,46853,SS,5.0,25,0.4,39.2968,1.8880000000000001 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,2.2169 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,2.2276000000000002 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,2.2752000000000003 -16,2,1,46853,TT,3.6,25,0.05,2.45605,2.2169 -16,2,1,46853,TT,3.6,25,0.05,9.8242,2.2274 -16,2,1,46853,TT,3.6,25,0.05,39.2968,2.2752000000000003 -16,2,1,46853,TT,3.6,25,0.4,2.45605,2.2155 -16,2,1,46853,TT,3.6,25,0.4,9.8242,2.2265 -16,2,1,46853,TT,3.6,25,0.4,39.2968,2.274 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,1.6523 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,1.6619 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,1.6992 -64,2,4,66821,FF,5.0,25,0.05,2.45605,1.6526000000000003 -64,2,4,66821,FF,5.0,25,0.05,9.8242,1.6615000000000002 -64,2,4,66821,FF,5.0,25,0.05,39.2968,1.6989000000000003 -64,2,4,66821,FF,5.0,25,0.4,2.45605,1.6514000000000002 -64,2,4,66821,FF,5.0,25,0.4,9.8242,1.6621000000000001 -64,2,4,66821,FF,5.0,25,0.4,39.2968,1.6979000000000002 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,1.7235 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,1.7336 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,1.7746 -64,2,4,66821,SS,5.0,25,0.05,2.45605,1.7236 -64,2,4,66821,SS,5.0,25,0.05,9.8242,1.7332 -64,2,4,66821,SS,5.0,25,0.05,39.2968,1.7749 -64,2,4,66821,SS,5.0,25,0.4,2.45605,1.7249 -64,2,4,66821,SS,5.0,25,0.4,9.8242,1.7345 -64,2,4,66821,SS,5.0,25,0.4,39.2968,1.7753000000000003 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,2.0566 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,2.0700000000000003 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,2.1247 -64,2,4,66821,TT,3.6,25,0.05,2.45605,2.0569 -64,2,4,66821,TT,3.6,25,0.05,9.8242,2.0712000000000006 -64,2,4,66821,TT,3.6,25,0.05,39.2968,2.1243 -64,2,4,66821,TT,3.6,25,0.4,2.45605,2.0575000000000006 -64,2,4,66821,TT,3.6,25,0.4,9.8242,2.0712000000000006 -64,2,4,66821,TT,3.6,25,0.4,39.2968,2.1244 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,1.7495000000000003 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,1.7561000000000002 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,1.7857 -16,1,1,44918,FF,5.0,25,0.05,2.45605,1.7488 -16,1,1,44918,FF,5.0,25,0.05,9.8242,1.7553 -16,1,1,44918,FF,5.0,25,0.05,39.2968,1.7849000000000002 -16,1,1,44918,FF,5.0,25,0.4,2.45605,1.7487 -16,1,1,44918,FF,5.0,25,0.4,9.8242,1.7550000000000001 -16,1,1,44918,FF,5.0,25,0.4,39.2968,1.7854000000000003 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,1.8221 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,1.8306 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,1.8645000000000003 -16,1,1,44918,SS,5.0,25,0.05,2.45605,1.8229 -16,1,1,44918,SS,5.0,25,0.05,9.8242,1.8298000000000003 -16,1,1,44918,SS,5.0,25,0.05,39.2968,1.8645000000000003 -16,1,1,44918,SS,5.0,25,0.4,2.45605,1.8223000000000003 -16,1,1,44918,SS,5.0,25,0.4,9.8242,1.829 -16,1,1,44918,SS,5.0,25,0.4,39.2968,1.8636000000000001 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,2.1882 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,2.199 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,2.2476 -16,1,1,44918,TT,3.6,25,0.05,2.45605,2.1871 -16,1,1,44918,TT,3.6,25,0.05,9.8242,2.198 -16,1,1,44918,TT,3.6,25,0.05,39.2968,2.2471 -16,1,1,44918,TT,3.6,25,0.4,2.45605,2.186 -16,1,1,44918,TT,3.6,25,0.4,9.8242,2.1974000000000005 -16,1,1,44918,TT,3.6,25,0.4,39.2968,2.2482 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,1.6930000000000003 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,1.7023 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,1.7384000000000002 -32,3,2,61533,FF,5.0,25,0.05,2.45605,1.6936 -32,3,2,61533,FF,5.0,25,0.05,9.8242,1.7029 -32,3,2,61533,FF,5.0,25,0.05,39.2968,1.7383000000000002 -32,3,2,61533,FF,5.0,25,0.4,2.45605,1.6926 -32,3,2,61533,FF,5.0,25,0.4,9.8242,1.7030000000000003 -32,3,2,61533,FF,5.0,25,0.4,39.2968,1.7383000000000002 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,1.7645 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,1.7747000000000002 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,1.815 -32,3,2,61533,SS,5.0,25,0.05,2.45605,1.766 -32,3,2,61533,SS,5.0,25,0.05,9.8242,1.7753000000000003 -32,3,2,61533,SS,5.0,25,0.05,39.2968,1.8152000000000001 -32,3,2,61533,SS,5.0,25,0.4,2.45605,1.7669 -32,3,2,61533,SS,5.0,25,0.4,9.8242,1.777 -32,3,2,61533,SS,5.0,25,0.4,39.2968,1.8152000000000001 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,2.1084000000000005 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,2.1226000000000003 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,2.1758 -32,3,2,61533,TT,3.6,25,0.05,2.45605,2.1088 -32,3,2,61533,TT,3.6,25,0.05,9.8242,2.1235 -32,3,2,61533,TT,3.6,25,0.05,39.2968,2.1756 -32,3,2,61533,TT,3.6,25,0.4,2.45605,2.1091000000000006 -32,3,2,61533,TT,3.6,25,0.4,9.8242,2.1213000000000006 -32,3,2,61533,TT,3.6,25,0.4,39.2968,2.1751 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,1.6751 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,1.6843000000000001 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,1.7199 -32,2,2,55960,FF,5.0,25,0.05,2.45605,1.6754 -32,2,2,55960,FF,5.0,25,0.05,9.8242,1.6838000000000002 -32,2,2,55960,FF,5.0,25,0.05,39.2968,1.7202000000000002 -32,2,2,55960,FF,5.0,25,0.4,2.45605,1.6771 -32,2,2,55960,FF,5.0,25,0.4,9.8242,1.6857 -32,2,2,55960,FF,5.0,25,0.4,39.2968,1.7212000000000003 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,1.7473 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,1.7574 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,1.7962 -32,2,2,55960,SS,5.0,25,0.05,2.45605,1.7467 -32,2,2,55960,SS,5.0,25,0.05,9.8242,1.7568 -32,2,2,55960,SS,5.0,25,0.05,39.2968,1.7966000000000002 -32,2,2,55960,SS,5.0,25,0.4,2.45605,1.7470000000000003 -32,2,2,55960,SS,5.0,25,0.4,9.8242,1.7571000000000003 -32,2,2,55960,SS,5.0,25,0.4,39.2968,1.7965000000000002 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,2.0848 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,2.0981 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,2.1533 -32,2,2,55960,TT,3.6,25,0.05,2.45605,2.0851 -32,2,2,55960,TT,3.6,25,0.05,9.8242,2.0985 -32,2,2,55960,TT,3.6,25,0.05,39.2968,2.1534 -32,2,2,55960,TT,3.6,25,0.4,2.45605,2.087 -32,2,2,55960,TT,3.6,25,0.4,9.8242,2.1005 -32,2,2,55960,TT,3.6,25,0.4,39.2968,2.1537 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,1.7972 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,1.8042 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,1.8323000000000003 -16,3,1,49288,FF,5.0,25,0.05,2.45605,1.7976000000000003 -16,3,1,49288,FF,5.0,25,0.05,9.8242,1.8042 -16,3,1,49288,FF,5.0,25,0.05,39.2968,1.8332 -16,3,1,49288,FF,5.0,25,0.4,2.45605,1.7986000000000002 -16,3,1,49288,FF,5.0,25,0.4,9.8242,1.8053 -16,3,1,49288,FF,5.0,25,0.4,39.2968,1.8329000000000002 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,1.8728 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,1.8801 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,1.9131 -16,3,1,49288,SS,5.0,25,0.05,2.45605,1.873 -16,3,1,49288,SS,5.0,25,0.05,9.8242,1.8798000000000001 -16,3,1,49288,SS,5.0,25,0.05,39.2968,1.9137000000000002 -16,3,1,49288,SS,5.0,25,0.4,2.45605,1.8741000000000003 -16,3,1,49288,SS,5.0,25,0.4,9.8242,1.882 -16,3,1,49288,SS,5.0,25,0.4,39.2968,1.9137000000000002 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,2.2478000000000002 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,2.2586 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,2.3049000000000004 -16,3,1,49288,TT,3.6,25,0.05,2.45605,2.2489 -16,3,1,49288,TT,3.6,25,0.05,9.8242,2.2599 -16,3,1,49288,TT,3.6,25,0.05,39.2968,2.3051000000000004 -16,3,1,49288,TT,3.6,25,0.4,2.45605,2.2488 -16,3,1,49288,TT,3.6,25,0.4,9.8242,2.2592000000000003 -16,3,1,49288,TT,3.6,25,0.4,39.2968,2.3051000000000004 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,1.6302000000000003 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,1.6383000000000003 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,1.6746 -64,1,4,56307,FF,5.0,25,0.05,2.45605,1.6295 -64,1,4,56307,FF,5.0,25,0.05,9.8242,1.6381 -64,1,4,56307,FF,5.0,25,0.05,39.2968,1.6744 -64,1,4,56307,FF,5.0,25,0.4,2.45605,1.6302000000000003 -64,1,4,56307,FF,5.0,25,0.4,9.8242,1.6389000000000002 -64,1,4,56307,FF,5.0,25,0.4,39.2968,1.674 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,1.7001 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,1.7103 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,1.7491000000000003 -64,1,4,56307,SS,5.0,25,0.05,2.45605,1.7005000000000001 -64,1,4,56307,SS,5.0,25,0.05,9.8242,1.7093 -64,1,4,56307,SS,5.0,25,0.05,39.2968,1.7491000000000003 -64,1,4,56307,SS,5.0,25,0.4,2.45605,1.6997 -64,1,4,56307,SS,5.0,25,0.4,9.8242,1.7094 -64,1,4,56307,SS,5.0,25,0.4,39.2968,1.7490000000000003 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,2.0304 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,2.0431 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,2.0968 -64,1,4,56307,TT,3.6,25,0.05,2.45605,2.0301000000000005 -64,1,4,56307,TT,3.6,25,0.05,9.8242,2.0428000000000006 -64,1,4,56307,TT,3.6,25,0.05,39.2968,2.0958 -64,1,4,56307,TT,3.6,25,0.4,2.45605,2.0293000000000005 -64,1,4,56307,TT,3.6,25,0.4,9.8242,2.0441 -64,1,4,56307,TT,3.6,25,0.4,39.2968,2.0968 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,1.6570000000000003 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,1.6657000000000002 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,1.7021000000000002 -32,1,2,50620,FF,5.0,25,0.05,2.45605,1.6565000000000003 -32,1,2,50620,FF,5.0,25,0.05,9.8242,1.6653 -32,1,2,50620,FF,5.0,25,0.05,39.2968,1.7012 -32,1,2,50620,FF,5.0,25,0.4,2.45605,1.6566000000000003 -32,1,2,50620,FF,5.0,25,0.4,9.8242,1.6649 -32,1,2,50620,FF,5.0,25,0.4,39.2968,1.7007 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,1.7273000000000003 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,1.7378000000000002 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,1.7765 -32,1,2,50620,SS,5.0,25,0.05,2.45605,1.7264 -32,1,2,50620,SS,5.0,25,0.05,9.8242,1.7376 -32,1,2,50620,SS,5.0,25,0.05,39.2968,1.7772000000000001 -32,1,2,50620,SS,5.0,25,0.4,2.45605,1.7272000000000003 -32,1,2,50620,SS,5.0,25,0.4,9.8242,1.7377 -32,1,2,50620,SS,5.0,25,0.4,39.2968,1.7766 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,2.0632 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,2.0767000000000007 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,2.1305 -32,1,2,50620,TT,3.6,25,0.05,2.45605,2.0621 -32,1,2,50620,TT,3.6,25,0.05,9.8242,2.0756 -32,1,2,50620,TT,3.6,25,0.05,39.2968,2.1304 -32,1,2,50620,TT,3.6,25,0.4,2.45605,2.0626 -32,1,2,50620,TT,3.6,25,0.4,9.8242,2.0747000000000004 -32,1,2,50620,TT,3.6,25,0.4,39.2968,2.129 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,1.8218000000000003 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,1.8282000000000003 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,1.8565000000000003 -16,4,1,51796,FF,5.0,25,0.05,2.45605,1.8219 -16,4,1,51796,FF,5.0,25,0.05,9.8242,1.829 -16,4,1,51796,FF,5.0,25,0.05,39.2968,1.8567000000000002 -16,4,1,51796,FF,5.0,25,0.4,2.45605,1.8197000000000003 -16,4,1,51796,FF,5.0,25,0.4,9.8242,1.827 -16,4,1,51796,FF,5.0,25,0.4,39.2968,1.8559 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,1.8981 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,1.9056000000000002 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,1.9388000000000003 -16,4,1,51796,SS,5.0,25,0.05,2.45605,1.8991000000000002 -16,4,1,51796,SS,5.0,25,0.05,9.8242,1.9061 -16,4,1,51796,SS,5.0,25,0.05,39.2968,1.9387000000000003 -16,4,1,51796,SS,5.0,25,0.4,2.45605,1.8991000000000002 -16,4,1,51796,SS,5.0,25,0.4,9.8242,1.9077 -16,4,1,51796,SS,5.0,25,0.4,39.2968,1.9395000000000002 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,1.8666000000000003 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,1.873 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,1.9037 -16,4,1,51796,TT,5.0,25,0.05,2.45605,1.8657 -16,4,1,51796,TT,5.0,25,0.05,9.8242,1.8727 -16,4,1,51796,TT,5.0,25,0.05,39.2968,1.9036 -16,4,1,51796,TT,5.0,25,0.4,2.45605,1.8673 -16,4,1,51796,TT,5.0,25,0.4,9.8242,1.8746 -16,4,1,51796,TT,5.0,25,0.4,39.2968,1.9043 diff --git a/technology/scn4m_subm/sim_data/leakage_data.csv b/technology/scn4m_subm/sim_data/leakage_data.csv deleted file mode 100644 index 484f38b5..00000000 --- a/technology/scn4m_subm/sim_data/leakage_data.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,leakage_power -16,2,1,46853,FF,5.0,25,0.0125,2.45605,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.05,2.45605,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.05,9.8242,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.05,39.2968,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.4,2.45605,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.4,9.8242,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.4,39.2968,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.05,2.45605,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.05,9.8242,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.05,39.2968,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.4,2.45605,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.4,9.8242,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.4,39.2968,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.05,2.45605,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.05,9.8242,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.05,39.2968,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.4,2.45605,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.4,9.8242,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.4,39.2968,0.0009555021000000003 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.05,2.45605,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.05,9.8242,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.05,39.2968,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.4,2.45605,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.4,9.8242,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.4,39.2968,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.05,2.45605,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.05,9.8242,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.05,39.2968,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.4,2.45605,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.4,9.8242,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.4,39.2968,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.05,2.45605,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.05,9.8242,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.05,39.2968,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.4,2.45605,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.4,9.8242,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.4,39.2968,0.0011742999999999999 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,0.0005716487 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,0.0005716487 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,0.0005716487 -16,1,1,44918,FF,5.0,25,0.05,2.45605,0.0005716487 -16,1,1,44918,FF,5.0,25,0.05,9.8242,0.0005716487 -16,1,1,44918,FF,5.0,25,0.05,39.2968,0.0005716487 -16,1,1,44918,FF,5.0,25,0.4,2.45605,0.0005716487 -16,1,1,44918,FF,5.0,25,0.4,9.8242,0.0005716487 -16,1,1,44918,FF,5.0,25,0.4,39.2968,0.0005716487 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,0.0005716487 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,0.0005716487 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,0.0005716487 -16,1,1,44918,SS,5.0,25,0.05,2.45605,0.0005716487 -16,1,1,44918,SS,5.0,25,0.05,9.8242,0.0005716487 -16,1,1,44918,SS,5.0,25,0.05,39.2968,0.0005716487 -16,1,1,44918,SS,5.0,25,0.4,2.45605,0.0005716487 -16,1,1,44918,SS,5.0,25,0.4,9.8242,0.0005716487 -16,1,1,44918,SS,5.0,25,0.4,39.2968,0.0005716487 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,0.0005716487 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,0.0005716487 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,0.0005716487 -16,1,1,44918,TT,3.6,25,0.05,2.45605,0.0005716487 -16,1,1,44918,TT,3.6,25,0.05,9.8242,0.0005716487 -16,1,1,44918,TT,3.6,25,0.05,39.2968,0.0005716487 -16,1,1,44918,TT,3.6,25,0.4,2.45605,0.0005716487 -16,1,1,44918,TT,3.6,25,0.4,9.8242,0.0005716487 -16,1,1,44918,TT,3.6,25,0.4,39.2968,0.0005716487 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,0.0012508 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,0.0012508 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,0.0012508 -32,3,2,61533,FF,5.0,25,0.05,2.45605,0.0012508 -32,3,2,61533,FF,5.0,25,0.05,9.8242,0.0012508 -32,3,2,61533,FF,5.0,25,0.05,39.2968,0.0012508 -32,3,2,61533,FF,5.0,25,0.4,2.45605,0.0012508 -32,3,2,61533,FF,5.0,25,0.4,9.8242,0.0012508 -32,3,2,61533,FF,5.0,25,0.4,39.2968,0.0012508 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,0.0012508 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,0.0012508 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,0.0012508 -32,3,2,61533,SS,5.0,25,0.05,2.45605,0.0012508 -32,3,2,61533,SS,5.0,25,0.05,9.8242,0.0012508 -32,3,2,61533,SS,5.0,25,0.05,39.2968,0.0012508 -32,3,2,61533,SS,5.0,25,0.4,2.45605,0.0012508 -32,3,2,61533,SS,5.0,25,0.4,9.8242,0.0012508 -32,3,2,61533,SS,5.0,25,0.4,39.2968,0.0012508 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,0.0012508 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,0.0012508 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,0.0012508 -32,3,2,61533,TT,3.6,25,0.05,2.45605,0.0012508 -32,3,2,61533,TT,3.6,25,0.05,9.8242,0.0012508 -32,3,2,61533,TT,3.6,25,0.05,39.2968,0.0012508 -32,3,2,61533,TT,3.6,25,0.4,2.45605,0.0012508 -32,3,2,61533,TT,3.6,25,0.4,9.8242,0.0012508 -32,3,2,61533,TT,3.6,25,0.4,39.2968,0.0012508 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.05,2.45605,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.05,9.8242,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.05,39.2968,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.4,2.45605,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.4,9.8242,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.4,39.2968,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.05,2.45605,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.05,9.8242,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.05,39.2968,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.4,2.45605,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.4,9.8242,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.4,39.2968,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.05,2.45605,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.05,9.8242,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.05,39.2968,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.4,2.45605,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.4,9.8242,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.4,39.2968,0.0008144367999999999 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.05,2.45605,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.05,9.8242,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.05,39.2968,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.4,2.45605,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.4,9.8242,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.4,39.2968,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.05,2.45605,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.05,9.8242,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.05,39.2968,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.4,2.45605,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.4,9.8242,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.4,39.2968,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.05,2.45605,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.05,9.8242,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.05,39.2968,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.4,2.45605,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.4,9.8242,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.4,39.2968,0.0010107999999999998 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,0.0007435572 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,0.0007435572 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,0.0007435572 -64,1,4,56307,FF,5.0,25,0.05,2.45605,0.0007435572 -64,1,4,56307,FF,5.0,25,0.05,9.8242,0.0007435572 -64,1,4,56307,FF,5.0,25,0.05,39.2968,0.0007435572 -64,1,4,56307,FF,5.0,25,0.4,2.45605,0.0007435572 -64,1,4,56307,FF,5.0,25,0.4,9.8242,0.0007435572 -64,1,4,56307,FF,5.0,25,0.4,39.2968,0.0007435572 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,0.0007435572 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,0.0007435572 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,0.0007435572 -64,1,4,56307,SS,5.0,25,0.05,2.45605,0.0007435572 -64,1,4,56307,SS,5.0,25,0.05,9.8242,0.0007435572 -64,1,4,56307,SS,5.0,25,0.05,39.2968,0.0007435572 -64,1,4,56307,SS,5.0,25,0.4,2.45605,0.0007435572 -64,1,4,56307,SS,5.0,25,0.4,9.8242,0.0007435572 -64,1,4,56307,SS,5.0,25,0.4,39.2968,0.0007435572 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,0.0007435572 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,0.0007435572 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,0.0007435572 -64,1,4,56307,TT,3.6,25,0.05,2.45605,0.0007435572 -64,1,4,56307,TT,3.6,25,0.05,9.8242,0.0007435572 -64,1,4,56307,TT,3.6,25,0.05,39.2968,0.0007435572 -64,1,4,56307,TT,3.6,25,0.4,2.45605,0.0007435572 -64,1,4,56307,TT,3.6,25,0.4,9.8242,0.0007435572 -64,1,4,56307,TT,3.6,25,0.4,39.2968,0.0007435572 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,0.0006927326 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,0.0006927326 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,0.0006927326 -32,1,2,50620,FF,5.0,25,0.05,2.45605,0.0006927326 -32,1,2,50620,FF,5.0,25,0.05,9.8242,0.0006927326 -32,1,2,50620,FF,5.0,25,0.05,39.2968,0.0006927326 -32,1,2,50620,FF,5.0,25,0.4,2.45605,0.0006927326 -32,1,2,50620,FF,5.0,25,0.4,9.8242,0.0006927326 -32,1,2,50620,FF,5.0,25,0.4,39.2968,0.0006927326 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,0.0006927326 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,0.0006927326 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,0.0006927326 -32,1,2,50620,SS,5.0,25,0.05,2.45605,0.0006927326 -32,1,2,50620,SS,5.0,25,0.05,9.8242,0.0006927326 -32,1,2,50620,SS,5.0,25,0.05,39.2968,0.0006927326 -32,1,2,50620,SS,5.0,25,0.4,2.45605,0.0006927326 -32,1,2,50620,SS,5.0,25,0.4,9.8242,0.0006927326 -32,1,2,50620,SS,5.0,25,0.4,39.2968,0.0006927326 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,0.0006927326 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,0.0006927326 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,0.0006927326 -32,1,2,50620,TT,3.6,25,0.05,2.45605,0.0006927326 -32,1,2,50620,TT,3.6,25,0.05,9.8242,0.0006927326 -32,1,2,50620,TT,3.6,25,0.05,39.2968,0.0006927326 -32,1,2,50620,TT,3.6,25,0.4,2.45605,0.0006927326 -32,1,2,50620,TT,3.6,25,0.4,9.8242,0.0006927326 -32,1,2,50620,TT,3.6,25,0.4,39.2968,0.0006927326 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,0.0008160818 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,0.0008160818 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,0.0008160818 -16,4,1,51796,FF,5.0,25,0.05,2.45605,0.0008160818 -16,4,1,51796,FF,5.0,25,0.05,9.8242,0.0008160818 -16,4,1,51796,FF,5.0,25,0.05,39.2968,0.0008160818 -16,4,1,51796,FF,5.0,25,0.4,2.45605,0.0008160818 -16,4,1,51796,FF,5.0,25,0.4,9.8242,0.0008160818 -16,4,1,51796,FF,5.0,25,0.4,39.2968,0.0008160818 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,0.0008160818 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,0.0008160818 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,0.0008160818 -16,4,1,51796,SS,5.0,25,0.05,2.45605,0.0008160818 -16,4,1,51796,SS,5.0,25,0.05,9.8242,0.0008160818 -16,4,1,51796,SS,5.0,25,0.05,39.2968,0.0008160818 -16,4,1,51796,SS,5.0,25,0.4,2.45605,0.0008160818 -16,4,1,51796,SS,5.0,25,0.4,9.8242,0.0008160818 -16,4,1,51796,SS,5.0,25,0.4,39.2968,0.0008160818 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,0.0008160818 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,0.0008160818 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,0.0008160818 -16,4,1,51796,TT,5.0,25,0.05,2.45605,0.0008160818 -16,4,1,51796,TT,5.0,25,0.05,9.8242,0.0008160818 -16,4,1,51796,TT,5.0,25,0.05,39.2968,0.0008160818 -16,4,1,51796,TT,5.0,25,0.4,2.45605,0.0008160818 -16,4,1,51796,TT,5.0,25,0.4,9.8242,0.0008160818 -16,4,1,51796,TT,5.0,25,0.4,39.2968,0.0008160818 diff --git a/technology/scn4m_subm/sim_data/read0_power.csv b/technology/scn4m_subm/sim_data/read0_power.csv deleted file mode 100644 index 849549b8..00000000 --- a/technology/scn4m_subm/sim_data/read0_power.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,read0_power -16,2,1,46853,FF,5.0,25,0.0125,2.45605,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.05,2.45605,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.05,9.8242,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.05,39.2968,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.4,2.45605,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.4,9.8242,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.4,39.2968,16.673055555555557 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.05,2.45605,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.05,9.8242,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.05,39.2968,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.4,2.45605,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.4,9.8242,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.4,39.2968,15.053177777777778 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.05,2.45605,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.05,9.8242,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.05,39.2968,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.4,2.45605,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.4,9.8242,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.4,39.2968,5.970400000000001 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.05,2.45605,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.05,9.8242,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.05,39.2968,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.4,2.45605,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.4,9.8242,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.4,39.2968,20.371899999999997 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.05,2.45605,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.05,9.8242,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.05,39.2968,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.4,2.45605,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.4,9.8242,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.4,39.2968,18.479366666666667 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.05,2.45605,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.05,9.8242,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.05,39.2968,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.4,2.45605,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.4,9.8242,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.4,39.2968,7.1822333333333335 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.05,2.45605,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.05,9.8242,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.05,39.2968,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.4,2.45605,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.4,9.8242,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.4,39.2968,15.602522222222225 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.05,2.45605,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.05,9.8242,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.05,39.2968,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.4,2.45605,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.4,9.8242,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.4,39.2968,14.681844444444446 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.05,2.45605,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.05,9.8242,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.05,39.2968,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.4,2.45605,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.4,9.8242,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.4,39.2968,5.5341555555555555 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.05,2.45605,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.05,9.8242,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.05,39.2968,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.4,2.45605,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.4,9.8242,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.4,39.2968,19.71031111111111 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,17.8862 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,17.8862 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,17.8862 -32,3,2,61533,SS,5.0,25,0.05,2.45605,17.8862 -32,3,2,61533,SS,5.0,25,0.05,9.8242,17.8862 -32,3,2,61533,SS,5.0,25,0.05,39.2968,17.8862 -32,3,2,61533,SS,5.0,25,0.4,2.45605,17.8862 -32,3,2,61533,SS,5.0,25,0.4,9.8242,17.8862 -32,3,2,61533,SS,5.0,25,0.4,39.2968,17.8862 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.05,2.45605,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.05,9.8242,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.05,39.2968,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.4,2.45605,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.4,9.8242,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.4,39.2968,6.923377777777778 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.05,2.45605,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.05,9.8242,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.05,39.2968,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.4,2.45605,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.4,9.8242,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.4,39.2968,18.071544444444445 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.05,2.45605,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.05,9.8242,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.05,39.2968,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.4,2.45605,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.4,9.8242,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.4,39.2968,16.317744444444447 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.05,2.45605,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.05,9.8242,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.05,39.2968,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.4,2.45605,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.4,9.8242,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.4,39.2968,6.271166666666668 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.05,2.45605,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.05,9.8242,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.05,39.2968,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.4,2.45605,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.4,9.8242,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.4,39.2968,17.808344444444447 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,16.077 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,16.077 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,16.077 -16,3,1,49288,SS,5.0,25,0.05,2.45605,16.077 -16,3,1,49288,SS,5.0,25,0.05,9.8242,16.077 -16,3,1,49288,SS,5.0,25,0.05,39.2968,16.077 -16,3,1,49288,SS,5.0,25,0.4,2.45605,16.077 -16,3,1,49288,SS,5.0,25,0.4,9.8242,16.077 -16,3,1,49288,SS,5.0,25,0.4,39.2968,16.077 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.05,2.45605,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.05,9.8242,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.05,39.2968,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.4,2.45605,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.4,9.8242,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.4,39.2968,6.150088888888889 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.05,2.45605,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.05,9.8242,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.05,39.2968,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.4,2.45605,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.4,9.8242,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.4,39.2968,17.73747777777778 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.05,2.45605,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.05,9.8242,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.05,39.2968,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.4,2.45605,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.4,9.8242,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.4,39.2968,16.819411111111112 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.05,2.45605,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.05,9.8242,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.05,39.2968,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.4,2.45605,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.4,9.8242,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.4,39.2968,6.42408888888889 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.05,2.45605,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.05,9.8242,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.05,39.2968,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.4,2.45605,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.4,9.8242,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.4,39.2968,16.546355555555554 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.05,2.45605,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.05,9.8242,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.05,39.2968,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.4,2.45605,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.4,9.8242,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.4,39.2968,15.652822222222223 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,5.9406 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,5.9406 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,5.9406 -32,1,2,50620,TT,3.6,25,0.05,2.45605,5.9406 -32,1,2,50620,TT,3.6,25,0.05,9.8242,5.9406 -32,1,2,50620,TT,3.6,25,0.05,39.2968,5.9406 -32,1,2,50620,TT,3.6,25,0.4,2.45605,5.9406 -32,1,2,50620,TT,3.6,25,0.4,9.8242,5.9406 -32,1,2,50620,TT,3.6,25,0.4,39.2968,5.9406 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.05,2.45605,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.05,9.8242,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.05,39.2968,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.4,2.45605,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.4,9.8242,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.4,39.2968,18.96528888888889 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.05,2.45605,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.05,9.8242,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.05,39.2968,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.4,2.45605,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.4,9.8242,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.4,39.2968,17.086611111111115 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.05,2.45605,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.05,9.8242,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.05,39.2968,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.4,2.45605,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.4,9.8242,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.4,39.2968,17.49298888888889 diff --git a/technology/scn4m_subm/sim_data/read1_power.csv b/technology/scn4m_subm/sim_data/read1_power.csv deleted file mode 100644 index 6a3470b8..00000000 --- a/technology/scn4m_subm/sim_data/read1_power.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,read1_power -16,2,1,46853,FF,5.0,25,0.0125,2.45605,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.05,2.45605,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.05,9.8242,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.05,39.2968,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.4,2.45605,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.4,9.8242,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.4,39.2968,16.676000000000002 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.05,2.45605,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.05,9.8242,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.05,39.2968,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.4,2.45605,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.4,9.8242,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.4,39.2968,15.048222222222222 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.05,2.45605,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.05,9.8242,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.05,39.2968,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.4,2.45605,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.4,9.8242,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.4,39.2968,5.970233333333334 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.05,2.45605,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.05,9.8242,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.05,39.2968,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.4,2.45605,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.4,9.8242,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.4,39.2968,20.39606666666667 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.05,2.45605,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.05,9.8242,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.05,39.2968,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.4,2.45605,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.4,9.8242,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.4,39.2968,18.48441111111111 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.05,2.45605,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.05,9.8242,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.05,39.2968,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.4,2.45605,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.4,9.8242,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.4,39.2968,7.184488888888889 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.05,2.45605,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.05,9.8242,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.05,39.2968,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.4,2.45605,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.4,9.8242,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.4,39.2968,15.575122222222225 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.05,2.45605,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.05,9.8242,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.05,39.2968,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.4,2.45605,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.4,9.8242,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.4,39.2968,14.689155555555557 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.05,2.45605,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.05,9.8242,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.05,39.2968,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.4,2.45605,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.4,9.8242,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.4,39.2968,5.536955555555556 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.05,2.45605,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.05,9.8242,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.05,39.2968,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.4,2.45605,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.4,9.8242,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.4,39.2968,19.72533333333333 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.05,2.45605,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.05,9.8242,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.05,39.2968,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.4,2.45605,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.4,9.8242,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.4,39.2968,17.891011111111112 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.05,2.45605,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.05,9.8242,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.05,39.2968,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.4,2.45605,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.4,9.8242,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.4,39.2968,6.928544444444444 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.05,2.45605,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.05,9.8242,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.05,39.2968,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.4,2.45605,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.4,9.8242,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.4,39.2968,18.03156666666667 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.05,2.45605,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.05,9.8242,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.05,39.2968,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.4,2.45605,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.4,9.8242,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.4,39.2968,16.29516666666667 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.05,2.45605,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.05,9.8242,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.05,39.2968,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.4,2.45605,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.4,9.8242,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.4,39.2968,6.273288888888889 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,17.8174 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,17.8174 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,17.8174 -16,3,1,49288,FF,5.0,25,0.05,2.45605,17.8174 -16,3,1,49288,FF,5.0,25,0.05,9.8242,17.8174 -16,3,1,49288,FF,5.0,25,0.05,39.2968,17.8174 -16,3,1,49288,FF,5.0,25,0.4,2.45605,17.8174 -16,3,1,49288,FF,5.0,25,0.4,9.8242,17.8174 -16,3,1,49288,FF,5.0,25,0.4,39.2968,17.8174 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.05,2.45605,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.05,9.8242,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.05,39.2968,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.4,2.45605,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.4,9.8242,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.4,39.2968,16.06187777777778 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.05,2.45605,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.05,9.8242,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.05,39.2968,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.4,2.45605,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.4,9.8242,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.4,39.2968,6.1565666666666665 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.05,2.45605,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.05,9.8242,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.05,39.2968,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.4,2.45605,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.4,9.8242,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.4,39.2968,17.734988888888886 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.05,2.45605,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.05,9.8242,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.05,39.2968,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.4,2.45605,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.4,9.8242,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.4,39.2968,16.84127777777778 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.05,2.45605,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.05,9.8242,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.05,39.2968,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.4,2.45605,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.4,9.8242,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.4,39.2968,6.42288888888889 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.05,2.45605,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.05,9.8242,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.05,39.2968,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.4,2.45605,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.4,9.8242,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.4,39.2968,16.541811111111112 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.05,2.45605,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.05,9.8242,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.05,39.2968,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.4,2.45605,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.4,9.8242,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.4,39.2968,15.645522222222224 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.05,2.45605,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.05,9.8242,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.05,39.2968,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.4,2.45605,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.4,9.8242,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.4,39.2968,5.9442666666666675 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.05,2.45605,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.05,9.8242,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.05,39.2968,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.4,2.45605,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.4,9.8242,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.4,39.2968,18.936366666666668 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.05,2.45605,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.05,9.8242,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.05,39.2968,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.4,2.45605,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.4,9.8242,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.4,39.2968,17.10342222222222 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.05,2.45605,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.05,9.8242,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.05,39.2968,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.4,2.45605,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.4,9.8242,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.4,39.2968,17.458644444444445 diff --git a/technology/scn4m_subm/sim_data/rise_delay.csv b/technology/scn4m_subm/sim_data/rise_delay.csv deleted file mode 100644 index afed9e02..00000000 --- a/technology/scn4m_subm/sim_data/rise_delay.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,rise_delay -16,2,1,46853,FF,5.0,25,0.0125,2.45605,1.4938000000000002 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,1.5326 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,1.6802000000000001 -16,2,1,46853,FF,5.0,25,0.05,2.45605,1.4975 -16,2,1,46853,FF,5.0,25,0.05,9.8242,1.5366 -16,2,1,46853,FF,5.0,25,0.05,39.2968,1.6841 -16,2,1,46853,FF,5.0,25,0.4,2.45605,1.5540000000000003 -16,2,1,46853,FF,5.0,25,0.4,9.8242,1.5933000000000002 -16,2,1,46853,FF,5.0,25,0.4,39.2968,1.7406 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,1.546 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,1.5871 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,1.7390000000000003 -16,2,1,46853,SS,5.0,25,0.05,2.45605,1.5518 -16,2,1,46853,SS,5.0,25,0.05,9.8242,1.5922 -16,2,1,46853,SS,5.0,25,0.05,39.2968,1.7441 -16,2,1,46853,SS,5.0,25,0.4,2.45605,1.6087 -16,2,1,46853,SS,5.0,25,0.4,9.8242,1.6503 -16,2,1,46853,SS,5.0,25,0.4,39.2968,1.8022 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,1.8344000000000003 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,1.8822000000000003 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,2.0635000000000003 -16,2,1,46853,TT,3.6,25,0.05,2.45605,1.8402 -16,2,1,46853,TT,3.6,25,0.05,9.8242,1.8872000000000002 -16,2,1,46853,TT,3.6,25,0.05,39.2968,2.0700000000000003 -16,2,1,46853,TT,3.6,25,0.4,2.45605,1.9033000000000002 -16,2,1,46853,TT,3.6,25,0.4,9.8242,1.9512 -16,2,1,46853,TT,3.6,25,0.4,39.2968,2.1324 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,1.8070000000000002 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,1.8492 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,2.0125 -64,2,4,66821,FF,5.0,25,0.05,2.45605,1.811 -64,2,4,66821,FF,5.0,25,0.05,9.8242,1.8535000000000001 -64,2,4,66821,FF,5.0,25,0.05,39.2968,2.016 -64,2,4,66821,FF,5.0,25,0.4,2.45605,1.8676000000000001 -64,2,4,66821,FF,5.0,25,0.4,9.8242,1.9101 -64,2,4,66821,FF,5.0,25,0.4,39.2968,2.0732000000000004 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,1.8638000000000001 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,1.9071000000000002 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,2.0763 -64,2,4,66821,SS,5.0,25,0.05,2.45605,1.8675 -64,2,4,66821,SS,5.0,25,0.05,9.8242,1.9116 -64,2,4,66821,SS,5.0,25,0.05,39.2968,2.0798 -64,2,4,66821,SS,5.0,25,0.4,2.45605,1.9269 -64,2,4,66821,SS,5.0,25,0.4,9.8242,1.9710000000000003 -64,2,4,66821,SS,5.0,25,0.4,39.2968,2.1389 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,2.2213 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,2.2757000000000005 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,2.4855 -64,2,4,66821,TT,3.6,25,0.05,2.45605,2.2262 -64,2,4,66821,TT,3.6,25,0.05,9.8242,2.281 -64,2,4,66821,TT,3.6,25,0.05,39.2968,2.4907 -64,2,4,66821,TT,3.6,25,0.4,2.45605,2.2909000000000006 -64,2,4,66821,TT,3.6,25,0.4,9.8242,2.3447 -64,2,4,66821,TT,3.6,25,0.4,39.2968,2.5554 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,1.4932 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,1.5311000000000001 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,1.6784 -16,1,1,44918,FF,5.0,25,0.05,2.45605,1.4969000000000001 -16,1,1,44918,FF,5.0,25,0.05,9.8242,1.5359 -16,1,1,44918,FF,5.0,25,0.05,39.2968,1.6818000000000002 -16,1,1,44918,FF,5.0,25,0.4,2.45605,1.5468000000000002 -16,1,1,44918,FF,5.0,25,0.4,9.8242,1.5872000000000002 -16,1,1,44918,FF,5.0,25,0.4,39.2968,1.732 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,1.5465 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,1.5855 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,1.7358000000000002 -16,1,1,44918,SS,5.0,25,0.05,2.45605,1.5502 -16,1,1,44918,SS,5.0,25,0.05,9.8242,1.5898000000000003 -16,1,1,44918,SS,5.0,25,0.05,39.2968,1.7407 -16,1,1,44918,SS,5.0,25,0.4,2.45605,1.6046000000000002 -16,1,1,44918,SS,5.0,25,0.4,9.8242,1.6447 -16,1,1,44918,SS,5.0,25,0.4,39.2968,1.7955000000000003 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,1.8358000000000003 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,1.8833 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,2.0637 -16,1,1,44918,TT,3.6,25,0.05,2.45605,1.8410000000000002 -16,1,1,44918,TT,3.6,25,0.05,9.8242,1.8883 -16,1,1,44918,TT,3.6,25,0.05,39.2968,2.0690000000000004 -16,1,1,44918,TT,3.6,25,0.4,2.45605,1.8998 -16,1,1,44918,TT,3.6,25,0.4,9.8242,1.9467000000000003 -16,1,1,44918,TT,3.6,25,0.4,39.2968,2.1277 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,1.7466 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,1.7888000000000002 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,1.951 -32,3,2,61533,FF,5.0,25,0.05,2.45605,1.7509000000000001 -32,3,2,61533,FF,5.0,25,0.05,9.8242,1.7935000000000003 -32,3,2,61533,FF,5.0,25,0.05,39.2968,1.9557000000000002 -32,3,2,61533,FF,5.0,25,0.4,2.45605,1.8069 -32,3,2,61533,FF,5.0,25,0.4,9.8242,1.8495000000000001 -32,3,2,61533,FF,5.0,25,0.4,39.2968,2.0117 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,1.8027 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,1.8469000000000002 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,2.0147 -32,3,2,61533,SS,5.0,25,0.05,2.45605,1.8072000000000001 -32,3,2,61533,SS,5.0,25,0.05,9.8242,1.8516000000000001 -32,3,2,61533,SS,5.0,25,0.05,39.2968,2.0192 -32,3,2,61533,SS,5.0,25,0.4,2.45605,1.8658 -32,3,2,61533,SS,5.0,25,0.4,9.8242,1.9107 -32,3,2,61533,SS,5.0,25,0.4,39.2968,2.079 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,2.1397 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,2.1948 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,2.4041000000000006 -32,3,2,61533,TT,3.6,25,0.05,2.45605,2.1449 -32,3,2,61533,TT,3.6,25,0.05,9.8242,2.1999000000000004 -32,3,2,61533,TT,3.6,25,0.05,39.2968,2.4093 -32,3,2,61533,TT,3.6,25,0.4,2.45605,2.2086000000000006 -32,3,2,61533,TT,3.6,25,0.4,9.8242,2.2639 -32,3,2,61533,TT,3.6,25,0.4,39.2968,2.4734000000000003 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,1.7161000000000002 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,1.7588 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,1.9199 -32,2,2,55960,FF,5.0,25,0.05,2.45605,1.72 -32,2,2,55960,FF,5.0,25,0.05,9.8242,1.7622000000000002 -32,2,2,55960,FF,5.0,25,0.05,39.2968,1.9238 -32,2,2,55960,FF,5.0,25,0.4,2.45605,1.7759000000000003 -32,2,2,55960,FF,5.0,25,0.4,9.8242,1.8184 -32,2,2,55960,FF,5.0,25,0.4,39.2968,1.9794 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,1.7713000000000003 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,1.8156000000000003 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,1.9823000000000002 -32,2,2,55960,SS,5.0,25,0.05,2.45605,1.7763000000000002 -32,2,2,55960,SS,5.0,25,0.05,9.8242,1.8201 -32,2,2,55960,SS,5.0,25,0.05,39.2968,1.9870000000000003 -32,2,2,55960,SS,5.0,25,0.4,2.45605,1.8341 -32,2,2,55960,SS,5.0,25,0.4,9.8242,1.8781000000000003 -32,2,2,55960,SS,5.0,25,0.4,39.2968,2.0451 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,2.1025 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,2.1574 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,2.366 -32,2,2,55960,TT,3.6,25,0.05,2.45605,2.1063 -32,2,2,55960,TT,3.6,25,0.05,9.8242,2.1612 -32,2,2,55960,TT,3.6,25,0.05,39.2968,2.3698 -32,2,2,55960,TT,3.6,25,0.4,2.45605,2.1703 -32,2,2,55960,TT,3.6,25,0.4,9.8242,2.2248000000000006 -32,2,2,55960,TT,3.6,25,0.4,39.2968,2.4334 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,1.5062 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,1.5456 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,1.6936 -16,3,1,49288,FF,5.0,25,0.05,2.45605,1.5117 -16,3,1,49288,FF,5.0,25,0.05,9.8242,1.5506 -16,3,1,49288,FF,5.0,25,0.05,39.2968,1.6983 -16,3,1,49288,FF,5.0,25,0.4,2.45605,1.5674 -16,3,1,49288,FF,5.0,25,0.4,9.8242,1.6067 -16,3,1,49288,FF,5.0,25,0.4,39.2968,1.7538 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,1.5613 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,1.6019000000000003 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,1.7544 -16,3,1,49288,SS,5.0,25,0.05,2.45605,1.5662000000000003 -16,3,1,49288,SS,5.0,25,0.05,9.8242,1.6061000000000003 -16,3,1,49288,SS,5.0,25,0.05,39.2968,1.7587000000000002 -16,3,1,49288,SS,5.0,25,0.4,2.45605,1.6242000000000003 -16,3,1,49288,SS,5.0,25,0.4,9.8242,1.6645 -16,3,1,49288,SS,5.0,25,0.4,39.2968,1.817 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,1.8522000000000003 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,1.9004 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,2.0833 -16,3,1,49288,TT,3.6,25,0.05,2.45605,1.8586000000000003 -16,3,1,49288,TT,3.6,25,0.05,9.8242,1.9065000000000003 -16,3,1,49288,TT,3.6,25,0.05,39.2968,2.0888 -16,3,1,49288,TT,3.6,25,0.4,2.45605,1.9209000000000003 -16,3,1,49288,TT,3.6,25,0.4,9.8242,1.9689 -16,3,1,49288,TT,3.6,25,0.4,39.2968,2.1510000000000002 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,1.7980000000000003 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,1.8410000000000002 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,2.0055 -64,1,4,56307,FF,5.0,25,0.05,2.45605,1.8018 -64,1,4,56307,FF,5.0,25,0.05,9.8242,1.8449000000000002 -64,1,4,56307,FF,5.0,25,0.05,39.2968,2.0094000000000003 -64,1,4,56307,FF,5.0,25,0.4,2.45605,1.8579 -64,1,4,56307,FF,5.0,25,0.4,9.8242,1.9013 -64,1,4,56307,FF,5.0,25,0.4,39.2968,2.0651 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,1.8547000000000002 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,1.8986 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,2.0683 -64,1,4,56307,SS,5.0,25,0.05,2.45605,1.8586000000000003 -64,1,4,56307,SS,5.0,25,0.05,9.8242,1.9023000000000003 -64,1,4,56307,SS,5.0,25,0.05,39.2968,2.0722000000000005 -64,1,4,56307,SS,5.0,25,0.4,2.45605,1.9177000000000002 -64,1,4,56307,SS,5.0,25,0.4,9.8242,1.9612000000000003 -64,1,4,56307,SS,5.0,25,0.4,39.2968,2.1309 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,2.2058 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,2.2605000000000004 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,2.4711 -64,1,4,56307,TT,3.6,25,0.05,2.45605,2.2114000000000003 -64,1,4,56307,TT,3.6,25,0.05,9.8242,2.2665 -64,1,4,56307,TT,3.6,25,0.05,39.2968,2.4763 -64,1,4,56307,TT,3.6,25,0.4,2.45605,2.275 -64,1,4,56307,TT,3.6,25,0.4,9.8242,2.3298000000000005 -64,1,4,56307,TT,3.6,25,0.4,39.2968,2.5404 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,1.6865 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,1.7291 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,1.8895000000000002 -32,1,2,50620,FF,5.0,25,0.05,2.45605,1.6914000000000002 -32,1,2,50620,FF,5.0,25,0.05,9.8242,1.7333000000000003 -32,1,2,50620,FF,5.0,25,0.05,39.2968,1.8939 -32,1,2,50620,FF,5.0,25,0.4,2.45605,1.7472 -32,1,2,50620,FF,5.0,25,0.4,9.8242,1.7880000000000003 -32,1,2,50620,FF,5.0,25,0.4,39.2968,1.9504000000000001 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,1.7409000000000001 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,1.7842 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,1.9504000000000001 -32,1,2,50620,SS,5.0,25,0.05,2.45605,1.7450000000000003 -32,1,2,50620,SS,5.0,25,0.05,9.8242,1.7885000000000002 -32,1,2,50620,SS,5.0,25,0.05,39.2968,1.9549000000000003 -32,1,2,50620,SS,5.0,25,0.4,2.45605,1.8043 -32,1,2,50620,SS,5.0,25,0.4,9.8242,1.8470000000000002 -32,1,2,50620,SS,5.0,25,0.4,39.2968,2.0142 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,2.0660000000000003 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,2.1195 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,2.3282 -32,1,2,50620,TT,3.6,25,0.05,2.45605,2.0698 -32,1,2,50620,TT,3.6,25,0.05,9.8242,2.1242 -32,1,2,50620,TT,3.6,25,0.05,39.2968,2.3331 -32,1,2,50620,TT,3.6,25,0.4,2.45605,2.1344 -32,1,2,50620,TT,3.6,25,0.4,9.8242,2.1888 -32,1,2,50620,TT,3.6,25,0.4,39.2968,2.3966000000000003 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,1.5255 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,1.5651000000000002 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,1.7136000000000002 -16,4,1,51796,FF,5.0,25,0.05,2.45605,1.5287000000000002 -16,4,1,51796,FF,5.0,25,0.05,9.8242,1.5694 -16,4,1,51796,FF,5.0,25,0.05,39.2968,1.7179 -16,4,1,51796,FF,5.0,25,0.4,2.45605,1.5851 -16,4,1,51796,FF,5.0,25,0.4,9.8242,1.6246000000000003 -16,4,1,51796,FF,5.0,25,0.4,39.2968,1.7731 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,1.5803000000000003 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,1.6209 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,1.7744 -16,4,1,51796,SS,5.0,25,0.05,2.45605,1.5839 -16,4,1,51796,SS,5.0,25,0.05,9.8242,1.6246000000000003 -16,4,1,51796,SS,5.0,25,0.05,39.2968,1.7778000000000003 -16,4,1,51796,SS,5.0,25,0.4,2.45605,1.6416 -16,4,1,51796,SS,5.0,25,0.4,9.8242,1.6837000000000002 -16,4,1,51796,SS,5.0,25,0.4,39.2968,1.8361 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,1.5574000000000001 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,1.5984000000000003 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,1.7492 -16,4,1,51796,TT,5.0,25,0.05,2.45605,1.5622 -16,4,1,51796,TT,5.0,25,0.05,9.8242,1.6025000000000003 -16,4,1,51796,TT,5.0,25,0.05,39.2968,1.7526000000000002 -16,4,1,51796,TT,5.0,25,0.4,2.45605,1.618 -16,4,1,51796,TT,5.0,25,0.4,9.8242,1.6577 -16,4,1,51796,TT,5.0,25,0.4,39.2968,1.8096000000000003 diff --git a/technology/scn4m_subm/sim_data/rise_slew.csv b/technology/scn4m_subm/sim_data/rise_slew.csv deleted file mode 100644 index 967ff5d0..00000000 --- a/technology/scn4m_subm/sim_data/rise_slew.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,rise_slew -16,2,1,46853,FF,5.0,25,0.0125,2.45605,1.7733000000000003 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,1.7797000000000003 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,1.8085000000000002 -16,2,1,46853,FF,5.0,25,0.05,2.45605,1.7736 -16,2,1,46853,FF,5.0,25,0.05,9.8242,1.7796 -16,2,1,46853,FF,5.0,25,0.05,39.2968,1.8081000000000003 -16,2,1,46853,FF,5.0,25,0.4,2.45605,1.774 -16,2,1,46853,FF,5.0,25,0.4,9.8242,1.7812000000000001 -16,2,1,46853,FF,5.0,25,0.4,39.2968,1.8084 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,1.8483 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,1.8552000000000002 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,1.8888000000000003 -16,2,1,46853,SS,5.0,25,0.05,2.45605,1.8472 -16,2,1,46853,SS,5.0,25,0.05,9.8242,1.8547000000000002 -16,2,1,46853,SS,5.0,25,0.05,39.2968,1.8883 -16,2,1,46853,SS,5.0,25,0.4,2.45605,1.8462 -16,2,1,46853,SS,5.0,25,0.4,9.8242,1.8541000000000003 -16,2,1,46853,SS,5.0,25,0.4,39.2968,1.8880000000000001 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,2.2169 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,2.2276000000000002 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,2.2752000000000003 -16,2,1,46853,TT,3.6,25,0.05,2.45605,2.2169 -16,2,1,46853,TT,3.6,25,0.05,9.8242,2.2274 -16,2,1,46853,TT,3.6,25,0.05,39.2968,2.2752000000000003 -16,2,1,46853,TT,3.6,25,0.4,2.45605,2.2155 -16,2,1,46853,TT,3.6,25,0.4,9.8242,2.2265 -16,2,1,46853,TT,3.6,25,0.4,39.2968,2.274 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,1.6523 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,1.6619 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,1.6992 -64,2,4,66821,FF,5.0,25,0.05,2.45605,1.6526000000000003 -64,2,4,66821,FF,5.0,25,0.05,9.8242,1.6615000000000002 -64,2,4,66821,FF,5.0,25,0.05,39.2968,1.6989000000000003 -64,2,4,66821,FF,5.0,25,0.4,2.45605,1.6514000000000002 -64,2,4,66821,FF,5.0,25,0.4,9.8242,1.6621000000000001 -64,2,4,66821,FF,5.0,25,0.4,39.2968,1.6979000000000002 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,1.7235 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,1.7336 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,1.7746 -64,2,4,66821,SS,5.0,25,0.05,2.45605,1.7236 -64,2,4,66821,SS,5.0,25,0.05,9.8242,1.7332 -64,2,4,66821,SS,5.0,25,0.05,39.2968,1.7749 -64,2,4,66821,SS,5.0,25,0.4,2.45605,1.7249 -64,2,4,66821,SS,5.0,25,0.4,9.8242,1.7345 -64,2,4,66821,SS,5.0,25,0.4,39.2968,1.7753000000000003 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,2.0566 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,2.0700000000000003 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,2.1247 -64,2,4,66821,TT,3.6,25,0.05,2.45605,2.0569 -64,2,4,66821,TT,3.6,25,0.05,9.8242,2.0712000000000006 -64,2,4,66821,TT,3.6,25,0.05,39.2968,2.1243 -64,2,4,66821,TT,3.6,25,0.4,2.45605,2.0575000000000006 -64,2,4,66821,TT,3.6,25,0.4,9.8242,2.0712000000000006 -64,2,4,66821,TT,3.6,25,0.4,39.2968,2.1244 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,1.7495000000000003 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,1.7561000000000002 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,1.7857 -16,1,1,44918,FF,5.0,25,0.05,2.45605,1.7488 -16,1,1,44918,FF,5.0,25,0.05,9.8242,1.7553 -16,1,1,44918,FF,5.0,25,0.05,39.2968,1.7849000000000002 -16,1,1,44918,FF,5.0,25,0.4,2.45605,1.7487 -16,1,1,44918,FF,5.0,25,0.4,9.8242,1.7550000000000001 -16,1,1,44918,FF,5.0,25,0.4,39.2968,1.7854000000000003 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,1.8221 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,1.8306 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,1.8645000000000003 -16,1,1,44918,SS,5.0,25,0.05,2.45605,1.8229 -16,1,1,44918,SS,5.0,25,0.05,9.8242,1.8298000000000003 -16,1,1,44918,SS,5.0,25,0.05,39.2968,1.8645000000000003 -16,1,1,44918,SS,5.0,25,0.4,2.45605,1.8223000000000003 -16,1,1,44918,SS,5.0,25,0.4,9.8242,1.829 -16,1,1,44918,SS,5.0,25,0.4,39.2968,1.8636000000000001 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,2.1882 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,2.199 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,2.2476 -16,1,1,44918,TT,3.6,25,0.05,2.45605,2.1871 -16,1,1,44918,TT,3.6,25,0.05,9.8242,2.198 -16,1,1,44918,TT,3.6,25,0.05,39.2968,2.2471 -16,1,1,44918,TT,3.6,25,0.4,2.45605,2.186 -16,1,1,44918,TT,3.6,25,0.4,9.8242,2.1974000000000005 -16,1,1,44918,TT,3.6,25,0.4,39.2968,2.2482 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,1.6930000000000003 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,1.7023 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,1.7384000000000002 -32,3,2,61533,FF,5.0,25,0.05,2.45605,1.6936 -32,3,2,61533,FF,5.0,25,0.05,9.8242,1.7029 -32,3,2,61533,FF,5.0,25,0.05,39.2968,1.7383000000000002 -32,3,2,61533,FF,5.0,25,0.4,2.45605,1.6926 -32,3,2,61533,FF,5.0,25,0.4,9.8242,1.7030000000000003 -32,3,2,61533,FF,5.0,25,0.4,39.2968,1.7383000000000002 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,1.7645 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,1.7747000000000002 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,1.815 -32,3,2,61533,SS,5.0,25,0.05,2.45605,1.766 -32,3,2,61533,SS,5.0,25,0.05,9.8242,1.7753000000000003 -32,3,2,61533,SS,5.0,25,0.05,39.2968,1.8152000000000001 -32,3,2,61533,SS,5.0,25,0.4,2.45605,1.7669 -32,3,2,61533,SS,5.0,25,0.4,9.8242,1.777 -32,3,2,61533,SS,5.0,25,0.4,39.2968,1.8152000000000001 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,2.1084000000000005 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,2.1226000000000003 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,2.1758 -32,3,2,61533,TT,3.6,25,0.05,2.45605,2.1088 -32,3,2,61533,TT,3.6,25,0.05,9.8242,2.1235 -32,3,2,61533,TT,3.6,25,0.05,39.2968,2.1756 -32,3,2,61533,TT,3.6,25,0.4,2.45605,2.1091000000000006 -32,3,2,61533,TT,3.6,25,0.4,9.8242,2.1213000000000006 -32,3,2,61533,TT,3.6,25,0.4,39.2968,2.1751 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,1.6751 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,1.6843000000000001 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,1.7199 -32,2,2,55960,FF,5.0,25,0.05,2.45605,1.6754 -32,2,2,55960,FF,5.0,25,0.05,9.8242,1.6838000000000002 -32,2,2,55960,FF,5.0,25,0.05,39.2968,1.7202000000000002 -32,2,2,55960,FF,5.0,25,0.4,2.45605,1.6771 -32,2,2,55960,FF,5.0,25,0.4,9.8242,1.6857 -32,2,2,55960,FF,5.0,25,0.4,39.2968,1.7212000000000003 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,1.7473 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,1.7574 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,1.7962 -32,2,2,55960,SS,5.0,25,0.05,2.45605,1.7467 -32,2,2,55960,SS,5.0,25,0.05,9.8242,1.7568 -32,2,2,55960,SS,5.0,25,0.05,39.2968,1.7966000000000002 -32,2,2,55960,SS,5.0,25,0.4,2.45605,1.7470000000000003 -32,2,2,55960,SS,5.0,25,0.4,9.8242,1.7571000000000003 -32,2,2,55960,SS,5.0,25,0.4,39.2968,1.7965000000000002 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,2.0848 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,2.0981 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,2.1533 -32,2,2,55960,TT,3.6,25,0.05,2.45605,2.0851 -32,2,2,55960,TT,3.6,25,0.05,9.8242,2.0985 -32,2,2,55960,TT,3.6,25,0.05,39.2968,2.1534 -32,2,2,55960,TT,3.6,25,0.4,2.45605,2.087 -32,2,2,55960,TT,3.6,25,0.4,9.8242,2.1005 -32,2,2,55960,TT,3.6,25,0.4,39.2968,2.1537 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,1.7972 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,1.8042 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,1.8323000000000003 -16,3,1,49288,FF,5.0,25,0.05,2.45605,1.7976000000000003 -16,3,1,49288,FF,5.0,25,0.05,9.8242,1.8042 -16,3,1,49288,FF,5.0,25,0.05,39.2968,1.8332 -16,3,1,49288,FF,5.0,25,0.4,2.45605,1.7986000000000002 -16,3,1,49288,FF,5.0,25,0.4,9.8242,1.8053 -16,3,1,49288,FF,5.0,25,0.4,39.2968,1.8329000000000002 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,1.8728 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,1.8801 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,1.9131 -16,3,1,49288,SS,5.0,25,0.05,2.45605,1.873 -16,3,1,49288,SS,5.0,25,0.05,9.8242,1.8798000000000001 -16,3,1,49288,SS,5.0,25,0.05,39.2968,1.9137000000000002 -16,3,1,49288,SS,5.0,25,0.4,2.45605,1.8741000000000003 -16,3,1,49288,SS,5.0,25,0.4,9.8242,1.882 -16,3,1,49288,SS,5.0,25,0.4,39.2968,1.9137000000000002 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,2.2478000000000002 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,2.2586 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,2.3049000000000004 -16,3,1,49288,TT,3.6,25,0.05,2.45605,2.2489 -16,3,1,49288,TT,3.6,25,0.05,9.8242,2.2599 -16,3,1,49288,TT,3.6,25,0.05,39.2968,2.3051000000000004 -16,3,1,49288,TT,3.6,25,0.4,2.45605,2.2488 -16,3,1,49288,TT,3.6,25,0.4,9.8242,2.2592000000000003 -16,3,1,49288,TT,3.6,25,0.4,39.2968,2.3051000000000004 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,1.6302000000000003 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,1.6383000000000003 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,1.6746 -64,1,4,56307,FF,5.0,25,0.05,2.45605,1.6295 -64,1,4,56307,FF,5.0,25,0.05,9.8242,1.6381 -64,1,4,56307,FF,5.0,25,0.05,39.2968,1.6744 -64,1,4,56307,FF,5.0,25,0.4,2.45605,1.6302000000000003 -64,1,4,56307,FF,5.0,25,0.4,9.8242,1.6389000000000002 -64,1,4,56307,FF,5.0,25,0.4,39.2968,1.674 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,1.7001 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,1.7103 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,1.7491000000000003 -64,1,4,56307,SS,5.0,25,0.05,2.45605,1.7005000000000001 -64,1,4,56307,SS,5.0,25,0.05,9.8242,1.7093 -64,1,4,56307,SS,5.0,25,0.05,39.2968,1.7491000000000003 -64,1,4,56307,SS,5.0,25,0.4,2.45605,1.6997 -64,1,4,56307,SS,5.0,25,0.4,9.8242,1.7094 -64,1,4,56307,SS,5.0,25,0.4,39.2968,1.7490000000000003 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,2.0304 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,2.0431 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,2.0968 -64,1,4,56307,TT,3.6,25,0.05,2.45605,2.0301000000000005 -64,1,4,56307,TT,3.6,25,0.05,9.8242,2.0428000000000006 -64,1,4,56307,TT,3.6,25,0.05,39.2968,2.0958 -64,1,4,56307,TT,3.6,25,0.4,2.45605,2.0293000000000005 -64,1,4,56307,TT,3.6,25,0.4,9.8242,2.0441 -64,1,4,56307,TT,3.6,25,0.4,39.2968,2.0968 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,1.6570000000000003 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,1.6657000000000002 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,1.7021000000000002 -32,1,2,50620,FF,5.0,25,0.05,2.45605,1.6565000000000003 -32,1,2,50620,FF,5.0,25,0.05,9.8242,1.6653 -32,1,2,50620,FF,5.0,25,0.05,39.2968,1.7012 -32,1,2,50620,FF,5.0,25,0.4,2.45605,1.6566000000000003 -32,1,2,50620,FF,5.0,25,0.4,9.8242,1.6649 -32,1,2,50620,FF,5.0,25,0.4,39.2968,1.7007 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,1.7273000000000003 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,1.7378000000000002 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,1.7765 -32,1,2,50620,SS,5.0,25,0.05,2.45605,1.7264 -32,1,2,50620,SS,5.0,25,0.05,9.8242,1.7376 -32,1,2,50620,SS,5.0,25,0.05,39.2968,1.7772000000000001 -32,1,2,50620,SS,5.0,25,0.4,2.45605,1.7272000000000003 -32,1,2,50620,SS,5.0,25,0.4,9.8242,1.7377 -32,1,2,50620,SS,5.0,25,0.4,39.2968,1.7766 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,2.0632 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,2.0767000000000007 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,2.1305 -32,1,2,50620,TT,3.6,25,0.05,2.45605,2.0621 -32,1,2,50620,TT,3.6,25,0.05,9.8242,2.0756 -32,1,2,50620,TT,3.6,25,0.05,39.2968,2.1304 -32,1,2,50620,TT,3.6,25,0.4,2.45605,2.0626 -32,1,2,50620,TT,3.6,25,0.4,9.8242,2.0747000000000004 -32,1,2,50620,TT,3.6,25,0.4,39.2968,2.129 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,1.8218000000000003 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,1.8282000000000003 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,1.8565000000000003 -16,4,1,51796,FF,5.0,25,0.05,2.45605,1.8219 -16,4,1,51796,FF,5.0,25,0.05,9.8242,1.829 -16,4,1,51796,FF,5.0,25,0.05,39.2968,1.8567000000000002 -16,4,1,51796,FF,5.0,25,0.4,2.45605,1.8197000000000003 -16,4,1,51796,FF,5.0,25,0.4,9.8242,1.827 -16,4,1,51796,FF,5.0,25,0.4,39.2968,1.8559 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,1.8981 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,1.9056000000000002 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,1.9388000000000003 -16,4,1,51796,SS,5.0,25,0.05,2.45605,1.8991000000000002 -16,4,1,51796,SS,5.0,25,0.05,9.8242,1.9061 -16,4,1,51796,SS,5.0,25,0.05,39.2968,1.9387000000000003 -16,4,1,51796,SS,5.0,25,0.4,2.45605,1.8991000000000002 -16,4,1,51796,SS,5.0,25,0.4,9.8242,1.9077 -16,4,1,51796,SS,5.0,25,0.4,39.2968,1.9395000000000002 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,1.8666000000000003 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,1.873 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,1.9037 -16,4,1,51796,TT,5.0,25,0.05,2.45605,1.8657 -16,4,1,51796,TT,5.0,25,0.05,9.8242,1.8727 -16,4,1,51796,TT,5.0,25,0.05,39.2968,1.9036 -16,4,1,51796,TT,5.0,25,0.4,2.45605,1.8673 -16,4,1,51796,TT,5.0,25,0.4,9.8242,1.8746 -16,4,1,51796,TT,5.0,25,0.4,39.2968,1.9043 diff --git a/technology/scn4m_subm/sim_data/sim_data.csv b/technology/scn4m_subm/sim_data/sim_data.csv new file mode 100644 index 00000000..7547874e --- /dev/null +++ b/technology/scn4m_subm/sim_data/sim_data.csv @@ -0,0 +1,361 @@ +num_words,word_size,words_per_row,local_array_size,area,process,voltage,temperature,slew,load,rise_delay,fall_delay,rise_slew,fall_slew,write1_power,write0_power,read1_power,read0_power,leakage_power +1024,23,16,118,0,TT,5.0,25,0.0125,2.45605,5.3257,5.3257,1.5896,1.5896,224.82740672222224,612.9829622777778,607.3718511666667,607.2496289444446,0.014208 +1024,23,16,118,0,TT,5.0,25,0.0125,9.8242,5.3727,5.3727,1.616,1.616,224.82740672222224,612.9829622777778,607.3718511666667,607.2496289444446,0.014208 +1024,23,16,118,0,TT,5.0,25,0.0125,39.2968,5.5577000000000005,5.5577000000000005,1.7052,1.7052,224.82740672222224,612.9829622777778,607.3718511666667,607.2496289444446,0.014208 +1024,23,16,118,0,TT,5.0,25,0.05,2.45605,5.3308,5.3308,1.588,1.588,224.82740672222224,612.9829622777778,607.3718511666667,607.2496289444446,0.014208 +1024,23,16,118,0,TT,5.0,25,0.05,9.8242,5.3769,5.3769,1.6136000000000001,1.6136000000000001,224.82740672222224,612.9829622777778,607.3718511666667,607.2496289444446,0.014208 +1024,23,16,118,0,TT,5.0,25,0.05,39.2968,5.5625,5.5625,1.7062,1.7062,224.82740672222224,612.9829622777778,607.3718511666667,607.2496289444446,0.014208 +1024,23,16,118,0,TT,5.0,25,0.4,2.45605,5.3848,5.3848,1.5887,1.5887,224.82740672222224,612.9829622777778,607.3718511666667,607.2496289444446,0.014208 +1024,23,16,118,0,TT,5.0,25,0.4,9.8242,5.4293,5.4293,1.6143999999999998,1.6143999999999998,224.82740672222224,612.9829622777778,607.3718511666667,607.2496289444446,0.014208 +1024,23,16,118,0,TT,5.0,25,0.4,39.2968,5.6148,5.6148,1.7066999999999999,1.7066999999999999,224.82740672222224,612.9829622777778,607.3718511666667,607.2496289444446,0.014208 +128,18,2,7,0,TT,5.0,25,0.0125,2.45605,2.3794,2.3794,1.9038,1.9038,36.8490198,50.464130911111106,42.88001979999999,42.890130911111115,0.0061573 +128,18,2,7,0,TT,5.0,25,0.0125,9.8242,2.4221000000000004,2.4221000000000004,1.9203000000000001,1.9203000000000001,36.8490198,50.464130911111106,42.88001979999999,42.890130911111115,0.0061573 +128,18,2,7,0,TT,5.0,25,0.0125,39.2968,2.5852,2.5852,1.9765,1.9765,36.8490198,50.464130911111106,42.88001979999999,42.890130911111115,0.0061573 +128,18,2,7,0,TT,5.0,25,0.05,2.45605,2.3846,2.3846,1.9068,1.9068,36.8490198,50.464130911111106,42.88001979999999,42.890130911111115,0.0061573 +128,18,2,7,0,TT,5.0,25,0.05,9.8242,2.4276999999999997,2.4276999999999997,1.9207999999999998,1.9207999999999998,36.8490198,50.464130911111106,42.88001979999999,42.890130911111115,0.0061573 +128,18,2,7,0,TT,5.0,25,0.05,39.2968,2.5889,2.5889,1.9774999999999998,1.9774999999999998,36.8490198,50.464130911111106,42.88001979999999,42.890130911111115,0.0061573 +128,18,2,7,0,TT,5.0,25,0.4,2.45605,2.4343000000000004,2.4343000000000004,1.9052,1.9052,36.8490198,50.464130911111106,42.88001979999999,42.890130911111115,0.0061573 +128,18,2,7,0,TT,5.0,25,0.4,9.8242,2.4737,2.4737,1.9207999999999998,1.9207999999999998,36.8490198,50.464130911111106,42.88001979999999,42.890130911111115,0.0061573 +128,18,2,7,0,TT,5.0,25,0.4,39.2968,2.6404,2.6404,1.9793,1.9793,36.8490198,50.464130911111106,42.88001979999999,42.890130911111115,0.0061573 +128,12,4,38,0,TT,5.0,25,0.0125,2.45605,3.0334,3.0334,1.8818,1.8818,36.54689252222222,70.4785591888889,65.87200363333335,65.80544807777778,0.0012017 +128,12,4,38,0,TT,5.0,25,0.0125,9.8242,3.0724,3.0724,1.8950000000000002,1.8950000000000002,36.54689252222222,70.4785591888889,65.87200363333335,65.80544807777778,0.0012017 +128,12,4,38,0,TT,5.0,25,0.0125,39.2968,3.2311,3.2311,1.9507999999999999,1.9507999999999999,36.54689252222222,70.4785591888889,65.87200363333335,65.80544807777778,0.0012017 +128,12,4,38,0,TT,5.0,25,0.05,2.45605,3.0369,3.0369,1.8808,1.8808,36.54689252222222,70.4785591888889,65.87200363333335,65.80544807777778,0.0012017 +128,12,4,38,0,TT,5.0,25,0.05,9.8242,3.0789000000000004,3.0789000000000004,1.8949000000000003,1.8949000000000003,36.54689252222222,70.4785591888889,65.87200363333335,65.80544807777778,0.0012017 +128,12,4,38,0,TT,5.0,25,0.05,39.2968,3.2345,3.2345,1.9500000000000002,1.9500000000000002,36.54689252222222,70.4785591888889,65.87200363333335,65.80544807777778,0.0012017 +128,12,4,38,0,TT,5.0,25,0.4,2.45605,3.0887,3.0887,1.8835,1.8835,36.54689252222222,70.4785591888889,65.87200363333335,65.80544807777778,0.0012017 +128,12,4,38,0,TT,5.0,25,0.4,9.8242,3.1302999999999996,3.1302999999999996,1.8941999999999999,1.8941999999999999,36.54689252222222,70.4785591888889,65.87200363333335,65.80544807777778,0.0012017 +128,12,4,38,0,TT,5.0,25,0.4,39.2968,3.2857,3.2857,1.9506,1.9506,36.54689252222222,70.4785591888889,65.87200363333335,65.80544807777778,0.0012017 +2048,32,8,0,0,TT,5.0,25,0.0125,2.45605,4.107800999999999,4.107800999999999,2.418119,2.418119,72.59645279333334,147.76329612666666,139.25066279333336,138.05076279333332,0.07745576 +2048,32,8,0,0,TT,5.0,25,0.0125,9.8242,4.146399000000001,4.146399000000001,2.4387049999999997,2.4387049999999997,72.59645279333334,147.76329612666666,139.25066279333336,138.05076279333332,0.07745576 +2048,32,8,0,0,TT,5.0,25,0.0125,39.2968,4.299265,4.299265,2.512579,2.512579,72.59645279333334,147.76329612666666,139.25066279333336,138.05076279333332,0.07745576 +2048,32,8,0,0,TT,5.0,25,0.05,2.45605,4.111474,4.111474,2.418153,2.418153,72.59645279333334,147.76329612666666,139.25066279333336,138.05076279333332,0.07745576 +2048,32,8,0,0,TT,5.0,25,0.05,9.8242,4.150073,4.150073,2.4387540000000003,2.4387540000000003,72.59645279333334,147.76329612666666,139.25066279333336,138.05076279333332,0.07745576 +2048,32,8,0,0,TT,5.0,25,0.05,39.2968,4.302937,4.302937,2.512613,2.512613,72.59645279333334,147.76329612666666,139.25066279333336,138.05076279333332,0.07745576 +2048,32,8,0,0,TT,5.0,25,0.4,2.45605,4.1648700000000005,4.1648700000000005,2.418341,2.418341,72.59645279333334,147.76329612666666,139.25066279333336,138.05076279333332,0.07745576 +2048,32,8,0,0,TT,5.0,25,0.4,9.8242,4.203464,4.203464,2.438928,2.438928,72.59645279333334,147.76329612666666,139.25066279333336,138.05076279333332,0.07745576 +2048,32,8,0,0,TT,5.0,25,0.4,39.2968,4.35631,4.35631,2.512802,2.512802,72.59645279333334,147.76329612666666,139.25066279333336,138.05076279333332,0.07745576 +16,4,1,4,0,TT,5.0,25,0.0125,2.45605,1.6905,1.6905,1.7942,1.7942,15.848171559855558,20.850249337633333,18.529549337633334,18.519138226522223,0.0007197479 +16,4,1,4,0,TT,5.0,25,0.0125,9.8242,1.7296,1.7296,1.8031000000000001,1.8031000000000001,15.848171559855558,20.850249337633333,18.529549337633334,18.519138226522223,0.0007197479 +16,4,1,4,0,TT,5.0,25,0.0125,39.2968,1.8801,1.8801,1.8374000000000001,1.8374000000000001,15.848171559855558,20.850249337633333,18.529549337633334,18.519138226522223,0.0007197479 +16,4,1,4,0,TT,5.0,25,0.05,2.45605,1.6942,1.6942,1.7942,1.7942,15.848171559855558,20.850249337633333,18.529549337633334,18.519138226522223,0.0007197479 +16,4,1,4,0,TT,5.0,25,0.05,9.8242,1.7347,1.7347,1.8032,1.8032,15.848171559855558,20.850249337633333,18.529549337633334,18.519138226522223,0.0007197479 +16,4,1,4,0,TT,5.0,25,0.05,39.2968,1.8842,1.8842,1.8375000000000001,1.8375000000000001,15.848171559855558,20.850249337633333,18.529549337633334,18.519138226522223,0.0007197479 +16,4,1,4,0,TT,5.0,25,0.4,2.45605,1.7513,1.7513,1.7926,1.7926,15.848171559855558,20.850249337633333,18.529549337633334,18.519138226522223,0.0007197479 +16,4,1,4,0,TT,5.0,25,0.4,9.8242,1.7911,1.7911,1.8002,1.8002,15.848171559855558,20.850249337633333,18.529549337633334,18.519138226522223,0.0007197479 +16,4,1,4,0,TT,5.0,25,0.4,39.2968,1.94,1.94,1.8364000000000003,1.8364000000000003,15.848171559855558,20.850249337633333,18.529549337633334,18.519138226522223,0.0007197479 +256,9,4,15,0,TT,5.0,25,0.0125,2.45605,2.5514,2.5514,1.8206,1.8206,28.9865037,45.56072592222222,41.78883703333333,41.744281477777776,0.0028762 +256,9,4,15,0,TT,5.0,25,0.0125,9.8242,2.5893,2.5893,1.8331,1.8331,28.9865037,45.56072592222222,41.78883703333333,41.744281477777776,0.0028762 +256,9,4,15,0,TT,5.0,25,0.0125,39.2968,2.7430000000000003,2.7430000000000003,1.8849,1.8849,28.9865037,45.56072592222222,41.78883703333333,41.744281477777776,0.0028762 +256,9,4,15,0,TT,5.0,25,0.05,2.45605,2.5563,2.5563,1.8219999999999998,1.8219999999999998,28.9865037,45.56072592222222,41.78883703333333,41.744281477777776,0.0028762 +256,9,4,15,0,TT,5.0,25,0.05,9.8242,2.5945,2.5945,1.8363,1.8363,28.9865037,45.56072592222222,41.78883703333333,41.744281477777776,0.0028762 +256,9,4,15,0,TT,5.0,25,0.05,39.2968,2.7452,2.7452,1.8856999999999997,1.8856999999999997,28.9865037,45.56072592222222,41.78883703333333,41.744281477777776,0.0028762 +256,9,4,15,0,TT,5.0,25,0.4,2.45605,2.6058,2.6058,1.8229,1.8229,28.9865037,45.56072592222222,41.78883703333333,41.744281477777776,0.0028762 +256,9,4,15,0,TT,5.0,25,0.4,9.8242,2.645,2.645,1.8353000000000002,1.8353000000000002,28.9865037,45.56072592222222,41.78883703333333,41.744281477777776,0.0028762 +256,9,4,15,0,TT,5.0,25,0.4,39.2968,2.7955,2.7955,1.8870000000000002,1.8870000000000002,28.9865037,45.56072592222222,41.78883703333333,41.744281477777776,0.0028762 +64,7,2,10,0,TT,5.0,25,0.0125,2.45605,2.1983,2.1983,1.7582000000000002,1.7582000000000002,21.682222377777777,30.790900155555555,27.305189044444443,27.313044599999998,0.0015427000000000001 +64,7,2,10,0,TT,5.0,25,0.0125,9.8242,2.2420000000000004,2.2420000000000004,1.7702000000000002,1.7702000000000002,21.682222377777777,30.790900155555555,27.305189044444443,27.313044599999998,0.0015427000000000001 +64,7,2,10,0,TT,5.0,25,0.0125,39.2968,2.4085,2.4085,1.8142000000000003,1.8142000000000003,21.682222377777777,30.790900155555555,27.305189044444443,27.313044599999998,0.0015427000000000001 +64,7,2,10,0,TT,5.0,25,0.05,2.45605,2.2049000000000003,2.2049000000000003,1.7591000000000003,1.7591000000000003,21.682222377777777,30.790900155555555,27.305189044444443,27.313044599999998,0.0015427000000000001 +64,7,2,10,0,TT,5.0,25,0.05,9.8242,2.2474,2.2474,1.7708000000000002,1.7708000000000002,21.682222377777777,30.790900155555555,27.305189044444443,27.313044599999998,0.0015427000000000001 +64,7,2,10,0,TT,5.0,25,0.05,39.2968,2.4137,2.4137,1.8146000000000002,1.8146000000000002,21.682222377777777,30.790900155555555,27.305189044444443,27.313044599999998,0.0015427000000000001 +64,7,2,10,0,TT,5.0,25,0.4,2.45605,2.2614,2.2614,1.7573,1.7573,21.682222377777777,30.790900155555555,27.305189044444443,27.313044599999998,0.0015427000000000001 +64,7,2,10,0,TT,5.0,25,0.4,9.8242,2.3054,2.3054,1.7706000000000002,1.7706000000000002,21.682222377777777,30.790900155555555,27.305189044444443,27.313044599999998,0.0015427000000000001 +64,7,2,10,0,TT,5.0,25,0.4,39.2968,2.4719000000000007,2.4719000000000007,1.8149,1.8149,21.682222377777777,30.790900155555555,27.305189044444443,27.313044599999998,0.0015427000000000001 +1024,27,4,89,0,TT,5.0,25,0.0125,2.45605,4.752999999999999,4.752999999999999,1.9692000000000003,1.9692000000000003,76.69049837777779,196.1228317111111,188.3339428222222,188.3339428222222,0.015931999999999998 +1024,27,4,89,0,TT,5.0,25,0.0125,9.8242,4.7867,4.7867,1.9933,1.9933,76.69049837777779,196.1228317111111,188.3339428222222,188.3339428222222,0.015931999999999998 +1024,27,4,89,0,TT,5.0,25,0.0125,39.2968,4.920599999999999,4.920599999999999,2.0772,2.0772,76.69049837777779,196.1228317111111,188.3339428222222,188.3339428222222,0.015931999999999998 +1024,27,4,89,0,TT,5.0,25,0.05,2.45605,4.7577,4.7577,1.9670999999999998,1.9670999999999998,76.69049837777779,196.1228317111111,188.3339428222222,188.3339428222222,0.015931999999999998 +1024,27,4,89,0,TT,5.0,25,0.05,9.8242,4.7917000000000005,4.7917000000000005,1.9921000000000002,1.9921000000000002,76.69049837777779,196.1228317111111,188.3339428222222,188.3339428222222,0.015931999999999998 +1024,27,4,89,0,TT,5.0,25,0.05,39.2968,4.9255,4.9255,2.0772,2.0772,76.69049837777779,196.1228317111111,188.3339428222222,188.3339428222222,0.015931999999999998 +1024,27,4,89,0,TT,5.0,25,0.4,2.45605,4.8088999999999995,4.8088999999999995,1.9714,1.9714,76.69049837777779,196.1228317111111,188.3339428222222,188.3339428222222,0.015931999999999998 +1024,27,4,89,0,TT,5.0,25,0.4,9.8242,4.843299999999999,4.843299999999999,1.9912999999999998,1.9912999999999998,76.69049837777779,196.1228317111111,188.3339428222222,188.3339428222222,0.015931999999999998 +1024,27,4,89,0,TT,5.0,25,0.4,39.2968,4.9778,4.9778,2.0742000000000003,2.0742000000000003,76.69049837777779,196.1228317111111,188.3339428222222,188.3339428222222,0.015931999999999998 +1024,17,16,86,0,TT,5.0,25,0.0125,2.45605,4.6472999999999995,4.6472999999999995,1.7376999999999998,1.7376999999999998,152.15935575555557,397.1815779777778,392.57046686666666,392.4704668666666,0.010389 +1024,17,16,86,0,TT,5.0,25,0.0125,9.8242,4.6929,4.6929,1.7572,1.7572,152.15935575555557,397.1815779777778,392.57046686666666,392.4704668666666,0.010389 +1024,17,16,86,0,TT,5.0,25,0.0125,39.2968,4.8649,4.8649,1.8361999999999998,1.8361999999999998,152.15935575555557,397.1815779777778,392.57046686666666,392.4704668666666,0.010389 +1024,17,16,86,0,TT,5.0,25,0.05,2.45605,4.6525,4.6525,1.7368000000000001,1.7368000000000001,152.15935575555557,397.1815779777778,392.57046686666666,392.4704668666666,0.010389 +1024,17,16,86,0,TT,5.0,25,0.05,9.8242,4.698,4.698,1.7590000000000001,1.7590000000000001,152.15935575555557,397.1815779777778,392.57046686666666,392.4704668666666,0.010389 +1024,17,16,86,0,TT,5.0,25,0.05,39.2968,4.8704,4.8704,1.8384,1.8384,152.15935575555557,397.1815779777778,392.57046686666666,392.4704668666666,0.010389 +1024,17,16,86,0,TT,5.0,25,0.4,2.45605,4.7043,4.7043,1.7322000000000002,1.7322000000000002,152.15935575555557,397.1815779777778,392.57046686666666,392.4704668666666,0.010389 +1024,17,16,86,0,TT,5.0,25,0.4,9.8242,4.7493,4.7493,1.7550000000000001,1.7550000000000001,152.15935575555557,397.1815779777778,392.57046686666666,392.4704668666666,0.010389 +1024,17,16,86,0,TT,5.0,25,0.4,39.2968,4.9242,4.9242,1.8356999999999999,1.8356999999999999,152.15935575555557,397.1815779777778,392.57046686666666,392.4704668666666,0.010389 +64,26,4,23,0,TT,5.0,25,0.0125,2.45605,2.7270000000000003,2.7270000000000003,2.0789999999999997,2.0789999999999997,61.72745915555556,98.68668137777777,88.53012582222223,88.54757026666667,0.0065021 +64,26,4,23,0,TT,5.0,25,0.0125,9.8242,2.7698,2.7698,2.096,2.096,61.72745915555556,98.68668137777777,88.53012582222223,88.54757026666667,0.0065021 +64,26,4,23,0,TT,5.0,25,0.0125,39.2968,2.9347999999999996,2.9347999999999996,2.1588,2.1588,61.72745915555556,98.68668137777777,88.53012582222223,88.54757026666667,0.0065021 +64,26,4,23,0,TT,5.0,25,0.05,2.45605,2.7303,2.7303,2.0805,2.0805,61.72745915555556,98.68668137777777,88.53012582222223,88.54757026666667,0.0065021 +64,26,4,23,0,TT,5.0,25,0.05,9.8242,2.774,2.774,2.0965,2.0965,61.72745915555556,98.68668137777777,88.53012582222223,88.54757026666667,0.0065021 +64,26,4,23,0,TT,5.0,25,0.05,39.2968,2.9384,2.9384,2.1566,2.1566,61.72745915555556,98.68668137777777,88.53012582222223,88.54757026666667,0.0065021 +64,26,4,23,0,TT,5.0,25,0.4,2.45605,2.7782,2.7782,2.0789,2.0789,61.72745915555556,98.68668137777777,88.53012582222223,88.54757026666667,0.0065021 +64,26,4,23,0,TT,5.0,25,0.4,9.8242,2.8251,2.8251,2.0962,2.0962,61.72745915555556,98.68668137777777,88.53012582222223,88.54757026666667,0.0065021 +64,26,4,23,0,TT,5.0,25,0.4,39.2968,2.9871000000000003,2.9871000000000003,2.1631,2.1631,61.72745915555556,98.68668137777777,88.53012582222223,88.54757026666667,0.0065021 +256,8,1,1,0,TT,5.0,25,0.0125,2.45605,2.4123,2.4123,1.9422999999999997,1.9422999999999997,24.43911111111111,38.73888888888889,35.21633333333333,35.224777777777774,0.004372699999999999 +256,8,1,1,0,TT,5.0,25,0.0125,9.8242,2.452,2.452,1.9521,1.9521,24.43911111111111,38.73888888888889,35.21633333333333,35.224777777777774,0.004372699999999999 +256,8,1,1,0,TT,5.0,25,0.0125,39.2968,2.6063,2.6063,1.9916,1.9916,24.43911111111111,38.73888888888889,35.21633333333333,35.224777777777774,0.004372699999999999 +256,8,1,1,0,TT,5.0,25,0.05,2.45605,2.4164,2.4164,1.9434000000000002,1.9434000000000002,24.43911111111111,38.73888888888889,35.21633333333333,35.224777777777774,0.004372699999999999 +256,8,1,1,0,TT,5.0,25,0.05,9.8242,2.4562999999999997,2.4562999999999997,1.9538,1.9538,24.43911111111111,38.73888888888889,35.21633333333333,35.224777777777774,0.004372699999999999 +256,8,1,1,0,TT,5.0,25,0.05,39.2968,2.6101,2.6101,1.9926,1.9926,24.43911111111111,38.73888888888889,35.21633333333333,35.224777777777774,0.004372699999999999 +256,8,1,1,0,TT,5.0,25,0.4,2.45605,2.4678,2.4678,1.9439,1.9439,24.43911111111111,38.73888888888889,35.21633333333333,35.224777777777774,0.004372699999999999 +256,8,1,1,0,TT,5.0,25,0.4,9.8242,2.5065,2.5065,1.9544000000000001,1.9544000000000001,24.43911111111111,38.73888888888889,35.21633333333333,35.224777777777774,0.004372699999999999 +256,8,1,1,0,TT,5.0,25,0.4,39.2968,2.6608,2.6608,1.9925,1.9925,24.43911111111111,38.73888888888889,35.21633333333333,35.224777777777774,0.004372699999999999 +256,12,16,186,0,TT,5.0,25,0.0125,2.45605,6.025,6.025,0.71631,0.71631,114.42272562222222,336.0782811777778,333.9671700666666,334.0227256222222,0.0034601000000000002 +256,12,16,186,0,TT,5.0,25,0.0125,9.8242,6.0472,6.0472,0.74383,0.74383,114.42272562222222,336.0782811777778,333.9671700666666,334.0227256222222,0.0034601000000000002 +256,12,16,186,0,TT,5.0,25,0.0125,39.2968,6.1527,6.1527,0.8786999999999999,0.8786999999999999,114.42272562222222,336.0782811777778,333.9671700666666,334.0227256222222,0.0034601000000000002 +256,12,16,186,0,TT,5.0,25,0.05,2.45605,6.03,6.03,0.7150799999999999,0.7150799999999999,114.42272562222222,336.0782811777778,333.9671700666666,334.0227256222222,0.0034601000000000002 +256,12,16,186,0,TT,5.0,25,0.05,9.8242,6.0529,6.0529,0.74496,0.74496,114.42272562222222,336.0782811777778,333.9671700666666,334.0227256222222,0.0034601000000000002 +256,12,16,186,0,TT,5.0,25,0.05,39.2968,6.157800000000001,6.157800000000001,0.88048,0.88048,114.42272562222222,336.0782811777778,333.9671700666666,334.0227256222222,0.0034601000000000002 +256,12,16,186,0,TT,5.0,25,0.4,2.45605,6.0876,6.0876,0.72339,0.72339,114.42272562222222,336.0782811777778,333.9671700666666,334.0227256222222,0.0034601000000000002 +256,12,16,186,0,TT,5.0,25,0.4,9.8242,6.1095,6.1095,0.7495,0.7495,114.42272562222222,336.0782811777778,333.9671700666666,334.0227256222222,0.0034601000000000002 +256,12,16,186,0,TT,5.0,25,0.4,39.2968,6.2043,6.2043,0.88122,0.88122,114.42272562222222,336.0782811777778,333.9671700666666,334.0227256222222,0.0034601000000000002 +128,9,1,4,0,TT,5.0,25,0.0125,2.45605,2.2338999999999998,2.2338999999999998,1.9514,1.9514,22.3460908,33.13186857777778,29.085090800000003,29.100313022222224,0.0060641 +128,9,1,4,0,TT,5.0,25,0.0125,9.8242,2.2737000000000003,2.2737000000000003,1.9641,1.9641,22.3460908,33.13186857777778,29.085090800000003,29.100313022222224,0.0060641 +128,9,1,4,0,TT,5.0,25,0.0125,39.2968,2.4255,2.4255,2.0007,2.0007,22.3460908,33.13186857777778,29.085090800000003,29.100313022222224,0.0060641 +128,9,1,4,0,TT,5.0,25,0.05,2.45605,2.2380999999999998,2.2380999999999998,1.9512,1.9512,22.3460908,33.13186857777778,29.085090800000003,29.100313022222224,0.0060641 +128,9,1,4,0,TT,5.0,25,0.05,9.8242,2.2779000000000003,2.2779000000000003,1.9618,1.9618,22.3460908,33.13186857777778,29.085090800000003,29.100313022222224,0.0060641 +128,9,1,4,0,TT,5.0,25,0.05,39.2968,2.4292,2.4292,2.0008,2.0008,22.3460908,33.13186857777778,29.085090800000003,29.100313022222224,0.0060641 +128,9,1,4,0,TT,5.0,25,0.4,2.45605,2.2862,2.2862,1.9547999999999999,1.9547999999999999,22.3460908,33.13186857777778,29.085090800000003,29.100313022222224,0.0060641 +128,9,1,4,0,TT,5.0,25,0.4,9.8242,2.3274,2.3274,1.9621000000000002,1.9621000000000002,22.3460908,33.13186857777778,29.085090800000003,29.100313022222224,0.0060641 +128,9,1,4,0,TT,5.0,25,0.4,39.2968,2.4785,2.4785,2.0025,2.0025,22.3460908,33.13186857777778,29.085090800000003,29.100313022222224,0.0060641 +64,4,4,14,0,TT,5.0,25,0.0125,2.45605,2.2023,2.2023,1.6739,1.6739,19.620891355555557,27.9347358,25.812780244444447,25.7768358,0.0010562 +64,4,4,14,0,TT,5.0,25,0.0125,9.8242,2.2446,2.2446,1.6848000000000003,1.6848000000000003,19.620891355555557,27.9347358,25.812780244444447,25.7768358,0.0010562 +64,4,4,14,0,TT,5.0,25,0.0125,39.2968,2.407,2.407,1.7258000000000002,1.7258000000000002,19.620891355555557,27.9347358,25.812780244444447,25.7768358,0.0010562 +64,4,4,14,0,TT,5.0,25,0.05,2.45605,2.207,2.207,1.6747000000000003,1.6747000000000003,19.620891355555557,27.9347358,25.812780244444447,25.7768358,0.0010562 +64,4,4,14,0,TT,5.0,25,0.05,9.8242,2.2498,2.2498,1.6852,1.6852,19.620891355555557,27.9347358,25.812780244444447,25.7768358,0.0010562 +64,4,4,14,0,TT,5.0,25,0.05,39.2968,2.4118000000000004,2.4118000000000004,1.7265,1.7265,19.620891355555557,27.9347358,25.812780244444447,25.7768358,0.0010562 +64,4,4,14,0,TT,5.0,25,0.4,2.45605,2.2657000000000003,2.2657000000000003,1.6753000000000002,1.6753000000000002,19.620891355555557,27.9347358,25.812780244444447,25.7768358,0.0010562 +64,4,4,14,0,TT,5.0,25,0.4,9.8242,2.3089,2.3089,1.6854000000000002,1.6854000000000002,19.620891355555557,27.9347358,25.812780244444447,25.7768358,0.0010562 +64,4,4,14,0,TT,5.0,25,0.4,39.2968,2.4713,2.4713,1.7266,1.7266,19.620891355555557,27.9347358,25.812780244444447,25.7768358,0.0010562 +256,17,16,49,0,TT,5.0,25,0.0125,2.45605,3.7908,3.7908,1.8516000000000001,1.8516000000000001,129.3009468,293.23428013333336,287.9898356888889,287.9120579111111,0.007920700000000001 +256,17,16,49,0,TT,5.0,25,0.0125,9.8242,3.8348,3.8348,1.8718000000000001,1.8718000000000001,129.3009468,293.23428013333336,287.9898356888889,287.9120579111111,0.007920700000000001 +256,17,16,49,0,TT,5.0,25,0.0125,39.2968,3.9999,3.9999,1.9473,1.9473,129.3009468,293.23428013333336,287.9898356888889,287.9120579111111,0.007920700000000001 +256,17,16,49,0,TT,5.0,25,0.05,2.45605,3.7965999999999998,3.7965999999999998,1.8521,1.8521,129.3009468,293.23428013333336,287.9898356888889,287.9120579111111,0.007920700000000001 +256,17,16,49,0,TT,5.0,25,0.05,9.8242,3.8386000000000005,3.8386000000000005,1.8729,1.8729,129.3009468,293.23428013333336,287.9898356888889,287.9120579111111,0.007920700000000001 +256,17,16,49,0,TT,5.0,25,0.05,39.2968,4.0047,4.0047,1.9457,1.9457,129.3009468,293.23428013333336,287.9898356888889,287.9120579111111,0.007920700000000001 +256,17,16,49,0,TT,5.0,25,0.4,2.45605,3.8484999999999996,3.8484999999999996,1.8518,1.8518,129.3009468,293.23428013333336,287.9898356888889,287.9120579111111,0.007920700000000001 +256,17,16,49,0,TT,5.0,25,0.4,9.8242,3.8911000000000002,3.8911000000000002,1.8712,1.8712,129.3009468,293.23428013333336,287.9898356888889,287.9120579111111,0.007920700000000001 +256,17,16,49,0,TT,5.0,25,0.4,39.2968,4.0571,4.0571,1.9502000000000002,1.9502000000000002,129.3009468,293.23428013333336,287.9898356888889,287.9120579111111,0.007920700000000001 +32,18,1,18,0,TT,5.0,25,0.0125,2.45605,2.209,2.209,2.1099000000000006,2.1099000000000006,29.88528546666667,40.721318800000006,33.69027435555556,33.77198546666666,0.0018417000000000002 +32,18,1,18,0,TT,5.0,25,0.0125,9.8242,2.2501,2.2501,2.1211000000000007,2.1211000000000007,29.88528546666667,40.721318800000006,33.69027435555556,33.77198546666666,0.0018417000000000002 +32,18,1,18,0,TT,5.0,25,0.0125,39.2968,2.4038,2.4038,2.1644,2.1644,29.88528546666667,40.721318800000006,33.69027435555556,33.77198546666666,0.0018417000000000002 +32,18,1,18,0,TT,5.0,25,0.05,2.45605,2.2119,2.2119,2.1104000000000003,2.1104000000000003,29.88528546666667,40.721318800000006,33.69027435555556,33.77198546666666,0.0018417000000000002 +32,18,1,18,0,TT,5.0,25,0.05,9.8242,2.2547,2.2547,2.1211000000000007,2.1211000000000007,29.88528546666667,40.721318800000006,33.69027435555556,33.77198546666666,0.0018417000000000002 +32,18,1,18,0,TT,5.0,25,0.05,39.2968,2.4069,2.4069,2.1645000000000003,2.1645000000000003,29.88528546666667,40.721318800000006,33.69027435555556,33.77198546666666,0.0018417000000000002 +32,18,1,18,0,TT,5.0,25,0.4,2.45605,2.2642000000000007,2.2642000000000007,2.1102,2.1102,29.88528546666667,40.721318800000006,33.69027435555556,33.77198546666666,0.0018417000000000002 +32,18,1,18,0,TT,5.0,25,0.4,9.8242,2.3029000000000006,2.3029000000000006,2.1209,2.1209,29.88528546666667,40.721318800000006,33.69027435555556,33.77198546666666,0.0018417000000000002 +32,18,1,18,0,TT,5.0,25,0.4,39.2968,2.4582000000000006,2.4582000000000006,2.1643,2.1643,29.88528546666667,40.721318800000006,33.69027435555556,33.77198546666666,0.0018417000000000002 +512,22,16,249,0,TT,5.0,25,0.0125,2.45605,9.1026,9.1026,0.85974,0.85974,134.65717835555557,448.43495613333334,446.5349561333333,446.53495613333337,0.0034777000000000002 +512,22,16,249,0,TT,5.0,25,0.0125,9.8242,9.1256,9.1256,0.88659,0.88659,134.65717835555557,448.43495613333334,446.5349561333333,446.53495613333337,0.0034777000000000002 +512,22,16,249,0,TT,5.0,25,0.0125,39.2968,9.233600000000001,9.233600000000001,1.0059,1.0059,134.65717835555557,448.43495613333334,446.5349561333333,446.53495613333337,0.0034777000000000002 +512,22,16,249,0,TT,5.0,25,0.05,2.45605,9.105699999999999,9.105699999999999,0.85773,0.85773,134.65717835555557,448.43495613333334,446.5349561333333,446.53495613333337,0.0034777000000000002 +512,22,16,249,0,TT,5.0,25,0.05,9.8242,9.129800000000001,9.129800000000001,0.88561,0.88561,134.65717835555557,448.43495613333334,446.5349561333333,446.53495613333337,0.0034777000000000002 +512,22,16,249,0,TT,5.0,25,0.05,39.2968,9.2429,9.2429,1.0081,1.0081,134.65717835555557,448.43495613333334,446.5349561333333,446.53495613333337,0.0034777000000000002 +512,22,16,249,0,TT,5.0,25,0.4,2.45605,9.1572,9.1572,0.8616900000000001,0.8616900000000001,134.65717835555557,448.43495613333334,446.5349561333333,446.53495613333337,0.0034777000000000002 +512,22,16,249,0,TT,5.0,25,0.4,9.8242,9.174,9.174,0.88166,0.88166,134.65717835555557,448.43495613333334,446.5349561333333,446.53495613333337,0.0034777000000000002 +512,22,16,249,0,TT,5.0,25,0.4,39.2968,9.291599999999999,9.291599999999999,1.0115999999999998,1.0115999999999998,134.65717835555557,448.43495613333334,446.5349561333333,446.53495613333337,0.0034777000000000002 +512,15,8,85,0,TT,5.0,25,0.0125,2.45605,4.6874,4.6874,1.2886000000000002,1.2886000000000002,84.94418406666668,232.0217396222222,227.26618406666665,227.2884062888889,0.0048161 +512,15,8,85,0,TT,5.0,25,0.0125,9.8242,4.7363,4.7363,1.3074000000000001,1.3074000000000001,84.94418406666668,232.0217396222222,227.26618406666665,227.2884062888889,0.0048161 +512,15,8,85,0,TT,5.0,25,0.0125,39.2968,4.9209000000000005,4.9209000000000005,1.3851,1.3851,84.94418406666668,232.0217396222222,227.26618406666665,227.2884062888889,0.0048161 +512,15,8,85,0,TT,5.0,25,0.05,2.45605,4.6914,4.6914,1.2906,1.2906,84.94418406666668,232.0217396222222,227.26618406666665,227.2884062888889,0.0048161 +512,15,8,85,0,TT,5.0,25,0.05,9.8242,4.7406,4.7406,1.3103,1.3103,84.94418406666668,232.0217396222222,227.26618406666665,227.2884062888889,0.0048161 +512,15,8,85,0,TT,5.0,25,0.05,39.2968,4.9269,4.9269,1.3835,1.3835,84.94418406666668,232.0217396222222,227.26618406666665,227.2884062888889,0.0048161 +512,15,8,85,0,TT,5.0,25,0.4,2.45605,4.7431,4.7431,1.2966,1.2966,84.94418406666668,232.0217396222222,227.26618406666665,227.2884062888889,0.0048161 +512,15,8,85,0,TT,5.0,25,0.4,9.8242,4.7923,4.7923,1.3116,1.3116,84.94418406666668,232.0217396222222,227.26618406666665,227.2884062888889,0.0048161 +512,15,8,85,0,TT,5.0,25,0.4,39.2968,4.978,4.978,1.3878,1.3878,84.94418406666668,232.0217396222222,227.26618406666665,227.2884062888889,0.0048161 +512,27,4,60,0,TT,5.0,25,0.0125,2.45605,4.4687,4.4687,1.9662000000000002,1.9662000000000002,78.17984213333332,195.6196199111111,187.54184213333332,187.48628657777778,0.012265 +512,27,4,60,0,TT,5.0,25,0.0125,9.8242,4.5089,4.5089,1.9830999999999999,1.9830999999999999,78.17984213333332,195.6196199111111,187.54184213333332,187.48628657777778,0.012265 +512,27,4,60,0,TT,5.0,25,0.0125,39.2968,4.6682999999999995,4.6682999999999995,2.0622999999999996,2.0622999999999996,78.17984213333332,195.6196199111111,187.54184213333332,187.48628657777778,0.012265 +512,27,4,60,0,TT,5.0,25,0.05,2.45605,4.473199999999999,4.473199999999999,1.9638000000000002,1.9638000000000002,78.17984213333332,195.6196199111111,187.54184213333332,187.48628657777778,0.012265 +512,27,4,60,0,TT,5.0,25,0.05,9.8242,4.511500000000001,4.511500000000001,1.9837,1.9837,78.17984213333332,195.6196199111111,187.54184213333332,187.48628657777778,0.012265 +512,27,4,60,0,TT,5.0,25,0.05,39.2968,4.673,4.673,2.0700000000000003,2.0700000000000003,78.17984213333332,195.6196199111111,187.54184213333332,187.48628657777778,0.012265 +512,27,4,60,0,TT,5.0,25,0.4,2.45605,4.5252,4.5252,1.9637000000000002,1.9637000000000002,78.17984213333332,195.6196199111111,187.54184213333332,187.48628657777778,0.012265 +512,27,4,60,0,TT,5.0,25,0.4,9.8242,4.5657,4.5657,1.9853,1.9853,78.17984213333332,195.6196199111111,187.54184213333332,187.48628657777778,0.012265 +512,27,4,60,0,TT,5.0,25,0.4,39.2968,4.7243,4.7243,2.0608,2.0608,78.17984213333332,195.6196199111111,187.54184213333332,187.48628657777778,0.012265 +16,12,1,1,0,TT,5.0,25,0.0125,2.45605,2.0042,2.0042,1.8484,1.8484,23.98822222222222,33.28411111111111,28.561777777777777,28.602333333333334,0.00094617 +16,12,1,1,0,TT,5.0,25,0.0125,9.8242,2.0433000000000003,2.0433000000000003,1.8601,1.8601,23.98822222222222,33.28411111111111,28.561777777777777,28.602333333333334,0.00094617 +16,12,1,1,0,TT,5.0,25,0.0125,39.2968,2.1924,2.1924,1.9045999999999998,1.9045999999999998,23.98822222222222,33.28411111111111,28.561777777777777,28.602333333333334,0.00094617 +16,12,1,1,0,TT,5.0,25,0.05,2.45605,2.0089,2.0089,1.8493,1.8493,23.98822222222222,33.28411111111111,28.561777777777777,28.602333333333334,0.00094617 +16,12,1,1,0,TT,5.0,25,0.05,9.8242,2.0471,2.0471,1.8615,1.8615,23.98822222222222,33.28411111111111,28.561777777777777,28.602333333333334,0.00094617 +16,12,1,1,0,TT,5.0,25,0.05,39.2968,2.1961,2.1961,1.9041000000000001,1.9041000000000001,23.98822222222222,33.28411111111111,28.561777777777777,28.602333333333334,0.00094617 +16,12,1,1,0,TT,5.0,25,0.4,2.45605,2.0563000000000002,2.0563000000000002,1.8477,1.8477,23.98822222222222,33.28411111111111,28.561777777777777,28.602333333333334,0.00094617 +16,12,1,1,0,TT,5.0,25,0.4,9.8242,2.0966,2.0966,1.86,1.86,23.98822222222222,33.28411111111111,28.561777777777777,28.602333333333334,0.00094617 +16,12,1,1,0,TT,5.0,25,0.4,39.2968,2.2477,2.2477,1.9063999999999999,1.9063999999999999,23.98822222222222,33.28411111111111,28.561777777777777,28.602333333333334,0.00094617 +256,27,8,191,0,TT,5.0,25,0.0125,2.45605,6.3106,6.3106,0.71324,0.71324,149.500669,446.5340023333333,438.3673356666667,438.1895578888888,0.0089528 +256,27,8,191,0,TT,5.0,25,0.0125,9.8242,6.3352,6.3352,0.7453,0.7453,149.500669,446.5340023333333,438.3673356666667,438.1895578888888,0.0089528 +256,27,8,191,0,TT,5.0,25,0.0125,39.2968,6.4193,6.4193,0.87204,0.87204,149.500669,446.5340023333333,438.3673356666667,438.1895578888888,0.0089528 +256,27,8,191,0,TT,5.0,25,0.05,2.45605,6.3072,6.3072,0.70922,0.70922,149.500669,446.5340023333333,438.3673356666667,438.1895578888888,0.0089528 +256,27,8,191,0,TT,5.0,25,0.05,9.8242,6.3389,6.3389,0.74499,0.74499,149.500669,446.5340023333333,438.3673356666667,438.1895578888888,0.0089528 +256,27,8,191,0,TT,5.0,25,0.05,39.2968,6.424,6.424,0.87564,0.87564,149.500669,446.5340023333333,438.3673356666667,438.1895578888888,0.0089528 +256,27,8,191,0,TT,5.0,25,0.4,2.45605,6.3716,6.3716,0.7237300000000001,0.7237300000000001,149.500669,446.5340023333333,438.3673356666667,438.1895578888888,0.0089528 +256,27,8,191,0,TT,5.0,25,0.4,9.8242,6.4003,6.4003,0.75818,0.75818,149.500669,446.5340023333333,438.3673356666667,438.1895578888888,0.0089528 +256,27,8,191,0,TT,5.0,25,0.4,39.2968,6.4839,6.4839,0.88076,0.88076,149.500669,446.5340023333333,438.3673356666667,438.1895578888888,0.0089528 +1024,64,4,0,0,TT,5.0,25,0.0125,2.45605,3.9389999999999996,3.9389999999999996,2.8754999999999997,2.8754999999999997,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.0125,9.8242,3.9711999999999996,3.9711999999999996,2.9102,2.9102,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.0125,39.2968,4.1078,4.1078,3.0068,3.0068,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.05,2.45605,3.9441999999999995,3.9441999999999995,2.877,2.877,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.05,9.8242,3.9760999999999997,3.9760999999999997,2.9089,2.9089,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.05,39.2968,4.1107,4.1107,2.9932,2.9932,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.4,2.45605,3.9938999999999996,3.9938999999999996,2.8765,2.8765,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.4,9.8242,4.0249999999999995,4.0249999999999995,2.9085,2.9085,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.4,39.2968,4.1619,4.1619,3.0039,3.0039,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +512,64,4,0,0,TT,5.0,25,0.0125,2.45605,3.6412999999999998,3.6412999999999998,2.9203,2.9203,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.0125,9.8242,3.6843000000000004,3.6843000000000004,2.9427999999999996,2.9427999999999996,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.0125,39.2968,3.8491,3.8491,3.0345999999999997,3.0345999999999997,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.05,2.45605,3.6469,3.6469,2.919,2.919,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.05,9.8242,3.6885999999999997,3.6885999999999997,2.9484,2.9484,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.05,39.2968,3.8536999999999995,3.8536999999999995,3.0319,3.0319,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.4,2.45605,3.6950000000000003,3.6950000000000003,2.9087,2.9087,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.4,9.8242,3.7396,3.7396,2.9424,2.9424,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.4,39.2968,3.9026,3.9026,3.0359,3.0359,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +256,5,16,75,0,TT,5.0,25,0.0125,2.45605,4.1845,4.1845,1.3765,1.3765,51.840046777777786,129.62249122222224,127.55582455555557,127.56693566666667,0.0025569 +256,5,16,75,0,TT,5.0,25,0.0125,9.8242,4.2315,4.2315,1.3939,1.3939,51.840046777777786,129.62249122222224,127.55582455555557,127.56693566666667,0.0025569 +256,5,16,75,0,TT,5.0,25,0.0125,39.2968,4.4106,4.4106,1.4662,1.4662,51.840046777777786,129.62249122222224,127.55582455555557,127.56693566666667,0.0025569 +256,5,16,75,0,TT,5.0,25,0.05,2.45605,4.1879,4.1879,1.3772,1.3772,51.840046777777786,129.62249122222224,127.55582455555557,127.56693566666667,0.0025569 +256,5,16,75,0,TT,5.0,25,0.05,9.8242,4.235,4.235,1.3949,1.3949,51.840046777777786,129.62249122222224,127.55582455555557,127.56693566666667,0.0025569 +256,5,16,75,0,TT,5.0,25,0.05,39.2968,4.414,4.414,1.4664,1.4664,51.840046777777786,129.62249122222224,127.55582455555557,127.56693566666667,0.0025569 +256,5,16,75,0,TT,5.0,25,0.4,2.45605,4.239299999999999,4.239299999999999,1.3811,1.3811,51.840046777777786,129.62249122222224,127.55582455555557,127.56693566666667,0.0025569 +256,5,16,75,0,TT,5.0,25,0.4,9.8242,4.2888,4.2888,1.3971,1.3971,51.840046777777786,129.62249122222224,127.55582455555557,127.56693566666667,0.0025569 +256,5,16,75,0,TT,5.0,25,0.4,39.2968,4.4662999999999995,4.4662999999999995,1.4678,1.4678,51.840046777777786,129.62249122222224,127.55582455555557,127.56693566666667,0.0025569 +32,4,2,5,0,TT,5.0,25,0.0125,2.45605,1.9796,1.9796,1.6975000000000002,1.6975000000000002,17.335467220422224,23.716600553755555,21.373600553755555,21.366367220422223,0.0010005999999999997 +32,4,2,5,0,TT,5.0,25,0.0125,9.8242,2.0223,2.0223,1.7083,1.7083,17.335467220422224,23.716600553755555,21.373600553755555,21.366367220422223,0.0010005999999999997 +32,4,2,5,0,TT,5.0,25,0.0125,39.2968,2.1876,2.1876,1.7504000000000002,1.7504000000000002,17.335467220422224,23.716600553755555,21.373600553755555,21.366367220422223,0.0010005999999999997 +32,4,2,5,0,TT,5.0,25,0.05,2.45605,1.9840000000000002,1.9840000000000002,1.6970000000000003,1.6970000000000003,17.335467220422224,23.716600553755555,21.373600553755555,21.366367220422223,0.0010005999999999997 +32,4,2,5,0,TT,5.0,25,0.05,9.8242,2.0275,2.0275,1.7091000000000003,1.7091000000000003,17.335467220422224,23.716600553755555,21.373600553755555,21.366367220422223,0.0010005999999999997 +32,4,2,5,0,TT,5.0,25,0.05,39.2968,2.1934000000000005,2.1934000000000005,1.7500000000000002,1.7500000000000002,17.335467220422224,23.716600553755555,21.373600553755555,21.366367220422223,0.0010005999999999997 +32,4,2,5,0,TT,5.0,25,0.4,2.45605,2.041,2.041,1.6989000000000003,1.6989000000000003,17.335467220422224,23.716600553755555,21.373600553755555,21.366367220422223,0.0010005999999999997 +32,4,2,5,0,TT,5.0,25,0.4,9.8242,2.0844,2.0844,1.7089,1.7089,17.335467220422224,23.716600553755555,21.373600553755555,21.366367220422223,0.0010005999999999997 +32,4,2,5,0,TT,5.0,25,0.4,39.2968,2.2503,2.2503,1.7506000000000002,1.7506000000000002,17.335467220422224,23.716600553755555,21.373600553755555,21.366367220422223,0.0010005999999999997 +1024,32,8,0,0,TT,5.0,25,0.0125,2.45605,3.8730520000000004,3.8730520000000004,2.43798,2.43798,72.02970836222222,135.6051450288889,127.26716725111113,126.08171169555557,0.043460429999999994 +1024,32,8,0,0,TT,5.0,25,0.0125,9.8242,3.916978,3.916978,2.45722,2.45722,72.02970836222222,135.6051450288889,127.26716725111113,126.08171169555557,0.043460429999999994 +1024,32,8,0,0,TT,5.0,25,0.0125,39.2968,4.086529,4.086529,2.5252760000000003,2.5252760000000003,72.02970836222222,135.6051450288889,127.26716725111113,126.08171169555557,0.043460429999999994 +1024,32,8,0,0,TT,5.0,25,0.05,2.45605,3.8767210000000003,3.8767210000000003,2.437937,2.437937,72.02970836222222,135.6051450288889,127.26716725111113,126.08171169555557,0.043460429999999994 +1024,32,8,0,0,TT,5.0,25,0.05,9.8242,3.9206489999999996,3.9206489999999996,2.4572000000000003,2.4572000000000003,72.02970836222222,135.6051450288889,127.26716725111113,126.08171169555557,0.043460429999999994 +1024,32,8,0,0,TT,5.0,25,0.05,39.2968,4.090199,4.090199,2.525238,2.525238,72.02970836222222,135.6051450288889,127.26716725111113,126.08171169555557,0.043460429999999994 +1024,32,8,0,0,TT,5.0,25,0.4,2.45605,3.930139,3.930139,2.438209,2.438209,72.02970836222222,135.6051450288889,127.26716725111113,126.08171169555557,0.043460429999999994 +1024,32,8,0,0,TT,5.0,25,0.4,9.8242,3.9740740000000003,3.9740740000000003,2.457417,2.457417,72.02970836222222,135.6051450288889,127.26716725111113,126.08171169555557,0.043460429999999994 +1024,32,8,0,0,TT,5.0,25,0.4,39.2968,4.1436079999999995,4.1436079999999995,2.525525,2.525525,72.02970836222222,135.6051450288889,127.26716725111113,126.08171169555557,0.043460429999999994 +1024,16,16,40,0,TT,5.0,25,0.0125,2.45605,3.6791,3.6791,1.8413,1.8413,109.98269777777779,245.0382533333333,239.98269777777776,239.97158666666667,0.013148 +1024,16,16,40,0,TT,5.0,25,0.0125,9.8242,3.7229,3.7229,1.8624999999999998,1.8624999999999998,109.98269777777779,245.0382533333333,239.98269777777776,239.97158666666667,0.013148 +1024,16,16,40,0,TT,5.0,25,0.0125,39.2968,3.8823999999999996,3.8823999999999996,1.9379000000000002,1.9379000000000002,109.98269777777779,245.0382533333333,239.98269777777776,239.97158666666667,0.013148 +1024,16,16,40,0,TT,5.0,25,0.05,2.45605,3.6825,3.6825,1.8407,1.8407,109.98269777777779,245.0382533333333,239.98269777777776,239.97158666666667,0.013148 +1024,16,16,40,0,TT,5.0,25,0.05,9.8242,3.7251,3.7251,1.8607,1.8607,109.98269777777779,245.0382533333333,239.98269777777776,239.97158666666667,0.013148 +1024,16,16,40,0,TT,5.0,25,0.05,39.2968,3.8879,3.8879,1.9375,1.9375,109.98269777777779,245.0382533333333,239.98269777777776,239.97158666666667,0.013148 +1024,16,16,40,0,TT,5.0,25,0.4,2.45605,3.7347,3.7347,1.8417999999999999,1.8417999999999999,109.98269777777779,245.0382533333333,239.98269777777776,239.97158666666667,0.013148 +1024,16,16,40,0,TT,5.0,25,0.4,9.8242,3.7769999999999997,3.7769999999999997,1.8598,1.8598,109.98269777777779,245.0382533333333,239.98269777777776,239.97158666666667,0.013148 +1024,16,16,40,0,TT,5.0,25,0.4,39.2968,3.9406999999999996,3.9406999999999996,1.9379000000000002,1.9379000000000002,109.98269777777779,245.0382533333333,239.98269777777776,239.97158666666667,0.013148 +32,32,1,31,0,TT,5.0,25,0.0125,2.45605,2.5207,2.5207,2.4005,2.4005,44.109890444444446,63.85544599999999,52.51689044444444,52.668445999999996,0.0019519 +32,32,1,31,0,TT,5.0,25,0.0125,9.8242,2.5648,2.5648,2.4122,2.4122,44.109890444444446,63.85544599999999,52.51689044444444,52.668445999999996,0.0019519 +32,32,1,31,0,TT,5.0,25,0.0125,39.2968,2.7257,2.7257,2.4602999999999997,2.4602999999999997,44.109890444444446,63.85544599999999,52.51689044444444,52.668445999999996,0.0019519 +32,32,1,31,0,TT,5.0,25,0.05,2.45605,2.5245,2.5245,2.4004000000000003,2.4004000000000003,44.109890444444446,63.85544599999999,52.51689044444444,52.668445999999996,0.0019519 +32,32,1,31,0,TT,5.0,25,0.05,9.8242,2.5679999999999996,2.5679999999999996,2.4128999999999996,2.4128999999999996,44.109890444444446,63.85544599999999,52.51689044444444,52.668445999999996,0.0019519 +32,32,1,31,0,TT,5.0,25,0.05,39.2968,2.7292,2.7292,2.4623,2.4623,44.109890444444446,63.85544599999999,52.51689044444444,52.668445999999996,0.0019519 +32,32,1,31,0,TT,5.0,25,0.4,2.45605,2.5745,2.5745,2.4031000000000002,2.4031000000000002,44.109890444444446,63.85544599999999,52.51689044444444,52.668445999999996,0.0019519 +32,32,1,31,0,TT,5.0,25,0.4,9.8242,2.6187,2.6187,2.4128000000000003,2.4128000000000003,44.109890444444446,63.85544599999999,52.51689044444444,52.668445999999996,0.0019519 +32,32,1,31,0,TT,5.0,25,0.4,39.2968,2.7769999999999997,2.7769999999999997,2.4624,2.4624,44.109890444444446,63.85544599999999,52.51689044444444,52.668445999999996,0.0019519 +256,12,8,17,0,TT,5.0,25,0.0125,2.45605,2.7676,2.7676,1.7774999999999999,1.7774999999999999,47.93060078888888,77.37504523333331,72.66315634444445,72.60826745555556,0.0036631000000000003 +256,12,8,17,0,TT,5.0,25,0.0125,9.8242,2.8077,2.8077,1.7962,1.7962,47.93060078888888,77.37504523333331,72.66315634444445,72.60826745555556,0.0036631000000000003 +256,12,8,17,0,TT,5.0,25,0.0125,39.2968,2.9633,2.9633,1.8543,1.8543,47.93060078888888,77.37504523333331,72.66315634444445,72.60826745555556,0.0036631000000000003 +256,12,8,17,0,TT,5.0,25,0.05,2.45605,2.7717,2.7717,1.7771,1.7771,47.93060078888888,77.37504523333331,72.66315634444445,72.60826745555556,0.0036631000000000003 +256,12,8,17,0,TT,5.0,25,0.05,9.8242,2.8114,2.8114,1.7935,1.7935,47.93060078888888,77.37504523333331,72.66315634444445,72.60826745555556,0.0036631000000000003 +256,12,8,17,0,TT,5.0,25,0.05,39.2968,2.9674,2.9674,1.8547,1.8547,47.93060078888888,77.37504523333331,72.66315634444445,72.60826745555556,0.0036631000000000003 +256,12,8,17,0,TT,5.0,25,0.4,2.45605,2.8236,2.8236,1.7793,1.7793,47.93060078888888,77.37504523333331,72.66315634444445,72.60826745555556,0.0036631000000000003 +256,12,8,17,0,TT,5.0,25,0.4,9.8242,2.8652,2.8652,1.7949000000000002,1.7949000000000002,47.93060078888888,77.37504523333331,72.66315634444445,72.60826745555556,0.0036631000000000003 +256,12,8,17,0,TT,5.0,25,0.4,39.2968,3.0201,3.0201,1.8546,1.8546,47.93060078888888,77.37504523333331,72.66315634444445,72.60826745555556,0.0036631000000000003 +1024,21,4,54,0,TT,5.0,25,0.0125,2.45605,4.2813,4.2813,1.9376,1.9376,60.464658477777775,148.56643625555557,142.1108807,142.09976958888888,0.014947 +1024,21,4,54,0,TT,5.0,25,0.0125,9.8242,4.315099999999999,4.315099999999999,1.9670999999999998,1.9670999999999998,60.464658477777775,148.56643625555557,142.1108807,142.09976958888888,0.014947 +1024,21,4,54,0,TT,5.0,25,0.0125,39.2968,4.452,4.452,2.0305,2.0305,60.464658477777775,148.56643625555557,142.1108807,142.09976958888888,0.014947 +1024,21,4,54,0,TT,5.0,25,0.05,2.45605,4.2855,4.2855,1.9365,1.9365,60.464658477777775,148.56643625555557,142.1108807,142.09976958888888,0.014947 +1024,21,4,54,0,TT,5.0,25,0.05,9.8242,4.32,4.32,1.9608,1.9608,60.464658477777775,148.56643625555557,142.1108807,142.09976958888888,0.014947 +1024,21,4,54,0,TT,5.0,25,0.05,39.2968,4.455,4.455,2.0303,2.0303,60.464658477777775,148.56643625555557,142.1108807,142.09976958888888,0.014947 +1024,21,4,54,0,TT,5.0,25,0.4,2.45605,4.3357,4.3357,1.9341999999999997,1.9341999999999997,60.464658477777775,148.56643625555557,142.1108807,142.09976958888888,0.014947 +1024,21,4,54,0,TT,5.0,25,0.4,9.8242,4.3711,4.3711,1.9544000000000001,1.9544000000000001,60.464658477777775,148.56643625555557,142.1108807,142.09976958888888,0.014947 +1024,21,4,54,0,TT,5.0,25,0.4,39.2968,4.5081,4.5081,2.0328,2.0328,60.464658477777775,148.56643625555557,142.1108807,142.09976958888888,0.014947 +64,10,4,21,0,TT,5.0,25,0.0125,2.45605,2.7878,2.7878,1.8436,1.8436,32.458114055555555,57.41644738888889,53.57099183333334,53.47993627777778,0.0014953999999999998 +64,10,4,21,0,TT,5.0,25,0.0125,9.8242,2.8291,2.8291,1.8564,1.8564,32.458114055555555,57.41644738888889,53.57099183333334,53.47993627777778,0.0014953999999999998 +64,10,4,21,0,TT,5.0,25,0.0125,39.2968,2.986,2.986,1.9082000000000001,1.9082000000000001,32.458114055555555,57.41644738888889,53.57099183333334,53.47993627777778,0.0014953999999999998 +64,10,4,21,0,TT,5.0,25,0.05,2.45605,2.7923000000000004,2.7923000000000004,1.8427,1.8427,32.458114055555555,57.41644738888889,53.57099183333334,53.47993627777778,0.0014953999999999998 +64,10,4,21,0,TT,5.0,25,0.05,9.8242,2.8345000000000002,2.8345000000000002,1.8558,1.8558,32.458114055555555,57.41644738888889,53.57099183333334,53.47993627777778,0.0014953999999999998 +64,10,4,21,0,TT,5.0,25,0.05,39.2968,2.9912,2.9912,1.9081000000000001,1.9081000000000001,32.458114055555555,57.41644738888889,53.57099183333334,53.47993627777778,0.0014953999999999998 +64,10,4,21,0,TT,5.0,25,0.4,2.45605,2.8435000000000006,2.8435000000000006,1.8387,1.8387,32.458114055555555,57.41644738888889,53.57099183333334,53.47993627777778,0.0014953999999999998 +64,10,4,21,0,TT,5.0,25,0.4,9.8242,2.8846000000000003,2.8846000000000003,1.8521000000000003,1.8521000000000003,32.458114055555555,57.41644738888889,53.57099183333334,53.47993627777778,0.0014953999999999998 +64,10,4,21,0,TT,5.0,25,0.4,39.2968,3.0418,3.0418,1.9047000000000003,1.9047000000000003,32.458114055555555,57.41644738888889,53.57099183333334,53.47993627777778,0.0014953999999999998 +1024,128,4,0,0,TT,5.0,25,0.0125,2.45605,5.2075,5.2075,4.051799999999999,4.051799999999999,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.0125,9.8242,5.2404,5.2404,4.0874,4.0874,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.0125,39.2968,5.3863,5.3863,4.2315,4.2315,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.05,2.45605,5.2121,5.2121,4.0489,4.0489,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.05,9.8242,5.2452,5.2452,4.093699999999999,4.093699999999999,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.05,39.2968,5.3919,5.3919,4.225300000000001,4.225300000000001,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.4,2.45605,5.2619,5.2619,4.0632,4.0632,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.4,9.8242,5.2953,5.2953,4.1129,4.1129,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.4,39.2968,5.441,5.441,4.2496,4.2496,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +16,6,1,1,0,TT,5.0,25,0.0125,2.45605,1.8236,1.8236,1.7121000000000002,1.7121000000000002,18.285366666666665,24.638744444444445,21.480811111111116,21.497922222222222,0.0007500222000000001 +16,6,1,1,0,TT,5.0,25,0.0125,9.8242,1.8633,1.8633,1.7214,1.7214,18.285366666666665,24.638744444444445,21.480811111111116,21.497922222222222,0.0007500222000000001 +16,6,1,1,0,TT,5.0,25,0.0125,39.2968,2.0134000000000003,2.0134000000000003,1.7596000000000003,1.7596000000000003,18.285366666666665,24.638744444444445,21.480811111111116,21.497922222222222,0.0007500222000000001 +16,6,1,1,0,TT,5.0,25,0.05,2.45605,1.8286,1.8286,1.7109,1.7109,18.285366666666665,24.638744444444445,21.480811111111116,21.497922222222222,0.0007500222000000001 +16,6,1,1,0,TT,5.0,25,0.05,9.8242,1.868,1.868,1.7208000000000003,1.7208000000000003,18.285366666666665,24.638744444444445,21.480811111111116,21.497922222222222,0.0007500222000000001 +16,6,1,1,0,TT,5.0,25,0.05,39.2968,2.0181000000000004,2.0181000000000004,1.7592000000000003,1.7592000000000003,18.285366666666665,24.638744444444445,21.480811111111116,21.497922222222222,0.0007500222000000001 +16,6,1,1,0,TT,5.0,25,0.4,2.45605,1.8833,1.8833,1.7105000000000001,1.7105000000000001,18.285366666666665,24.638744444444445,21.480811111111116,21.497922222222222,0.0007500222000000001 +16,6,1,1,0,TT,5.0,25,0.4,9.8242,1.9225000000000003,1.9225000000000003,1.7205,1.7205,18.285366666666665,24.638744444444445,21.480811111111116,21.497922222222222,0.0007500222000000001 +16,6,1,1,0,TT,5.0,25,0.4,39.2968,2.0725000000000002,2.0725000000000002,1.7584,1.7584,18.285366666666665,24.638744444444445,21.480811111111116,21.497922222222222,0.0007500222000000001 +256,7,4,25,0,TT,5.0,25,0.0125,2.45605,2.6953,2.6953,1.7642,1.7642,25.913082833333338,43.82208283333333,40.87163838888889,40.824971722222216,0.0022841 +256,7,4,25,0,TT,5.0,25,0.0125,9.8242,2.7351,2.7351,1.7759,1.7759,25.913082833333338,43.82208283333333,40.87163838888889,40.824971722222216,0.0022841 +256,7,4,25,0,TT,5.0,25,0.0125,39.2968,2.8953,2.8953,1.8226,1.8226,25.913082833333338,43.82208283333333,40.87163838888889,40.824971722222216,0.0022841 +256,7,4,25,0,TT,5.0,25,0.05,2.45605,2.6982,2.6982,1.7644,1.7644,25.913082833333338,43.82208283333333,40.87163838888889,40.824971722222216,0.0022841 +256,7,4,25,0,TT,5.0,25,0.05,9.8242,2.7396,2.7396,1.777,1.777,25.913082833333338,43.82208283333333,40.87163838888889,40.824971722222216,0.0022841 +256,7,4,25,0,TT,5.0,25,0.05,39.2968,2.8996000000000004,2.8996000000000004,1.8234,1.8234,25.913082833333338,43.82208283333333,40.87163838888889,40.824971722222216,0.0022841 +256,7,4,25,0,TT,5.0,25,0.4,2.45605,2.7504,2.7504,1.7642,1.7642,25.913082833333338,43.82208283333333,40.87163838888889,40.824971722222216,0.0022841 +256,7,4,25,0,TT,5.0,25,0.4,9.8242,2.791,2.791,1.7762,1.7762,25.913082833333338,43.82208283333333,40.87163838888889,40.824971722222216,0.0022841 +256,7,4,25,0,TT,5.0,25,0.4,39.2968,2.9499,2.9499,1.8280999999999998,1.8280999999999998,25.913082833333338,43.82208283333333,40.87163838888889,40.824971722222216,0.0022841 +512,8,8,0,0,TT,5.0,25,0.0125,2.45605,2.642827,2.642827,2.0061489999999997,2.0061489999999997,28.867441217000003,40.82671455033332,37.591421217,37.12537455033333,0.006893357 +512,8,8,0,0,TT,5.0,25,0.0125,9.8242,2.684537,2.684537,2.018579,2.018579,28.867441217000003,40.82671455033332,37.591421217,37.12537455033333,0.006893357 +512,8,8,0,0,TT,5.0,25,0.0125,39.2968,2.846583,2.846583,2.068286,2.068286,28.867441217000003,40.82671455033332,37.591421217,37.12537455033333,0.006893357 +512,8,8,0,0,TT,5.0,25,0.05,2.45605,2.64698,2.64698,2.006086,2.006086,28.867441217000003,40.82671455033332,37.591421217,37.12537455033333,0.006893357 +512,8,8,0,0,TT,5.0,25,0.05,9.8242,2.6886900000000002,2.6886900000000002,2.018453,2.018453,28.867441217000003,40.82671455033332,37.591421217,37.12537455033333,0.006893357 +512,8,8,0,0,TT,5.0,25,0.05,39.2968,2.85074,2.85074,2.06824,2.06824,28.867441217000003,40.82671455033332,37.591421217,37.12537455033333,0.006893357 +512,8,8,0,0,TT,5.0,25,0.4,2.45605,2.699419,2.699419,2.006116,2.006116,28.867441217000003,40.82671455033332,37.591421217,37.12537455033333,0.006893357 +512,8,8,0,0,TT,5.0,25,0.4,9.8242,2.74113,2.74113,2.018647,2.018647,28.867441217000003,40.82671455033332,37.591421217,37.12537455033333,0.006893357 +512,8,8,0,0,TT,5.0,25,0.4,39.2968,2.9031849999999997,2.9031849999999997,2.06833,2.06833,28.867441217000003,40.82671455033332,37.591421217,37.12537455033333,0.006893357 +256,32,4,0,0,TT,5.0,25,0.0125,2.45605,2.8734,2.8734,2.493693,2.493693,45.32144644211111,58.1135264421111,50.190636442111106,49.33116755322223,0.01655847 +256,32,4,0,0,TT,5.0,25,0.0125,9.8242,2.917456,2.917456,2.5114490000000003,2.5114490000000003,45.32144644211111,58.1135264421111,50.190636442111106,49.33116755322223,0.01655847 +256,32,4,0,0,TT,5.0,25,0.0125,39.2968,3.086642,3.086642,2.573498,2.573498,45.32144644211111,58.1135264421111,50.190636442111106,49.33116755322223,0.01655847 +256,32,4,0,0,TT,5.0,25,0.05,2.45605,2.8768920000000002,2.8768920000000002,2.493699,2.493699,45.32144644211111,58.1135264421111,50.190636442111106,49.33116755322223,0.01655847 +256,32,4,0,0,TT,5.0,25,0.05,9.8242,2.920957,2.920957,2.5114569999999996,2.5114569999999996,45.32144644211111,58.1135264421111,50.190636442111106,49.33116755322223,0.01655847 +256,32,4,0,0,TT,5.0,25,0.05,39.2968,3.090142,3.090142,2.5735140000000003,2.5735140000000003,45.32144644211111,58.1135264421111,50.190636442111106,49.33116755322223,0.01655847 +256,32,4,0,0,TT,5.0,25,0.4,2.45605,2.930365,2.930365,2.493711,2.493711,45.32144644211111,58.1135264421111,50.190636442111106,49.33116755322223,0.01655847 +256,32,4,0,0,TT,5.0,25,0.4,9.8242,2.974399,2.974399,2.51145,2.51145,45.32144644211111,58.1135264421111,50.190636442111106,49.33116755322223,0.01655847 +256,32,4,0,0,TT,5.0,25,0.4,39.2968,3.143585,3.143585,2.573481,2.573481,45.32144644211111,58.1135264421111,50.190636442111106,49.33116755322223,0.01655847 +1024,8,16,0,0,TT,5.0,25,0.0125,2.45605,3.27198,3.27198,1.914543,1.914543,40.31096571155555,62.794343489333336,59.662805711555556,59.200690156,0.00871889 +1024,8,16,0,0,TT,5.0,25,0.0125,9.8242,3.315868,3.315868,1.9286310000000002,1.9286310000000002,40.31096571155555,62.794343489333336,59.662805711555556,59.200690156,0.00871889 +1024,8,16,0,0,TT,5.0,25,0.0125,39.2968,3.486812,3.486812,1.986824,1.986824,40.31096571155555,62.794343489333336,59.662805711555556,59.200690156,0.00871889 +1024,8,16,0,0,TT,5.0,25,0.05,2.45605,3.275609,3.275609,1.914646,1.914646,40.31096571155555,62.794343489333336,59.662805711555556,59.200690156,0.00871889 +1024,8,16,0,0,TT,5.0,25,0.05,9.8242,3.319507,3.319507,1.928694,1.928694,40.31096571155555,62.794343489333336,59.662805711555556,59.200690156,0.00871889 +1024,8,16,0,0,TT,5.0,25,0.05,39.2968,3.490454,3.490454,1.986933,1.986933,40.31096571155555,62.794343489333336,59.662805711555556,59.200690156,0.00871889 +1024,8,16,0,0,TT,5.0,25,0.4,2.45605,3.329209,3.329209,1.914326,1.914326,40.31096571155555,62.794343489333336,59.662805711555556,59.200690156,0.00871889 +1024,8,16,0,0,TT,5.0,25,0.4,9.8242,3.373105,3.373105,1.9282409999999999,1.9282409999999999,40.31096571155555,62.794343489333336,59.662805711555556,59.200690156,0.00871889 +1024,8,16,0,0,TT,5.0,25,0.4,39.2968,3.544086,3.544086,1.9865069999999998,1.9865069999999998,40.31096571155555,62.794343489333336,59.662805711555556,59.200690156,0.00871889 +32,14,2,23,0,TT,5.0,25,0.0125,2.45605,2.5462000000000002,2.5462000000000002,1.897,1.897,30.58740777932222,45.71697444598889,40.13923000154445,40.116407779322216,0.00062602 +32,14,2,23,0,TT,5.0,25,0.0125,9.8242,2.5903,2.5903,1.9105000000000003,1.9105000000000003,30.58740777932222,45.71697444598889,40.13923000154445,40.116407779322216,0.00062602 +32,14,2,23,0,TT,5.0,25,0.0125,39.2968,2.7584000000000004,2.7584000000000004,1.9589000000000003,1.9589000000000003,30.58740777932222,45.71697444598889,40.13923000154445,40.116407779322216,0.00062602 +32,14,2,23,0,TT,5.0,25,0.05,2.45605,2.5529,2.5529,1.8974,1.8974,30.58740777932222,45.71697444598889,40.13923000154445,40.116407779322216,0.00062602 +32,14,2,23,0,TT,5.0,25,0.05,9.8242,2.5974,2.5974,1.9100000000000001,1.9100000000000001,30.58740777932222,45.71697444598889,40.13923000154445,40.116407779322216,0.00062602 +32,14,2,23,0,TT,5.0,25,0.05,39.2968,2.7638,2.7638,1.9584000000000001,1.9584000000000001,30.58740777932222,45.71697444598889,40.13923000154445,40.116407779322216,0.00062602 +32,14,2,23,0,TT,5.0,25,0.4,2.45605,2.6001000000000003,2.6001000000000003,1.8961000000000001,1.8961000000000001,30.58740777932222,45.71697444598889,40.13923000154445,40.116407779322216,0.00062602 +32,14,2,23,0,TT,5.0,25,0.4,9.8242,2.6458,2.6458,1.9087000000000003,1.9087000000000003,30.58740777932222,45.71697444598889,40.13923000154445,40.116407779322216,0.00062602 +32,14,2,23,0,TT,5.0,25,0.4,39.2968,2.8107,2.8107,1.9577,1.9577,30.58740777932222,45.71697444598889,40.13923000154445,40.116407779322216,0.00062602 +256,8,8,0,0,TT,5.0,25,0.0125,2.45605,2.584639,2.584639,2.003465,2.003465,28.942199588888894,39.024744033333334,35.7326807,35.20688958888889,0.004490322000000001 +256,8,8,0,0,TT,5.0,25,0.0125,9.8242,2.626468,2.626468,2.016286,2.016286,28.942199588888894,39.024744033333334,35.7326807,35.20688958888889,0.004490322000000001 +256,8,8,0,0,TT,5.0,25,0.0125,39.2968,2.7888520000000003,2.7888520000000003,2.066452,2.066452,28.942199588888894,39.024744033333334,35.7326807,35.20688958888889,0.004490322000000001 +256,8,8,0,0,TT,5.0,25,0.05,2.45605,2.58826,2.58826,2.0035160000000003,2.0035160000000003,28.942199588888894,39.024744033333334,35.7326807,35.20688958888889,0.004490322000000001 +256,8,8,0,0,TT,5.0,25,0.05,9.8242,2.630093,2.630093,2.016346,2.016346,28.942199588888894,39.024744033333334,35.7326807,35.20688958888889,0.004490322000000001 +256,8,8,0,0,TT,5.0,25,0.05,39.2968,2.792471,2.792471,2.066436,2.066436,28.942199588888894,39.024744033333334,35.7326807,35.20688958888889,0.004490322000000001 +256,8,8,0,0,TT,5.0,25,0.4,2.45605,2.641029,2.641029,2.0033879999999997,2.0033879999999997,28.942199588888894,39.024744033333334,35.7326807,35.20688958888889,0.004490322000000001 +256,8,8,0,0,TT,5.0,25,0.4,9.8242,2.682862,2.682862,2.01641,2.01641,28.942199588888894,39.024744033333334,35.7326807,35.20688958888889,0.004490322000000001 +256,8,8,0,0,TT,5.0,25,0.4,39.2968,2.8452539999999997,2.8452539999999997,2.06649,2.06649,28.942199588888894,39.024744033333334,35.7326807,35.20688958888889,0.004490322000000001 +512,32,4,0,0,TT,5.0,25,0.0125,2.45605,3.1152170000000003,3.1152170000000003,2.479908,2.479908,55.86348936444444,82.6295638088889,72.78315714222222,71.51401158666665,0.04059002 +512,32,4,0,0,TT,5.0,25,0.0125,9.8242,3.155912,3.155912,2.498457,2.498457,55.86348936444444,82.6295638088889,72.78315714222222,71.51401158666665,0.04059002 +512,32,4,0,0,TT,5.0,25,0.0125,39.2968,3.315606,3.315606,2.56431,2.56431,55.86348936444444,82.6295638088889,72.78315714222222,71.51401158666665,0.04059002 +512,32,4,0,0,TT,5.0,25,0.05,2.45605,3.118836,3.118836,2.48003,2.48003,55.86348936444444,82.6295638088889,72.78315714222222,71.51401158666665,0.04059002 +512,32,4,0,0,TT,5.0,25,0.05,9.8242,3.159527,3.159527,2.498586,2.498586,55.86348936444444,82.6295638088889,72.78315714222222,71.51401158666665,0.04059002 +512,32,4,0,0,TT,5.0,25,0.05,39.2968,3.319226,3.319226,2.5644009999999997,2.5644009999999997,55.86348936444444,82.6295638088889,72.78315714222222,71.51401158666665,0.04059002 +512,32,4,0,0,TT,5.0,25,0.4,2.45605,3.1722930000000003,3.1722930000000003,2.479757,2.479757,55.86348936444444,82.6295638088889,72.78315714222222,71.51401158666665,0.04059002 +512,32,4,0,0,TT,5.0,25,0.4,9.8242,3.212987,3.212987,2.4984189999999997,2.4984189999999997,55.86348936444444,82.6295638088889,72.78315714222222,71.51401158666665,0.04059002 +512,32,4,0,0,TT,5.0,25,0.4,39.2968,3.3726700000000003,3.3726700000000003,2.564297,2.564297,55.86348936444444,82.6295638088889,72.78315714222222,71.51401158666665,0.04059002 diff --git a/technology/scn4m_subm/sim_data/write0_power.csv b/technology/scn4m_subm/sim_data/write0_power.csv deleted file mode 100644 index 6cc34240..00000000 --- a/technology/scn4m_subm/sim_data/write0_power.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,write0_power -16,2,1,46853,FF,5.0,25,0.0125,2.45605,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.05,2.45605,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.05,9.8242,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.05,39.2968,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.4,2.45605,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.4,9.8242,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.4,39.2968,18.51111111111111 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.05,2.45605,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.05,9.8242,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.05,39.2968,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.4,2.45605,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.4,9.8242,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.4,39.2968,16.669833333333333 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.05,2.45605,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.05,9.8242,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.05,39.2968,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.4,2.45605,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.4,9.8242,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.4,39.2968,6.557822222222223 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.05,2.45605,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.05,9.8242,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.05,39.2968,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.4,2.45605,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.4,9.8242,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.4,39.2968,22.194266666666664 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.05,2.45605,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.05,9.8242,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.05,39.2968,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.4,2.45605,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.4,9.8242,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.4,39.2968,20.079666666666668 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.05,2.45605,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.05,9.8242,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.05,39.2968,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.4,2.45605,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.4,9.8242,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.4,39.2968,7.7370222222222225 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.05,2.45605,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.05,9.8242,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.05,39.2968,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.4,2.45605,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.4,9.8242,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.4,39.2968,17.124444444444446 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.05,2.45605,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.05,9.8242,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.05,39.2968,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.4,2.45605,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.4,9.8242,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.4,39.2968,16.054355555555553 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.05,2.45605,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.05,9.8242,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.05,39.2968,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.4,2.45605,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.4,9.8242,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.4,39.2968,6.014788888888889 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.05,2.45605,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.05,9.8242,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.05,39.2968,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.4,2.45605,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.4,9.8242,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.4,39.2968,21.896033333333335 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.05,2.45605,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.05,9.8242,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.05,39.2968,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.4,2.45605,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.4,9.8242,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.4,39.2968,19.810144444444447 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.05,2.45605,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.05,9.8242,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.05,39.2968,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.4,2.45605,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.4,9.8242,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.4,39.2968,7.5868777777777785 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.05,2.45605,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.05,9.8242,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.05,39.2968,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.4,2.45605,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.4,9.8242,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.4,39.2968,19.912277777777778 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.05,2.45605,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.05,9.8242,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.05,39.2968,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.4,2.45605,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.4,9.8242,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.4,39.2968,17.958355555555556 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.05,2.45605,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.05,9.8242,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.05,39.2968,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.4,2.45605,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.4,9.8242,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.4,39.2968,6.832988888888889 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.05,2.45605,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.05,9.8242,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.05,39.2968,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.4,2.45605,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.4,9.8242,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.4,39.2968,19.964633333333335 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.05,2.45605,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.05,9.8242,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.05,39.2968,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.4,2.45605,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.4,9.8242,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.4,39.2968,18.017455555555554 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.05,2.45605,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.05,9.8242,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.05,39.2968,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.4,2.45605,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.4,9.8242,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.4,39.2968,6.829933333333334 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.05,2.45605,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.05,9.8242,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.05,39.2968,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.4,2.45605,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.4,9.8242,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.4,39.2968,19.206566666666667 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.05,2.45605,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.05,9.8242,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.05,39.2968,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.4,2.45605,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.4,9.8242,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.4,39.2968,18.17966666666667 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.05,2.45605,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.05,9.8242,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.05,39.2968,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.4,2.45605,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.4,9.8242,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.4,39.2968,6.889222222222222 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.05,2.45605,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.05,9.8242,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.05,39.2968,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.4,2.45605,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.4,9.8242,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.4,39.2968,18.07902222222222 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.05,2.45605,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.05,9.8242,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.05,39.2968,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.4,2.45605,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.4,9.8242,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.4,39.2968,17.033544444444445 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.05,2.45605,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.05,9.8242,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.05,39.2968,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.4,2.45605,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.4,9.8242,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.4,39.2968,6.437566666666667 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,21.5115 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,21.5115 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,21.5115 -16,4,1,51796,FF,5.0,25,0.05,2.45605,21.5115 -16,4,1,51796,FF,5.0,25,0.05,9.8242,21.5115 -16,4,1,51796,FF,5.0,25,0.05,39.2968,21.5115 -16,4,1,51796,FF,5.0,25,0.4,2.45605,21.5115 -16,4,1,51796,FF,5.0,25,0.4,9.8242,21.5115 -16,4,1,51796,FF,5.0,25,0.4,39.2968,21.5115 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,19.3902 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,19.3902 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,19.3902 -16,4,1,51796,SS,5.0,25,0.05,2.45605,19.3902 -16,4,1,51796,SS,5.0,25,0.05,9.8242,19.3902 -16,4,1,51796,SS,5.0,25,0.05,39.2968,19.3902 -16,4,1,51796,SS,5.0,25,0.4,2.45605,19.3902 -16,4,1,51796,SS,5.0,25,0.4,9.8242,19.3902 -16,4,1,51796,SS,5.0,25,0.4,39.2968,19.3902 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.05,2.45605,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.05,9.8242,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.05,39.2968,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.4,2.45605,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.4,9.8242,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.4,39.2968,19.861788888888885 diff --git a/technology/scn4m_subm/sim_data/write1_power.csv b/technology/scn4m_subm/sim_data/write1_power.csv deleted file mode 100644 index 66002ccc..00000000 --- a/technology/scn4m_subm/sim_data/write1_power.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,write1_power -16,2,1,46853,FF,5.0,25,0.0125,2.45605,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.05,2.45605,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.05,9.8242,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.05,39.2968,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.4,2.45605,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.4,9.8242,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.4,39.2968,14.552122222222222 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.05,2.45605,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.05,9.8242,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.05,39.2968,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.4,2.45605,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.4,9.8242,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.4,39.2968,13.17188888888889 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,5.0991 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,5.0991 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,5.0991 -16,2,1,46853,TT,3.6,25,0.05,2.45605,5.0991 -16,2,1,46853,TT,3.6,25,0.05,9.8242,5.0991 -16,2,1,46853,TT,3.6,25,0.05,39.2968,5.0991 -16,2,1,46853,TT,3.6,25,0.4,2.45605,5.0991 -16,2,1,46853,TT,3.6,25,0.4,9.8242,5.0991 -16,2,1,46853,TT,3.6,25,0.4,39.2968,5.0991 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.05,2.45605,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.05,9.8242,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.05,39.2968,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.4,2.45605,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.4,9.8242,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.4,39.2968,17.173877777777776 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.05,2.45605,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.05,9.8242,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.05,39.2968,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.4,2.45605,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.4,9.8242,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.4,39.2968,15.558922222222224 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.05,2.45605,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.05,9.8242,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.05,39.2968,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.4,2.45605,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.4,9.8242,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.4,39.2968,5.990855555555556 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.05,2.45605,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.05,9.8242,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.05,39.2968,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.4,2.45605,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.4,9.8242,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.4,39.2968,13.361055555555557 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.05,2.45605,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.05,9.8242,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.05,39.2968,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.4,2.45605,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.4,9.8242,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.4,39.2968,12.38438888888889 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.05,2.45605,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.05,9.8242,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.05,39.2968,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.4,2.45605,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.4,9.8242,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.4,39.2968,4.642466666666667 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.05,2.45605,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.05,9.8242,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.05,39.2968,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.4,2.45605,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.4,9.8242,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.4,39.2968,17.334066666666665 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.05,2.45605,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.05,9.8242,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.05,39.2968,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.4,2.45605,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.4,9.8242,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.4,39.2968,15.700577777777776 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.05,2.45605,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.05,9.8242,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.05,39.2968,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.4,2.45605,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.4,9.8242,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.4,39.2968,5.999477777777778 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.05,2.45605,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.05,9.8242,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.05,39.2968,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.4,2.45605,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.4,9.8242,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.4,39.2968,15.736833333333331 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.05,2.45605,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.05,9.8242,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.05,39.2968,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.4,2.45605,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.4,9.8242,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.4,39.2968,14.229766666666668 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.05,2.45605,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.05,9.8242,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.05,39.2968,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.4,2.45605,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.4,9.8242,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.4,39.2968,5.425977777777778 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.05,2.45605,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.05,9.8242,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.05,39.2968,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.4,2.45605,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.4,9.8242,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.4,39.2968,15.804955555555559 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.05,2.45605,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.05,9.8242,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.05,39.2968,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.4,2.45605,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.4,9.8242,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.4,39.2968,14.276855555555557 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.05,2.45605,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.05,9.8242,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.05,39.2968,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.4,2.45605,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.4,9.8242,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.4,39.2968,5.408322222222222 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.05,2.45605,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.05,9.8242,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.05,39.2968,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.4,2.45605,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.4,9.8242,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.4,39.2968,15.151033333333336 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.05,2.45605,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.05,9.8242,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.05,39.2968,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.4,2.45605,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.4,9.8242,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.4,39.2968,14.15878888888889 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.05,2.45605,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.05,9.8242,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.05,39.2968,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.4,2.45605,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.4,9.8242,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.4,39.2968,5.381711111111112 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.05,2.45605,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.05,9.8242,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.05,39.2968,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.4,2.45605,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.4,9.8242,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.4,39.2968,14.238744444444443 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.05,2.45605,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.05,9.8242,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.05,39.2968,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.4,2.45605,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.4,9.8242,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.4,39.2968,13.271822222222221 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.05,2.45605,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.05,9.8242,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.05,39.2968,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.4,2.45605,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.4,9.8242,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.4,39.2968,5.0185666666666675 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.05,2.45605,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.05,9.8242,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.05,39.2968,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.4,2.45605,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.4,9.8242,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.4,39.2968,17.082644444444444 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.05,2.45605,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.05,9.8242,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.05,39.2968,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.4,2.45605,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.4,9.8242,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.4,39.2968,15.400877777777778 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.05,2.45605,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.05,9.8242,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.05,39.2968,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.4,2.45605,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.4,9.8242,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.4,39.2968,15.886588888888888 diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 1812d19e..dc6cd866 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -119,6 +119,8 @@ layer["m4"] = (31, 0) layer["text"] = (63, 0) layer["boundary"] = (63, 0) +use_purpose = {} + # Layer names for external PDKs layer_names = {} layer_names["active"] = "active"