diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 0f5deee2..8014b81c 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -930,8 +930,8 @@ class bank(design.design):
             inst1_bl_name = self.bl_names[port]+"_{}"
             inst1_br_name = self.br_names[port]+"_{}"
             
-        self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
-                              inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name)
+        self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
+                                    inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name)
         
     def route_write_driver_to_sense_amp(self, port):
         """ Routing of BL and BR between write driver and sense amp """
@@ -972,6 +972,37 @@ class bank(design.design):
             din_name = "din{0}_{1}".format(port,row)
             self.copy_layout_pin(self.write_driver_array_inst[port], data_name, din_name)
             
+    def channel_route_bitlines(self, inst1, inst2, num_bits,
+                               inst1_bl_name="bl_{}", inst1_br_name="br_{}",
+                               inst2_bl_name="bl_{}", inst2_br_name="br_{}"):
+        """
+        Route the bl and br of two modules using the channel router.
+        """
+        
+        # determine top and bottom automatically.
+        # since they don't overlap, we can just check the bottom y coordinate.
+        if inst1.by() < inst2.by():
+            (bottom_inst, bottom_bl_name, bottom_br_name) = (inst1, inst1_bl_name, inst1_br_name)
+            (top_inst, top_bl_name, top_br_name) = (inst2, inst2_bl_name, inst2_br_name)
+        else:
+            (bottom_inst, bottom_bl_name, bottom_br_name) = (inst2, inst2_bl_name, inst2_br_name)
+            (top_inst, top_bl_name, top_br_name) = (inst1, inst1_bl_name, inst1_br_name)
+
+
+        # Channel route each mux separately since we don't minimize the number
+        # of tracks in teh channel router yet. If we did, we could route all the bits at once!
+        offset = bottom_inst.ul() + vector(0,self.m1_pitch)
+        for bit in range(num_bits):
+            bottom_names = [bottom_bl_name.format(bit), bottom_br_name.format(bit)]
+            top_names = [top_bl_name.format(bit), top_br_name.format(bit)]            
+            route_map = list(zip(bottom_names, top_names))
+            bottom_pins = {key: bottom_inst.get_pin(key) for key in bottom_names }
+            top_pins = {key: top_inst.get_pin(key) for key in top_names }
+            all_pins = {**bottom_pins, **top_pins}
+            debug.check(len(all_pins)==len(bottom_pins)+len(top_pins),"Duplicate named pins in bitline channel route.")
+            self.create_horizontal_channel_route(route_map, all_pins, offset)
+            
+
     def connect_bitlines(self, inst1, inst2, num_bits,
                          inst1_bl_name="bl_{}", inst1_br_name="br_{}",
                          inst2_bl_name="bl_{}", inst2_br_name="br_{}"):