diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py
index c2860ec6..d5f9eedb 100644
--- a/compiler/pgates/precharge.py
+++ b/compiler/pgates/precharge.py
@@ -1,12 +1,12 @@
 import contact
-import pgate
+import design
 import debug
 from tech import drc, parameter
 from vector import vector
 from globals import OPTS
 from sram_factory import factory
 
-class precharge(pgate.pgate):
+class precharge(design.design):
     """
     Creates a single precharge cell
     This module implements the precharge bitline cell used in the design.
@@ -14,6 +14,7 @@ class precharge(pgate.pgate):
     def __init__(self, name, size=1, bitcell_bl="bl", bitcell_br="br"):
 
         debug.info(2, "creating precharge cell {0}".format(name))
+        design.design.__init__(self, name)
 
         self.bitcell = factory.create(module_type="bitcell")
         self.beta = parameter["beta"]
@@ -22,9 +23,13 @@ class precharge(pgate.pgate):
         self.bitcell_bl = bitcell_bl
         self.bitcell_br = bitcell_br
         
-        # Creates the netlist and layout        
-        pgate.pgate.__init__(self, name)
         
+        # Creates the netlist and layout
+        # Since it has variable height, it is not a pgate.
+        self.create_netlist()
+        if not OPTS.netlist_only:        
+            self.create_layout()
+            self.DRC_LVS()
 
     def create_netlist(self):
         self.add_pins()
@@ -150,7 +155,6 @@ class precharge(pgate.pgate):
         self.add_via_center(layers=("poly", "contact", "metal1"),
                             offset=offset)
 
-
         # adds the en rail on metal1
         self.add_layout_pin_segment_center(text="en_bar",
                                            layer="metal1",
diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py
index c0686bbb..c2124d63 100644
--- a/compiler/pgates/ptx.py
+++ b/compiler/pgates/ptx.py
@@ -29,6 +29,7 @@ class ptx(design.design):
         # replace periods with underscore for newer spice compatibility
         name=name.replace('.','_')
         debug.info(3, "creating ptx {0}".format(name))
+        design.design.__init__(self, name)
 
         self.tx_type = tx_type
         self.mults = mults
@@ -38,8 +39,7 @@ class ptx(design.design):
         self.num_contacts = num_contacts
 
         # Do NOT create the netlist and layout (not a pgate)
-        design.design.__init__(self, name)
-
+        # Since it has variable height, it is not a pgate.
         self.create_netlist()
         # We must always create ptx layout for pbitcell
         # some transistor sizes in other netlist depend on pbitcell
diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py
index 70579cf5..88e76e07 100644
--- a/compiler/pgates/single_level_column_mux.py
+++ b/compiler/pgates/single_level_column_mux.py
@@ -7,7 +7,7 @@ from globals import OPTS
 from sram_factory import factory
 import logical_effort
 
-class single_level_column_mux(pgate.gate):
+class single_level_column_mux(pgate.pgate):
     """
     This module implements the columnmux bitline cell used in the design.
     Creates a single columnmux cell with the given integer size relative