diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py
index 9c077ed7..581f9484 100644
--- a/compiler/modules/write_mask_and_array.py
+++ b/compiler/modules/write_mask_and_array.py
@@ -126,7 +126,7 @@ class write_mask_and_array(design.design):
         for supply in ["gnd", "vdd"]:
             supply_pin_left = self.and2_insts[0].get_pin(supply)
             supply_pin_right = self.and2_insts[self.num_wmasks - 1].get_pin(supply)
-            self.add_path("m1", [supply_pin_left.lc(), supply_pin_right.rc()])
+            self.add_path(supply_pin_left.layer, [supply_pin_left.lc(), supply_pin_right.rc()])
             
     def get_cin(self):
         """Get the relative capacitance of all the input connections in the bank"""