diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 9230be55..7aa9641d 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -70,6 +70,11 @@ class delay(simulation):
         self.read_meas_objs[-1].meta_str = "read1"
         self.read_meas_objs.append(power_measure("read0_power", "FALL", measure_scale=1e3))
         self.read_meas_objs[-1].meta_str = "read0"
+        
+        #This will later add a half-period to the spice time delay. Only for reading 0.
+        for obj in self.read_meas_objs:
+            if obj.meta_str is "read0":
+                obj.meta_add_delay = True
 
         trig_name = "Xsram.s_en{}" #Sense amp enable
         if len(self.all_ports) == 1: #special naming case for single port sram bitlines which does not include the port in name
@@ -104,13 +109,16 @@ class delay(simulation):
         self.bitline_delay_objs[-1].meta_str = "read0"
         self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[1], trig_name, br_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9))
         self.bitline_delay_objs[-1].meta_str = "read1"
-
+        #Enforces the time delay on the bitline measurements for read0 or read1
+        for obj in self.bitline_delay_objs:
+            obj.meta_add_delay = True
+        
     def create_write_port_measurement_objects(self):
         """Create the measurements used for read ports: delays, slews, powers"""
         self.write_meas_objs = []
 
         self.write_meas_objs.append(power_measure("write1_power", "RISE", measure_scale=1e3))
-        self.write_meas_objs[-1].meta_str = "read1"
+        self.write_meas_objs[-1].meta_str = "write1"
         self.write_meas_objs.append(power_measure("write0_power", "FALL", measure_scale=1e3))
         self.write_meas_objs[-1].meta_str = "write0"
      
@@ -284,12 +292,15 @@ class delay(simulation):
         #vdd is arguably constant as that is true for a single lib file.
         if delay_obj.meta_str == "read0":
             #Falling delay are measured starting from neg. clk edge. Delay adjusted to that.
-            meas_cycle_delay = self.cycle_times[self.measure_cycles[port][delay_obj.meta_str]] + self.period/2
+            meas_cycle_delay = self.cycle_times[self.measure_cycles[port][delay_obj.meta_str]]
         elif delay_obj.meta_str == "read1":
             meas_cycle_delay = self.cycle_times[self.measure_cycles[port][delay_obj.meta_str]]
         else:
             debug.error("Unrecognised delay Index={}".format(delay_obj.meta_str),1)
             
+        if delay_obj.meta_add_delay:    
+            meas_cycle_delay += self.period/2
+            
         return (meas_cycle_delay, meas_cycle_delay, self.vdd_voltage, port)
     
     def get_power_measure_variants(self, port, power_obj, operation):
diff --git a/compiler/characterizer/measurements.py b/compiler/characterizer/measurements.py
index aec4d769..e3d16584 100644
--- a/compiler/characterizer/measurements.py
+++ b/compiler/characterizer/measurements.py
@@ -10,8 +10,9 @@ class spice_measurement(ABC):
         #Names must be unique for correct spice simulation, but not enforced here.
         self.name = measure_name
         self.measure_scale = measure_scale
-        self.meta_str = None #Some measurements set this, set here to be clear on existence
-        
+        #Some meta values used externally. variables are added here for consistency accross the objects
+        self.meta_str = None 
+        self.meta_add_delay = False
     @abstractmethod
     def get_measure_function(self):
         return None    
diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index 9d022324..d83cbd0d 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -177,9 +177,9 @@ class control_logic(design.design):
         """Use a basic heuristic to determine the size of the delay chain used for the Sense Amp Enable """
         #FIXME: The minimum was 2 fanout, now it will not pass DRC unless it is 3. Why?
         delay_fanout = 3 # This can be anything >=3
-        # Delay stages Must be non-inverting
+        # Model poorly captures delay of the column mux. Be pessismistic for column mux
         if self.words_per_row >= 2:
-            delay_stages = 4
+            delay_stages = 8
         else:
             delay_stages = 2