diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py
index 055bf412..e4c77987 100644
--- a/compiler/base/hierarchy_design.py
+++ b/compiler/base/hierarchy_design.py
@@ -64,8 +64,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
             self.sp_write(tempspice)
             self.gds_write(tempgds)
 
-            num_drc_errors = verify.run_drc(self.name, tempgds, final_verification) 
-            num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification) 
+            num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) 
+            num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) 
             debug.check(num_drc_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_drc_errors))
             debug.check(num_lvs_errors == 0,"LVS failed for {0} with {1} errors(s)".format(self.name,num_lvs_errors))
             total_drc_errors += num_drc_errors
@@ -83,7 +83,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
             global total_drc_errors
             tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name)
             self.gds_write(tempgds)
-            num_errors = verify.run_drc(self.name, tempgds, final_verification)  
+            num_errors = verify.run_drc(self.name, tempgds, final_verification=final_verification)  
             total_drc_errors += num_errors
             debug.check(num_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_error))
 
@@ -100,7 +100,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
             tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name)
             self.sp_write(tempspice)
             self.gds_write(tempgds)
-            num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification)
+            num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification)
             total_lvs_errors += num_errors
             debug.check(num_errors == 0,"LVS failed for {0} with {1} error(s)".format(self.name,num_errors))
             os.remove(tempspice)
diff --git a/compiler/globals.py b/compiler/globals.py
index 4fed4cd9..e08e381f 100644
--- a/compiler/globals.py
+++ b/compiler/globals.py
@@ -507,16 +507,16 @@ def report_status():
         debug.print_raw("Netlist only mode (no physical design is being done, netlist_only=False to disable).")
     
     if not OPTS.route_supplies:
-        debug.print_raw("Design supply routing skipped for run-time (incomplete GDS will not be saved) (route_supplies=True to enable).")
+        debug.print_raw("Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing).")
         
     if not OPTS.inline_lvsdrc:
-        debug.print_raw("DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to enable).")
+        debug.print_raw("DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).")
 
     if not OPTS.check_lvsdrc:
         debug.print_raw("DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).")
 
     if OPTS.analytical_delay:
-        debug.print_raw("Characterization is disabled (using analytical delay models) (analytical_delay=False to enable).")
+        debug.print_raw("Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).")
     else:
         if OPTS.spice_name!="":
             debug.print_raw("Performing simulation-based characterization with {}".format(OPTS.spice_name))
diff --git a/compiler/openram.py b/compiler/openram.py
index 9bd3b898..97ada256 100755
--- a/compiler/openram.py
+++ b/compiler/openram.py
@@ -58,10 +58,7 @@ debug.print_raw("Words per row: {}".format(c.words_per_row))
 output_extensions = ["sp","v","lib","py","html","log"]
 # Only output lef/gds if back-end
 if not OPTS.netlist_only:
-    output_extensions.extend(["lef"])
-    # Only output gds if final routing
-    if OPTS.route_supplies:
-        output_extensions.extend(["gds"])
+    output_extensions.extend(["lef","gds"])
         
 output_files = ["{0}{1}.{2}".format(OPTS.output_path,OPTS.output_name,x) for x in output_extensions]
 debug.print_raw("Output files are: ")
diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py
index 5e7ac08a..c4f41f77 100644
--- a/compiler/sram/sram.py
+++ b/compiler/sram/sram.py
@@ -75,13 +75,12 @@ class sram():
             self.lef_write(lefname)
             print_time("LEF", datetime.datetime.now(), start_time)
 
-            if OPTS.route_supplies:
-                # Write the layout
-                start_time = datetime.datetime.now()
-                gdsname = OPTS.output_path + self.s.name + ".gds"
-                debug.print_raw("GDS: Writing to {0}".format(gdsname))
-                self.gds_write(gdsname)
-                print_time("GDS", datetime.datetime.now(), start_time)
+            # Write the layout
+            start_time = datetime.datetime.now()
+            gdsname = OPTS.output_path + self.s.name + ".gds"
+            debug.print_raw("GDS: Writing to {0}".format(gdsname))
+            self.gds_write(gdsname)
+            print_time("GDS", datetime.datetime.now(), start_time)
 
         # Save the spice file
         start_time = datetime.datetime.now()
@@ -130,4 +129,4 @@ class sram():
         vname = OPTS.output_path + self.s.name + ".v"
         debug.print_raw("Verilog: Writing to {0}".format(vname))
         self.verilog_write(vname)
-        print_time("Verilog", datetime.datetime.now(), start_time)
\ No newline at end of file
+        print_time("Verilog", datetime.datetime.now(), start_time)