OpenRAM/compiler/sram_8_128_scn4m_subm.html

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sram_8_128_scn4m_subm,128,1,1,0,0,scn4m_subm,25,5.0,FF,0.404,/home/jesse/openram/compiler/./,/home/jesse/openram/compiler/./sram_8_128_scn4m_subm_FF_5p0V_25C.lib,8,8166adc512f36a28a6334c995999ac60a5fe5388,2020-06-24,True,skipped,skipped,0,din0[7:0],0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,dout0[7:0],1.938,2.019,1.938,2.019,0.006,0.014,0.006,0.014,csb0,0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,addr0[6:0],0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,web0,0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,power,!csb0 & clk0 & !web0,Read,6.878835450277779,power,!csb0 & !clk0 & web0,Write,6.878835450277779,leak,csb0,0.001282,END
sram_8_128_scn4m_subm,128,1,1,0,0,scn4m_subm,25,5.0,SS,0.493,/home/jesse/openram/compiler/./,/home/jesse/openram/compiler/./sram_8_128_scn4m_subm_SS_5p0V_25C.lib,8,8166adc512f36a28a6334c995999ac60a5fe5388,2020-06-24,True,skipped,skipped,0,din0[7:0],0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,dout0[7:0],2.368,2.467,2.368,2.467,0.007,0.017,0.007,0.017,csb0,0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,addr0[6:0],0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,web0,0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,power,!csb0 & clk0 & !web0,Read,5.628138095681816,power,!csb0 & !clk0 & web0,Write,5.628138095681816,leak,csb0,0.001282,END
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<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Operating Conditions</p><table id= "data"><thead><tr><th>Parameter</th><th>Min</th><th>Typ</th><th>Max</th><th>Units</th></tr></thead><tbody><tr><tr><td>Power supply (VDD) range</td><td>5.0</td><td>5.0</td><td>5.0</td><td>Volts</td></tr><tr><td>Operating Temperature</td><td>25</td><td>25</td><td>25</td><td>Celsius</td></tr><tr><td>Operating Frequency (F)</td><td></td><td></td><td>2227</td><td>MHz</td></tr></tr></tbody></table>
<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Timing Data</p><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Using analytical model: results may not be precise</p><table id= "data"><thead><tr><th>Parameter</th><th>Min</th><th>Max</th><th>Units</th></tr></thead><tbody><tr><tr><td>din0[7:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>din0[7:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>din0[7:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>din0[7:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>dout0[7:0] cell rise</td><td>1.938</td><td>2.467</td><td>ns</td></tr><tr><td>dout0[7:0] cell fall</td><td>2.153</td><td>2.243</td><td>ns</td></tr><tr><td>dout0[7:0] rise transition</td><td>0.006</td><td>0.015</td><td>ns</td></tr><tr><td>dout0[7:0] fall transition</td><td>0.006</td><td>0.015</td><td>ns</td></tr><tr><td>csb0 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>csb0 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>csb0 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>csb0 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>addr0[6:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>addr0[6:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>addr0[6:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>addr0[6:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>web0 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>web0 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>web0 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>web0 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr></tr></tbody></table>
<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Power Data</p><table id= "data"><thead><tr><th>Pins</th><th>Mode</th><th>Power</th><th>Units</th></tr></thead><tbody><tr><tr><td>!csb0 & clk0 & !web0</td><td>Read Rising</td><td>6.1909</td><td>mW</td></tr><tr><td>!csb0 & clk0 & !web0</td><td>Read Falling</td><td>6.1909</td><td>mW</td></tr><tr><td>!csb0 & !clk0 & web0</td><td>Write Rising</td><td>6.1909</td><td>mW</td></tr><tr><td>!csb0 & !clk0 & web0</td><td>Write Falling</td><td>6.1909</td><td>mW</td></tr><tr><td>csb0</td><td>leakage</td><td>0.001282</td><td>mW</td></tr></tr></tbody></table>
<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Characterization Corners</p><table id= "data"><thead><tr><th>Transistor Type</th><th>Power Supply</th><th>Temperature</th><th>Corner Name</th></tr></thead><tbody><tr><tr><td>TT</td><td>5.0</td><td>25</td><td>_TT_5p0V_25C.lib</td></tr><tr><td>FF</td><td>5.0</td><td>25</td><td>_FF_5p0V_25C.lib</td></tr><tr><td>SS</td><td>5.0</td><td>25</td><td>_SS_5p0V_25C.lib</td></tr></tr></tbody></table>
<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Deliverables</p><table id= "data"><thead><tr><th>Type</th><th>Description</th><th>Link</th></tr></thead><tbody><tr><!--.db<tr><td>.db</td><td>Compiled .lib</td><td><a href="sram_8_128_scn4m_subm_TT_5p0V_25C.db">sram_8_128_scn4m_subm_TT_5p0V_25C.db</a></td></tr>.db--><!--.db<tr><td>.db</td><td>Compiled .lib</td><td><a href="sram_8_128_scn4m_subm_FF_5p0V_25C.db">sram_8_128_scn4m_subm_FF_5p0V_25C.db</a></td></tr>.db--><!--.db<tr><td>.db</td><td>Compiled .lib</td><td><a href="sram_8_128_scn4m_subm_SS_5p0V_25C.db">sram_8_128_scn4m_subm_SS_5p0V_25C.db</a></td></tr>.db--><tr><td>.html</td><td>This datasheet</td><td><a href="sram_8_128_scn4m_subm.html">sram_8_128_scn4m_subm.html</a></td></tr><tr><td>.lib</td><td>Synthesis models</td><td><a href="sram_8_128_scn4m_subm_TT_5p0V_25C.lib">sram_8_128_scn4m_subm_TT_5p0V_25C.lib</a></td></tr><tr><td>.lib</td><td>Synthesis models</td><td><a href="file:///home/jesse/openram/compiler/./sram_8_128_scn4m_subm_FF_5p0V_25C.lib">sram_8_128_scn4m_subm_FF_5p0V_25C.lib</a></td></tr><tr><td>.lib</td><td>Synthesis models</td><td><a href="file:///home/jesse/openram/compiler/./sram_8_128_scn4m_subm_SS_5p0V_25C.lib">sram_8_128_scn4m_subm_SS_5p0V_25C.lib</a></td></tr><tr><td>.log</td><td>OpenRAM compile log</td><td><a href="sram_8_128_scn4m_subm.log">sram_8_128_scn4m_subm.log</a></td></tr><tr><td>.py</td><td>OpenRAM configuration file</td><td><a href="sram_8_128_scn4m_subm.py">sram_8_128_scn4m_subm.py</a></td></tr><tr><td>.sp</td><td>SPICE netlists</td><td><a href="sram_8_128_scn4m_subm.sp">sram_8_128_scn4m_subm.sp</a></td></tr><tr><td>.v</td><td>Verilog simulation models</td><td><a href="sram_8_128_scn4m_subm.v">sram_8_128_scn4m_subm.v</a></td></tr></tr></tbody></table>