mirror of https://github.com/VLSIDA/OpenRAM.git
28 lines
872 B
Plaintext
28 lines
872 B
Plaintext
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<?xml version="1.0" encoding="utf-8"?>
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<technology>
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<name>SCMOS</name>
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<description/>
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<dbu>0.001</dbu>
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<base-path/>
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<layer-properties_file>mosis.lyp</layer-properties_file>
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<add-other-layers>true</add-other-layers>
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<connectivity>
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<connection>Active,ActX,Metal1</connection>
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<connection>Poly1,P1Con,Metal1</connection>
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<connection>Metal1,Via,Metal2</connection>
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<connection>Metal2,Via2,Metal3</connection>
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<connection>Metal3,Via3,Metal4</connection>
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<symbols>Active='43/0'</symbols>
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<symbols>Poly1='46/0'</symbols>
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<symbols>P1Con='47/0'</symbols>
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<symbols>ActX='48/0'</symbols>
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<symbols>Metal1='49/0'</symbols>
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<symbols>Via='50/0'</symbols>
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<symbols>Metal2='51/0'</symbols>
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<symbols>Via2='61/0'</symbols>
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<symbols>Metal3.='62/0'</symbols>
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<symbols>Via3='30/0'</symbols>
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<symbols>Metal4='31/0'</symbols>
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</connectivity>
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</technology>
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