mirror of https://github.com/VLSIDA/OpenRAM.git
28 lines
870 B
Python
28 lines
870 B
Python
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from template import template
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from globals import OPTS
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class sram_multibank:
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def __init__(self, sram):
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dict = {
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'module_name': OPTS.output_name,
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'bank_module_name': OPTS.output_name + '_1bank',
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'vdd': 'vdd',
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'gnd': 'gnd',
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'ports': sram.all_ports,
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'rw_ports': sram.readwrite_ports,
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'r_ports': sram.read_ports,
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'w_ports': sram.write_ports,
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'banks': sram.banks,
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'data_width': sram.word_size,
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'addr_width': sram.addr_size,
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'bank_sel': list(range(sram.num_banks)),
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'num_wmask': sram.num_wmasks
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}
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def verilog_write():
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t = template('../sram/sram_multibank_template.v', dict)
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t.write(OPTS.output_name + '.v')
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