mirror of https://github.com/VLSIDA/OpenRAM.git
30 lines
861 B
SourcePawn
30 lines
861 B
SourcePawn
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*master-slave flip-flop with both output and inverted ouput
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.subckt dlatch din dout dout_bar clk clk_bar vdd gnd
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*clk inverter
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mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1
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mNff1 clk_bar clk gnd gnd n W=0.9u L=0.6u m=1
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*transmission gate 1
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mtmP1 din clk int1 vdd p W=1.8u L=0.6u m=1
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mtmN1 din clk_bar int1 gnd n W=0.9u L=0.6u m=1
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*foward inverter
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mPff3 dout_bar int1 vdd vdd p W=1.8u L=0.6u m=1
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mNff3 dout_bar int1 gnd gnd n W=0.9u L=0.6u m=1
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*backward inverter
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mPff4 dout dout_bar vdd vdd p W=1.8u L=0.6u m=1
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mNf4 dout dout_bar gnd gnd n W=0.9u L=0.6u m=1
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*transmission gate 2
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mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1
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mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1
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.ends dlatch
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.subckt ms_flop din dout dout_bar clk vdd gnd
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xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
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xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
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.ends flop
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