

sram_2_16_scn4m_subm.html
DRC: skipped
LVS: skipped
Ports and Configuration (DEBUG)
| Type | Description |
|---|---|
| WORD_SIZE | 2 |
| NUM_WORDS | 16 |
| NUM_BANKS | 1 |
| NUM_RW_PORTS | 1 |
| NUM_R_PORTS | 1 |
| NUM_W_PORTS | 1 |
| Area | 0 |
Operating Conditions
| Parameter | Min | Typ | Max | Units |
|---|---|---|---|---|
| Power supply (VDD) range | 5.0 | 5.0 | 5.0 | Volts |
| Operating Temperature | 25 | 25 | 25 | Celsius |
| Operating Frequency (F)* | unknown | MHz |
Timing and Current Data
| Parameter | Min | Max | Units |
|---|---|---|---|
| Cycle time | 2 | 3 | 4 |
| Access time | 2 | 3 | 4 |
| Positive clk setup | 2 | 3 | 4 |
| Positive clk hold | 2 | 3 | 4 |
| DIN0[1:0] setup rising | 0.009 | 0.009 | ns |
| DIN0[1:0] setup falling | 0.009 | 0.009 | ns |
| DIN0[1:0] hold rising | 0.001 | 0.001 | ns |
| DIN0[1:0] hold falling | 0.001 | 0.001 | ns |
| DIN1[1:0] setup rising | 0.009 | 0.009 | ns |
| DIN1[1:0] setup falling | 0.009 | 0.009 | ns |
| DIN1[1:0] hold rising | 0.001 | 0.001 | ns |
| DIN1[1:0] hold falling | 0.001 | 0.001 | ns |
| DOUT0[1:0] cell rise | 0.079 | 0.079 | ns |
| DOUT0[1:0] cell fall | 0.079 | 0.079 | ns |
| DOUT0[1:0] rise transition | 0.001 | 0.001 | ns |
| DOUT0[1:0] fall transition | 0.001 | 0.001 | ns |
| DOUT2[1:0] cell rise | 0.079 | 0.079 | ns |
| DOUT2[1:0] cell fall | 0.079 | 0.079 | ns |
| DOUT2[1:0] rise transition | 0.001 | 0.001 | ns |
| DOUT2[1:0] fall transition | 0.001 | 0.001 | ns |
| CSb0 setup rising | 0.009 | 0.009 | ns |
| CSb0 setup falling | 0.009 | 0.009 | ns |
| CSb0 hold rising | 0.001 | 0.001 | ns |
| CSb0 hold falling | 0.001 | 0.001 | ns |
| CSb1 setup rising | 0.009 | 0.009 | ns |
| CSb1 setup falling | 0.009 | 0.009 | ns |
| CSb1 hold rising | 0.001 | 0.001 | ns |
| CSb1 hold falling | 0.001 | 0.001 | ns |
| CSb2 setup rising | 0.009 | 0.009 | ns |
| CSb2 setup falling | 0.009 | 0.009 | ns |
| CSb2 hold rising | 0.001 | 0.001 | ns |
| CSb2 hold falling | 0.001 | 0.001 | ns |
| ADDR0[3:0] setup rising | 0.009 | 0.009 | ns |
| ADDR0[3:0] setup falling | 0.009 | 0.009 | ns |
| ADDR0[3:0] hold rising | 0.001 | 0.001 | ns |
| ADDR0[3:0] hold falling | 0.001 | 0.001 | ns |
| ADDR1[3:0] setup rising | 0.009 | 0.009 | ns |
| ADDR1[3:0] setup falling | 0.009 | 0.009 | ns |
| ADDR1[3:0] hold rising | 0.001 | 0.001 | ns |
| ADDR1[3:0] hold falling | 0.001 | 0.001 | ns |
| ADDR2[3:0] setup rising | 0.009 | 0.009 | ns |
| ADDR2[3:0] setup falling | 0.009 | 0.009 | ns |
| ADDR2[3:0] hold rising | 0.001 | 0.001 | ns |
| ADDR2[3:0] hold falling | 0.001 | 0.001 | ns |
| WEb0 setup rising | 0.009 | 0.009 | ns |
| WEb0 setup falling | 0.009 | 0.009 | ns |
| WEb0 hold rising | 0.001 | 0.001 | ns |
| WEb0 hold falling | 0.001 | 0.001 | ns |
| AC current | 2 | 3 | 4 |
| Standby current | 2 | 3 | 4 |
Characterization Corners
| Corner Name | Process | Power Supply | Temperature | Library Name Suffix |
|---|---|---|---|---|
| TT | Typical - Typical | 5.0 | 25 | _TT_5p0V_25C.lib |
Deliverables
| Type | Description | Link |
|---|---|---|
| .sp | SPICE netlists | sram_2_16_scn4m_subm.sp |
| .v | Verilog simulation models | sram_2_16_scn4m_subm.v |
| .html | This datasheet | sram_2_16_scn4m_subm.html |
| .lib | Synthesis models | sram_2_16_scn4m_subm_TT_5p0V_25C.lib |
| .py | OpenRAM configuration file | sram_2_16_scn4m_subm.py |
*Feature only supported with characterizer