VLSIDAOpenRAM

sram_2_16_scn4m_subm.html

DRC: skipped

LVS: skipped

Ports and Configuration (DEBUG)

TypeDescription
WORD_SIZE2
NUM_WORDS16
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS1
NUM_W_PORTS1
Area0

Operating Conditions

ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)*unknownMHz

Timing and Current Data

ParameterMinMaxUnits
Cycle time234
Access time234
Positive clk setup234
Positive clk hold234
DIN0[1:0] setup rising0.0090.009ns
DIN0[1:0] setup falling0.0090.009ns
DIN0[1:0] hold rising0.0010.001ns
DIN0[1:0] hold falling0.0010.001ns
DIN1[1:0] setup rising0.0090.009ns
DIN1[1:0] setup falling0.0090.009ns
DIN1[1:0] hold rising0.0010.001ns
DIN1[1:0] hold falling0.0010.001ns
DOUT0[1:0] cell rise0.0790.079ns
DOUT0[1:0] cell fall0.0790.079ns
DOUT0[1:0] rise transition0.0010.001ns
DOUT0[1:0] fall transition0.0010.001ns
DOUT2[1:0] cell rise0.0790.079ns
DOUT2[1:0] cell fall0.0790.079ns
DOUT2[1:0] rise transition0.0010.001ns
DOUT2[1:0] fall transition0.0010.001ns
CSb0 setup rising0.0090.009ns
CSb0 setup falling0.0090.009ns
CSb0 hold rising0.0010.001ns
CSb0 hold falling0.0010.001ns
CSb1 setup rising0.0090.009ns
CSb1 setup falling0.0090.009ns
CSb1 hold rising0.0010.001ns
CSb1 hold falling0.0010.001ns
CSb2 setup rising0.0090.009ns
CSb2 setup falling0.0090.009ns
CSb2 hold rising0.0010.001ns
CSb2 hold falling0.0010.001ns
ADDR0[3:0] setup rising0.0090.009ns
ADDR0[3:0] setup falling0.0090.009ns
ADDR0[3:0] hold rising0.0010.001ns
ADDR0[3:0] hold falling0.0010.001ns
ADDR1[3:0] setup rising0.0090.009ns
ADDR1[3:0] setup falling0.0090.009ns
ADDR1[3:0] hold rising0.0010.001ns
ADDR1[3:0] hold falling0.0010.001ns
ADDR2[3:0] setup rising0.0090.009ns
ADDR2[3:0] setup falling0.0090.009ns
ADDR2[3:0] hold rising0.0010.001ns
ADDR2[3:0] hold falling0.0010.001ns
WEb0 setup rising0.0090.009ns
WEb0 setup falling0.0090.009ns
WEb0 hold rising0.0010.001ns
WEb0 hold falling0.0010.001ns
AC current234
Standby current234

Characterization Corners

Corner NameProcessPower SupplyTemperatureLibrary Name Suffix
TTTypical - Typical5.025_TT_5p0V_25C.lib

Deliverables

TypeDescriptionLink
.spSPICE netlistssram_2_16_scn4m_subm.sp
.vVerilog simulation modelssram_2_16_scn4m_subm.v
.htmlThis datasheetsram_2_16_scn4m_subm.html
.libSynthesis modelssram_2_16_scn4m_subm_TT_5p0V_25C.lib
.pyOpenRAM configuration filesram_2_16_scn4m_subm.py

*Feature only supported with characterizer