WARNING: file __init__.py: line 79: Did not find Magic.

|==============================================================================|
|=========                       OpenRAM v1.1.6                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: openram-user-group@ucsc.edu           =========|
|=========        Development help: openram-dev-group@ucsc.edu        =========|
|=========               Temp dir: /home/jesse/output/                =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 09/23/2020 00:16:38
Technology: sky130
Total size: 256 bits
Word size: 16
Words: 16
Banks: 1
Write size: 8
RW ports: 1
R-only ports: 1
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
Words per row: 1
Output files are: 
/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.lvs
/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.sp
/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.v
/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.lib
/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.py
/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.html
/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.log
/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.lef
/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.gds
ERROR: file hierarchy_spice.py: line 176: Connection mismatch:
Inst (6) -> Mod (5)
bl_0_0 -> bl0
br_0_0 -> br0
bl_1_0 -> bl1
br_1_0 -> br1
vdd -> vdd
gnd -> 

