[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /home/jesse/output/
[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/run2.py
[globals/read_config]: Output saved in /home/jesse/openram/compiler/./
[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
[globals/init_paths]: Creating temp directory: /home/jesse/output/
[verify/<module>]: Initializing verify...
[verify/<module>]: LVS/DRC/PEX disabled.
[characterizer/<module>]: Initializing characterizer...
[characterizer/<module>]: Analytical model enabled.
[globals/setup_bitcell]: Using bitcell: bitcell
|==============================================================================|
|=========                       OpenRAM v1.1.5                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: openram-user-group@ucsc.edu           =========|
|=========        Development help: openram-dev-group@ucsc.edu        =========|
|=========               Temp dir: /home/jesse/output/                =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 06/24/2020 00:31:44
Technology: scn4m_subm
Total size: 1024 bits
Word size: 8
Words: 128
Banks: 1
Write size: None
RW ports: 1
R-only ports: 0
W-only ports: 0
Netlist only mode (no physical design is being done, netlist_only=False to disable).
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
[sram_config/recompute_sizes]: Recomputing with words per row: 4
[sram_config/recompute_sizes]: Rows: 32 Cols: 32
[sram_config/recompute_sizes]: Row addr size: 5 Col addr size: 2 Bank addr size: 7
Words per row: 4
Output files are: 
/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.sp
/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.v
/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.lib
/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.py
/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.html
/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.log
[dff_array/__init__]: Creating row_addr_dff rows=5 cols=1
[dff_array/__init__]: Creating col_addr_dff rows=1 cols=2
[dff_array/__init__]: Creating data_dff rows=1 cols=8
[precharge_array/__init__]: Creating precharge_array
[sense_amp_array/__init__]: Creating sense_amp_array
[single_level_column_mux_array/__init__]: Creating single_level_column_mux_array
[write_driver_array/__init__]: Creating write_driver_array
[and2_dec/__init__]: Creating and2_dec and2_dec
[and3_dec/__init__]: Creating and3_dec and3_dec
[wordline_driver_array/__init__]: Creating wordline_driver_array
[wordline_driver/__init__]: Creating wordline_driver wordline_driver
[replica_bitcell_array/__init__]: Creating replica_bitcell_array 32 x 32
[bitcell_base_array/__init__]: Creating bitcell_array 32 x 32
[bitcell_base_array/__init__]: Creating dummy_array 1 x 32
[bitcell_base_array/__init__]: Creating dummy_array_0 35 x 1
[bitcell_base_array/__init__]: Creating dummy_array_1 35 x 1
[and2_dec/__init__]: Creating and2_dec and2_dec_0
[control_logic/__init__]: Creating control_logic_rw
[dff_buf/__init__]: Creating dff_buf
[dff_buf_array/__init__]: Creating dff_buf_array
[dff_buf/__init__]: Creating dff_buf_0
[pand2/__init__]: Creating pand2 pand2
[pdriver/__init__]: creating pdriver pdriver
[pbuf/__init__]: creating pbuf with size of 32
[pdriver/__init__]: creating pdriver pdriver_0
[pdriver/__init__]: creating pdriver pdriver_1
[pand3/__init__]: Creating pand3 pand3
[pdriver/__init__]: creating pdriver pdriver_2
[pand3/__init__]: Creating pand3 pand3_0
[pdriver/__init__]: creating pdriver pdriver_3
[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
** Submodules: 0.2 seconds
** SRAM creation: 0.2 seconds
SP: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm.sp
** Spice writing: 0.0 seconds
LIB: Characterizing... 
[characterizer.lib/prepare_tables]: Loads: [ 2.45605  9.8242  39.2968 ]
[characterizer.lib/prepare_tables]: Slews: [0.0125 0.05   0.4   ]
[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 5.0, 25), ('FF', 5.0, 25), ('SS', 5.0, 25)]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm_TT_5p0V_25C.lib
[characterizer.delay/analytical_power]: Dynamic Power: 12.381903810499999 mW
[characterizer.delay/analytical_power]: Leakage Power: 0.001282 mW
[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 2.1528469533910437, 0.006179820369407407
[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 2.170895864473266, 0.00798471147762963
[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.2430915088021552, 0.015204275910518518
[characterizer.delay/analytical_delay]: 0.05, 2.45605, 2.1528469533910437, 0.006179820369407407
[characterizer.delay/analytical_delay]: 0.05, 9.8242, 2.170895864473266, 0.00798471147762963
[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.2430915088021552, 0.015204275910518518
[characterizer.delay/analytical_delay]: 0.4, 2.45605, 2.1528469533910437, 0.006179820369407407
[characterizer.delay/analytical_delay]: 0.4, 9.8242, 2.170895864473266, 0.00798471147762963
[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.2430915088021552, 0.015204275910518518
[characterizer.lib/characterize_corners]: Corner: ('FF', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm_FF_5p0V_25C.lib
[characterizer.delay/analytical_power]: Dynamic Power: 13.757670900555558 mW
[characterizer.delay/analytical_power]: Leakage Power: 0.001282 mW
[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 1.9375622580519398, 0.0055618383324666665
[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 1.9538062780259398, 0.007186240329866667
[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.01878235792194, 0.013683848319466669
[characterizer.delay/analytical_delay]: 0.05, 2.45605, 1.9375622580519398, 0.0055618383324666665
[characterizer.delay/analytical_delay]: 0.05, 9.8242, 1.9538062780259398, 0.007186240329866667
[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.01878235792194, 0.013683848319466669
[characterizer.delay/analytical_delay]: 0.4, 2.45605, 1.9375622580519398, 0.0055618383324666665
[characterizer.delay/analytical_delay]: 0.4, 9.8242, 1.9538062780259398, 0.007186240329866667
[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.01878235792194, 0.013683848319466669
[characterizer.lib/characterize_corners]: Corner: ('SS', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm_SS_5p0V_25C.lib
[characterizer.delay/analytical_power]: Dynamic Power: 11.256276191363632 mW
[characterizer.delay/analytical_power]: Leakage Power: 0.001282 mW
[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 2.3681316487301483, 0.006797802406348149
[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 2.387985450920593, 0.008783182625392592
[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.4674006596823705, 0.016724703501570373
[characterizer.delay/analytical_delay]: 0.05, 2.45605, 2.3681316487301483, 0.006797802406348149
[characterizer.delay/analytical_delay]: 0.05, 9.8242, 2.387985450920593, 0.008783182625392592
[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.4674006596823705, 0.016724703501570373
[characterizer.delay/analytical_delay]: 0.4, 2.45605, 2.3681316487301483, 0.006797802406348149
[characterizer.delay/analytical_delay]: 0.4, 9.8242, 2.387985450920593, 0.008783182625392592
[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.4674006596823705, 0.016724703501570373
** Characterization: 0.3 seconds
Config: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm.py
** Config: 0.0 seconds
Datasheet: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm.html
** Datasheet: 0.0 seconds
Verilog: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm.v
** Verilog: 0.0 seconds
[globals/cleanup_paths]: Purging temp directory: /home/jesse/output/
** End: 0.5 seconds
