[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Setting up paths...
[globals/setup_paths]: Temporary files saved in /home/jesse/output/
[globals/read_config]: Configuration file is /home/jesse/compiler/example_configs/s8config.py
[globals/read_config]: Output saved in /home/jesse/openram/sram_0.05/
[globals/import_tech]: Importing technology: sky130
[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
[globals/init_paths]: Creating temp directory: /home/jesse/output/
[verify/<module>]: Initializing verify...
[verify/<module>]: LVS/DRC/PEX disabled.
[characterizer/<module>]: Initializing characterizer...
[characterizer/<module>]: Finding spice simulator.
[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r
|==============================================================================|
|=========                       OpenRAM v1.1.5                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: openram-user-group@ucsc.edu           =========|
|=========        Development help: openram-dev-group@ucsc.edu        =========|
|=========               Temp dir: /home/jesse/output/                =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 07/01/2020 04:43:37
Technology: sky130
Total size: 256 bits
Word size: 16
Words: 16
Banks: 1
Write size: 8
RW ports: 1
R-only ports: 1
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Performing simulation-based characterization with ngspice
[bitcell_1rw_1r/__init__]: Create bitcell with 1RW and 1R Port
[sram_config/recompute_sizes]: Recomputing with words per row: 1
[sram_config/recompute_sizes]: Rows: 16 Cols: 16
[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
Words per row: 1
Output files are: 
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.sp
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.v
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.lib
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.py
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.html
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.log
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.lef
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.gds
[sram/__init__]: create sram of size 16 with 16 num of words 1 banks
[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
[dff_array/__init__]: Creating data_dff rows=1 cols=16
[dff_array/__init__]: Creating wmask_dff rows=1 cols=2
[bank/__init__]: create sram of size 16 with 16 words
[port_data/__init__]: create data port of size 16 with 1 words per row
[precharge/__init__]: creating precharge cell precharge
[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
[pgate/bin_width]: binning pmos tx, target: 0.55, found 0.55 x 1 = 0.55
[precharge_array/__init__]: Creating precharge_array
[precharge/__init__]: creating precharge cell precharge_0
[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
[sense_amp_array/__init__]: Creating sense_amp_array
[sense_amp/__init__]: Create sense_amp
[write_driver_array/__init__]: Creating write_driver_array
[write_driver/__init__]: Create write_driver
[write_mask_and_array/__init__]: Creating write_mask_and_array
[pand2/__init__]: Creating pand2 pand2
[pnand2/__init__]: creating pnand2 structure pnand2 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12
[pdriver/__init__]: creating pdriver pdriver
[pinv/__init__]: creating pinv structure pinv with size of 2.0
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pgate/bin_width]: binning pmos tx, target: 0.36, found 0.42 x 1 = 0.42
[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pinv/determine_tx_mults]: pinv bin count: 2 pinv bin error: 0.06481481481481488 percent error 0.03240740740740744
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12
[port_data/__init__]: create data port of size 16 with 1 words per row
[precharge_array/__init__]: Creating precharge_array_0
[precharge/__init__]: creating precharge cell precharge_1
[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
[port_address/__init__]: create data port of cols 16 rows 16
[and2_dec/__init__]: Creating and2_dec and2_dec
[pinv_dec/__init__]: creating pinv_dec structure pinv_dec with size of 1
[pinv/__init__]: creating pinv structure pinv_dec with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12
[and3_dec/__init__]: Creating and3_dec and3_dec
[wordline_driver_array/__init__]: Creating wordline_driver_array
[wordline_driver/__init__]: Creating wordline_driver wordline_driver
[pinv_dec/__init__]: creating pinv_dec structure pinv_dec_0 with size of 16
[pinv/__init__]: creating pinv structure pinv_dec_0 with size of 16
[pgate/bin_width]: binning nmos tx, target: 5.76, found 7.0 x 1 = 7.0
[pgate/bin_width]: binning pmos tx, target: 17.28, found 7.0 x 3 = 21.0
[pgate/bin_width]: binning nmos tx, target: 7.0, found 7.0 x 1 = 7.0
[pgate/bin_width]: binning pmos tx, target: 7.0, found 7.0 x 1 = 7.0
[replica_bitcell_array/__init__]: Creating replica_bitcell_array 16 x 16
[bitcell_base_array/__init__]: Creating bitcell_array 16 x 16
[replica_bitcell_1rw_1r/__init__]: Create replica bitcell 1rw+1r object
[dummy_bitcell_1rw_1r/__init__]: Create dummy bitcell 1rw+1r object
[col_cap_bitcell_1rw_1r/__init__]: Create col_cap bitcell 1rw+1r object
[bitcell_base_array/__init__]: Creating dummy_array 1 x 16
[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16
[bitcell_base_array/__init__]: Creating row_cap_array 20 x 1
[row_cap_bitcell_1rw_1r/__init__]: Create row_cap bitcell 1rw+1r object
[bitcell_base_array/__init__]: Creating row_cap_array_0 20 x 1
[control_logic/__init__]: Creating control_logic_rw
[dff_buf/__init__]: Creating dff_buf
[pinv/__init__]: creating pinv structure pinv_0 with size of 2
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pinv/determine_tx_mults]: pinv bin count: 4 pinv bin error: 0.12962962962962976 percent error 0.03240740740740744
[pinv/__init__]: creating pinv structure pinv_1 with size of 4
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999
[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
[pinv/determine_tx_mults]: pinv bin count: 6 pinv bin error: 0.44212962962962954 percent error 0.07368827160493825
[pgate/bin_width]: binning nmos tx, target: 1.68, found 1.68 x 1 = 1.68
[pgate/bin_width]: binning pmos tx, target: 1.6499999999999997, found 1.65 x 1 = 1.65
[dff_buf_array/__init__]: Creating dff_buf_array
[dff_buf/__init__]: Creating dff_buf_0
[pand2/__init__]: Creating pand2 pand2_0
[pnand2/__init__]: creating pnand2 structure pnand2_0 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pdriver/__init__]: creating pdriver pdriver_0
[pinv/__init__]: creating pinv structure pinv_2 with size of 12
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0
[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04
[pinv/determine_tx_mults]: pinv bin count: 8 pinv bin error: 0.6890432098765432 percent error 0.0861304012345679
[pgate/bin_width]: binning nmos tx, target: 1.68, found 1.68 x 1 = 1.68
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pbuf/__init__]: creating pbuf with size of 16
[pinv/__init__]: creating pinv structure pinv_3 with size of 16
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0
[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0
[pinv/determine_tx_mults]: pinv bin count: 10 pinv bin error: 0.7723765432098766 percent error 0.07723765432098766
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pdriver/__init__]: creating pdriver pdriver_1
[pinv/__init__]: creating pinv structure pinv_4 with size of 1
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pinv/determine_tx_mults]: pinv bin count: 12 pinv bin error: 0.8094135802469137 percent error 0.0674511316872428
[pinv/__init__]: creating pinv structure pinv_5 with size of 1
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pinv/determine_tx_mults]: pinv bin count: 14 pinv bin error: 0.8464506172839508 percent error 0.06046075837742505
[pinv/__init__]: creating pinv structure pinv_6 with size of 4
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999
[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
[pinv/determine_tx_mults]: pinv bin count: 16 pinv bin error: 1.1589506172839505 percent error 0.07243441358024691
[pinv/__init__]: creating pinv structure pinv_7 with size of 13
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 14.04, found 2.0 x 8 = 16.0
[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.68, found 1.68 x 3 = 5.04
[pinv/determine_tx_mults]: pinv bin count: 18 pinv bin error: 1.3754748338081673 percent error 0.07641526854489818
[pgate/bin_width]: binning nmos tx, target: 1.68, found 1.68 x 1 = 1.68
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pinv/__init__]: creating pinv structure pinv_8 with size of 38
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 41.04, found 2.0 x 21 = 42.0
[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.68, found 2.0 x 7 = 14.0
[pinv/determine_tx_mults]: pinv bin count: 20 pinv bin error: 1.4222584595391614 percent error 0.07111292297695807
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pdriver/__init__]: creating pdriver pdriver_2
[pinv/__init__]: creating pinv structure pinv_9 with size of 2
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pinv/determine_tx_mults]: pinv bin count: 22 pinv bin error: 1.4870732743539763 percent error 0.06759423974336255
[pinv/__init__]: creating pinv structure pinv_10 with size of 5
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 5.3999999999999995, found 2.0 x 3 = 6.0
[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.7999999999999998, found 2.0 x 1 = 2.0
[pinv/determine_tx_mults]: pinv bin count: 24 pinv bin error: 1.7092954965761986 percent error 0.07122064569067495
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pand3/__init__]: Creating pand3 pand3
[pnand3/__init__]: creating pnand3 structure pnand3 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
[pdriver/__init__]: creating pdriver pdriver_3
[pinv/__init__]: creating pinv structure pinv_11 with size of 24
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 25.919999999999998, found 2.0 x 13 = 26.0
[pinv/determine_tx_mults]: prebinning nmos tx, target: 8.64, found 2.0 x 5 = 10.0
[pinv/determine_tx_mults]: pinv bin count: 26 pinv bin error: 1.8697893237366925 percent error 0.07191497398987279
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pand3/__init__]: Creating pand3 pand3_0
[pdriver/__init__]: creating pdriver pdriver_4
[pinv/__init__]: creating pinv structure pinv_12 with size of 16
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0
[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0
[pinv/determine_tx_mults]: pinv bin count: 28 pinv bin error: 1.9531226570700257 percent error 0.06975438060964377
[pinv/__init__]: creating pinv structure pinv_13 with size of 1
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pinv/determine_tx_mults]: pinv bin count: 30 pinv bin error: 1.9901596941070627 percent error 0.06633865647023543
[pnand2/__init__]: creating pnand2 structure pnand2_1 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
[pinv/__init__]: creating pinv structure pinv_14 with size of 1
[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pinv/determine_tx_mults]: pinv bin count: 32 pinv bin error: 2.0271967311441 percent error 0.06334989784825312
[control_logic/__init__]: Creating control_logic_r
[dff_buf_array/__init__]: Creating dff_buf_array_0
[pdriver/__init__]: creating pdriver pdriver_5
[pinv/__init__]: creating pinv structure pinv_15 with size of 12
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0
[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04
[pinv/determine_tx_mults]: pinv bin count: 34 pinv bin error: 2.2741103113910133 percent error 0.06688559739385333
[pinv/__init__]: creating pinv structure pinv_16 with size of 37
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
[pinv/determine_tx_mults]: prebinning pmos tx, target: 39.96, found 2.0 x 20 = 40.0
[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.32, found 2.0 x 7 = 14.0
[pinv/determine_tx_mults]: pinv bin count: 36 pinv bin error: 2.3261623634430655 percent error 0.06461562120675182
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
** Submodules: 8.6 seconds
** Placement: 0.0 seconds
*** Init supply router: 56.2 seconds
[supply_hannan_router/route]: Running hannan supply router on vdd and gnd...
[supply_hannan_router/retrieve_pins]: Retrieving pins for vdd.
[supply_hannan_router/retrieve_pins]: Retrieving pins for gnd.
[supply_hannan_router/route]: Building matrix
