diff --git a/modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/python/post_processing.ipynb b/modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/python/post_processing.ipynb
index 1d7f5d26..170e737d 100644
--- a/modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/python/post_processing.ipynb
+++ b/modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/python/post_processing.ipynb
@@ -196,7 +196,7 @@
   {
    "cell_type": "code",
    "execution_count": null,
-   "id": "2a7c33e2-fd3d-43be-ab3f-d1f630d38efa",
+   "id": "404c4379-5644-49e8-bae3-b8f6ac8e6285",
    "metadata": {},
    "outputs": [],
    "source": []
@@ -204,15 +204,7 @@
   {
    "cell_type": "code",
    "execution_count": null,
-   "id": "b1c0d2a7-82ae-4713-be1f-be941dc23ba5",
-   "metadata": {},
-   "outputs": [],
-   "source": []
-  },
-  {
-   "cell_type": "code",
-   "execution_count": null,
-   "id": "ea02aa0a-f209-45d3-b321-0188bfec0304",
+   "id": "c99051b8-3609-4599-81e0-17041ebbfa01",
    "metadata": {},
    "outputs": [],
    "source": []
diff --git a/modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/schematic/compression_1/harmonic_balance.sch b/modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/schematic/compression_1/harmonic_balance.sch
index a342b089..9f44b8af 100644
--- a/modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/schematic/compression_1/harmonic_balance.sch
+++ b/modules/module_2_50GHz_MPA/part_3_nonlinear_analysis/schematic/compression_1/harmonic_balance.sch
@@ -1,6 +1,6 @@
 <Qucs Schematic 24.4.1>
 <Properties>
-  <View=684,-224,3196,1235,0.598379,0,61>
+  <View=384,-924,4780,1451,0.732959,550,583>
   <Grid=10,10,1>
   <DataSet=harmonic_balance.dat>
   <DataDisplay=harmonic_balance.dpl>
@@ -40,7 +40,7 @@
   <GND * 1 1330 500 0 0 0 0>
   <Iac I1 1 1330 450 20 -26 0 1 "y" 1 "50e9" 0 "0" 0 "0" 0>
   <.SW SW1 1 1280 -60 0 61 0 0 "HB1" 1 "lin" 1 "y" 1 "0.0001" 1 "0.05" 1 "51" 1>
-  <SpicePar SpicePar1 1 1070 410 -28 16 0 0 "y=1" 1>
+  <SpicePar SpicePar1 1 1460 490 -28 16 0 0 "y=1" 1>
 </Components>
 <Wires>
   <1780 320 1780 400 "" 0 0 0 "">
@@ -76,10 +76,10 @@
   <1920 260 1920 260 "Vcc" 1950 230 0 "">
 </Wires>
 <Diagrams>
-  <Rect 2060 630 240 160 3 #c0c0c0 1 00 1 -2.5e+11 1e+11 2.5e+11 1 -0.173797 1 2 1 -1 1 1 315 0 225 1 0 0 "" "" "">
+  <Rect 2060 630 240 160 3 #c0c0c0 1 00 1 -2.5e+11 1e+11 2.5e+11 1 -0.468251 2 5.15076 1 -1 1 1 315 0 225 1 0 0 "" "" "">
 	<"xyce/V(VIN)" #0000ff 0 3 0 6 0>
   </Rect>
-  <Rect 2060 430 240 160 3 #c0c0c0 1 00 1 -2.5e+11 1e+11 2.5e+11 1 -0.0005 0.002 0.006 1 -1 1 1 315 0 225 1 0 0 "" "" "">
+  <Rect 2060 430 240 160 3 #c0c0c0 1 00 1 -2.5e+11 1e+11 2.5e+11 1 -0.0025 0.02 0.0275 1 -1 1 1 315 0 225 1 0 0 "" "" "">
 	<"xyce/I(PR2)" #0000ff 0 3 0 6 0>
   </Rect>
   <Rect 2360 430 240 160 3 #c0c0c0 1 00 1 -2.5e+11 1e+11 2.5e+11 1 -0.0005 0.002 0.006 1 -1 1 1 315 0 225 1 0 0 "" "" "">
diff --git a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sch b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sch
index 22b998b1..08ccdea3 100644
--- a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sch
+++ b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sch
@@ -153,7 +153,7 @@ C {opin.sym} 140 -470 0 1 {name=p8 lab=out+}
 C {lab_pin.sym} 650 -570 3 0 {name=p9 sig_type=std_logic lab=vdd}
 C {lab_pin.sym} 700 -740 2 0 {name=p10 sig_type=std_logic lab=vdd}
 C {sg13g2_pr/sg13_lv_pmos.sym} 630 -740 0 0 {name=M13
-l=0.300u
+l=0.3u
 w=18u
 ng=4
 m=1
diff --git a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/comparator_tb.sch b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/comparator_tb.sch
index 33e9d7af..49597aaa 100644
--- a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/comparator_tb.sch
+++ b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/comparator_tb.sch
@@ -5,14 +5,14 @@ V {}
 S {}
 E {}
 B 2 20 -1225 820 -825 {flags=graph
-y1=0.046228722
-y2=1.0862287
+y1=0
+y2=1.3
 ypos1=0
 ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=0
+x1=-1e-07
 
 divx=5
 subdivx=4
@@ -24,10 +24,10 @@ dataset=-1
 unitx=1
 logx=0
 logy=0
-x2=1e-06
+x2=9e-07
 color=4
 node=clk}
-B 2 20 -805 820 -405 {flags=graph
+B 2 20 -885 820 -485 {flags=graph
 y1=0.59
 y2=0.61
 ypos1=0
@@ -35,7 +35,7 @@ ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=0
+x1=-1e-07
 
 divx=5
 subdivx=4
@@ -47,7 +47,7 @@ dataset=-1
 unitx=1
 logx=0
 logy=0
-x2=1e-06
+x2=9e-07
 
 
 color=4
@@ -60,7 +60,7 @@ ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=0
+x1=-1e-07
 
 divx=5
 subdivx=4
@@ -72,7 +72,7 @@ dataset=-1
 unitx=1
 logx=0
 logy=0
-x2=1e-06
+x2=9e-07
 
 
 color=4
@@ -85,7 +85,7 @@ ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=0
+x1=-1e-07
 
 divx=5
 subdivx=4
@@ -97,7 +97,7 @@ dataset=-1
 unitx=1
 logx=0
 logy=0
-x2=1e-06
+x2=9e-07
 
 color=4
 node=outp}
@@ -109,7 +109,7 @@ ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=0
+x1=-1e-07
 
 divx=5
 subdivx=4
@@ -121,7 +121,7 @@ dataset=-1
 unitx=1
 logx=0
 logy=0
-x2=1e-06
+x2=9e-07
 
 
 color=4
@@ -185,7 +185,6 @@ lab=GND}
 C {devices/code_shown.sym} -675 -490 0 0 {name=MODEL only_toplevel=false
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
 .lib cornerMOSlv.lib mos_tt
 "}
 C {devices/code_shown.sym} -685 -780 0 0 {name=NGSPICE only_toplevel=false 
@@ -228,24 +227,24 @@ C {lab_pin.sym} 500 -230 2 0 {name=p10 sig_type=std_logic lab=outp}
 C {lab_pin.sym} 500 -210 2 0 {name=p11 sig_type=std_logic lab=outm}
 C {capa.sym} 80 -110 0 0 {name=C1
 m=1
-value=16.384p
+value=6.4p
 footprint=1206
 device="ceramic capacitor"}
 C {gnd.sym} 80 -60 0 0 {name=l4 lab=GND}
 C {gnd.sym} 80 -380 2 0 {name=l5 lab=GND}
 C {capa.sym} 80 -330 2 0 {name=C2
 m=1
-value=16.384p
+value=6.4p
 footprint=1206
 device="ceramic capacitor"}
 C {capa.sym} 460 -260 2 0 {name=C4
 m=1
-value=15f
+value=50f
 footprint=1206
 device="ceramic capacitor"}
 C {capa.sym} 460 -180 0 0 {name=C3
 m=1
-value=15f
+value=50f
 footprint=1206
 device="ceramic capacitor"}
 C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
diff --git a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/offset_MC_analysis.sch b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/offset_MC_analysis.sch
index f2dc22f7..4ecda0b3 100644
--- a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/offset_MC_analysis.sch
+++ b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/offset_MC_analysis.sch
@@ -80,24 +80,24 @@ C {lab_pin.sym} 500 -230 2 0 {name=p10 sig_type=std_logic lab=outp}
 C {lab_pin.sym} 500 -210 2 0 {name=p11 sig_type=std_logic lab=outm}
 C {capa.sym} 80 -110 0 0 {name=C1
 m=1
-value=16.384p
+value=6.4p
 footprint=1206
 device="ceramic capacitor"}
 C {gnd.sym} 80 -60 0 0 {name=l4 lab=GND}
 C {gnd.sym} 80 -380 2 0 {name=l5 lab=GND}
 C {capa.sym} 80 -330 2 0 {name=C2
 m=1
-value=16.384p
+value=6.4p
 footprint=1206
 device="ceramic capacitor"}
 C {capa.sym} 460 -260 2 0 {name=C4
 m=1
-value=10f
+value=50f
 footprint=1206
 device="ceramic capacitor"}
 C {capa.sym} 460 -180 0 0 {name=C3
 m=1
-value=10f
+value=50f
 footprint=1206
 device="ceramic capacitor"}
 C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
diff --git a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/statistical_calculation/histogram_plots/histogram.png b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/statistical_calculation/histogram_plots/histogram.png
index 7f55ee85..162b399d 100644
Binary files a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/statistical_calculation/histogram_plots/histogram.png and b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/statistical_calculation/histogram_plots/histogram.png differ
diff --git a/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/SAR_ADC_tb.sch b/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/SAR_ADC_tb.sch
index 1c0d77b4..a946f38e 100644
--- a/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/SAR_ADC_tb.sch
+++ b/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/SAR_ADC_tb.sch
@@ -28,8 +28,8 @@ cdac_v-"
 hilight_wave=0
 hcursor1_y=1.2502139}
 B 2 2015 -1430 2815 -1030 {flags=graph
-y1=-0.6
-y2=0.6
+y1=-0.36
+y2=0.84
 ypos1=0
 ypos2=2
 divy=5
@@ -115,12 +115,8 @@ N 1750 -1090 1750 -1060 {lab=clk_comp}
 N 260 -1240 260 -1220 {lab=bias}
 N 260 -1160 260 -1150 {lab=GND}
 N 900 -1040 900 -1020 {lab=clk_samp}
-N 1940 -1210 1940 -1180 {lab=Op}
-N 1900 -1180 1940 -1180 {lab=Op}
-N 1940 -1160 1940 -1130 {lab=Om}
-N 1900 -1160 1940 -1160 {lab=Om}
-N 1940 -1290 1940 -1270 {lab=GND}
-N 1940 -1070 1940 -1050 {lab=GND}
+N 1900 -1180 1950 -1180 {lab=Op}
+N 1900 -1160 1950 -1160 {lab=Om}
 N 920 -1230 1040 -1230 {lab=#net25}
 N 1300 -1330 1300 -1290 {lab=vdd}
 N 1300 -1330 1370 -1330 {lab=vdd}
@@ -146,8 +142,6 @@ N 1300 -1050 1300 -1020 {lab=vdd}
 N 1370 -1020 1370 -870 {lab=vdd}
 N 1360 -1230 1620 -1230 {lab=CDAC_v+}
 N 1360 -1110 1620 -1110 {lab=CDAC_v-}
-N 1940 -1180 1950 -1180 {lab=Op}
-N 1940 -1160 1950 -1160 {lab=Om}
 N 300 -1240 300 -1220 {lab=clk_samp}
 N 300 -1180 300 -1150 {lab=GND}
 N 300 -980 300 -960 {lab=dac_clk}
@@ -291,18 +285,6 @@ C {devices/lab_pin.sym} 260 -1240 2 1 {name=p68 sig_type=std_logic lab=bias}
 C {devices/lab_pin.sym} 900 -1140 2 0 {name=p22 sig_type=std_logic lab=clk_samp}
 C {devices/lab_pin.sym} 840 -1020 2 0 {name=p21 sig_type=std_logic lab=vdd}
 C {devices/lab_pin.sym} 900 -1020 2 0 {name=p23 sig_type=std_logic lab=clk_samp}
-C {capa.sym} 1940 -1240 2 0 {name=C1
-m=1
-value=50f
-footprint=1206
-device="ceramic capacitor"}
-C {capa.sym} 1940 -1100 0 0 {name=C2
-m=1
-value=50f
-footprint=1206
-device="ceramic capacitor"}
-C {gnd.sym} 1940 -1050 0 1 {name=l5 lab=GND}
-C {gnd.sym} 1940 -1290 2 1 {name=l14 lab=GND}
 C {devices/lab_pin.sym} 1400 -1230 3 1 {name=p74 sig_type=std_logic lab=CDAC_v+}
 C {devices/lab_pin.sym} 1400 -1110 1 1 {name=p73 sig_type=std_logic lab=CDAC_v-}
 C {devices/lab_pin.sym} 700 -1230 2 1 {name=p25 sig_type=std_logic lab=vin_pos}
diff --git a/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/SAR_ADC.md b/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc.md
similarity index 100%
rename from modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/SAR_ADC.md
rename to modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc.md