diff --git a/modules/module_0_foundations/inverter/inverter.sch b/modules/module_0_foundations/PEX/inverter/inverter.sch
similarity index 100%
rename from modules/module_0_foundations/inverter/inverter.sch
rename to modules/module_0_foundations/PEX/inverter/inverter.sch
diff --git a/modules/module_0_foundations/inverter/inverter.sym b/modules/module_0_foundations/PEX/inverter/inverter.sym
similarity index 100%
rename from modules/module_0_foundations/inverter/inverter.sym
rename to modules/module_0_foundations/PEX/inverter/inverter.sym
diff --git a/modules/module_0_foundations/inverter/inverter_tb.sch b/modules/module_0_foundations/PEX/inverter/inverter_tb.sch
similarity index 100%
rename from modules/module_0_foundations/inverter/inverter_tb.sch
rename to modules/module_0_foundations/PEX/inverter/inverter_tb.sch
diff --git a/modules/module_0_foundations/inverter/xschemrc b/modules/module_0_foundations/PEX/inverter/xschemrc
similarity index 100%
rename from modules/module_0_foundations/inverter/xschemrc
rename to modules/module_0_foundations/PEX/inverter/xschemrc
diff --git a/modules/module_0_foundations/inverter_example/inverter.sch b/modules/module_0_foundations/inverter_example/inverter.sch
new file mode 100644
index 00000000..6bd2b256
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/inverter.sch
@@ -0,0 +1,50 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 330 -280 370 -280 {lab=Vin}
+N 330 -280 330 -190 {lab=Vin}
+N 330 -190 370 -190 {lab=Vin}
+N 410 -230 490 -230 {lab=Vout}
+N 410 -230 410 -220 {lab=Vout}
+N 410 -250 410 -230 {lab=Vout}
+N 410 -160 410 -130 {lab=Gnd}
+N 410 -340 410 -310 {lab=Vdd}
+N 410 -280 520 -280 {lab=#net1}
+N 410 -340 520 -340 {lab=Vdd}
+N 410 -190 520 -190 {lab=#net2}
+N 410 -130 520 -130 {lab=Gnd}
+C {sg13g2_pr/sg13_lv_nmos.sym} 390 -190 0 0 {name=M1
+l=0.45u
+w=1.0u
+ng=1
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} 390 -280 0 0 {name=M2
+l=0.45u
+w=2.0u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {iopin.sym} 490 -230 2 1 {name=p2 lab=Vout}
+C {iopin.sym} 410 -340 2 0 {name=p5 lab=Vdd}
+C {iopin.sym} 330 -240 2 0 {name=p6 lab=Vin}
+C {iopin.sym} 410 -130 2 0 {name=p1 lab=Gnd}
+C {sg13g2_pr/ntap1.sym} 520 -310 0 0 {name=R1
+model=ntap1
+spiceprefix=X
+w=0.78e-6
+l=0.78e-6
+}
+C {sg13g2_pr/ptap1.sym} 520 -160 2 1 {name=R2
+model=ptap1
+spiceprefix=X
+w=0.78e-6
+l=0.78e-6
+}
diff --git a/modules/module_0_foundations/inverter_example/inverter.sym b/modules/module_0_foundations/inverter_example/inverter.sym
new file mode 100644
index 00000000..a911df0e
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/inverter.sym
@@ -0,0 +1,26 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"}
+V {}
+S {}
+E {}
+L 7 -70 -80 -70 -60 {}
+L 7 -150 0 -130 0 {}
+L 7 110 0 130 0 {}
+L 7 -70 70 -70 90 {}
+B 5 -72.5 -82.5 -67.5 -77.5 {name=Vdd dir=inout}
+B 5 -152.5 -2.5 -147.5 2.5 {name=Vin dir=inout}
+B 5 127.5 -2.5 132.5 2.5 {name=Vout dir=inout}
+B 5 -72.5 87.5 -67.5 92.5 {name=Gnd dir=inout}
+A 4 105 0 7.071067811865476 135 360 {}
+P 4 5 100 0 -130 -80 -130 90 100 0 100 0 {}
+T {@symname
+
+} -84 -6 0 0 0.3 0.3 {}
+T {@name} -45 -32 0 0 0.2 0.2 {}
+T {Vdd} -74 -55 3 1 0.2 0.2 {}
+T {Vin} -125 -4 0 0 0.2 0.2 {}
+T {Vout} 80 -9 0 1 0.2 0.2 {}
+T {Gnd} -66 65 1 1 0.2 0.2 {}
diff --git a/modules/module_0_foundations/inverter_example/inverter_tb.sch b/modules/module_0_foundations/inverter_example/inverter_tb.sch
new file mode 100644
index 00000000..8b83cd4b
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/inverter_tb.sch
@@ -0,0 +1,87 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+B 2 710 -550 1510 -150 {flags=graph
+y1=-0.0023
+y2=1.3
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=2e-06
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+node=vout
+color=4
+dataset=-1
+unitx=1
+logx=0
+logy=0
+}
+N 150 -170 150 -140 {lab=Vin}
+N 70 -170 70 -140 {lab=Vdd}
+N 70 -80 70 -60 {lab=GND}
+N 110 -60 150 -60 {lab=GND}
+N 150 -80 150 -60 {lab=GND}
+N 110 -60 110 -50 {lab=GND}
+N 70 -60 110 -60 {lab=GND}
+N 320 -410 320 -380 {lab=Vdd}
+N 320 -210 320 -190 {lab=GND}
+N 220 -300 240 -300 {lab=Vin}
+N 520 -300 540 -300 {lab=Vout}
+C {vsource.sym} 150 -110 0 0 {name=V1 value="PULSE(0 1.2 0.5u 10n 10n 1u 2u 1)" savecurrent=false}
+C {vsource.sym} 70 -110 0 0 {name=V2 value=1.2 savecurrent=false}
+C {gnd.sym} 110 -50 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 150 -170 0 0 {name=p1 sig_type=std_logic lab=Vin}
+C {lab_pin.sym} 70 -170 0 0 {name=p3 sig_type=std_logic lab=Vdd}
+C {code_shown.sym} 40 -540 0 0 {name=NGSPICE
+only_toplevel=true
+value="
+.control
+save all
+tran 50n 2u 
+write test_inverter.raw
+.endc
+" }
+C {devices/code_shown.sym} 280 -540 0 0 {name=MODEL only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib cornerMOSlv.lib mos_tt
+.lib cornerRES.lib res_typ
+
+"}
+C {launcher.sym} 770 -120 0 0 {name=h5
+descr="load waves" 
+tclcommand="xschem raw_read $netlist_dir/test_inverter.raw tran"
+}
+C {inverter.sym} 390 -300 0 0 {name=x1}
+C {lab_pin.sym} 220 -300 0 0 {name=p2 sig_type=std_logic lab=Vin}
+C {gnd.sym} 320 -190 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 320 -410 0 0 {name=p4 sig_type=std_logic lab=Vdd}
+C {lab_pin.sym} 540 -300 0 1 {name=p5 sig_type=std_logic lab=Vout}
+C {inverter.sym} 590 -10 0 0 {name=x2
+
+* NGSPICE file created from inverter.ext - technology: ihp-sg13g2
+
+.subckt inverter_pex Vdd Vin Vout Gnd
+X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
+X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
+C0 Vout Vin 0.10077f
+C1 Vin Vdd 0.14482f
+C2 Vout Vdd 0.13155f
+R0 Vin Vin.n0 7.52248
+C3 Vout Gnd 0.39245f
+C4 Vin Gnd 0.64666f
+C5 Vdd Gnd 0.15308f
+.ends
+
+
+
+}
diff --git a/modules/module_0_foundations/inverter_example/layout/inverter.gds b/modules/module_0_foundations/inverter_example/layout/inverter.gds
new file mode 100644
index 00000000..c5e1d2ac
Binary files /dev/null and b/modules/module_0_foundations/inverter_example/layout/inverter.gds differ
diff --git a/modules/module_0_foundations/inverter_example/layout/inverter_extracted.cir b/modules/module_0_foundations/inverter_example/layout/inverter_extracted.cir
new file mode 100644
index 00000000..d4acf2dc
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/layout/inverter_extracted.cir
@@ -0,0 +1,10 @@
+* Extracted by KLayout with SG13G2 LVS runset on : 07/07/2025 16:12
+
+.SUBCKT inverter Gnd Vout Vin Vdd
+M$1 Gnd Vin Vout \$1 sg13_lv_nmos L=0.45u W=1u AS=0.34p AD=0.34p PS=2.68u
++ PD=2.68u
+M$2 Vdd Vin Vout \$2 sg13_lv_pmos L=0.45u W=2u AS=0.68p AD=0.68p PS=4.68u
++ PD=4.68u
+R$3 \$2 Vdd ntap1 A=0.6084p P=3.12u
+R$4 \$1 Gnd ptap1 A=0.6084p P=3.12u
+.ENDS inverter
diff --git a/modules/module_0_foundations/inverter_example/layout/inverter_flat.gds b/modules/module_0_foundations/inverter_example/layout/inverter_flat.gds
new file mode 100644
index 00000000..cbd1ef23
Binary files /dev/null and b/modules/module_0_foundations/inverter_example/layout/inverter_flat.gds differ
diff --git a/modules/module_0_foundations/inverter_example/pex/kpex.sh b/modules/module_0_foundations/inverter_example/pex/kpex.sh
new file mode 100755
index 00000000..66e40b0a
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/kpex.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+set -e
+
+# Hardcoded paths (except PDK stuff)
+PYTHON_ENV="/home/pedersen/misc/klayout_pex/bin/activate"
+KPEX_MAGIC_EXE="/home/pedersen/.local/bin/magic"
+LAYOUT_PATH="../layout/inverter.gds"
+SCHEMATIC="../simulations/inverter.spice"
+
+
+PDK_NAME="ihp_sg13g2"
+MAGICRC="$PDK_ROOT/$PDK_NAME/libs.tech/magic/ihp-sg13g2.magicrc"
+
+# Activate Python environment
+source "$PYTHON_ENV"
+
+# Run parasitic extraction with kpex
+kpex \
+  --pdk "$PDK_NAME" \
+  --magic \
+  --schematic "$SCHEMATIC" \
+  --gds "$LAYOUT_PATH" \
+  --magicrc "$MAGICRC" \
+  --magic_mode RC \
+  --magic_cthresh 0.02 \
+  --magic_rthresh 50 \
+  --magic_short resistor \
+  --magic_merge conservative \
+  --out_dir ./pex_output
+
diff --git a/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.ext b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.ext
new file mode 100644
index 00000000..6d6be98c
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.ext
@@ -0,0 +1,23 @@
+timestamp 0
+version 8.3
+tech ihp-sg13g2
+style ngspice()
+scale 1000 1 0.5
+resistclasses 3000000 67000 110 88 88 88 88 18 11
+parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
+port "Vout" 2 266 -211 298 -173 m1
+port "Vin" 3 95 -213 127 -175 m1
+port "Vdd" 5 -205 318 -173 356 m1
+port "Gnd" 4 20 -732 52 -694 m1
+node "ptap1_0.sub!" 0 0 28 -796 isosub 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 1 392.446 266 -211 m1 0 0 0 0 91916 2354 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 0 646.659 95 -213 m1 0 0 0 0 13590 482 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vdd" 1 153.076 -205 318 m1 0 0 0 0 42800 1364 0 0 0 0 0 0 0 0 0 0 0 0
+equiv "Vdd" "ntap1_0.well"
+substrate "Gnd" 0 0 20 -732 m1 0 0 0 0 21536 1036 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vdd" "Vin" 144.819
+cap "Vdd" "Vout" 131.55
+cap "Vout" "Vin" 100.772
+device msubckt sg13_lv_nmos 67 -562 68 -561 l=90 w=200 "Gnd" "Vin" 180 0 "Gnd" 200 13600,536 "Vout" 200 13600,536
+device msubckt sg13_lv_pmos 67 9 68 10 l=90 w=400 "Vdd" "Vin" 180 0 "Vdd" 400 27200,936 "Vout" 400 27200,936
diff --git a/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.res.ext b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.res.ext
new file mode 100644
index 00000000..bd9d4315
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.res.ext
@@ -0,0 +1,28 @@
+scale 1000 1 0.5
+rnode "Gnd.t1" 0 0 29 -462 0
+rnode "Gnd.t0" 0 0 112 -462 0
+rnode "Gnd.n0" 0 0 62 -754 0
+rnode "Gnd" 0 0 20 -732 0
+resist "Gnd" "Gnd.n0" 0.0257609
+resist "Gnd.n0" "Gnd.t1" 6.29433
+resist "Gnd.n0" "Gnd.t0" 1079.2
+rnode "Vout.t1" 0 0 195 311 0
+rnode "Vout.t0" 0 0 195 -462 0
+rnode "Vout" 0 0 266 -211 0
+resist "Vout" "Vout.t1" 3.28762
+resist "Vout" "Vout.t0" 6.19274
+rnode "Vdd" 0 0 -205 318 0
+rnode "Vdd.t0" 0 0 29 379 0
+rnode "Vdd.n0" 0 0 -153 379 0
+rnode "Vdd.n1" 0 0 -153 379 0
+rnode "ntap1_0.well" 0 0 112 209 0
+resist "Vdd.n0" "Vdd" 0.0476667
+resist "Vdd.n0" "Vdd.t0" 3.15328
+resist "ntap1_0.well" "Vdd.n1" 4.25
+resist "Vdd.n1" "Vdd.n0" 8.5
+resist "Vdd.n1" "Vdd" 8.51467
+rnode "Vin.t0" 0 0 111 -158 0
+rnode "Vin" 0 0 95 -213 0
+resist "Vin" "Vin.t0" 7.52198
+device msubckt sg13_lv_nmos 67 -562 68 -561  "Gnd.t0" "Vin.t0" 180 0 "Gnd.t1" 200 13600,536 "Vout.t0" 200 13600,536
+device msubckt sg13_lv_pmos 67 9 68 10  "ntap1_0.well" "Vin.t0" 180 0 "Vdd.t0" 400 27200,936 "Vout.t1" 400 27200,936
diff --git a/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl
new file mode 100644
index 00000000..f1b9136a
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl
@@ -0,0 +1,25 @@
+# Generated by kpex 0.3.7
+crashbackups stop
+drc off
+gds read /home/pedersen/misc/inverter_example/layout/inverter.gds
+load inverter
+select top cell
+flatten inverter_flat
+load inverter_flat
+cellname delete inverter -noprompt
+cellname rename inverter_flat inverter
+select top cell
+extract path /home/pedersen/misc/inverter_example/pex/pex_output/inverter__inverter/magic_RC
+extract all
+ext2sim labels on
+ext2sim -p /home/pedersen/misc/inverter_example/pex/pex_output/inverter__inverter/magic_RC
+extresist tolerance 1
+extresist all
+ext2spice short resistor
+ext2spice merge conservative
+ext2spice cthresh 0.02
+ext2spice extresist on
+ext2spice subcircuits top on
+ext2spice format ngspice
+ext2spice -p /home/pedersen/misc/inverter_example/pex/pex_output/inverter__inverter/magic_RC -o /home/pedersen/misc/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter.pex.spice
+quit -noprompt
diff --git a/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz
new file mode 100644
index 00000000..69d9e25f
Binary files /dev/null and b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter__inverter/magic_RC/inverter_MAGIC_report.rdb.gz differ
diff --git a/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter.ext b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter.ext
new file mode 100644
index 00000000..7c84aff7
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter.ext
@@ -0,0 +1,24 @@
+timestamp 0
+version 8.3
+tech ihp-sg13g2
+style ngspice()
+scale 1000 1 0.5
+resistclasses 3000000 67000 110 88 88 88 88 18 11
+parameters sg13_lv_nmos l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sg13_lv_pmos l=l w=w a1=as p1=ps a2=ad p2=pd
+port "Vout" 3 266 -211 298 -173 m1
+port "Vin" 4 95 -213 127 -175 m1
+port "Vdd" 6 -237 285 -137 405 m1
+port "well" 2 -265 267 -109 423 nw
+port "Gnd" 5 -22 -770 78 -670 m1
+node "sub!" 0 0 28 -796 isosub 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 1 392.446 266 -211 m1 0 0 0 0 91916 2354 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 0 646.659 95 -213 m1 0 0 0 0 13590 482 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vdd" 1 153.076 -237 285 m1 0 0 0 0 42800 1364 0 0 0 0 0 0 0 0 0 0 0 0
+equiv "Vdd" "well"
+substrate "Gnd" 0 0 -22 -770 m1 0 0 0 0 21536 1036 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vout" "Vdd" 131.55
+cap "Vout" "Vin" 100.772
+cap "Vdd" "Vin" 144.819
+device msubckt sg13_lv_nmos 67 -562 68 -561 l=90 w=200 "Gnd" "Vin" 180 0 "Gnd" 200 13600,536 "Vout" 200 13600,536
+device msubckt sg13_lv_pmos 67 9 68 10 l=90 w=400 "Vdd" "Vin" 180 0 "Vdd" 400 27200,936 "Vout" 400 27200,936
diff --git a/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter.res.ext b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter.res.ext
new file mode 100644
index 00000000..7e5187e5
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter.res.ext
@@ -0,0 +1,28 @@
+scale 1000 1 0.5
+rnode "well" 0 0 -265 267 0
+rnode "Vdd" 0 -0 -237 285 0
+resist "Vdd" "well" 8.53119
+rnode "Gnd.t1" 0 0 29 -462 0
+rnode "Gnd.t0" 0 0 112 -462 0
+rnode "Gnd.n0" 0 0 62 -754 0
+rnode "Gnd" 0 0 -22 -770 0
+resist "Gnd" "Gnd.n0" 0.055709
+resist "Gnd.n0" "Gnd.t1" 6.307
+resist "Gnd.n0" "Gnd.t0" 1079.19
+rnode "Vout.t1" 0 0 195 311 0
+rnode "Vout.t0" 0 0 195 -462 0
+rnode "Vout" 0 0 266 -211 0
+resist "Vout" "Vout.t1" 3.28762
+resist "Vout" "Vout.t0" 6.19274
+rnode "Vdd" 0 0 -237 285 0
+rnode "Vdd.t0" 0 0 29 379 0
+rnode "Vdd.n0" 0 0 -153 379 0
+rnode "well" 0 0 112 209 0
+resist "Vdd.n0" "Vdd" 0.0465926
+resist "Vdd.n0" "Vdd.t0" 3.18546
+resist "well" "Vdd.n0" 8.48516
+rnode "Vin.t0" 0 0 111 -158 0
+rnode "Vin" 0 0 95 -213 0
+resist "Vin" "Vin.t0" 7.52198
+device msubckt sg13_lv_nmos 67 -562 68 -561  "Gnd.t0" "Vin.t0" 180 0 "Gnd.t1" 200 13600,536 "Vout.t0" 200 13600,536
+device msubckt sg13_lv_pmos 67 9 68 10  "well" "Vin.t0" 180 0 "Vdd.t0" 400 27200,936 "Vout.t1" 400 27200,936
diff --git a/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl
new file mode 100644
index 00000000..4e277c56
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter_MAGIC_RC_Script.tcl
@@ -0,0 +1,25 @@
+# Generated by kpex 0.3.7
+crashbackups stop
+drc off
+gds read /home/pedersen/misc/inverter_example/layout/inverter_flat.gds
+load inverter
+select top cell
+flatten inverter_flat
+load inverter_flat
+cellname delete inverter -noprompt
+cellname rename inverter_flat inverter
+select top cell
+extract path /home/pedersen/misc/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC
+extract all
+ext2sim labels on
+ext2sim -p /home/pedersen/misc/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC
+extresist tolerance 1
+extresist all
+ext2spice short resistor
+ext2spice merge conservative
+ext2spice cthresh 0.02
+ext2spice extresist on
+ext2spice subcircuits top on
+ext2spice format ngspice
+ext2spice -p /home/pedersen/misc/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC -o /home/pedersen/misc/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter.pex.spice
+quit -noprompt
diff --git a/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter_MAGIC_report.rdb.gz b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter_MAGIC_report.rdb.gz
new file mode 100644
index 00000000..9e99b475
Binary files /dev/null and b/modules/module_0_foundations/inverter_example/pex/pex_output/inverter_flat__inverter/magic_RC/inverter_MAGIC_report.rdb.gz differ
diff --git a/modules/module_0_foundations/inverter_example/pex/python/insert_netlist_to_sym.py b/modules/module_0_foundations/inverter_example/pex/python/insert_netlist_to_sym.py
new file mode 100644
index 00000000..8c69e8f3
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/python/insert_netlist_to_sym.py
@@ -0,0 +1,74 @@
+import sys
+import os
+
+def extract_netlist_and_topcell(spice_path):
+    with open(spice_path, 'r') as f:
+        lines = f.readlines()
+
+    netlist = []
+    topcell = None
+    inside_subckt = False
+
+    for line in lines:
+        if line.strip().startswith(".subckt"):
+            parts = line.strip().split()
+            if len(parts) > 1:
+                topcell = parts[1]
+            inside_subckt = True
+        if inside_subckt:
+            netlist.append(line.rstrip())
+        if line.strip().startswith(".ends"):
+            break
+
+    if not topcell:
+        raise ValueError("Topcell name not found in SPICE file.")
+
+    return topcell, "\n".join(netlist)
+
+def modify_sym_file(sym_path, output_dir, topcell, netlist):
+    with open(sym_path, 'r') as f:
+        sym_lines = f.readlines()
+
+    new_sym_lines = []
+    inserted = False
+
+    for line in sym_lines:
+        if line.strip().startswith("K {type=subcircuit"):
+            new_sym_lines.append(line)
+            continue
+        elif line.strip().startswith("template=") and not inserted:
+            new_template = (
+                f'template="name=x1\n'
+                f'schematic={topcell}\n'
+                f'spice_sym_def=\n'
+                f'\\\\"\n'
+                f'{netlist}\n'
+                f'\\\\"\n'
+                f'"'
+            )
+            new_sym_lines.append(new_template + "\n")
+            inserted = True
+        else:
+            new_sym_lines.append(line)
+
+    filename = os.path.basename(sym_path)
+    out_path = os.path.join(output_dir, filename)
+
+    os.makedirs(output_dir, exist_ok=True)
+
+    with open(out_path, 'w') as f:
+        f.writelines(new_sym_lines)
+
+    print(f"Saved modified .sym to: {out_path}")
+
+if __name__ == "__main__":
+    if len(sys.argv) != 4:
+        print("Usage: python insert_netlist_to_sym.py <netlist.spice> <symbol.sym> <output_folder>")
+        sys.exit(1)
+
+    spice_file = sys.argv[1]
+    sym_file = sys.argv[2]
+    output_folder = sys.argv[3]
+
+    topcell, netlist = extract_netlist_and_topcell(spice_file)
+    modify_sym_file(sym_file, output_folder, topcell, netlist)
diff --git a/modules/module_0_foundations/inverter_example/pex/python/insert_pex_subckt.py b/modules/module_0_foundations/inverter_example/pex/python/insert_pex_subckt.py
new file mode 100644
index 00000000..8a03f7ec
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/python/insert_pex_subckt.py
@@ -0,0 +1,123 @@
+import sys
+import os
+
+def load_text_file(file_path):
+    with open(file_path, 'r') as f:
+        return f.read()
+
+def save_text_file(file_path, text):
+    with open(file_path, 'w') as f:
+        f.write(text)
+
+def read_spice_definition(spice_path):
+    with open(spice_path, "r") as f:
+        lines = f.readlines()
+
+    subckt_line_index = next((i for i, line in enumerate(lines) if line.strip().lower().startswith(".subckt")), None)
+    if subckt_line_index is None:
+        raise ValueError(f"No .subckt line found in SPICE file: {spice_path}")
+
+    parts = lines[subckt_line_index].strip().split()
+    subckt_name = parts[1]
+    new_subckt_name = subckt_name
+    parts[1] = new_subckt_name
+    lines[subckt_line_index] = ' '.join(parts) + '\n'
+
+    definition_lines = []
+    recording = False
+    for line in lines:
+        if line.strip().lower().startswith(".subckt"):
+            recording = True
+        if recording:
+            definition_lines.append(line.rstrip())
+        if line.strip().lower() == ".ends":
+            break
+
+    return new_subckt_name, '\n'.join(definition_lines)
+
+def find_subckt_location(subckt_name, schematic_file):
+    text_content = load_text_file(schematic_file)
+    return text_content.find(subckt_name + '.sym')
+
+def find_first_curly_brackets_span(text, start_pos):
+    open_pos = text.find('{', start_pos)
+    if open_pos == -1:
+        return None, None
+
+    depth = 1
+    for i in range(open_pos + 1, len(text)):
+        if text[i] == '{':
+            depth += 1
+        elif text[i] == '}':
+            depth -= 1
+            if depth == 0:
+                return open_pos, i
+    return None, None
+
+def replace_curly_brackets_content(text, start_idx, end_idx, new_content, subckt_name):
+    content = text[start_idx+1:end_idx].strip('\n ')
+    lines = content.splitlines()
+
+    name_line_index = next((i for i, line in enumerate(lines) if line.strip().startswith("name=")), None)
+    schematic_line = "schematic=" + subckt_name
+    if name_line_index is None:
+        new_lines = ['spice_sym_def="', new_content.strip(), '"'] + lines
+    else:
+        new_lines = (
+            lines[:name_line_index+1] +
+            [schematic_line] +
+            ['spice_sym_def="', new_content.strip(), '"'] +
+            lines[name_line_index+1:]
+        )
+
+    return text[:start_idx+1] + '\n' + '\n'.join(new_lines) + '\n' + text[end_idx:]
+
+def process_pair(spice_path, schematic_path):
+    print(f"\nProcessing:\n  SPICE: {spice_path}\n  Schematic: {schematic_path}")
+    try:
+        subckt_name, definition = read_spice_definition(spice_path)
+        print(f"  Subcircuit name: {subckt_name}")
+    except Exception as e:
+        print(f"  Error reading spice file: {e}")
+        return
+
+    # If subckt_name ends with '_pex', strip it for schematic search
+    search_subckt_name = subckt_name
+    if subckt_name.endswith("_pex"):
+        search_subckt_name = subckt_name[:-4]
+
+    location = find_subckt_location(search_subckt_name, schematic_path)
+    if location == -1:
+        print(f"  '{search_subckt_name}.sym' not found in schematic file.")
+        return
+
+    schematic_content = load_text_file(schematic_path)
+    start_idx, end_idx = find_first_curly_brackets_span(schematic_content, location)
+    if start_idx is None:
+        print("  No matching curly brackets found after .sym device.")
+        return
+
+    new_schematic_content = replace_curly_brackets_content(
+        schematic_content, start_idx, end_idx, definition, subckt_name
+    )
+
+    # Save the file in the current working directory (where script is run)
+    base_name = os.path.basename(schematic_path)
+    name, ext = os.path.splitext(base_name)
+    new_filename = os.path.join(os.getcwd(), f"{name}_pex{ext}")
+
+    save_text_file(new_filename, new_schematic_content)
+    
+    print(f"  Replacement done and new schematic file saved as:\n    {new_filename}")
+
+if __name__ == "__main__":
+    if len(sys.argv) != 3:
+        print("Usage:\n  python3 script.py <schematic.sch> <spice_file.spice>")
+        sys.exit(1)
+
+    schematic = sys.argv[1]
+    spice_path = sys.argv[2]
+
+    print(f"Starting processing with schematic='{schematic}', spice='{spice_path}'")  # Debug print
+
+    process_pair(spice_path, schematic)
diff --git a/modules/module_0_foundations/inverter_example/pex/python/match_subckt_order.py b/modules/module_0_foundations/inverter_example/pex/python/match_subckt_order.py
new file mode 100644
index 00000000..10a1ddfc
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/python/match_subckt_order.py
@@ -0,0 +1,59 @@
+import sys
+import re
+from pathlib import Path
+
+def get_original_io_order(original_netlist_path):
+    io_pins = []
+
+    with open(original_netlist_path, "r") as f:
+        for line in f:
+            stripped = line.strip()
+            # Look for .subckt line, case-insensitive
+            if stripped.lower().startswith(".subckt"):
+                tokens = stripped.split()
+                if len(tokens) >= 3:
+                    io_pins = tokens[2:]
+                    break
+
+    if not io_pins:
+        raise ValueError("Could not find IO pins in original schematic")
+
+    return io_pins
+
+def reorder_pex_subckt(pex_path, correct_order):
+    with open(pex_path, "r") as f:
+        lines = f.readlines()
+
+    new_lines = []
+    subckt_found = False
+
+    for line in lines:
+        if line.strip().lower().startswith(".subckt") and not subckt_found:
+            tokens = line.strip().split()
+            subckt_name = tokens[1]
+            ports = tokens[2:]
+
+            if set(ports) != set(correct_order):
+                raise ValueError("Port names in PEX netlist don't match original IO pins")
+
+            reordered_line = ".subckt " + subckt_name + "_pex " + " ".join(correct_order) + "\n"
+            new_lines.append(reordered_line)
+            subckt_found = True
+        else:
+            new_lines.append(line)
+
+    with open(pex_path, "w") as f:
+        f.writelines(new_lines)
+
+    print(f"Rewrote subckt line in {pex_path}")
+
+if __name__ == "__main__":
+    if len(sys.argv) != 3:
+        print("Usage: python patch_pex_order.py <pex_spice_path> <original_schematic_spice_path>")
+        sys.exit(1)
+
+    pex_spice = Path(sys.argv[1])
+    original_schematic = Path(sys.argv[2])
+
+    io_order = get_original_io_order(original_schematic)
+    reorder_pex_subckt(pex_spice, io_order)
diff --git a/modules/module_0_foundations/inverter_example/pex/python/xschem_rc.py b/modules/module_0_foundations/inverter_example/pex/python/xschem_rc.py
new file mode 100644
index 00000000..8a070c62
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/python/xschem_rc.py
@@ -0,0 +1,37 @@
+import sys
+def generate_xschemrc(custom_paths):
+    lines = [
+        "# xschemrc - Custom configuration file for xschem",
+        "# This file sources another xschemrc file from a known location",
+        "",
+        "# Source the base configuration from a known location",
+        "source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc",
+        "",
+        "# (Optional) Add any custom overrides or extensions below",
+        '# set xschem_library_path /home/user/my_libs',
+        '# set xschem_gui_font "Monospace 10"',
+        "",
+        "append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem"
+    ]
+
+    # Append each custom path with the prefix "../"
+    for path in custom_paths:
+        lines.append(f"append XSCHEM_LIBRARY_PATH :{path}")
+
+    return "\n".join(lines) + "\n"
+
+def main():
+    if len(sys.argv) < 2:
+        print("Usage: python3 make_xschemrc.py <path1> [<path2> ... <pathN>]")
+        sys.exit(1)
+
+    custom_paths = sys.argv[1:]
+    content = generate_xschemrc(custom_paths)
+
+    with open("xschemrc", "w") as f:
+        f.write(content)
+
+    print(f"xschemrc file generated with {len(custom_paths)} custom paths.")
+
+if __name__ == "__main__":
+    main()
diff --git a/modules/module_0_foundations/inverter_example/pex/run_kpex.sh b/modules/module_0_foundations/inverter_example/pex/run_kpex.sh
new file mode 100755
index 00000000..b4d7296f
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/run_kpex.sh
@@ -0,0 +1,103 @@
+#!/bin/bash
+set -e
+
+###############################################################################
+#                        ⬇⬇⬇ USER CONFIGURATION ⬇⬇⬇                         #
+###############################################################################
+
+# Activate Python environment (adjust this path to your Python venv activate script) Or if you python version is >3.12 ignore asuming klayout_pex is installed
+PYTHON_ENV="$HOME/misc/klayout_pex/bin/activate" 
+# Example: /home/username/misc/klayout_pex/bin/activate
+
+# Path to Magic executable used by kpex (adjust if installed elsewhere)
+KPEX_MAGIC_EXE="$HOME/.local/bin/magic" 
+# Example: /usr/local/bin/magic or ~/.local/bin/magic
+
+# Cell and schematic names (do NOT include file extensions)
+SYM_DIR="../inverter.sym"          # The name of your top cell / device under test (DUT)
+#TESTBENCH_NAME="inverter_tb"  # Name of your testbench schematic (without extension)
+
+# Paths relative to this script or absolute paths
+#SPICE_DIR="../simulations"    # Directory containing netlist/spice files for testbench
+LAYOUT_DIR="../layout/inverter_flat.gds"        # Directory containing layout files (.gds etc.)
+
+# Important: Path to your PDK root directory must be set externally in env variable PDK_ROOT
+
+PDK_NAME="ihp_sg13g2"         # Your PDK name (must match PDK_ROOT contents)
+MAGICRC="$PDK_ROOT/$PDK/libs.tech/magic/ihp-sg13g2.magicrc"
+# The magicrc file for your PDK, used during extraction
+
+SCHEMATIC="../simulations/inverter.spice"
+
+##############################################################################################################################################################
+#                       					⛔ DO NOT TOUCH BELOW THIS LINE ⛔  Unless you see clear issue with your setup :)                 				 #
+##############################################################################################################################################################
+
+
+# Check if required files exist before proceeding
+if [[ ! -f "$PYTHON_ENV" ]]; then
+  echo "[ERROR] Python environment activate script not found: $PYTHON_ENV"
+  exit 1
+fi
+
+if [[ ! -x "$KPEX_MAGIC_EXE" ]]; then
+  echo "[ERROR] Magic executable not found or not executable: $KPEX_MAGIC_EXE"
+  exit 1
+fi
+
+if [[ ! -f "$LAYOUT_DIR" ]]; then
+  echo "[ERROR] Layout GDS file not found: $LAYOUT_DIR"
+  exit 1
+fi
+
+
+if [[ ! -f "$MAGICRC" ]]; then
+  echo "[ERROR] Magicrc file for PDK not found: $MAGICRC"
+  exit 1
+fi
+
+# Activate Python virtual environment
+echo "[INFO] Activating Python environment..."
+source "$PYTHON_ENV"
+
+echo "[INFO] Using MAGIC executable: $KPEX_MAGIC_EXE"
+
+# Run parasitic extraction with kpex
+echo "[INFO] Running parasitic extraction with KPEX..."
+kpex \
+  --pdk "$PDK_NAME" \
+  --magic \
+  --schematic "$SCHEMATIC"\
+  --gds "$LAYOUT_DIR" \
+  --magicrc "$MAGICRC" \
+  --magic_mode RC \
+  --magic_cthresh 0.02 \
+  --magic_rthresh 50 \
+  --magic_short resistor \
+  --magic_merge conservative \
+  --out_dir ./pex_output
+
+# Find the generated spice file (assuming only one)
+spice_location=$(find ./pex_output -type f -name "*.spice" ! -name "*_dummy_schematic.spice" | head -n 1)
+
+
+if [[ -z "$spice_location" ]]; then
+  echo "[ERROR] No .spice file found in pex_output directory"
+  exit 1
+fi
+
+echo "[INFO] Found extracted spice file: $spice_location"
+
+# Run Python script to fix port ordering in the extracted netlist
+echo "[INFO] Reordering subcircuit pins to match original schematic..."
+echo "$spice_location"
+echo "$SCHEMATIC"
+#python3 python/match_subckt_order.py "$spice_location" "$SCHEMATIC"
+
+
+
+echo "[INFO] Creating DUT symbol with pex netlist"
+python3 python/insert_netlist_to_sym.py "$spice_location" "$SYM_DIR" xschem_pex_symbol
+
+cd xschem_pex_symbol
+echo "[✅ DONE] Modified symbol, including pex netlist generated and saved in: $(pwd)/"
diff --git a/modules/module_0_foundations/inverter_example/pex/xschem/inverter_tb_pex.sch b/modules/module_0_foundations/inverter_example/pex/xschem/inverter_tb_pex.sch
new file mode 100644
index 00000000..9e8395e5
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/xschem/inverter_tb_pex.sch
@@ -0,0 +1,84 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+B 2 710 -550 1510 -150 {flags=graph
+y1=-0.0023
+y2=1.3
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=2e-06
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+node=vout
+color=4
+dataset=-1
+unitx=1
+logx=0
+logy=0
+}
+N 150 -170 150 -140 {lab=Vin}
+N 70 -170 70 -140 {lab=Vdd}
+N 70 -80 70 -60 {lab=GND}
+N 110 -60 150 -60 {lab=GND}
+N 150 -80 150 -60 {lab=GND}
+N 110 -60 110 -50 {lab=GND}
+N 70 -60 110 -60 {lab=GND}
+N 320 -410 320 -380 {lab=Vdd}
+N 320 -210 320 -190 {lab=GND}
+N 220 -300 240 -300 {lab=Vin}
+N 520 -300 540 -300 {lab=Vout}
+C {vsource.sym} 150 -110 0 0 {name=V1 value="PULSE(0 1.2 0.5u 10n 10n 1u 2u 1)" savecurrent=false}
+C {vsource.sym} 70 -110 0 0 {name=V2 value=1.2 savecurrent=false}
+C {gnd.sym} 110 -50 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 150 -170 0 0 {name=p1 sig_type=std_logic lab=Vin}
+C {lab_pin.sym} 70 -170 0 0 {name=p3 sig_type=std_logic lab=Vdd}
+C {code_shown.sym} 40 -660 0 0 {name=NGSPICE
+only_toplevel=true
+value="
+.control
+save all
+tran 50n 2u 
+write test_inverter.raw
+.endc
+" }
+C {devices/code_shown.sym} 280 -540 0 0 {name=MODEL only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib cornerMOSlv.lib mos_tt
+.lib cornerRES.lib res_typ
+
+"}
+C {launcher.sym} 770 -120 0 0 {name=h5
+descr="load waves" 
+tclcommand="xschem raw_read $netlist_dir/test_inverter.raw tran"
+}
+C {inverter.sym} 390 -300 0 0 {
+name=x1
+schematic=inverter_pex
+spice_sym_def="
+.subckt inverter_pex Vdd Vin Vout Gnd
+X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
+X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
+C0 Vout Vin 0.10077f
+C1 Vin Vdd 0.14482f
+C2 Vout Vdd 0.13155f
+R0 Vin Vin.n0 7.52248
+C3 Vout Gnd 0.39245f
+C4 Vin Gnd 0.64666f
+C5 Vdd Gnd 0.15308f
+.ends
+"
+}
+C {lab_pin.sym} 220 -300 0 0 {name=p2 sig_type=std_logic lab=Vin}
+C {gnd.sym} 320 -190 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 320 -410 0 0 {name=p4 sig_type=std_logic lab=Vdd}
+C {lab_pin.sym} 540 -300 0 1 {name=p5 sig_type=std_logic lab=Vout}
diff --git a/modules/module_0_foundations/inverter_example/pex/xschem/xschemrc b/modules/module_0_foundations/inverter_example/pex/xschem/xschemrc
new file mode 100644
index 00000000..49665ae7
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/xschem/xschemrc
@@ -0,0 +1,12 @@
+# xschemrc - Custom configuration file for xschem
+# This file sources another xschemrc file from a known location
+
+# Source the base configuration from a known location
+source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
+
+# (Optional) Add any custom overrides or extensions below
+# set xschem_library_path /home/user/my_libs
+# set xschem_gui_font "Monospace 10"
+
+append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
+append XSCHEM_LIBRARY_PATH :../../
diff --git a/modules/module_0_foundations/inverter_example/pex/xschem_pex_symbol/inverter.sym b/modules/module_0_foundations/inverter_example/pex/xschem_pex_symbol/inverter.sym
new file mode 100644
index 00000000..5d614e96
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/pex/xschem_pex_symbol/inverter.sym
@@ -0,0 +1,45 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1
+schematic=inverter
+spice_sym_def=
+\\"
+.subckt inverter well Vout Vin Gnd Vdd
+R0 Vdd well 0.000000
+X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
+X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
+C0 Vdd Vout 0.13155f
+C1 Vin Vout 0.10077f
+C2 Vin Vdd 0.14482f
+R1 Vdd well 8.53169
+R2 Vin Vin.n0 7.52248
+R3 well Vdd 8.53069
+C3 Vout Gnd 0.39245f
+C4 Vin Gnd 0.64666f
+C5 Vdd Gnd 0.15308f
+.ends
+\\"
+"
+V {}
+S {}
+E {}
+L 7 -70 -80 -70 -60 {}
+L 7 -150 0 -130 0 {}
+L 7 110 0 130 0 {}
+L 7 -70 70 -70 90 {}
+B 5 -72.5 -82.5 -67.5 -77.5 {name=Vdd dir=inout}
+B 5 -152.5 -2.5 -147.5 2.5 {name=Vin dir=inout}
+B 5 127.5 -2.5 132.5 2.5 {name=Vout dir=inout}
+B 5 -72.5 87.5 -67.5 92.5 {name=Gnd dir=inout}
+A 4 105 0 7.071067811865476 135 360 {}
+P 4 5 100 0 -130 -80 -130 90 100 0 100 0 {}
+T {@symname
+
+} -84 -6 0 0 0.3 0.3 {}
+T {@name} -45 -32 0 0 0.2 0.2 {}
+T {Vdd} -74 -55 3 1 0.2 0.2 {}
+T {Vin} -125 -4 0 0 0.2 0.2 {}
+T {Vout} 80 -9 0 1 0.2 0.2 {}
+T {Gnd} -66 65 1 1 0.2 0.2 {}
diff --git a/modules/module_0_foundations/inverter_example/python_test/new_symbol/inverter.sym b/modules/module_0_foundations/inverter_example/python_test/new_symbol/inverter.sym
new file mode 100644
index 00000000..3d756788
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/python_test/new_symbol/inverter.sym
@@ -0,0 +1,42 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1
+schematic=inverter_pex
+spice_sym_def=
+\\"
+.subckt inverter_pex Vdd Vin Vout Gnd
+X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
+X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
+C0 Vout Vin 0.10077f
+C1 Vin Vdd 0.14482f
+C2 Vout Vdd 0.13155f
+R0 Vin Vin.n0 7.52248
+C3 Vout Gnd 0.39245f
+C4 Vin Gnd 0.64666f
+C5 Vdd Gnd 0.15308f
+.ends
+\\"
+"
+V {}
+S {}
+E {}
+L 7 -70 -80 -70 -60 {}
+L 7 -150 0 -130 0 {}
+L 7 110 0 130 0 {}
+L 7 -70 70 -70 90 {}
+B 5 -72.5 -82.5 -67.5 -77.5 {name=Vdd dir=inout}
+B 5 -152.5 -2.5 -147.5 2.5 {name=Vin dir=inout}
+B 5 127.5 -2.5 132.5 2.5 {name=Vout dir=inout}
+B 5 -72.5 87.5 -67.5 92.5 {name=Gnd dir=inout}
+A 4 105 0 7.071067811865476 135 360 {}
+P 4 5 100 0 -130 -80 -130 90 100 0 100 0 {}
+T {@symname
+
+} -84 -6 0 0 0.3 0.3 {}
+T {@name} -45 -32 0 0 0.2 0.2 {}
+T {Vdd} -74 -55 3 1 0.2 0.2 {}
+T {Vin} -125 -4 0 0 0.2 0.2 {}
+T {Vout} 80 -9 0 1 0.2 0.2 {}
+T {Gnd} -66 65 1 1 0.2 0.2 {}
diff --git a/modules/module_0_foundations/inverter_example/python_test/script.py b/modules/module_0_foundations/inverter_example/python_test/script.py
new file mode 100644
index 00000000..8c69e8f3
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/python_test/script.py
@@ -0,0 +1,74 @@
+import sys
+import os
+
+def extract_netlist_and_topcell(spice_path):
+    with open(spice_path, 'r') as f:
+        lines = f.readlines()
+
+    netlist = []
+    topcell = None
+    inside_subckt = False
+
+    for line in lines:
+        if line.strip().startswith(".subckt"):
+            parts = line.strip().split()
+            if len(parts) > 1:
+                topcell = parts[1]
+            inside_subckt = True
+        if inside_subckt:
+            netlist.append(line.rstrip())
+        if line.strip().startswith(".ends"):
+            break
+
+    if not topcell:
+        raise ValueError("Topcell name not found in SPICE file.")
+
+    return topcell, "\n".join(netlist)
+
+def modify_sym_file(sym_path, output_dir, topcell, netlist):
+    with open(sym_path, 'r') as f:
+        sym_lines = f.readlines()
+
+    new_sym_lines = []
+    inserted = False
+
+    for line in sym_lines:
+        if line.strip().startswith("K {type=subcircuit"):
+            new_sym_lines.append(line)
+            continue
+        elif line.strip().startswith("template=") and not inserted:
+            new_template = (
+                f'template="name=x1\n'
+                f'schematic={topcell}\n'
+                f'spice_sym_def=\n'
+                f'\\\\"\n'
+                f'{netlist}\n'
+                f'\\\\"\n'
+                f'"'
+            )
+            new_sym_lines.append(new_template + "\n")
+            inserted = True
+        else:
+            new_sym_lines.append(line)
+
+    filename = os.path.basename(sym_path)
+    out_path = os.path.join(output_dir, filename)
+
+    os.makedirs(output_dir, exist_ok=True)
+
+    with open(out_path, 'w') as f:
+        f.writelines(new_sym_lines)
+
+    print(f"Saved modified .sym to: {out_path}")
+
+if __name__ == "__main__":
+    if len(sys.argv) != 4:
+        print("Usage: python insert_netlist_to_sym.py <netlist.spice> <symbol.sym> <output_folder>")
+        sys.exit(1)
+
+    spice_file = sys.argv[1]
+    sym_file = sys.argv[2]
+    output_folder = sys.argv[3]
+
+    topcell, netlist = extract_netlist_and_topcell(spice_file)
+    modify_sym_file(sym_file, output_folder, topcell, netlist)
diff --git a/modules/module_0_foundations/inverter_example/xschemrc b/modules/module_0_foundations/inverter_example/xschemrc
new file mode 100644
index 00000000..0d8170e0
--- /dev/null
+++ b/modules/module_0_foundations/inverter_example/xschemrc
@@ -0,0 +1,18 @@
+# xschemrc - Custom configuration file for xschem
+# This file sources another xschemrc file from a known location
+
+# Source the base configuration from a known location
+source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
+
+# (Optional) Add any custom overrides or extensions below
+# set xschem_library_path /home/user/my_libs
+# set xschem_gui_font "Monospace 10"
+
+#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
+###only if you dont have this setup already ### 
+###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
+
+
+#### Add custom libraries (directories with .lib files)
+append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
+
diff --git a/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/pex_output/DIFF_COMPARATOR_flat__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.ext b/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/pex_output/DIFF_COMPARATOR_flat__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.ext
index 8af82d36..059e15c1 100644
--- a/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/pex_output/DIFF_COMPARATOR_flat__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.ext
+++ b/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/pex_output/DIFF_COMPARATOR_flat__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.ext
@@ -27,6 +27,29 @@ node "a_1245_3300#" 64 1428.73 1245 3300 pdif 0 0 0 0 646952 33468 462832 13040
 node "w_805_2869#" 1242572 5.18828 805 2869 pw 182658 17438 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 node "vdd" 58 17973.9 127 335 m6 0 0 0 0 2395440 52908 883744 19072 642880 13104 642880 13104 1340864 17360 6062752 36968 0 0
 substrate "gnd" 0 0 -513 -440 m7 0 0 0 0 2036008 30746 224000 4320 224000 4320 224000 4320 654400 6472 1331200 8256 9608000 48040
+cap "out-" "a_687_2445#" 894.529
+cap "w_805_2869#" "V+" 10.369
+cap "vdd" "V-" 4062.84
+cap "out-" "a_1245_3300#" 367.947
+cap "vbias" "clk" 198.783
+cap "out-" "a_944_1911#" 611.611
+cap "w_805_2869#" "a_687_2445#" 3.06666
+cap "clk" "a_687_2445#" 238.332
+cap "w_805_2869#" "a_1245_3300#" 12.1813
+cap "clk" "a_1245_3300#" 447.822
+cap "w_805_2869#" "a_944_1911#" 4.42903
+cap "clk" "a_944_1911#" 247.428
+cap "out-" "V-" 3.46102
+cap "vdd" "a_1752_817#" 7111.46
+cap "w_805_2869#" "V-" 10.604
+cap "vdd" "out+" 1847.73
+cap "V+" "a_687_2445#" 130.641
+cap "V+" "a_1245_3300#" 769.244
+cap "vbias" "a_687_2445#" 4.05638
+cap "V+" "a_944_1911#" 1081.99
+cap "vbias" "a_1245_3300#" 2.78546
+cap "a_687_2445#" "a_1245_3300#" 11353.4
+cap "vbias" "a_944_1911#" 3.01856
 cap "a_944_1911#" "a_687_2445#" 2249.36
 cap "clk" "a_1752_817#" 502.499
 cap "out-" "out+" 93.2996
@@ -59,29 +82,6 @@ cap "vdd" "a_944_1911#" 1108.93
 cap "out-" "V+" 7.34235
 cap "V-" "out+" 9.67399
 cap "out-" "vbias" 0.0904886
-cap "out-" "a_687_2445#" 894.529
-cap "w_805_2869#" "V+" 10.369
-cap "vdd" "V-" 4062.84
-cap "out-" "a_1245_3300#" 367.947
-cap "vbias" "clk" 198.783
-cap "out-" "a_944_1911#" 611.611
-cap "w_805_2869#" "a_687_2445#" 3.06666
-cap "clk" "a_687_2445#" 238.332
-cap "w_805_2869#" "a_1245_3300#" 12.1813
-cap "clk" "a_1245_3300#" 447.822
-cap "w_805_2869#" "a_944_1911#" 4.42903
-cap "clk" "a_944_1911#" 247.428
-cap "out-" "V-" 3.46102
-cap "vdd" "a_1752_817#" 7111.46
-cap "w_805_2869#" "V-" 10.604
-cap "vdd" "out+" 1847.73
-cap "V+" "a_687_2445#" 130.641
-cap "V+" "a_1245_3300#" 769.244
-cap "vbias" "a_687_2445#" 4.05638
-cap "V+" "a_944_1911#" 1081.99
-cap "vbias" "a_1245_3300#" 2.78546
-cap "a_687_2445#" "a_1245_3300#" 11353.4
-cap "vbias" "a_944_1911#" 3.01856
 device msubckt sg13_lv_nmos 3710 1075 3711 1076 l=40 w=800 "gnd" "gnd" 80 0 "gnd" 0 0 "gnd" 1600 30400,876
 device msubckt sg13_lv_nmos 3594 1075 3595 1076 l=40 w=800 "gnd" "clk" 80 0 "a_944_1911#" 800 57600,944 "gnd" 800 30400,876
 device msubckt sg13_lv_nmos 3410 1075 3411 1076 l=40 w=800 "gnd" "a_687_2445#" 80 0 "gnd" 800 30400,876 "a_944_1911#" 800 57600,944
diff --git a/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/pex_output/DIFF_COMPARATOR_flat__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.res.ext b/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/pex_output/DIFF_COMPARATOR_flat__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.res.ext
index 1ac375c1..148c162c 100644
--- a/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/pex_output/DIFF_COMPARATOR_flat__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.res.ext
+++ b/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/pex_output/DIFF_COMPARATOR_flat__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.res.ext
@@ -1,2452 +1 @@
-scale 1000 1 0.5
-rnode "out-.n0" 0 0 1362 2684 0
-rnode "out-.n1" 0 0 1453 2406 0
-rnode "out-.n2" 0 0 2029 2406 0
-rnode "out-.n3" 0 0 1325 2407 0
-rnode "out-.n4" 0 0 1769 2407 0
-rnode "out-.n5" 0 0 1695 2407 0
-rnode "out-.n6" 0 0 1621 2407 0
-rnode "out-.n7" 0 0 1554 2684 0
-rnode "out-.n8" 0 0 1453 2406 0
-rnode "out-.n9" 0 0 1325 2639 0
-rnode "out-.n10" 0 0 2034 2684 0
-rnode "out-.n11" 0 0 1325 2639 0
-rnode "out-.n12" 0 0 1769 2639 0
-rnode "out-.n13" 0 0 1695 2639 0
-rnode "out-.n14" 0 0 2029 2406 0
-rnode "out-.n15" 0 0 1938 2684 0
-rnode "out-.n16" 0 0 1938 2684 0
-rnode "out-.n17" 0 0 1933 2406 0
-rnode "out-.n18" 0 0 1933 2406 0
-rnode "out-.n19" 0 0 1842 2684 0
-rnode "out-.n20" 0 0 1842 2684 0
-rnode "out-.n21" 0 0 1837 2406 0
-rnode "out-.n22" 0 0 1837 2406 0
-rnode "out-.n23" 0 0 1746 2684 0
-rnode "out-.n24" 0 0 1746 2684 0
-rnode "out-.n25" 0 0 1741 2406 0
-rnode "out-.n26" 0 0 1741 2406 0
-rnode "out-.n27" 0 0 1645 2406 0
-rnode "out-.n28" 0 0 1645 2406 0
-rnode "out-.n29" 0 0 1650 2684 0
-rnode "out-.n30" 0 0 1650 2684 0
-rnode "out-.n31" 0 0 1554 2684 0
-rnode "out-.n32" 0 0 1621 2639 0
-rnode "out-.t3" 0 0 1325 2639 0
-rnode "out-.n33" 0 0 1325 2639 0
-rnode "out-.n34" 0 0 1458 2684 0
-rnode "out-.n35" 0 0 1458 2684 0
-rnode "out-.n36" 0 0 1549 2406 0
-rnode "out-.n37" 0 0 1549 2406 0
-rnode "out-.n38" 0 0 1325 2407 0
-rnode "out-.t2" 0 0 1325 2407 0
-rnode "out-.n39" 0 0 1325 2407 0
-rnode "out-.n40" 0 0 1357 2406 0
-rnode "out-.n41" 0 0 1067 2780 0
-rnode "out-.n42" 0 0 971 2684 0
-rnode "out-.n43" 0 0 779 2780 0
-rnode "out-.t0" 0 0 753 2407 0
-rnode "out-.n44" 0 0 875 2684 0
-rnode "out-.n45" 0 0 1093 2639 0
-rnode "out-.n46" 0 0 779 2780 0
-rnode "out-.t1" 0 0 1093 2639 0
-rnode "out-.n47" 0 0 1093 2639 0
-rnode "out-.n48" 0 0 1067 2684 0
-rnode "out-.n49" 0 0 1067 2684 0
-rnode "out-.n50" 0 0 750 2732 0
-rnode "out-" 0 0 -1819 2721 0
-resist "out-.n40" "out-.n0" 0.00101852
-resist "out-.n35" "out-.n8" 0.00101852
-resist "out-.n36" "out-.n7" 0.00101852
-resist "out-.n29" "out-.n28" 0.00101852
-resist "out-.n26" "out-.n24" 0.00101852
-resist "out-.n22" "out-.n20" 0.00101852
-resist "out-.n18" "out-.n16" 0.00101852
-resist "out-.n50" "out-.n49" 0.0122081
-resist "out-.n50" "out-.n41" 0.0122081
-resist "out-.n46" "out-.n43" 0.0129159
-resist "out-.n48" "out-.n47" 0.0129159
-resist "out-.n23" "out-.n12" 0.0136022
-resist "out-.n32" "out-.n30" 0.0171505
-resist "out-.n8" "out-.n0" 0.018537
-resist "out-.n36" "out-.n35" 0.018537
-resist "out-.n28" "out-.n7" 0.018537
-resist "out-.n29" "out-.n26" 0.018537
-resist "out-.n24" "out-.n22" 0.018537
-resist "out-.n20" "out-.n18" 0.018537
-resist "out-.n16" "out-.n14" 0.018537
-resist "out-.n19" "out-.n11" 0.022945
-resist "out-.n31" "out-.n9" 0.0264934
-resist "out-.n30" "out-.n13" 0.0266129
-resist "out-.n45" "out-.n44" 0.0288633
-resist "out-.n45" "out-.n42" 0.0288633
-resist "out-.n23" "out-.n13" 0.0301613
-resist "out-.n34" "out-.n9" 0.0312246
-resist "out-.n15" "out-.n11" 0.0347729
-resist "out-.n32" "out-.n31" 0.0396237
-resist "out-.n19" "out-.n12" 0.043172
-resist "out-.n15" "out-.n10" 0.0445428
-resist "out-.n46" "out-.n44" 0.0448402
-resist "out-.n47" "out-.n42" 0.0448402
-resist "out-.n27" "out-.n6" 0.0455172
-resist "out-.n34" "out-.n33" 0.0463193
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-resist "out-.n38" "out-.n37" 0.0741771
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-resist "out-.n25" "out-.n5" 0.0872414
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-resist "out-.n17" "out-.n3" 0.100729
-resist "out-.n38" "out-.n1" 0.108315
-resist "out-.n50" "out-.n40" 0.126344
-resist "out-.n21" "out-.n4" 0.128966
-resist "out-.n37" "out-.n6" 0.136552
-resist "out-.n39" "out-.n1" 0.142578
-resist "out-.n17" "out-.n2" 0.146386
-resist "out-" "out-.n50" 1.468
-resist "out-.n16" "out-.n15" 4.5
-resist "out-.n20" "out-.n19" 4.5
-resist "out-.n24" "out-.n23" 4.5
-resist "out-.n30" "out-.n29" 4.5
-resist "out-.n31" "out-.n7" 4.5
-resist "out-.n35" "out-.n34" 4.5
-resist "out-.n33" "out-.n0" 4.51144
-resist "out-.n14" "out-.n10" 4.51423
-resist "out-.n49" "out-.t0" 5.16366
-resist "out-.t2" "out-.n3" 8.46556
-resist "out-.t2" "out-.n38" 8.46556
-resist "out-.t3" "out-.n11" 8.48957
-resist "out-.t3" "out-.n9" 8.48957
-resist "out-.t1" "out-.n45" 8.49046
-resist "out-.n39" "out-.t2" 8.49578
-resist "out-.n47" "out-.t1" 8.49814
-resist "out-.t1" "out-.n46" 8.49814
-resist "out-.t3" "out-.n10" 8.49873
-resist "out-.t2" "out-.n2" 8.49956
-resist "out-.n33" "out-.t3" 8.5005
-resist "out-.n49" "out-.n48" 9
-resist "out-.n49" "out-.n42" 9
-resist "out-.n49" "out-.n44" 9
-resist "out-.n49" "out-.n43" 9
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-resist "out-.n14" "out-.n2" 9.03653
-resist "out-.n40" "out-.n39" 9.04031
-resist "out-.t3" "out-.n12" 17
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-resist "out-.t3" "out-.n32" 17
-resist "out-.t2" "out-.n4" 17
-resist "out-.t2" "out-.n5" 17
-resist "out-.t2" "out-.n6" 17
-rnode "clk.t1" 0 161.509 3614 1475 0
-rnode "clk.t2" 0 663.67 1686 1653 0
-rnode "clk.t0" 0 93.9403 790 1475 0
-rnode "clk.n0" 0 700.289 1438 1009 0
-rnode "clk.n1" 0 1273.79 1589 -930 0
-rnode "clk" 0 106.803 1620 -950 0
-resist "clk" "clk.n1" 0.573617
-resist "clk.n1" "clk.n0" 2.20393
-resist "clk.n0" "clk.t2" 12.2994
-resist "clk.n0" "clk.t0" 29.4504
-resist "clk.n1" "clk.t1" 32.2505
-rnode "out+.n0" 0 0 3042 2684 0
-rnode "out+.t3" 0 0 2339 2407 0
-rnode "out+.n1" 0 0 2339 2407 0
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-rnode "vdd.n219" 0 6.33321 2058 1255 0
-rnode "vdd.n220" 0 8.9102 2058 1255 0
-rnode "vdd.n221" 0 3.24851 1962 1255 0
-rnode "vdd.n222" 0 8.9102 1962 1255 0
-rnode "vdd.n223" 0 8.9102 1866 1255 0
-rnode "vdd.n224" 0 6.03995 1866 1255 0
-rnode "vdd.n225" 0 6.43812 1782 1255 0
-rnode "vdd.t4" 0 72.1422 1782 1255 0
-rnode "vdd.n226" 0 6.43812 1782 1255 0
-rnode "vdd.n227" 0 22.4846 2634 1255 0
-rnode "vdd.n228" 0 10.4452 2724 481 0
-rnode "vdd.n229" 0 10.4503 2724 385 0
-rnode "vdd.n230" 0 14.1753 2724 481 0
-rnode "vdd.n231" 0 100.197 2724 433 0
-rnode "vdd.n232" 0 10.4503 2724 481 0
-rnode "vdd.n233" 0 14.1753 2724 481 0
-rnode "vdd.n234" 0 14.1753 2724 385 0
-rnode "vdd.n235" 0 14.1753 2724 385 0
-rnode "vdd.n236" 0 10.4452 2724 385 0
-rnode "vdd.n237" 0 78.6762 2772 433 0
-rnode "vdd.n238" 0 79.7733 2823 957 0
-rnode "vdd.n239" 0 21.2025 2634 983 0
-rnode "vdd.n240" 0 6.03995 2538 983 0
-rnode "vdd.n241" 0 8.9102 2538 983 0
-rnode "vdd.n242" 0 3.24851 2442 983 0
-rnode "vdd.n243" 0 8.9102 2442 983 0
-rnode "vdd.n244" 0 6.33321 2346 983 0
-rnode "vdd.n245" 0 8.9102 2346 983 0
-rnode "vdd.n246" 0 5.87903 2250 983 0
-rnode "vdd.n247" 0 8.9102 2250 983 0
-rnode "vdd.n248" 0 5.87903 2154 983 0
-rnode "vdd.n249" 0 8.9102 2154 983 0
-rnode "vdd.n250" 0 6.33321 2058 983 0
-rnode "vdd.n251" 0 8.9102 2058 983 0
-rnode "vdd.n252" 0 8.9102 1962 983 0
-rnode "vdd.n253" 0 3.24851 1962 983 0
-rnode "vdd.n254" 0 4.4551 1922 983 0
-rnode "vdd.t5" 0 72.1422 1782 983 0
-rnode "vdd.n255" 0 6.43812 1782 983 0
-rnode "vdd.n256" 0 21.2025 1770 983 0
-rnode "vdd.n257" 0 79.7733 1581 957 0
-rnode "vdd.n258" 0 78.6762 1632 433 0
-rnode "vdd.n259" 0 10.4452 1680 481 0
-rnode "vdd.n260" 0 14.1753 1680 481 0
-rnode "vdd.n261" 0 14.1753 1680 385 0
-rnode "vdd.n262" 0 14.1753 1680 385 0
-rnode "vdd.n263" 0 10.4503 1680 385 0
-rnode "vdd.n264" 0 100.197 1680 433 0
-rnode "vdd.n265" 0 434.161 1680 433 0
-rnode "vdd.n266" 0 717.317 214 597 0
-rnode "vdd" 0 41.6864 127 335 0
-resist "vdd.n148" "vdd.n69" 0.0005
-resist "vdd.n146" "vdd.n81" 0.0005
-resist "vdd.n145" "vdd.n84" 0.0005
-resist "vdd.n87" "vdd.n83" 0.0005
-resist "vdd.n138" "vdd.n109" 0.0005
-resist "vdd.n109" "vdd.n83" 0.0005
-resist "vdd.n87" "vdd.n84" 0.0005
-resist "vdd.n146" "vdd.n145" 0.0005
-resist "vdd.n148" "vdd.n81" 0.0005
-resist "vdd.n69" "vdd.n6" 0.0005
-resist "vdd.n137" "vdd.t1" 0.0005
-resist "vdd.n136" "vdd.n134" 0.0005
-resist "vdd.n133" "vdd.n132" 0.0005
-resist "vdd.n131" "vdd.n130" 0.0005
-resist "vdd.t0" "vdd.n129" 0.0005
-resist "vdd.n128" "vdd.n127" 0.0005
-resist "vdd.n126" "vdd.n125" 0.0005
-resist "vdd.n124" "vdd.n123" 0.0005
-resist "vdd.n123" "vdd.n122" 0.0005
-resist "vdd.n125" "vdd.n124" 0.0005
-resist "vdd.n127" "vdd.n126" 0.0005
-resist "vdd.n129" "vdd.n128" 0.0005
-resist "vdd.n130" "vdd.t0" 0.0005
-resist "vdd.n132" "vdd.n131" 0.0005
-resist "vdd.n134" "vdd.n133" 0.0005
-resist "vdd.n137" "vdd.n136" 0.0005
-resist "vdd.n147" "vdd.n82" 0.000642845
-resist "vdd.n138" "vdd.n135" 0.00083332
-resist "vdd.n135" "vdd.n6" 0.00116667
-resist "vdd.n122" "vdd.n82" 0.00135713
-resist "vdd" "vdd.n266" 0.00477439
-resist "vdd.n101" "vdd.n0" 0.0230488
-resist "vdd.n101" "vdd.n100" 0.0230488
-resist "vdd.n100" "vdd.n65" 0.0230488
-resist "vdd.n158" "vdd.n65" 0.0230488
-resist "vdd.n159" "vdd.n158" 0.0230488
-resist "vdd.n187" "vdd.n1" 0.0230488
-resist "vdd.n34" "vdd.n1" 0.0230488
-resist "vdd.n44" "vdd.n34" 0.0230488
-resist "vdd.n54" "vdd.n44" 0.0230488
-resist "vdd.n64" "vdd.n54" 0.0230488
-resist "vdd.n60" "vdd.n56" 0.0302722
-resist "vdd.n59" "vdd.n58" 0.0302722
-resist "vdd.n165" "vdd.n164" 0.0302722
-resist "vdd.n24" "vdd.n22" 0.0302722
-resist "vdd.n118" "vdd.n117" 0.0302722
-resist "vdd.n112" "vdd.n110" 0.0302722
-resist "vdd.n107" "vdd.n106" 0.0302722
-resist "vdd.n90" "vdd.n88" 0.0302722
-resist "vdd.n96" "vdd.n92" 0.0302722
-resist "vdd.n95" "vdd.n94" 0.0302722
-resist "vdd.n78" "vdd.n77" 0.0302722
-resist "vdd.n72" "vdd.n70" 0.0302722
-resist "vdd.n154" "vdd.n67" 0.0302722
-resist "vdd.n153" "vdd.n152" 0.0302722
-resist "vdd.n50" "vdd.n46" 0.0302722
-resist "vdd.n49" "vdd.n48" 0.0302722
-resist "vdd.n40" "vdd.n36" 0.0302722
-resist "vdd.n39" "vdd.n38" 0.0302722
-resist "vdd.n30" "vdd.n26" 0.0302722
-resist "vdd.n29" "vdd.n28" 0.0302722
-resist "vdd.n15" "vdd.n14" 0.0302722
-resist "vdd.n9" "vdd.n7" 0.0302722
-resist "vdd.n183" "vdd.n3" 0.0302722
-resist "vdd.n182" "vdd.n181" 0.0302722
-resist "vdd.n230" "vdd.n228" 0.0302722
-resist "vdd.n236" "vdd.n235" 0.0302722
-resist "vdd.n260" "vdd.n259" 0.0302722
-resist "vdd.n261" "vdd.n190" 0.0302722
-resist "vdd.n62" "vdd.n61" 0.0303751
-resist "vdd.n57" "vdd.n55" 0.0303751
-resist "vdd.n163" "vdd.n23" 0.0303751
-resist "vdd.n162" "vdd.n161" 0.0303751
-resist "vdd.n116" "vdd.n111" 0.0303751
-resist "vdd.n115" "vdd.n114" 0.0303751
-resist "vdd.n105" "vdd.n89" 0.0303751
-resist "vdd.n104" "vdd.n103" 0.0303751
-resist "vdd.n98" "vdd.n97" 0.0303751
-resist "vdd.n93" "vdd.n91" 0.0303751
-resist "vdd.n76" "vdd.n71" 0.0303751
-resist "vdd.n75" "vdd.n74" 0.0303751
-resist "vdd.n156" "vdd.n155" 0.0303751
-resist "vdd.n68" "vdd.n66" 0.0303751
-resist "vdd.n52" "vdd.n51" 0.0303751
-resist "vdd.n47" "vdd.n45" 0.0303751
-resist "vdd.n42" "vdd.n41" 0.0303751
-resist "vdd.n37" "vdd.n35" 0.0303751
-resist "vdd.n32" "vdd.n31" 0.0303751
-resist "vdd.n27" "vdd.n25" 0.0303751
-resist "vdd.n13" "vdd.n8" 0.0303751
-resist "vdd.n12" "vdd.n11" 0.0303751
-resist "vdd.n185" "vdd.n184" 0.0303751
-resist "vdd.n4" "vdd.n2" 0.0303751
-resist "vdd.n233" "vdd.n232" 0.0303751
-resist "vdd.n234" "vdd.n229" 0.0303751
-resist "vdd.n191" "vdd.n189" 0.0303751
-resist "vdd.n263" "vdd.n262" 0.0303751
-resist "vdd.n253" "vdd.n201" 0.0375
-resist "vdd.n242" "vdd.n197" 0.0375
-resist "vdd.n221" "vdd.n209" 0.0375
-resist "vdd.n211" "vdd.n205" 0.0375
-resist "vdd.n250" "vdd.n200" 0.0491377
-resist "vdd.n244" "vdd.n198" 0.0491377
-resist "vdd.n219" "vdd.n208" 0.0491377
-resist "vdd.n213" "vdd.n206" 0.0491377
-resist "vdd.n254" "vdd.n253" 0.05
-resist "vdd.n242" "vdd.n196" 0.05
-resist "vdd.n221" "vdd.n210" 0.05
-resist "vdd.n211" "vdd.n204" 0.05
-resist "vdd.n265" "vdd.n188" 0.0572927
-resist "vdd.n248" "vdd.n199" 0.06
-resist "vdd.n246" "vdd.n199" 0.06
-resist "vdd.n217" "vdd.n207" 0.06
-resist "vdd.n215" "vdd.n207" 0.06
-resist "vdd.n61" "vdd.n57" 0.0603429
-resist "vdd.n60" "vdd.n59" 0.0603429
-resist "vdd.n164" "vdd.n24" 0.0603429
-resist "vdd.n163" "vdd.n162" 0.0603429
-resist "vdd.n117" "vdd.n112" 0.0603429
-resist "vdd.n116" "vdd.n115" 0.0603429
-resist "vdd.n106" "vdd.n90" 0.0603429
-resist "vdd.n105" "vdd.n104" 0.0603429
-resist "vdd.n96" "vdd.n95" 0.0603429
-resist "vdd.n97" "vdd.n93" 0.0603429
-resist "vdd.n77" "vdd.n72" 0.0603429
-resist "vdd.n76" "vdd.n75" 0.0603429
-resist "vdd.n154" "vdd.n153" 0.0603429
-resist "vdd.n155" "vdd.n68" 0.0603429
-resist "vdd.n50" "vdd.n49" 0.0603429
-resist "vdd.n51" "vdd.n47" 0.0603429
-resist "vdd.n40" "vdd.n39" 0.0603429
-resist "vdd.n41" "vdd.n37" 0.0603429
-resist "vdd.n30" "vdd.n29" 0.0603429
-resist "vdd.n31" "vdd.n27" 0.0603429
-resist "vdd.n14" "vdd.n9" 0.0603429
-resist "vdd.n13" "vdd.n12" 0.0603429
-resist "vdd.n183" "vdd.n182" 0.0603429
-resist "vdd.n184" "vdd.n4" 0.0603429
-resist "vdd.n234" "vdd.n233" 0.0603429
-resist "vdd.n235" "vdd.n230" 0.0603429
-resist "vdd.n261" "vdd.n260" 0.0603429
-resist "vdd.n262" "vdd.n191" 0.0603429
-resist "vdd.n255" "vdd.n194" 0.0616377
-resist "vdd.n240" "vdd.n195" 0.0616377
-resist "vdd.n225" "vdd.n224" 0.0616377
-resist "vdd.n226" "vdd.n203" 0.0616377
-resist "vdd.n254" "vdd.n194" 0.07
-resist "vdd.n240" "vdd.n196" 0.07
-resist "vdd.n224" "vdd.n210" 0.07
-resist "vdd.n204" "vdd.n203" 0.07
-resist "vdd.n248" "vdd.n200" 0.0716377
-resist "vdd.n246" "vdd.n198" 0.0716377
-resist "vdd.n217" "vdd.n208" 0.0716377
-resist "vdd.n215" "vdd.n206" 0.0716377
-resist "vdd.n266" "vdd.n265" 0.0804512
-resist "vdd.n250" "vdd.n201" 0.0825
-resist "vdd.n244" "vdd.n197" 0.0825
-resist "vdd.n219" "vdd.n209" 0.0825
-resist "vdd.n213" "vdd.n205" 0.0825
-resist "vdd.n168" "vdd.n6" 0.0893978
-resist "vdd.n223" "vdd.n192" 0.096
-resist "vdd.n223" "vdd.n222" 0.096
-resist "vdd.n222" "vdd.n220" 0.096
-resist "vdd.n220" "vdd.n218" 0.096
-resist "vdd.n218" "vdd.n216" 0.096
-resist "vdd.n216" "vdd.n214" 0.096
-resist "vdd.n214" "vdd.n212" 0.096
-resist "vdd.n212" "vdd.n202" 0.096
-resist "vdd.n227" "vdd.n202" 0.096
-resist "vdd.n256" "vdd.n193" 0.096
-resist "vdd.n252" "vdd.n193" 0.096
-resist "vdd.n252" "vdd.n251" 0.096
-resist "vdd.n251" "vdd.n249" 0.096
-resist "vdd.n249" "vdd.n247" 0.096
-resist "vdd.n247" "vdd.n245" 0.096
-resist "vdd.n245" "vdd.n243" 0.096
-resist "vdd.n243" "vdd.n241" 0.096
-resist "vdd.n241" "vdd.n239" 0.096
-resist "vdd.n266" "vdd.n0" 0.142354
-resist "vdd.n167" "vdd.n21" 0.179215
-resist "vdd.n188" "vdd.n187" 0.222805
-resist "vdd.t1" "vdd.n6" 0.236111
-resist "vdd.n159" "vdd.n64" 0.244976
-resist "vdd.n142" "vdd.n141" 0.250746
-resist "vdd.n178" "vdd.n177" 0.25113
-resist "vdd.n144" "vdd.n143" 0.256563
-resist "vdd.n85" "vdd.n80" 0.261323
-resist "vdd.n174" "vdd.n173" 0.261707
-resist "vdd.n150" "vdd.n149" 0.266629
-resist "vdd.n176" "vdd.n175" 0.267735
-resist "vdd.n170" "vdd.n169" 0.272284
-resist "vdd.n172" "vdd.n171" 0.272616
-resist "vdd.n173" "vdd.n172" 0.29861
-resist "vdd.n177" "vdd.n176" 0.30337
-resist "vdd.n171" "vdd.n170" 0.316707
-resist "vdd.n149" "vdd.n80" 0.322402
-resist "vdd.n175" "vdd.n174" 0.327284
-resist "vdd.n144" "vdd.n85" 0.327672
-resist "vdd.n143" "vdd.n142" 0.332414
-resist "vdd.n179" "vdd.n178" 0.337861
-resist "vdd.n141" "vdd.n140" 0.338249
-resist "vdd.n121" "vdd.n120" 0.350429
-resist "vdd.n150" "vdd.n21" 0.405064
-resist "vdd.n6" "vdd.n5" 0.433988
-resist "vdd.n139" "vdd.n138" 0.513236
-resist "vdd.n179" "vdd.n5" 0.896718
-resist "vdd.n140" "vdd.n139" 1.0662
-resist "vdd.n265" "vdd.n264" 1.1
-resist "vdd.n231" "vdd.n188" 1.1
-resist "vdd.n158" "vdd.n157" 1.1
-resist "vdd.n73" "vdd.n65" 1.1
-resist "vdd.n100" "vdd.n99" 1.1
-resist "vdd.n102" "vdd.n101" 1.1
-resist "vdd.n113" "vdd.n0" 1.1
-resist "vdd.n160" "vdd.n159" 1.1
-resist "vdd.n187" "vdd.n186" 1.1
-resist "vdd.n10" "vdd.n1" 1.1
-resist "vdd.n34" "vdd.n33" 1.1
-resist "vdd.n44" "vdd.n43" 1.1
-resist "vdd.n54" "vdd.n53" 1.1
-resist "vdd.n64" "vdd.n63" 1.1
-resist "vdd.n139" "vdd.n121" 1.21108
-resist "vdd.n121" "vdd.n5" 1.27246
-resist "vdd.n169" "vdd.n168" 1.2829
-resist "vdd.n168" "vdd.n167" 1.52512
-resist "vdd.n169" "vdd.n20" 1.66793
-resist "vdd.n167" "vdd.n166" 1.66793
-resist "vdd.n140" "vdd.n119" 1.66793
-resist "vdd.n142" "vdd.n108" 1.66793
-resist "vdd.n144" "vdd.n86" 1.66793
-resist "vdd.n80" "vdd.n79" 1.66793
-resist "vdd.n151" "vdd.n150" 1.66793
-resist "vdd.n171" "vdd.n19" 1.66793
-resist "vdd.n173" "vdd.n18" 1.66793
-resist "vdd.n175" "vdd.n17" 1.66793
-resist "vdd.n177" "vdd.n16" 1.66793
-resist "vdd.n180" "vdd.n179" 1.66793
-resist "vdd.n147" "vdd.n6" 1.88889
-resist "vdd.n238" "vdd.n237" 1.89887
-resist "vdd.n258" "vdd.n257" 1.89887
-resist "vdd.n176" "vdd.n6" 1.9976
-resist "vdd.n172" "vdd.n6" 1.99768
-resist "vdd.n63" "vdd.n62" 2.25719
-resist "vdd.n63" "vdd.n55" 2.25719
-resist "vdd.n160" "vdd.n23" 2.25719
-resist "vdd.n161" "vdd.n160" 2.25719
-resist "vdd.n113" "vdd.n111" 2.25719
-resist "vdd.n114" "vdd.n113" 2.25719
-resist "vdd.n102" "vdd.n89" 2.25719
-resist "vdd.n103" "vdd.n102" 2.25719
-resist "vdd.n99" "vdd.n98" 2.25719
-resist "vdd.n99" "vdd.n91" 2.25719
-resist "vdd.n73" "vdd.n71" 2.25719
-resist "vdd.n74" "vdd.n73" 2.25719
-resist "vdd.n157" "vdd.n156" 2.25719
-resist "vdd.n157" "vdd.n66" 2.25719
-resist "vdd.n53" "vdd.n52" 2.25719
-resist "vdd.n53" "vdd.n45" 2.25719
-resist "vdd.n43" "vdd.n42" 2.25719
-resist "vdd.n43" "vdd.n35" 2.25719
-resist "vdd.n33" "vdd.n32" 2.25719
-resist "vdd.n33" "vdd.n25" 2.25719
-resist "vdd.n10" "vdd.n8" 2.25719
-resist "vdd.n11" "vdd.n10" 2.25719
-resist "vdd.n186" "vdd.n185" 2.25719
-resist "vdd.n186" "vdd.n2" 2.25719
-resist "vdd.n231" "vdd.n229" 2.25719
-resist "vdd.n232" "vdd.n231" 2.25719
-resist "vdd.n264" "vdd.n263" 2.25719
-resist "vdd.n264" "vdd.n189" 2.25719
-resist "vdd.n56" "vdd.n20" 2.28067
-resist "vdd.n58" "vdd.n20" 2.28067
-resist "vdd.n166" "vdd.n165" 2.28067
-resist "vdd.n166" "vdd.n22" 2.28067
-resist "vdd.n119" "vdd.n118" 2.28067
-resist "vdd.n119" "vdd.n110" 2.28067
-resist "vdd.n108" "vdd.n107" 2.28067
-resist "vdd.n108" "vdd.n88" 2.28067
-resist "vdd.n92" "vdd.n86" 2.28067
-resist "vdd.n94" "vdd.n86" 2.28067
-resist "vdd.n79" "vdd.n78" 2.28067
-resist "vdd.n79" "vdd.n70" 2.28067
-resist "vdd.n151" "vdd.n67" 2.28067
-resist "vdd.n152" "vdd.n151" 2.28067
-resist "vdd.n46" "vdd.n19" 2.28067
-resist "vdd.n48" "vdd.n19" 2.28067
-resist "vdd.n36" "vdd.n18" 2.28067
-resist "vdd.n38" "vdd.n18" 2.28067
-resist "vdd.n26" "vdd.n17" 2.28067
-resist "vdd.n28" "vdd.n17" 2.28067
-resist "vdd.n16" "vdd.n15" 2.28067
-resist "vdd.n16" "vdd.n7" 2.28067
-resist "vdd.n180" "vdd.n3" 2.28067
-resist "vdd.n181" "vdd.n180" 2.28067
-resist "vdd.n237" "vdd.n236" 2.28067
-resist "vdd.n237" "vdd.n228" 2.28067
-resist "vdd.n258" "vdd.n190" 2.28067
-resist "vdd.n259" "vdd.n258" 2.28067
-resist "vdd.n138" "vdd.n82" 2.42901
-resist "vdd.n120" "vdd.t2" 2.49177
-resist "vdd.n120" "vdd.t8" 2.49551
-resist "vdd.n21" "vdd.n6" 2.7349
-resist "vdd.n148" "vdd.n147" 2.83333
-resist "vdd.n147" "vdd.n146" 2.83333
-resist "vdd.n147" "vdd.n84" 2.83333
-resist "vdd.n147" "vdd.n83" 2.83333
-resist "vdd.n178" "vdd.n6" 4.15998
-resist "vdd.n174" "vdd.n6" 4.15998
-resist "vdd.n170" "vdd.n6" 4.15998
-resist "vdd.n143" "vdd.n84" 4.16004
-resist "vdd.n146" "vdd.n85" 4.16016
-resist "vdd.n141" "vdd.n83" 4.16016
-resist "vdd.n149" "vdd.n148" 4.16042
-resist "vdd.n61" "vdd.n60" 4.5
-resist "vdd.n59" "vdd.n57" 4.5
-resist "vdd.n164" "vdd.n163" 4.5
-resist "vdd.n162" "vdd.n24" 4.5
-resist "vdd.n117" "vdd.n116" 4.5
-resist "vdd.n115" "vdd.n112" 4.5
-resist "vdd.n106" "vdd.n105" 4.5
-resist "vdd.n104" "vdd.n90" 4.5
-resist "vdd.n97" "vdd.n96" 4.5
-resist "vdd.n95" "vdd.n93" 4.5
-resist "vdd.n77" "vdd.n76" 4.5
-resist "vdd.n75" "vdd.n72" 4.5
-resist "vdd.n155" "vdd.n154" 4.5
-resist "vdd.n153" "vdd.n68" 4.5
-resist "vdd.n51" "vdd.n50" 4.5
-resist "vdd.n49" "vdd.n47" 4.5
-resist "vdd.n41" "vdd.n40" 4.5
-resist "vdd.n39" "vdd.n37" 4.5
-resist "vdd.n31" "vdd.n30" 4.5
-resist "vdd.n29" "vdd.n27" 4.5
-resist "vdd.n14" "vdd.n13" 4.5
-resist "vdd.n12" "vdd.n9" 4.5
-resist "vdd.n184" "vdd.n183" 4.5
-resist "vdd.n182" "vdd.n4" 4.5
-resist "vdd.n233" "vdd.n230" 4.5
-resist "vdd.n235" "vdd.n234" 4.5
-resist "vdd.n260" "vdd.n191" 4.5
-resist "vdd.n262" "vdd.n261" 4.5
-resist "vdd.n62" "vdd.n56" 4.56124
-resist "vdd.n58" "vdd.n55" 4.56124
-resist "vdd.n165" "vdd.n23" 4.56124
-resist "vdd.n161" "vdd.n22" 4.56124
-resist "vdd.n118" "vdd.n111" 4.56124
-resist "vdd.n114" "vdd.n110" 4.56124
-resist "vdd.n107" "vdd.n89" 4.56124
-resist "vdd.n103" "vdd.n88" 4.56124
-resist "vdd.n98" "vdd.n92" 4.56124
-resist "vdd.n94" "vdd.n91" 4.56124
-resist "vdd.n78" "vdd.n71" 4.56124
-resist "vdd.n74" "vdd.n70" 4.56124
-resist "vdd.n156" "vdd.n67" 4.56124
-resist "vdd.n152" "vdd.n66" 4.56124
-resist "vdd.n52" "vdd.n46" 4.56124
-resist "vdd.n48" "vdd.n45" 4.56124
-resist "vdd.n42" "vdd.n36" 4.56124
-resist "vdd.n38" "vdd.n35" 4.56124
-resist "vdd.n32" "vdd.n26" 4.56124
-resist "vdd.n28" "vdd.n25" 4.56124
-resist "vdd.n15" "vdd.n8" 4.56124
-resist "vdd.n11" "vdd.n7" 4.56124
-resist "vdd.n185" "vdd.n3" 4.56124
-resist "vdd.n181" "vdd.n2" 4.56124
-resist "vdd.n236" "vdd.n229" 4.56124
-resist "vdd.n232" "vdd.n228" 4.56124
-resist "vdd.n263" "vdd.n190" 4.56124
-resist "vdd.n259" "vdd.n189" 4.56124
-resist "vdd.n257" "vdd.n256" 4.689
-resist "vdd.n239" "vdd.n238" 4.689
-resist "vdd.n238" "vdd.n227" 5.20486
-resist "vdd.n257" "vdd.n192" 5.20486
-resist "vdd.n135" "vdd.n121" 5.66728
-resist "vdd.t5" "vdd.n195" 8.47868
-resist "vdd.t5" "vdd.n198" 8.47868
-resist "vdd.t5" "vdd.n200" 8.47868
-resist "vdd.n255" "vdd.t5" 8.47868
-resist "vdd.n226" "vdd.t4" 8.47868
-resist "vdd.t4" "vdd.n206" 8.47868
-resist "vdd.t4" "vdd.n208" 8.47868
-resist "vdd.t4" "vdd.n225" 8.47868
-resist "vdd.n122" "vdd.n6" 8.5
-resist "vdd.n124" "vdd.n6" 8.5
-resist "vdd.n126" "vdd.n6" 8.5
-resist "vdd.n128" "vdd.n6" 8.5
-resist "vdd.t0" "vdd.n6" 8.5
-resist "vdd.n131" "vdd.n6" 8.5
-resist "vdd.n133" "vdd.n6" 8.5
-resist "vdd.n136" "vdd.n6" 8.5
-resist "vdd.n150" "vdd.n69" 8.5005
-resist "vdd.n81" "vdd.n80" 8.5005
-resist "vdd.n145" "vdd.n144" 8.5005
-resist "vdd.n142" "vdd.n87" 8.5005
-resist "vdd.n140" "vdd.n109" 8.5005
-resist "vdd.n138" "vdd.n137" 8.5005
-resist "vdd.n138" "vdd.n134" 8.5005
-resist "vdd.n138" "vdd.n132" 8.5005
-resist "vdd.n138" "vdd.n130" 8.5005
-resist "vdd.n138" "vdd.n129" 8.5005
-resist "vdd.n138" "vdd.n127" 8.5005
-resist "vdd.n138" "vdd.n125" 8.5005
-resist "vdd.n138" "vdd.n123" 8.5005
-resist "vdd.n203" "vdd.n202" 9
-resist "vdd.n224" "vdd.n223" 9
-resist "vdd.n222" "vdd.n221" 9
-resist "vdd.n220" "vdd.n219" 9
-resist "vdd.n218" "vdd.n217" 9
-resist "vdd.n216" "vdd.n215" 9
-resist "vdd.n214" "vdd.n213" 9
-resist "vdd.n212" "vdd.n211" 9
-resist "vdd.n241" "vdd.n240" 9
-resist "vdd.n194" "vdd.n193" 9
-resist "vdd.n253" "vdd.n252" 9
-resist "vdd.n251" "vdd.n250" 9
-resist "vdd.n249" "vdd.n248" 9
-resist "vdd.n247" "vdd.n246" 9
-resist "vdd.n245" "vdd.n244" 9
-resist "vdd.n243" "vdd.n242" 9
-resist "vdd.n256" "vdd.n255" 9.05914
-resist "vdd.n239" "vdd.n195" 9.05914
-resist "vdd.n225" "vdd.n192" 9.05914
-resist "vdd.n227" "vdd.n226" 9.05914
-resist "vdd.t5" "vdd.n196" 17
-resist "vdd.t5" "vdd.n197" 17
-resist "vdd.t5" "vdd.n199" 17
-resist "vdd.t5" "vdd.n201" 17
-resist "vdd.t5" "vdd.n254" 17
-resist "vdd.t4" "vdd.n204" 17
-resist "vdd.t4" "vdd.n205" 17
-resist "vdd.t4" "vdd.n207" 17
-resist "vdd.t4" "vdd.n209" 17
-resist "vdd.t4" "vdd.n210" 17
-killnode "a_687_2445#"
-rnode "a_687_2445.t1" 0 380.87 916 1105 0
-rnode "a_687_2445.t0" 0 380.87 810 1475 0
-rnode "a_687_2445.n0" 0 28.0974 916 1771 0
-rnode "a_687_2445.t4" 0 639.364 2757 4387 0
-rnode "a_687_2445.t5" 0 589.433 2757 3445 0
-rnode "a_687_2445.n1" 0 1755.8 2629 3445 0
-rnode "a_687_2445.t6" 0 507.043 3430 1475 0
-rnode "a_687_2445.n2" 0 2338.61 2301 3170 0
-rnode "a_687_2445.t2" 0 616.633 2015 4859 0
-rnode "a_687_2445.t3" 0 589.44 1867 3917 0
-rnode "a_687_2445.n3" 0 1675.86 1765 3917 0
-rnode "a_687_2445.n4" 0 887.58 1765 3170 0
-rnode "a_687_2445.t7" 0 808.703 1209 2569 0
-rnode "a_687_2445.n5" 0 1007.27 1210 2523 0
-rnode "a_687_2445.n6" 0 385.196 882 1782 0
-rnode "a_687_2445.n7" 0 36.8109 882 1686 0
-rnode "a_687_2445.n8" 0 36.8109 882 1590 0
-rnode "a_687_2445.n9" 0 0 916 1771 0
-rnode "a_687_2445.n10" 0 28.0974 916 1697 0
-rnode "a_687_2445.n11" 0 30.7419 916 1475 0
-rnode "a_687_2445.n12" 0 36.8109 882 1590 0
-rnode "a_687_2445.n13" 0 36.8109 882 1494 0
-rnode "a_687_2445.n14" 0 36.8109 882 1398 0
-rnode "a_687_2445.n15" 0 36.8109 882 1302 0
-rnode "a_687_2445.n16" 0 0 916 1475 0
-rnode "a_687_2445.n17" 0 25.4529 916 1401 0
-rnode "a_687_2445.n18" 0 31.7335 916 1179 0
-rnode "a_687_2445.n19" 0 14.9809 916 1105 0
-rnode "a_687_2445.n20" 0 24.7037 882 1110 0
-rnode "a_687_2445.n21" 0 100.612 882 1302 0
-rnode "a_687_2445.n22" 0 31.8181 882 1206 0
-rnode "a_687_2445.n23" 0 36.8109 882 1206 0
-rnode "a_687_2445.n24" 0 24.4613 882 1206 0
-rnode "a_687_2445.n25" 0 31.7335 916 1253 0
-rnode "a_687_2445.n26" 0 24.4613 882 1302 0
-rnode "a_687_2445.n27" 0 31.7335 916 1327 0
-rnode "a_687_2445.n28" 0 24.4613 882 1398 0
-rnode "a_687_2445.n29" 0 36.8109 882 1398 0
-rnode "a_687_2445.n30" 0 36.8109 882 1494 0
-rnode "a_687_2445.n31" 0 24.4613 882 1494 0
-rnode "a_687_2445.n32" 0 31.7335 916 1549 0
-rnode "a_687_2445.n33" 0 24.4613 882 1590 0
-rnode "a_687_2445.n34" 0 31.7335 916 1623 0
-rnode "a_687_2445.n35" 0 24.4613 882 1686 0
-rnode "a_687_2445.n36" 0 36.8109 882 1686 0
-rnode "a_687_2445.n37" 0 29.5254 882 1782 0
-rnode "a_687_2445.n38" 0 49.6163 882 1782 0
-rnode "a_687_2445.n39" 0 0.135644 848 1811 0
-resist "a_687_2445.n39" "a_687_2445.t1" 0.0005
-resist "a_687_2445.n39" "a_687_2445.t0" 0.0005
-resist "a_687_2445.n28" "a_687_2445.n17" 0.0033
-resist "a_687_2445.n20" "a_687_2445.n19" 0.0055
-resist "a_687_2445.n35" "a_687_2445.n10" 0.0121
-resist "a_687_2445.n38" "a_687_2445.n0" 0.0121
-resist "a_687_2445.n31" "a_687_2445.n11" 0.0209
-resist "a_687_2445.n27" "a_687_2445.n26" 0.0275
-resist "a_687_2445.n24" "a_687_2445.n18" 0.0297
-resist "a_687_2445.n34" "a_687_2445.n33" 0.0363
-resist "a_687_2445.n16" "a_687_2445.n11" 0.0411028
-resist "a_687_2445.n9" "a_687_2445.n0" 0.0411028
-resist "a_687_2445.n17" "a_687_2445.n16" 0.0411028
-resist "a_687_2445.n10" "a_687_2445.n9" 0.0411028
-resist "a_687_2445.n33" "a_687_2445.n32" 0.0451
-resist "a_687_2445.n25" "a_687_2445.n24" 0.0517
-resist "a_687_2445.n26" "a_687_2445.n25" 0.0539
-resist "a_687_2445.n32" "a_687_2445.n31" 0.0605
-resist "a_687_2445.n35" "a_687_2445.n34" 0.0693
-resist "a_687_2445.n23" "a_687_2445.n22" 0.0721677
-resist "a_687_2445.n20" "a_687_2445.n18" 0.0759
-resist "a_687_2445.n28" "a_687_2445.n27" 0.0781
-resist "a_687_2445.n23" "a_687_2445.n15" 0.145655
-resist "a_687_2445.n29" "a_687_2445.n15" 0.145655
-resist "a_687_2445.n30" "a_687_2445.n29" 0.145655
-resist "a_687_2445.n30" "a_687_2445.n8" 0.145655
-resist "a_687_2445.n36" "a_687_2445.n8" 0.145655
-resist "a_687_2445.n37" "a_687_2445.n36" 0.145655
-resist "a_687_2445.n21" "a_687_2445.n14" 0.145655
-resist "a_687_2445.n14" "a_687_2445.n13" 0.145655
-resist "a_687_2445.n13" "a_687_2445.n12" 0.145655
-resist "a_687_2445.n12" "a_687_2445.n7" 0.145655
-resist "a_687_2445.n7" "a_687_2445.n6" 0.145655
-resist "a_687_2445.n4" "a_687_2445.n2" 0.336914
-resist "a_687_2445.n2" "a_687_2445.n1" 2.62903
-resist "a_687_2445.n4" "a_687_2445.n3" 2.71954
-resist "a_687_2445.n22" "a_687_2445.n21" 4.64616
-resist "a_687_2445.n5" "a_687_2445.n4" 5.41759
-resist "a_687_2445.n16" "a_687_2445.t0" 8.4802
-resist "a_687_2445.n9" "a_687_2445.t0" 8.4802
-resist "a_687_2445.n39" "a_687_2445.n38" 8.59084
-resist "a_687_2445.n26" "a_687_2445.n15" 9
-resist "a_687_2445.n24" "a_687_2445.n23" 9
-resist "a_687_2445.n29" "a_687_2445.n28" 9
-resist "a_687_2445.n31" "a_687_2445.n30" 9
-resist "a_687_2445.n33" "a_687_2445.n8" 9
-resist "a_687_2445.n36" "a_687_2445.n35" 9
-resist "a_687_2445.n38" "a_687_2445.n37" 9
-resist "a_687_2445.n21" "a_687_2445.n15" 9
-resist "a_687_2445.n37" "a_687_2445.n6" 9
-resist "a_687_2445.n36" "a_687_2445.n7" 9
-resist "a_687_2445.n12" "a_687_2445.n8" 9
-resist "a_687_2445.n30" "a_687_2445.n13" 9
-resist "a_687_2445.n29" "a_687_2445.n14" 9
-resist "a_687_2445.n22" "a_687_2445.n20" 9.07333
-resist "a_687_2445.n6" "a_687_2445.n5" 10.1265
-resist "a_687_2445.n3" "a_687_2445.t3" 10.7763
-resist "a_687_2445.n1" "a_687_2445.t5" 10.7822
-resist "a_687_2445.n3" "a_687_2445.t2" 11.3694
-resist "a_687_2445.n1" "a_687_2445.t4" 11.3743
-resist "a_687_2445.n5" "a_687_2445.t7" 16.5253
-resist "a_687_2445.n19" "a_687_2445.t1" 17
-resist "a_687_2445.n19" "a_687_2445.t0" 17
-resist "a_687_2445.n18" "a_687_2445.t1" 17
-resist "a_687_2445.n18" "a_687_2445.t0" 17
-resist "a_687_2445.n25" "a_687_2445.t1" 17
-resist "a_687_2445.n25" "a_687_2445.t0" 17
-resist "a_687_2445.n27" "a_687_2445.t1" 17
-resist "a_687_2445.n27" "a_687_2445.t0" 17
-resist "a_687_2445.n17" "a_687_2445.t1" 17
-resist "a_687_2445.n11" "a_687_2445.t1" 17
-resist "a_687_2445.n32" "a_687_2445.t1" 17
-resist "a_687_2445.n32" "a_687_2445.t0" 17
-resist "a_687_2445.n34" "a_687_2445.t1" 17
-resist "a_687_2445.n34" "a_687_2445.t0" 17
-resist "a_687_2445.n10" "a_687_2445.t1" 17
-resist "a_687_2445.n0" "a_687_2445.t1" 17
-resist "a_687_2445.n2" "a_687_2445.t6" 42.3311
-killnode "a_1245_3300#"
-rnode "a_1245_3300.t0" 0 514.371 1645 3562 0
-rnode "a_1245_3300.n0" 0 465.628 1575 3562 0
-rnode "a_1245_3300.n1" 0 219.916 1842 2124 0
-rnode "a_1245_3300.n2" 0 69.2027 1866 2129 0
-rnode "a_1245_3300.n3" 0 46.9363 1866 2129 0
-rnode "a_1245_3300.n4" 0 63.1201 1782 2129 0
-rnode "a_1245_3300.n5" 0 34.6014 2482 2129 0
-rnode "a_1245_3300.n6" 0 34.6014 2412 2129 0
-rnode "a_1245_3300.n7" 0 15.4 1782 2129 0
-rnode "a_1245_3300.n8" 0 34.6014 2202 2129 0
-rnode "a_1245_3300.n9" 0 15.4 1782 2129 0
-rnode "a_1245_3300.n10" 0 34.6014 1992 2129 0
-rnode "a_1245_3300.n11" 0 45.6936 2154 2129 0
-rnode "a_1245_3300.n12" 0 69.2027 2154 2129 0
-rnode "a_1245_3300.n13" 0 49.1983 2058 2129 0
-rnode "a_1245_3300.n14" 0 45.6936 2250 2129 0
-rnode "a_1245_3300.n15" 0 69.2027 2250 2129 0
-rnode "a_1245_3300.n16" 0 0.033832 2346 2129 0
-rnode "a_1245_3300.t16" 0 386.309 2412 1585 0
-rnode "a_1245_3300.n17" 0 261.357 2412 1585 0
-rnode "a_1245_3300.n18" 0 439.647 1912 1857 0
-rnode "a_1245_3300.t17" 0 431.063 2412 1857 0
-rnode "a_1245_3300.n19" 0 255.144 2412 1857 0
-rnode "a_1245_3300.n20" 0 438.158 2316 1857 0
-rnode "a_1245_3300.n21" 0 69.2027 2538 2129 0
-rnode "a_1245_3300.t12" 0 509.755 2535 3329 0
-rnode "a_1245_3300.t13" 0 507.412 2535 3561 0
-rnode "a_1245_3300.n22" 0 642.866 2447 3560 0
-rnode "a_1245_3300.t11" 0 507.412 2535 4271 0
-rnode "a_1245_3300.n23" 0 465.068 2447 4271 0
-rnode "a_1245_3300.t10" 0 507.412 2535 4503 0
-rnode "a_1245_3300.n24" 0 399.818 2447 4503 0
-rnode "a_1245_3300.n25" 0 1219.78 2447 5134 0
-rnode "a_1245_3300.t14" 0 515.144 1275 3801 0
-rnode "a_1245_3300.t15" 0 507.431 1275 4033 0
-rnode "a_1245_3300.n26" 0 1048.54 1955 4033 0
-rnode "a_1245_3300.t8" 0 507.431 1275 4743 0
-rnode "a_1245_3300.n27" 0 464.614 1955 4743 0
-rnode "a_1245_3300.t9" 0 507.412 1867 4975 0
-rnode "a_1245_3300.n28" 0 194.496 1955 4975 0
-rnode "a_1245_3300.n29" 0 1019.62 1955 5134 0
-rnode "a_1245_3300.t4" 0 514.371 1645 4272 0
-rnode "a_1245_3300.n30" 0 465.628 1575 4272 0
-rnode "a_1245_3300.t5" 0 514.371 1645 4504 0
-rnode "a_1245_3300.n31" 0 400.378 1575 4504 0
-rnode "a_1245_3300.n32" 0 1070.98 1575 5064 0
-rnode "a_1245_3300.n33" 0 862.176 2817 5134 0
-rnode "a_1245_3300.t2" 0 514.349 2905 4974 0
-rnode "a_1245_3300.n34" 0 195.949 2817 4974 0
-rnode "a_1245_3300.t3" 0 514.349 2905 4742 0
-rnode "a_1245_3300.n35" 0 465.651 2817 4742 0
-rnode "a_1245_3300.t6" 0 514.349 2905 4032 0
-rnode "a_1245_3300.n36" 0 465.651 2817 4032 0
-rnode "a_1245_3300.t7" 0 514.349 2905 3800 0
-rnode "a_1245_3300.n37" 0 947.586 2817 3800 0
-rnode "a_1245_3300.n38" 0 833.861 2634 2129 0
-rnode "a_1245_3300.n39" 0 55.7418 2634 2129 0
-rnode "a_1245_3300.n40" 0 46.9363 2538 2129 0
-rnode "a_1245_3300.n41" 0 69.2027 2538 2129 0
-rnode "a_1245_3300.n42" 0 25.2302 2442 2129 0
-rnode "a_1245_3300.n43" 0 49.1983 2346 2129 0
-rnode "a_1245_3300.n44" 0 69.2027 2346 2129 0
-rnode "a_1245_3300.n45" 0 69.2027 2442 2129 0
-rnode "a_1245_3300.n46" 0 54.7855 2442 2129 0
-rnode "a_1245_3300.n47" 0 219.916 2386 2124 0
-rnode "a_1245_3300.n48" 0 67.761 2154 2129 0
-rnode "a_1245_3300.n49" 0 61.9941 2058 2129 0
-rnode "a_1245_3300.n50" 0 69.2027 2058 2129 0
-rnode "a_1245_3300.n51" 0 0.033832 1962 2129 0
-rnode "a_1245_3300.n52" 0 69.2027 1962 2129 0
-rnode "a_1245_3300.n53" 0 25.2302 1962 2129 0
-rnode "a_1245_3300.n54" 0 34.6014 1922 2129 0
-rnode "a_1245_3300.t18" 0 380.317 1782 2129 0
-rnode "a_1245_3300.n55" 0 63.1201 1782 2129 0
-rnode "a_1245_3300.n56" 0 55.7418 1770 2129 0
-rnode "a_1245_3300.n57" 0 622.184 1770 2129 0
-rnode "a_1245_3300.n58" 0 750.362 1575 3330 0
-rnode "a_1245_3300.t1" 0 514.348 1645 3368 0
-resist "a_1245_3300.n53" "a_1245_3300.n10" 0.0284483
-resist "a_1245_3300.n42" "a_1245_3300.n6" 0.0284483
-resist "a_1245_3300.n16" "a_1245_3300.n15" 0.0367671
-resist "a_1245_3300.n51" "a_1245_3300.n2" 0.0367671
-resist "a_1245_3300.n52" "a_1245_3300.n51" 0.0367671
-resist "a_1245_3300.n44" "a_1245_3300.n16" 0.0367671
-resist "a_1245_3300.n13" "a_1245_3300.n9" 0.0374181
-resist "a_1245_3300.n43" "a_1245_3300.n7" 0.0374181
-resist "a_1245_3300.n54" "a_1245_3300.n53" 0.037931
-resist "a_1245_3300.n42" "a_1245_3300.n5" 0.037931
-resist "a_1245_3300.n47" "a_1245_3300.n46" 0.0424828
-resist "a_1245_3300.n11" "a_1245_3300.n8" 0.0455172
-resist "a_1245_3300.n14" "a_1245_3300.n8" 0.0455172
-resist "a_1245_3300.n55" "a_1245_3300.n3" 0.0469008
-resist "a_1245_3300.n40" "a_1245_3300.n4" 0.0469008
-resist "a_1245_3300.n54" "a_1245_3300.n3" 0.0531034
-resist "a_1245_3300.n40" "a_1245_3300.n5" 0.0531034
-resist "a_1245_3300.n11" "a_1245_3300.n9" 0.0544871
-resist "a_1245_3300.n14" "a_1245_3300.n7" 0.0544871
-resist "a_1245_3300.n57" "a_1245_3300.n1" 0.0546207
-resist "a_1245_3300.n29" "a_1245_3300.n28" 0.0559429
-resist "a_1245_3300.n34" "a_1245_3300.n33" 0.0565714
-resist "a_1245_3300.n49" "a_1245_3300.n1" 0.0576552
-resist "a_1245_3300.n13" "a_1245_3300.n10" 0.0625862
-resist "a_1245_3300.n43" "a_1245_3300.n6" 0.0625862
-resist "a_1245_3300.n48" "a_1245_3300.n47" 0.0697931
-resist "a_1245_3300.n46" "a_1245_3300.n21" 0.0728276
-resist "a_1245_3300.n38" "a_1245_3300.n21" 0.0728276
-resist "a_1245_3300.n49" "a_1245_3300.n48" 0.0728276
-resist "a_1245_3300.n56" "a_1245_3300.n2" 0.0728276
-resist "a_1245_3300.n52" "a_1245_3300.n50" 0.0728276
-resist "a_1245_3300.n50" "a_1245_3300.n12" 0.0728276
-resist "a_1245_3300.n15" "a_1245_3300.n12" 0.0728276
-resist "a_1245_3300.n45" "a_1245_3300.n44" 0.0728276
-resist "a_1245_3300.n45" "a_1245_3300.n41" 0.0728276
-resist "a_1245_3300.n41" "a_1245_3300.n39" 0.0728276
-resist "a_1245_3300.n58" "a_1245_3300.n0" 0.145829
-resist "a_1245_3300.n31" "a_1245_3300.n30" 0.145829
-resist "a_1245_3300.n37" "a_1245_3300.n36" 0.145829
-resist "a_1245_3300.n35" "a_1245_3300.n34" 0.145829
-resist "a_1245_3300.n28" "a_1245_3300.n27" 0.145829
-resist "a_1245_3300.n24" "a_1245_3300.n23" 0.145829
-resist "a_1245_3300.n47" "a_1245_3300.n20" 0.167829
-resist "a_1245_3300.n18" "a_1245_3300.n1" 0.167829
-resist "a_1245_3300.n33" "a_1245_3300.n25" 0.232571
-resist "a_1245_3300.n32" "a_1245_3300.n29" 0.238857
-resist "a_1245_3300.n29" "a_1245_3300.n25" 0.291572
-resist "a_1245_3300.n32" "a_1245_3300.n31" 0.352
-resist "a_1245_3300.n25" "a_1245_3300.n24" 0.352629
-resist "a_1245_3300.n30" "a_1245_3300.n0" 0.446286
-resist "a_1245_3300.n36" "a_1245_3300.n35" 0.446286
-resist "a_1245_3300.n27" "a_1245_3300.n26" 0.446286
-resist "a_1245_3300.n23" "a_1245_3300.n22" 0.446914
-resist "a_1245_3300.n58" "a_1245_3300.n57" 0.852885
-resist "a_1245_3300.n17" "a_1245_3300.t16" 1.12252
-resist "a_1245_3300.n19" "a_1245_3300.t17" 1.12262
-resist "a_1245_3300.n38" "a_1245_3300.n37" 1.13921
-resist "a_1245_3300.n47" "a_1245_3300.n16" 4.48551
-resist "a_1245_3300.n51" "a_1245_3300.n1" 4.48551
-resist "a_1245_3300.n33" "a_1245_3300.n32" 5.28069
-resist "a_1245_3300.t18" "a_1245_3300.n4" 8.48394
-resist "a_1245_3300.t18" "a_1245_3300.n7" 8.48394
-resist "a_1245_3300.t18" "a_1245_3300.n9" 8.48394
-resist "a_1245_3300.n55" "a_1245_3300.t18" 8.48394
-resist "a_1245_3300.n41" "a_1245_3300.n21" 9
-resist "a_1245_3300.n39" "a_1245_3300.n38" 9
-resist "a_1245_3300.n46" "a_1245_3300.n45" 9
-resist "a_1245_3300.n50" "a_1245_3300.n49" 9
-resist "a_1245_3300.n48" "a_1245_3300.n12" 9
-resist "a_1245_3300.n57" "a_1245_3300.n56" 9
-resist "a_1245_3300.n41" "a_1245_3300.n40" 9
-resist "a_1245_3300.n3" "a_1245_3300.n2" 9
-resist "a_1245_3300.n53" "a_1245_3300.n52" 9
-resist "a_1245_3300.n50" "a_1245_3300.n13" 9
-resist "a_1245_3300.n12" "a_1245_3300.n11" 9
-resist "a_1245_3300.n15" "a_1245_3300.n14" 9
-resist "a_1245_3300.n44" "a_1245_3300.n43" 9
-resist "a_1245_3300.n45" "a_1245_3300.n42" 9
-resist "a_1245_3300.n56" "a_1245_3300.n55" 9.045
-resist "a_1245_3300.n39" "a_1245_3300.n4" 9.045
-resist "a_1245_3300.n20" "a_1245_3300.n19" 9.42479
-resist "a_1245_3300.n20" "a_1245_3300.n17" 9.59461
-resist "a_1245_3300.n19" "a_1245_3300.n18" 9.60058
-resist "a_1245_3300.n18" "a_1245_3300.n17" 9.77278
-resist "a_1245_3300.n37" "a_1245_3300.t7" 10.7416
-resist "a_1245_3300.n36" "a_1245_3300.t6" 10.7416
-resist "a_1245_3300.n35" "a_1245_3300.t3" 10.7416
-resist "a_1245_3300.n34" "a_1245_3300.t2" 10.7416
-resist "a_1245_3300.n0" "a_1245_3300.t0" 10.7424
-resist "a_1245_3300.n30" "a_1245_3300.t4" 10.7424
-resist "a_1245_3300.n31" "a_1245_3300.t5" 10.7424
-resist "a_1245_3300.t1" "a_1245_3300.n58" 10.7443
-resist "a_1245_3300.n26" "a_1245_3300.t15" 11.0407
-resist "a_1245_3300.n27" "a_1245_3300.t8" 11.0407
-resist "a_1245_3300.n28" "a_1245_3300.t9" 11.0433
-resist "a_1245_3300.n22" "a_1245_3300.t13" 11.0433
-resist "a_1245_3300.n23" "a_1245_3300.t11" 11.0433
-resist "a_1245_3300.n24" "a_1245_3300.t10" 11.0433
-resist "a_1245_3300.n26" "a_1245_3300.t14" 11.1865
-resist "a_1245_3300.n22" "a_1245_3300.t12" 11.1885
-resist "a_1245_3300.t18" "a_1245_3300.n5" 17
-resist "a_1245_3300.t18" "a_1245_3300.n6" 17
-resist "a_1245_3300.t18" "a_1245_3300.n8" 17
-resist "a_1245_3300.t18" "a_1245_3300.n10" 17
-resist "a_1245_3300.t18" "a_1245_3300.n54" 17
-rnode "V-.t2" 0 418.128 3223 3482 0
-rnode "V-.t1" 0 576.992 2111 4896 0
-rnode "V-.t3" 0 501.749 2111 3954 0
-rnode "V-.n0" 0 213.798 2111 3954 0
-rnode "V-.n1" 0 211.122 2293 4338 0
-rnode "V-.t0" 0 341.019 2291 4350 0
-rnode "V-.n2" 0 1132.22 3226 4387 0
-rnode "V-" 0 704.976 3313 6717 0
-resist "V-.n1" "V-.n0" 0.931927
-resist "V-" "V-.n2" 1.57733
-resist "V-.n0" "V-.t3" 7.51096
-resist "V-.t0" "V-.n1" 7.51096
-resist "V-.t3" "V-.t1" 15.8151
-resist "V-.n2" "V-.t0" 16.5316
-resist "V-.n1" "V-.t1" 17.1078
-resist "V-.n0" "V-.t2" 17.1124
-resist "V-.n2" "V-.t2" 17.1787
-device msubckt sg13_lv_pmos 1752 1623 1753 1624  "vdd.t1" "clk.t2" 120 0 "a_1245_3300.t16" 900 61200,1936 "a_1752_817.t3" 900 34200,976
-device msubckt sg13_lv_nmos 3281 2445 3282 2446  "gnd.t4" "a_944_1911.t6" 80 0 "out+.t0" 400 27200,936 "gnd.t5" 400 15200,476
-device msubckt sg13_lv_pmos 2357 3954 2358 3955  "vdd.t1" "V+.t2" 80 0 "a_944_1911.t2" 800 30400,876 "a_1245_3300.t6" 800 54400,1736
-device msubckt sg13_lv_pmos 1752 1157 1753 1158  "vdd.t1" "vbias.t0" 120 0 "a_1752_817.t0" 900 34200,976 "vdd.t4" 900 34200,976
-device msubckt sg13_lv_pmos 2309 2561 2310 2562  "vdd.t1" "a_944_1911.t6" 80 0 "vdd.t8" 800 30400,876 "out+.t2" 800 54400,1736
-device msubckt sg13_lv_pmos 1752 1895 1753 1896  "vdd.t1" "clk.t2" 120 0 "a_1245_3300.t17" 900 34200,976 "a_1752_817.t4" 900 34200,976
-device msubckt sg13_lv_pmos 1295 2445 1296 2446  "vdd.t1" "a_687_2445.t7" 80 0 "out-.t2" 800 54400,1736 "vdd.t2" 800 30400,876
-device msubckt sg13_lv_pmos 1245 4310 1246 4311  "vdd.t0" "V+.t1" 80 0 "a_1245_3300.t4" 800 54400,1736 "a_944_1911.t3" 800 30400,876
-device msubckt sg13_lv_pmos 1752 1759 1753 1760  "vdd.t1" "clk.t2" 120 0 "a_1752_817.t3" 900 34200,976 "a_1245_3300.t17" 900 34200,976
-device msubckt sg13_lv_pmos 1752 2031 1753 2032  "vdd.t1" "clk.t2" 120 0 "a_1752_817.t4" 900 34200,976 "a_1245_3300.t18" 900 61200,1936
-device msubckt sg13_lv_pmos 1245 4781 1246 4782  "vdd.t0" "V-.t1" 80 0 "a_1245_3300.t8" 800 54400,1736 "a_687_2445.t2" 800 30400,876
-device msubckt sg13_lv_pmos 1245 3484 1246 3485  "vdd.t0" "V+.t0" 80 0 "a_944_1911.t4" 800 30400,876 "a_1245_3300.t0" 800 54400,1736
-device msubckt sg13_lv_pmos 1245 3839 1246 3840  "vdd.t0" "V-.t3" 80 0 "a_1245_3300.t14" 800 54400,1736 "a_687_2445.t3" 800 30400,876
-device msubckt sg13_lv_pmos 2357 4425 2358 4426  "vdd.t1" "V-.t0" 80 0 "a_687_2445.t4" 800 30400,876 "a_1245_3300.t10" 800 54400,1736
-device msubckt sg13_lv_pmos 1752 885 1753 886  "vdd.t1" "vbias.t0" 120 0 "a_1752_817.t1" 900 61200,1936 "vdd.t5" 900 34200,976
-device msubckt sg13_lv_pmos 2357 4896 2358 4897  "vdd.t1" "V+.t3" 80 0 "a_944_1911.t5" 800 30400,876 "a_1245_3300.t2" 800 54400,1736
-device msubckt sg13_lv_nmos 3281 2561 3282 2562  "gnd.t6" "a_944_1911.t6" 80 0 "gnd.t5" 400 15200,476 "out+.t1" 400 27200,936
-device msubckt sg13_lv_nmos 723 2445 724 2446  "gnd.t20" "a_687_2445.t7" 80 0 "out-.t0" 400 27200,936 "gnd.t21" 400 15200,476
-device msubckt sg13_lv_pmos 1295 2561 1296 2562  "vdd.t1" "a_687_2445.t7" 80 0 "vdd.t2" 800 30400,876 "out-.t3" 800 54400,1736
-device msubckt sg13_lv_nmos 3594 1075 3595 1076  "gnd.t2" "clk.t1" 80 0 "a_944_1911.t0" 800 57600,944 "gnd.t3" 800 30400,876
-device msubckt sg13_lv_nmos 1070 1075 1071 1076  "gnd.t10" "gnd.t9" 80 0 "gnd.t8" 800 0 "gnd.t8" 800 30400,876
-device msubckt sg13_lv_pmos 2357 3367 2358 3368  "vdd.t1" "V-.t2" 80 0 "a_1245_3300.t12" 800 54400,1736 "a_687_2445.t5" 800 30400,876
-device msubckt sg13_lv_nmos 3710 1075 3711 1076  "gnd.t12" "gnd.t11" 80 0 "gnd.t3" 800 0 "gnd.t3" 800 30400,876
-device msubckt sg13_lv_pmos 1245 3955 1246 3956  "vdd.t0" "V-.t3" 80 0 "a_687_2445.t3" 800 30400,876 "a_1245_3300.t15" 800 54400,1736
-device msubckt sg13_lv_nmos 723 2561 724 2562  "gnd.t22" "a_687_2445.t7" 80 0 "gnd.t21" 400 15200,476 "out-.t1" 400 27200,936
-device msubckt sg13_lv_nmos 954 1075 955 1076  "gnd.t7" "a_944_1911.t7" 80 0 "a_687_2445.t1" 800 57600,944 "gnd.t8" 800 30400,876
-device msubckt sg13_lv_nmos 770 1075 771 1076  "gnd.t0" "clk.t0" 80 0 "gnd.t1" 800 30400,876 "a_687_2445.t0" 800 57600,944
-device msubckt sg13_lv_pmos 2357 4780 2358 4781  "vdd.t1" "V+.t3" 80 0 "a_1245_3300.t3" 800 54400,1736 "a_944_1911.t5" 800 30400,876
-device msubckt sg13_lv_nmos 3294 1075 3295 1076  "gnd.t14" "gnd.t13" 80 0 "gnd.t15" 800 0 "gnd.t16" 800 54400,1736
-device msubckt sg13_lv_pmos 2357 3483 2358 3484  "vdd.t1" "V-.t2" 80 0 "a_687_2445.t5" 800 30400,876 "a_1245_3300.t13" 800 54400,1736
-device msubckt sg13_lv_pmos 2357 3838 2358 3839  "vdd.t1" "V+.t2" 80 0 "a_1245_3300.t7" 800 54400,1736 "a_944_1911.t2" 800 30400,876
-device msubckt sg13_lv_pmos 1245 4426 1246 4427  "vdd.t0" "V+.t1" 80 0 "a_944_1911.t3" 800 30400,876 "a_1245_3300.t5" 800 54400,1736
-device msubckt sg13_lv_nmos 3410 1075 3411 1076  "gnd.t23" "a_687_2445.t6" 80 0 "gnd.t15" 800 30400,876 "a_944_1911.t1" 800 57600,944
-device msubckt sg13_lv_pmos 2309 2445 2310 2446  "vdd.t1" "a_944_1911.t6" 80 0 "out+.t3" 800 54400,1736 "vdd.t8" 800 30400,876
-device msubckt sg13_lv_pmos 1245 4897 1246 4898  "vdd.t0" "V-.t1" 80 0 "a_687_2445.t2" 800 30400,876 "a_1245_3300.t9" 800 54400,1736
-device msubckt sg13_lv_pmos 1752 1021 1753 1022  "vdd.t1" "vbias.t0" 120 0 "vdd.t5" 900 34200,976 "a_1752_817.t0" 900 34200,976
-device msubckt sg13_lv_nmos 654 1075 655 1076  "gnd.t18" "gnd.t17" 80 0 "gnd.t1" 800 0 "gnd.t19" 800 54400,1736
-device msubckt sg13_lv_pmos 1752 1293 1753 1294  "vdd.t1" "vbias.t0" 120 0 "vdd.t4" 900 34200,976 "a_1752_817.t2" 900 61200,1936
-device msubckt sg13_lv_pmos 1245 3368 1246 3369  "vdd.t0" "V+.t0" 80 0 "a_1245_3300.t1" 800 54400,1736 "a_944_1911.t4" 800 30400,876
-device msubckt sg13_lv_pmos 2357 4309 2358 4310  "vdd.t1" "V-.t0" 80 0 "a_1245_3300.t11" 800 54400,1736 "a_687_2445.t4" 800 30400,876
+scale 1000 1000 100
diff --git a/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/run_kpex.sh b/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/run_kpex.sh
index 5013a80e..7762adcf 100755
--- a/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/run_kpex.sh
+++ b/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator/pex/run_kpex.sh
@@ -6,10 +6,6 @@ set -e
 ###############################################################################
 
 
-# Path to Magic executable used by kpex (adjust if installed elsewhere)
-KPEX_MAGIC_EXE="$HOME/.local/bin/magic" 
-# Example: /usr/local/bin/magic or ~/.local/bin/magic
-
 #Path to symbol
 SYM_DIR="./DIFF_COMPARATOR.sym"       # Asuming you have a symbol for the DUT
 
@@ -27,11 +23,6 @@ SCHEMATIC="../layout/lvs_netlist/DIFF_COMPARATOR.spice" # Spicefile of the compa
 
 
 
-if [[ ! -x "$KPEX_MAGIC_EXE" ]]; then
-  echo "[ERROR] Magic executable not found or not executable: $KPEX_MAGIC_EXE"
-  exit 1
-fi
-
 if [[ ! -f "$LAYOUT_DIR" ]]; then
   echo "[ERROR] Layout GDS file not found: $LAYOUT_DIR"
   exit 1