diff --git a/.gitignore b/.gitignore index ed9c054a..90257c81 100644 --- a/.gitignore +++ b/.gitignore @@ -4,4 +4,6 @@ *.raw *.spice *.osdi -*.cdl +*.dat.ngspice +*.dat + diff --git a/modules/module_1_bandgap_reference/part_1_OTA/schematic/simulations/stage_OTA.cdl b/modules/module_1_bandgap_reference/part_1_OTA/schematic/simulations/stage_OTA.cdl new file mode 100644 index 00000000..3ef56606 --- /dev/null +++ b/modules/module_1_bandgap_reference/part_1_OTA/schematic/simulations/stage_OTA.cdl @@ -0,0 +1,14 @@ +** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sch +.subckt two_stage_OTA vdd iout v+ v- vout vss +*.PININFO v-:B v+:B vss:B vdd:B iout:B vout:B +M4 net3 net1 vss vss sg13_lv_nmos l=9.75u w=720n ng=1 m=1 +M3 net1 net1 vss vss sg13_lv_nmos l=9.75u w=720n ng=1 m=1 +M1 net1 v- net2 vdd sg13_lv_pmos l=3.64u w=3.705u ng=1 m=1 +M2 net3 v+ net2 vdd sg13_lv_pmos l=3.64u w=3.705u ng=1 m=1 +M5 net2 iout vdd vdd sg13_lv_pmos l=1.95u w=5.3u ng=1 m=1 +M7 vout iout vdd vdd sg13_lv_pmos l=2.08u w=75u ng=8 m=1 +M6 vout net3 vss vss sg13_lv_nmos l=9.75u w=28.8u ng=4 m=1 +M9 iout iout vdd vdd sg13_lv_pmos l=2.08u w=75u ng=8 m=1 +C2 net3 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1 +.ends +.end diff --git a/modules/module_1_bandgap_reference/part_3_layout/BGR_layout/final_bandgapreference/full_bandgap_layout_pads_filler_os.gds b/modules/module_1_bandgap_reference/part_3_layout/BGR_layout/final_bandgapreference/full_bandgap_layout_pads_filler_os.gds new file mode 100644 index 00000000..d2e3c2f6 Binary files /dev/null and b/modules/module_1_bandgap_reference/part_3_layout/BGR_layout/final_bandgapreference/full_bandgap_layout_pads_filler_os.gds differ diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/flipped_instance_input_stage.gds b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/flipped_instance_input_stage.gds new file mode 100644 index 00000000..a29b82a0 Binary files /dev/null and b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/flipped_instance_input_stage.gds differ diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/input_common_centroid.gds b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/input_common_centroid.gds new file mode 100644 index 00000000..608bc5d3 Binary files /dev/null and b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/input_common_centroid.gds differ diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/input_stage.gds b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/input_stage.gds new file mode 100644 index 00000000..2622c1c2 Binary files /dev/null and b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/input_stage.gds differ diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/output_stage_only_pmos.gds b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/output_stage_only_pmos.gds new file mode 100644 index 00000000..f9f4ff53 Binary files /dev/null and b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/flipped_layouts/output_stage_only_pmos.gds differ diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/schematic_mod/simulations/two_stage_OTA_layout.cdl b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/schematic_mod/simulations/two_stage_OTA_layout.cdl new file mode 100644 index 00000000..629d2aef --- /dev/null +++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/schematic_mod/simulations/two_stage_OTA_layout.cdl @@ -0,0 +1,23 @@ +** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/schematic_mod/two_stage_OTA_layout.sch +.subckt two_stage_OTA_layout v- v+ vss vdd iout vout +*.PININFO v-:B v+:B vss:B vdd:B iout:B vout:B +M1 dn3 v- dn2 bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +M2 dn4 v+ dn2 bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +M8 dn4 vdd vdd bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +M10 dn3 vdd vdd bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +M15 dn2 vdd vdd bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +M16 dn2 vdd vdd bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +R1 vdd bulk ntap1 A = 0.1979378e-9 P = 0.243602e-3 +M7 dn2 iout vdd bulk1 sg13_lv_pmos l=1.95u w=5.3u ng=1 m=1 +R2 vss bulk2 ptap1 A = 15.54345e-12 P=53.44e-6 +R3 vdd bulk1 ntap1 w=0.78e-6 l=0.78e-6 +M3 dn3 dn3 vss bulk2 sg13_lv_nmos l=9.75u w=720n ng=1 m=1 +M4 dn4 dn3 vss bulk2 sg13_lv_nmos l=9.75u w=720n ng=1 m=1 +M5 vout iout vdd bulk4 sg13_lv_pmos l=2.08u w=75u ng=8 m=1 +M6 vout dn4 vss bulk3 sg13_lv_nmos l=9.75u w=28.8u ng=4 m=1 +M9 iout iout vdd bulk4 sg13_lv_pmos l=2.08u w=75u ng=8 m=1 +C2 dn4 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1 +R4 vss bulk2 ptap1 A = 68.4036e-12, P = 0.24264e-3 +R5 vdd bulk3 ntap1 A = 95.5222e-12, P = 0.21292e-3 +.ends +.end diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/two_stage_OTA_layout.gds b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/two_stage_OTA_layout.gds new file mode 100644 index 00000000..06b0de6a Binary files /dev/null and b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/two_stage_OTA_layout.gds differ diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/simulations/input_common_centroid.cdl b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/simulations/input_common_centroid.cdl new file mode 100644 index 00000000..f42338f6 --- /dev/null +++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/simulations/input_common_centroid.cdl @@ -0,0 +1,13 @@ +** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/input_common_centroid.sch +.subckt input_common_centroid v- v+ vdd dn3 dn4 +*.PININFO v-:B v+:B vdd:B dn3:B dn4:B +M1 dn3 v- dn2 bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +M2 dn4 v+ dn2 bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +M8 dn4 vdd vdd bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +M10 dn3 vdd vdd bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +M15 dn2 vdd vdd bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +M16 dn2 vdd vdd bulk sg13_lv_pmos l=3.7u w=3.64u ng=1 m=2 +R1 vdd bulk ntap1 A = 0.1979248e-9 P = 0.2436e-3 + +.ends +.end diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/input_stage.gds b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/input_stage.gds new file mode 100644 index 00000000..10ce5e65 Binary files /dev/null and b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/input_stage.gds differ diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/input_stage_extracted.cir b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/input_stage_extracted.cir new file mode 100644 index 00000000..48dbdefc --- /dev/null +++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/input_stage_extracted.cir @@ -0,0 +1,12 @@ +* Extracted by KLayout with SG13G2 LVS runset on : 29/01/2025 15:40 + +.SUBCKT input_stage vss dn4 dn3 vdd dn2 iout +M$1 vss dn3 dn4 \$1 sg13_lv_nmos L=9.75u W=0.72u AS=0.2448p AD=0.2448p PS=2.12u ++ PD=2.12u +M$2 vss dn3 dn3 \$1 sg13_lv_nmos L=9.75u W=0.72u AS=0.2448p AD=0.2448p PS=2.12u ++ PD=2.12u +M$3 dn2 iout vdd \$8 sg13_lv_pmos L=1.95u W=5.3u AS=1.802p AD=1.802p PS=11.28u ++ PD=11.28u +R$4 \$8 vdd ntap1 A=7.5826p P=48.92u +R$5 \$1 vss ptap1 A=7.0975p P=56.78u +.ENDS input_stage diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/schematic_mod/input_stage.sch b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/schematic_mod/input_stage.sch new file mode 100644 index 00000000..1c60f8af --- /dev/null +++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/schematic_mod/input_stage.sch @@ -0,0 +1,97 @@ +v {xschem version=3.4.5 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +P 4 2 1525 -150 1525 -150 {} +N 655 -315 655 -275 { +lab=dn3} +N 655 -315 765 -315 { +lab=dn3} +N 765 -245 825 -245 { +lab=dn3} +N 765 -315 765 -245 { +lab=dn3} +N 695 -245 765 -245 { +lab=dn3} +N 655 -375 655 -315 { +lab=dn3} +N 595 -530 725 -530 { +lab=iout} +N 765 -500 765 -455 { +lab=dn2} +N 865 -375 865 -275 { +lab=dn4} +N 655 -185 865 -185 { +lab=vss} +N 265 -295 265 -260 { +lab=vss} +N 265 -380 265 -355 { +lab=bulk2} +N 865 -245 955 -245 { +lab=sub!} +N 655 -215 655 -185 { +lab=vss} +N 560 -245 655 -245 { +lab=sub!} +N 865 -215 865 -185 { +lab=vss} +N 385 -290 385 -255 { +lab=vdd} +N 385 -375 385 -350 { +lab=bulk1} +N 765 -580 765 -560 { +lab=vdd} +N 765 -530 845 -530 { +lab=bulk1} +C {sg13g2_pr/sg13_lv_pmos.sym} 745 -530 0 0 {name=M7 +l=1.95u +w=5.3u +ng=1 +m=1 +model=sg13_lv_pmos +spiceprefix=X +} +C {iopin.sym} 765 -185 1 1 {name=p16 lab=vss} +C {iopin.sym} 765 -580 1 1 {name=p19 lab=vdd} +C {lab_pin.sym} 955 -245 0 1 {name=p1 sig_type=std_logic lab=sub!} +C {sg13g2_pr/ptap1.sym} 265 -325 0 0 {name=R2 +model=ptap1 +spiceprefix=X +w=10e-6 +l=1.0e-6 +} +C {lab_pin.sym} 265 -260 0 0 {name=p4 sig_type=std_logic lab=vss} +C {lab_pin.sym} 265 -380 0 1 {name=p9 sig_type=std_logic lab=sub!} +C {iopin.sym} 865 -375 2 1 {name=p2 lab=dn4} +C {iopin.sym} 655 -375 2 1 {name=p5 lab=dn3} +C {iopin.sym} 765 -455 2 1 {name=p6 lab=dn2} +C {iopin.sym} 595 -530 2 0 {name=p7 lab=iout} +C {lab_pin.sym} 385 -255 0 0 {name=p8 sig_type=std_logic lab=vdd} +C {lab_pin.sym} 385 -375 0 1 {name=p10 sig_type=std_logic lab=bulk1} +C {sg13g2_pr/ntap1.sym} 385 -320 0 0 {name=R3 +model=ntap1 +spiceprefix=X +w=0.78e-6 +l=0.78e-6 +} +C {lab_pin.sym} 845 -530 0 1 {name=p11 sig_type=std_logic lab=bulk1} +C {sg13g2_pr/sg13_lv_nmos.sym} 675 -245 2 0 {name=M1 +l=9.75u +w=720n +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_nmos.sym} 845 -245 2 1 {name=M2 +l=9.75u +w=720n +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {lab_pin.sym} 565 -245 0 0 {name=p12 sig_type=std_logic lab=sub!} diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/schematic_mod/simulations/input_stage.cdl b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/schematic_mod/simulations/input_stage.cdl new file mode 100644 index 00000000..b1fc8e54 --- /dev/null +++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/schematic_mod/simulations/input_stage.cdl @@ -0,0 +1,12 @@ +** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_stage/schematic_mod/input_stage.sch +.subckt input_stage vss vdd dn4 dn3 dn2 iout +*.PININFO vss:B vdd:B dn4:B dn3:B dn2:B iout:B +M7 dn2 iout vdd bulk1 sg13_lv_pmos l=1.95u w=5.3u ng=1 m=1 +R2 vss bulk2 ptap1 A = 7.0975e-12 P=56.78e-6 +R3 vdd bulk1 ntap1 A = 7.5826e-12 P = 48.92e-6 +M1 dn3 dn3 vss bulk2 sg13_lv_nmos l=9.75u w=720n ng=1 m=1 +M2 dn4 dn3 vss bulk2 sg13_lv_nmos l=9.75u w=720n ng=1 m=1 +.ends +.end + + diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/output_stage.gds b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/output_stage.gds new file mode 100644 index 00000000..882cb1ad Binary files /dev/null and b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/output_stage.gds differ diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/output_stage_extracted.cir b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/output_stage_extracted.cir new file mode 100644 index 00000000..a576515e --- /dev/null +++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/output_stage_extracted.cir @@ -0,0 +1,13 @@ +* Extracted by KLayout with SG13G2 LVS runset on : 14/01/2025 15:57 + +.SUBCKT output_stage vout dn4 vdd iout vout|vss vout$1 dn4$1 +M$1 vout|vss dn4$1 vout|vss \$1 sg13_lv_nmos L=9.75u W=28.8u AS=6.552p ++ AD=6.552p PS=37.82u PD=37.82u +M$5 vdd iout iout \$4 sg13_lv_pmos L=2.08u W=75u AS=15.65625p AD=15.65625p ++ PS=87.715u PD=87.715u +M$13 vdd iout vout$1 \$4 sg13_lv_pmos L=2.08u W=75u AS=15.65625p AD=15.65625p ++ PS=87.715u PD=87.715u +C$21 dn4 vout cap_cmim w=22.295u l=22.295u A=497.067025p P=89.18u m=1 +R$22 \$4 vdd ntap1 A=95.5222p P=212.92u +R$23 \$1 vout|vss ptap1 A=68.4036p P=242.64u +.ENDS output_stage diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/schematic_mod/output_stage.sch b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/schematic_mod/output_stage.sch new file mode 100644 index 00000000..5e9b94db --- /dev/null +++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/schematic_mod/output_stage.sch @@ -0,0 +1,118 @@ +v {xschem version=3.4.5 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 660 -305 860 -305 { +lab=vss} +N 570 -575 570 -555 { +lab=iout} +N 570 -575 620 -575 { +lab=iout} +N 620 -625 640 -625 { +lab=iout} +N 570 -595 570 -575 { +lab=iout} +N 620 -625 620 -575 { +lab=iout} +N 610 -625 620 -625 { +lab=iout} +N 800 -625 820 -625 { +lab=iout} +N 860 -525 900 -525 { +lab=vout} +N 860 -595 860 -525 { +lab=vout} +N 760 -400 820 -400 { +lab=dn4} +N 760 -460 760 -400 { +lab=dn4} +N 660 -400 760 -400 { +lab=dn4} +N 860 -460 860 -430 { +lab=vout} +N 820 -460 860 -460 { +lab=vout} +N 860 -525 860 -460 { +lab=vout} +N 860 -375 860 -305 { +lab=vss} +N 1265 -385 1265 -355 { +lab=bulk3} +N 1265 -295 1265 -255 { +lab=vss} +N 860 -400 940 -400 { +lab=sub!} +N 860 -675 860 -655 { +lab=vdd} +N 570 -675 570 -655 { +lab=vdd} +N 505 -625 570 -625 { +lab=bulk4} +N 860 -625 930 -625 { +lab=bulk4} +N 1455 -385 1455 -355 { +lab=bulk4} +N 1455 -295 1455 -255 { +lab=vdd} +N 570 -675 860 -675 { +lab=vdd} +C {sg13g2_pr/sg13_lv_pmos.sym} 840 -625 0 0 {name=M7 +l=2.08u +w=75u +ng=8 +m=1 +model=sg13_lv_pmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_nmos.sym} 840 -400 2 1 {name=M6 +l=9.75u +w=28.8u +ng=4 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {iopin.sym} 855 -675 1 1 {name=p1 lab=vdd} +C {iopin.sym} 570 -555 0 1 {name=p3 lab=iout} +C {iopin.sym} 900 -525 0 0 {name=p8 lab=vout} +C {lab_pin.sym} 640 -625 0 1 {name=p7 sig_type=std_logic lab=iout} +C {lab_pin.sym} 800 -625 0 0 {name=p6 sig_type=std_logic lab=iout} +C {sg13g2_pr/sg13_lv_pmos.sym} 590 -625 0 1 {name=M9 +l=2.08u +w=75u +ng=8 +m=1 +model=sg13_lv_pmos +spiceprefix=X +} +C {sg13g2_pr/cap_cmim.sym} 790 -460 3 0 {name=C2 +model=cap_cmim +w=22.295e-6 +l=22.295e-6 +m=1 +spiceprefix=X} +C {lab_pin.sym} 1265 -385 0 0 {name=p23 sig_type=std_logic lab=sub! +} +C {lab_pin.sym} 1265 -255 2 0 {name=p24 sig_type=std_logic lab=vss} +C {lab_pin.sym} 940 -400 0 1 {name=p27 sig_type=std_logic lab=sub!} +C {sg13g2_pr/ptap1.sym} 1265 -325 0 0 {name=R2 +model=ptap1 +spiceprefix=X +R=262.847.0 +Imax=0.3e-6 +} +C {lab_pin.sym} 505 -625 0 0 {name=p36 sig_type=std_logic lab=bulk4} +C {lab_pin.sym} 930 -625 2 0 {name=p37 sig_type=std_logic lab=bulk4} +C {lab_pin.sym} 1455 -385 0 0 {name=p38 sig_type=std_logic lab=bulk4} +C {lab_pin.sym} 1455 -255 0 0 {name=p39 sig_type=std_logic lab=vdd} +C {sg13g2_pr/ntap1.sym} 1455 -325 0 0 {name=R5 +model=ntap1 +spiceprefix=X +R=262.847.0 +Imax=0.3e-6 +} +C {iopin.sym} 660 -305 0 1 {name=p2 lab=vss} +C {iopin.sym} 675 -400 1 1 {name=p4 lab=dn4} diff --git a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/schematic_mod/simulations/output_stage.cdl b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/schematic_mod/simulations/output_stage.cdl new file mode 100644 index 00000000..655573ba --- /dev/null +++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/schematic_mod/simulations/output_stage.cdl @@ -0,0 +1,12 @@ +** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/schematic_mod/output_stage.sch +.subckt output_stage vdd iout vout vss dn4 +*.PININFO vdd:B iout:B vout:B vss:B dn4:B +M7 vout iout vdd bulk3 sg13_lv_pmos l=2.08u w=75u ng=8 m=1 +M6 vout dn4 vss bulk2 sg13_lv_nmos l=9.75u w=28.8u ng=4 m=1 +M9 iout iout vdd bulk3 sg13_lv_pmos l=2.08u w=75u ng=8 m=1 +C2 dn4 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1 +R2 vss bulk2 ptap1 A = 68.4036e-12, P = 0.24264e-3 +R5 vdd bulk3 ntap1 A = 95.5222e-12, P = 0.21292e-3 +.ends +.end + diff --git a/modules/module_1_bandgap_reference/part_3_layout/pycell_macro/generator_modified.py b/modules/module_1_bandgap_reference/part_3_layout/pycell_macro/generator_modified.py new file mode 100644 index 00000000..3eb564c4 --- /dev/null +++ b/modules/module_1_bandgap_reference/part_3_layout/pycell_macro/generator_modified.py @@ -0,0 +1,282 @@ +""" +Module to automatically generate a gallery of devices out of a SPICE netlist by creating a new GDS file. +Can be used in Klayout's batch mode. For example: +klayout -n sg13g2 -zz -r generator.py -rd netlist=netlist.spice -rd output=macros/gallery.gds +""" + +import pathlib +import sys +import re +from typing import List, Dict +import pya +import klayout.db + +LIB = 'SG13_dev' + +def parse_netlist(netlist: str) -> List[Dict[str, str]]: + print("[DEBUG] Starting to parse netlist...") + + # Define regular expression patterns for each component type + patterns = { + 'ipin': re.compile(r"^\*\.ipin\s+(\S+)\s*$", re.MULTILINE), + 'opin': re.compile(r"^\*\.opin\s+(\S+)\s*$", re.MULTILINE), + 'iopin': re.compile(r"^\*\.iopin\s+(\S+)\s*$", re.MULTILINE), + 'bjt': re.compile( + r"^XQ(\S+)\s+\S+\s+\S+\s+\S+\s+\S+\s+(\S+)\s+Nx=([\d\.]+)(?:\s+le=([\d\.e-]+))?\s*$", + re.MULTILINE + ), + 'capacitor': re.compile( + r"^XC(\S+)\s+\S+\s+\S+\s+(\S+)\s+w=([\d\.e-]+)\s+l=([\d\.e-]+)\s+m=([\d\.]+)\s*$", + re.MULTILINE + ), + 'diode': re.compile( + r"^XD(\S+)\s+\S+\s+\S+\s+(\S+)\s+l=([\d\.a-zA-Z]+)\s+w=([\d\.a-zA-Z]+)\s*$", + re.MULTILINE + ), + 'resistor': re.compile( + r"^XR(\S+)\s+\S+\s+\S+\s+(\S+)\s+w=([\d\.e-]+)\s+l=([\d\.e-]+)\s+m=([\d\.]+)\s+b=([\d\.]+)\s*$", + re.MULTILINE + ), + 'mosfet': re.compile( + r"^XM(\S+)\s+\S+\s+\S+\s+\S+\s+\S+\s+(\S+)\s+w=([\d\.u-]+)\s+l=([\d\.u-]+)\s+ng=([\d\.]+)\s+m=([\d\.]+)(?:\s+rfmode=([\d\.]+))?\s*$", + re.MULTILINE + ), + 'tap': re.compile( + r"^XR(\S+)\s+\S+\s+\S+\s+(\S+)\s*$", + re.MULTILINE + ) + } + + components = [] + + # Parse each type of component + for component_type, pattern in patterns.items(): + matches = list(pattern.finditer(netlist)) + print(f"[DEBUG] Found {len(matches)} '{component_type}' components.") + for match in matches: + component = {'type': component_type} + if component_type in ['ipin', 'opin', 'iopin']: + component['name'] = match.group(1) + component['model'] = component_type + elif component_type == 'bjt': + component['name'] = f"XQ{match.group(1)}" + component['model'] = match.group(2) + component['Nx'] = match.group(3) + component['le'] = match.group(4) if match.group(4) else None + elif component_type == 'capacitor': + component['name'] = f"XC{match.group(1)}" + component['model'] = match.group(2) + component['w'] = match.group(3) + component['l'] = match.group(4) + component['m'] = match.group(5) + elif component_type == 'diode': + component['name'] = f"XD{match.group(1)}" + component['model'] = match.group(2) + component['l'] = match.group(3) + component['w'] = match.group(4) + elif component_type == 'resistor': + component['name'] = f"XR{match.group(1)}" + component['model'] = match.group(2) + component['w'] = match.group(3) + component['l'] = match.group(4) + component['m'] = match.group(5) + component['b'] = match.group(6) + elif component_type == 'mosfet': + component['name'] = f"XM{match.group(1)}" + component['model'] = match.group(2) + component['w'] = match.group(3) + component['l'] = match.group(4) + component['ng'] = match.group(5) + component['m'] = match.group(6) + component['rfmode'] = match.group(7) if match.group(7) else None + elif component_type == 'tap': + component['name'] = f"XR{match.group(1)}" + component['model'] = match.group(2) # Assuming group 2 is the model + else: + print(f"[WARNING] Unknown component type: {component_type}") + + components.append(component) + print(f"[DEBUG] Parsed component: {component}") + + print(f"[DEBUG] Total components parsed: {len(components)}") + return components + +def find_instances_by_model(components: List[Dict[str, str]], model_name: str) -> List[Dict[str, str]]: + print(f"[DEBUG] Filtering components for model: '{model_name}'") + filtered = [comp for comp in components if comp.get('model') == model_name] + print(f"[DEBUG] Found {len(filtered)} instances of model: '{model_name}'") + return filtered + +def generate_devices(netlist: str, output: str): + print("[DEBUG] Starting device generation...") + components = parse_netlist(netlist) + print("[DEBUG] Completed netlist parsing.") + + lib = pya.Library.library_by_name(LIB) + if lib is None: + print(f"[ERROR] Library '{LIB}' not found. Please ensure it is loaded in KLayout.") + sys.exit(1) + print(f"[DEBUG] Using library: '{LIB}'") + + layout = klayout.db.Layout(True) + layout.dbu = 0.001 + print(f"[DEBUG] Layout created with dbu={layout.dbu}") + + top_cell = layout.cell(layout.add_cell('gallery')) + print("[DEBUG] Created top-level cell 'gallery'.") + + # Define the order and models to process + models_to_process = [ + 'rppd', 'rhigh', 'rsil', + 'sg13_lv_nmos', 'sg13_hv_nmos', + 'sg13_lv_pmos', 'sg13_hv_pmos', + 'cap_cmim', 'dantenna', 'dpantenna' + ] + + # Initialize positioning variables + xstep = 0 + y_offset = 100 # Starting y offset + hmax = 0 # Maximum height of the current row + + for model_name in models_to_process: + print(f"[DEBUG] Processing model: '{model_name}'") + res = find_instances_by_model(components, model_name) + if not res: + print(f"[DEBUG] No instances found for model: '{model_name}'. Skipping.") + continue + + for item in res: + print(f"[DEBUG] Processing item: {item}") + try: + # Handle different models with varying parameters + if model_name in ['rppd', 'rhigh', 'rsil']: + width = float(item['w']) * 1e6 + length = float(item['l']) * 1e6 + bends = int(item['b']) + m = int(item['m']) + pcell_type = model_name + params = { + 'w': f'{width}u', + 'l': f'{length}u', + 'b': f'{bends}' + } + elif model_name in ['sg13_lv_nmos', 'sg13_hv_nmos', 'sg13_lv_pmos', 'sg13_hv_pmos']: + width = float(item['w'].rstrip('u')) # Remove 'u' if present + length = float(item['l'].rstrip('u')) + ng = int(item['ng']) + m = int(item['m']) + pcell_type = 'nmos' if 'nmos' in model_name else 'pmos' + if 'HV' in model_name: + pcell_type += 'HV' + params = { + 'w': f'{width}u', + 'l': f'{length}u', + 'ng': f'{ng}' + } + elif model_name in ['cap_cmim']: + width = float(item['w']) * 1e6 + length = float(item['l']) * 1e6 + m = int(item['m']) + pcell_type = model_name + params = { + 'w': f'{width}u', + 'l': f'{length}u' + } + elif model_name in ['dantenna', 'dpantenna']: + width = float(item['w'].rstrip('u')) + length = float(item['l'].rstrip('u')) + pcell_type = model_name + params = { + 'w': f'{width}u', + 'l': f'{length}u' + } + else: + print(f"[WARNING] Unhandled model type: '{model_name}'. Skipping.") + continue + + for i in range(1, m + 1): + print(f"[DEBUG] Creating PCell variant for '{pcell_type}' with params: {params}") + try: + pcell_decl = lib.layout().pcell_declaration(pcell_type) + if pcell_decl is None: + print(f"[ERROR] PCell declaration for '{pcell_type}' not found in library '{LIB}'.") + continue + + pcell = layout.add_pcell_variant(lib, pcell_decl.id(), params) + cell = layout.cell(pcell) + bbox = cell.bbox() + print(f"[DEBUG] Bounding box for PCell '{pcell_type}': {bbox}") + + # Positioning logic + xstep += 100 + bbox.width() + print(f"[DEBUG] Updated xstep: {xstep}") + + # Insert the PCell into the top cell + top_cell.insert(klayout.db.CellInstArray( + pcell, + klayout.db.Trans(klayout.db.Point(xstep, y_offset)) + )) + print(f"[DEBUG] Inserted '{pcell_type}' PCell at position ({xstep}, {y_offset})") + + # Update the maximum height for the current row + cell_h = bbox.height() + if cell_h > hmax: + hmax = cell_h + print(f"[DEBUG] Updated hmax: {hmax}") + + except Exception as e: + print(f"[ERROR] Exception while creating PCell for '{pcell_type}': {e}") + + # After processing each model, update y_offset for the next row + y_offset += hmax + hmax = 0 # Reset for the next row + xstep = 0 # Reset xstep for the next row + print(f"[DEBUG] Updated y_offset: {y_offset}") + + # Ensure output directory exists + try: + pathlib.Path(output).parent.mkdir(parents=True, exist_ok=True) + print(f"[DEBUG] Output directory '{pathlib.Path(output).parent}' is ready.") + except Exception as e: + print(f"[ERROR] Failed to create output directory: {e}") + sys.exit(1) + + # Write the layout to the output GDS file + try: + layout.write(output) + print(f"[DEBUG] Layout successfully written to '{output}'.") + except Exception as e: + print(f"[ERROR] Failed to write layout to '{output}': {e}") + sys.exit(1) + +def main(): + # Check for required arguments + try: + netlist + except NameError: + print("Missing netlist argument. Please define '-rd netlist='") + sys.exit(1) + + try: + output + except NameError: + print("Missing output argument. Please define '-rd output='") + sys.exit(1) + + print("[DEBUG] Opening netlist file...") + # Read the netlist content + try: + with open(netlist, 'r') as file: + netlist_content = file.read() + print(f"[DEBUG] Successfully read netlist file: '{netlist}'") + except Exception as e: + print(f"[ERROR] Failed to read netlist file '{netlist}': {e}") + sys.exit(1) + + # Generate devices and create GDS + generate_devices(netlist_content, output) + print(f'[INFO] GDS file created successfully. Open it using: klayout {output}') + +if __name__ == "__main__": + main() + diff --git a/modules/module_1_bandgap_reference/part_3_layout/startup_circuit/schematic_mod/startup_circuit.sch b/modules/module_1_bandgap_reference/part_3_layout/startup_circuit/schematic_mod/startup_circuit.sch new file mode 100644 index 00000000..abc813ed --- /dev/null +++ b/modules/module_1_bandgap_reference/part_3_layout/startup_circuit/schematic_mod/startup_circuit.sch @@ -0,0 +1,142 @@ +v {xschem version=3.4.5 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 485 -725 485 -670 { +lab=#net1} +N 630 -855 720 -855 { +lab=vdd} +N 560 -805 590 -805 { +lab=#net1} +N 485 -725 560 -725 { +lab=#net1} +N 485 -775 485 -725 { +lab=#net1} +N 560 -805 560 -725 { +lab=#net1} +N 525 -805 560 -805 { +lab=#net1} +N 630 -725 630 -670 { +lab=#net2} +N 485 -585 630 -585 { +lab=vss} +N 630 -610 630 -585 { +lab=vss} +N 525 -640 720 -640 { +lab=v-} +N 630 -725 680 -725 { +lab=#net2} +N 630 -775 630 -725 { +lab=#net2} +N 720 -640 720 -525 { +lab=v-} +N 720 -695 720 -640 { +lab=v-} +N 720 -525 795 -525 { +lab=v-} +N 425 -805 485 -805 { +lab=bulk6} +N 630 -805 675 -805 { +lab=bulk6} +N 630 -855 630 -835 { +lab=vdd} +N 485 -855 630 -855 { +lab=vdd} +N 485 -855 485 -835 { +lab=vdd} +N 575 -670 630 -670 { +lab=#net2} +N 575 -610 630 -610 { +lab=vss} +N 485 -610 485 -585 { +lab=vss} +N 420 -640 485 -640 { +lab=sub!} +N 720 -855 720 -755 { +lab=vdd} +N 720 -725 785 -725 { +lab=bulk5} +N 915 -570 915 -535 { +lab=vss} +N 915 -655 915 -630 { +lab=sub!} +N 915 -495 915 -465 { +lab=bulk6} +N 915 -405 915 -365 { +lab=vdd} +N 995 -495 995 -465 { +lab=bulk6} +N 995 -405 995 -365 { +lab=vdd} +C {sg13g2_pr/sg13_lv_nmos.sym} 505 -640 2 0 {name=M8 +l=10u +w=150n +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_pmos.sym} 505 -805 0 1 {name=M6 +l=1u +w=1u +ng=1 +m=1 +model=sg13_lv_pmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_pmos.sym} 610 -805 0 0 {name=M7 +l=1u +w=1u +ng=1 +m=1 +model=sg13_lv_pmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_pmos.sym} 700 -725 0 0 {name=M9 +l=4u +w=200n +ng=1 +m=1 +model=sg13_lv_pmos +spiceprefix=X +} +C {lab_pin.sym} 720 -855 0 1 {name=p5 sig_type=std_logic lab=vdd} +C {lab_pin.sym} 675 -805 0 1 {name=p4 sig_type=std_logic lab=bulk6} +C {lab_pin.sym} 425 -805 0 0 {name=p17 sig_type=std_logic lab=bulk6} +C {sg13g2_pr/cap_cmim.sym} 575 -640 0 0 {name=C1 +model=cap_cmim +w=18.195e-6 +l=18.195e-6 +m=1 +spiceprefix=X} +C {lab_pin.sym} 795 -525 3 0 {name=p1 sig_type=std_logic lab=v-} +C {lab_pin.sym} 505 -585 3 0 {name=p62 sig_type=std_logic lab=vss} +C {lab_pin.sym} 420 -640 0 0 {name=p63 sig_type=std_logic lab=sub!} +C {lab_pin.sym} 785 -725 0 1 {name=p64 sig_type=std_logic lab=bulk5} +C {sg13g2_pr/ptap1.sym} 915 -600 0 0 {name=R5 +model=ptap1 +spiceprefix=X +w=10e-6 +l=1.0e-6 +} +C {lab_pin.sym} 915 -535 0 0 {name=p33 sig_type=std_logic lab=vss} +C {lab_pin.sym} 915 -655 0 1 {name=p34 sig_type=std_logic lab=sub!} +C {lab_pin.sym} 915 -495 0 1 {name=p7 sig_type=std_logic lab=bulk6} +C {lab_pin.sym} 915 -365 0 0 {name=p16 sig_type=std_logic lab=vdd} +C {sg13g2_pr/ntap1.sym} 915 -435 0 0 {name=R9 +model=ntap1 +spiceprefix=X +R=8.463 +Imax=0.3e-6 +} +C {lab_pin.sym} 995 -495 0 1 {name=p2 sig_type=std_logic lab=bulk5} +C {lab_pin.sym} 995 -365 0 0 {name=p3 sig_type=std_logic lab=bulk5} +C {sg13g2_pr/ntap1.sym} 995 -435 0 0 {name=R1 +model=ntap1 +spiceprefix=X +R=8.463 +Imax=0.3e-6 +lab=bulk5} diff --git a/modules/module_1_bandgap_reference/part_3_layout/startup_circuit/start_up_circuit.gds b/modules/module_1_bandgap_reference/part_3_layout/startup_circuit/start_up_circuit.gds new file mode 100644 index 00000000..df3dbf7f Binary files /dev/null and b/modules/module_1_bandgap_reference/part_3_layout/startup_circuit/start_up_circuit.gds differ diff --git a/modules/module_2_50GHz_MPA/introduction.md b/modules/module_2_50GHz_MPA/introduction.md new file mode 100644 index 00000000..e69de29b diff --git a/modules/module_2_50GHz_MPA/part_1_biasing/biasing_of_bjt.md b/modules/module_2_50GHz_MPA/part_1_biasing/biasing_of_bjt.md new file mode 100644 index 00000000..e69de29b diff --git a/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_1_fingers/bias_1_fingers.dpl b/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_1_fingers/bias_1_fingers.dpl new file mode 100644 index 00000000..43c5f96a --- /dev/null +++ b/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_1_fingers/bias_1_fingers.dpl @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + <"ngspice/bias_1_fingers:ac.k" #0000ff 0 3 0 0 0> + + + + <"ngspice/bias_1_fingers:ac.v(s_1_1)" #0000ff 0 3 0 0 0> + + <"ngspice/bias_1_fingers:ac.v(s_2_2)" #ff0000 0 3 0 0 0> + + + + <"ngspice/bias_1_fingers:v(vb)" #0000ff 0 3 0 0 0> + <"ngspice/bias_1_fingers:v(vcc)" #0000ff 0 3 0 0 0> + <"ngspice/bias_1_fingers:i(pr1)" #0000ff 0 3 1 0 0> + + + + diff --git a/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_1_fingers/bias_1_fingers.sch b/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_1_fingers/bias_1_fingers.sch new file mode 100644 index 00000000..6673d66f --- /dev/null +++ b/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_1_fingers/bias_1_fingers.sch @@ -0,0 +1,94 @@ + + + + + + + + + + + + + + + + + + + + <.SP SP1 1 1410 -60 0 61 0 0 "lin" 1 "1 GHz" 1 "200 GHz" 1 "200" 1 "no" 0 "1" 0 "2" 0 "no" 0 "no" 0> + + + + + <.DC DC1 1 1570 -60 0 36 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + + + + + + + + + + + + + + + + + + + + + + + + <1780 320 1780 400 "" 0 0 0 ""> + <1910 -60 1910 -40 "" 0 0 0 ""> + <2030 320 2030 400 "" 0 0 0 ""> + <2240 400 2240 420 "" 0 0 0 ""> + <2240 310 2240 340 "" 0 0 0 ""> + <2060 270 2060 480 "" 0 0 0 ""> + <1360 270 1490 270 "" 0 0 0 ""> + <1360 270 1360 340 "" 0 0 0 ""> + <1550 480 1600 480 "" 0 0 0 ""> + <1600 480 2060 480 "" 0 0 0 ""> + <1600 440 1600 480 "" 0 0 0 ""> + <1790 270 1910 270 "" 0 0 0 ""> + <1910 270 2020 270 "" 0 0 0 ""> + <1910 270 1910 400 "" 0 0 0 ""> + <1910 400 1910 430 "" 0 0 0 ""> + <1780 400 1910 400 "" 0 0 0 ""> + <1910 400 2030 400 "" 0 0 0 ""> + <1550 270 1600 270 "" 0 0 0 ""> + <1600 270 1750 270 "" 0 0 0 ""> + <1600 270 1600 290 "" 0 0 0 ""> + <1600 350 1600 380 "Vb" 1550 340 14 ""> + <1910 -40 2030 -40 "" 0 0 0 ""> + <2030 -40 2030 20 "" 0 0 0 ""> + <1780 -40 1910 -40 "" 0 0 0 ""> + <1780 -40 1780 20 "" 0 0 0 ""> + <2030 80 2030 180 "" 0 0 0 ""> + <2030 180 2030 220 "" 0 0 0 ""> + <2030 180 2210 180 "" 0 0 0 ""> + <2390 100 2390 110 "" 0 0 0 ""> + <2270 100 2390 100 "" 0 0 0 ""> + <1780 80 1780 100 "" 0 0 0 ""> + <1780 100 2210 100 "" 0 0 0 ""> + <2340 400 2340 420 "" 0 0 0 ""> + <2340 310 2340 340 "" 0 0 0 ""> + <1420 480 1490 480 "" 0 0 0 ""> + <2270 180 2310 180 "" 0 0 0 ""> + <1780 100 1780 130 "" 0 0 0 ""> + <1780 190 1780 220 "Collector_voltage" 1810 170 14 ""> + <1910 -60 1910 -60 "Vcc" 1940 -90 0 ""> + <2240 310 2240 310 "Vb" 2270 280 0 ""> + <2340 310 2340 310 "Vcc" 2370 280 0 ""> + + + + + diff --git a/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_2_stability/bias_2_stability.dpl b/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_2_stability/bias_2_stability.dpl new file mode 100644 index 00000000..6bacdbae --- /dev/null +++ b/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_2_stability/bias_2_stability.dpl @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + <"ngspice/ac.k" #0000ff 0 3 0 0 0> + + + + <"ngspice/ac.v(s_1_1)" #0000ff 0 3 0 0 0> + + <"ngspice/ac.v(s_2_2)" #ff0000 0 3 0 0 0> + + + + <"ngspice/v(vcc)" #0000ff 0 3 1 0 0> + <"ngspice/v(vbase)" #0000ff 0 3 1 0 0> + <"ngspice/v(vb)" #0000ff 0 3 1 0 0> + <"ngspice/v(collector_voltage)" #0000ff 0 3 1 0 0> + <"ngspice/i(pr1)" #0000ff 0 3 1 0 0> + + + + diff --git a/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_2_stability/bias_2_stability.sch b/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_2_stability/bias_2_stability.sch new file mode 100644 index 00000000..3579026c --- /dev/null +++ b/modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_2_stability/bias_2_stability.sch @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + + <.SP SP1 1 -260 -60 0 61 0 0 "lin" 1 "1 GHz" 1 "200 GHz" 1 "200" 1 "no" 0 "1" 0 "2" 0 "no" 0 "no" 0> + + + + <.DC DC1 1 -100 -60 0 36 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <110 320 110 400 "" 0 0 0 ""> + <240 -60 240 -40 "" 0 0 0 ""> + <570 400 570 420 "" 0 0 0 ""> + <570 310 570 340 "" 0 0 0 ""> + <390 270 390 480 "" 0 0 0 ""> + <-120 270 -70 270 "" 0 0 0 ""> + <-310 270 -180 270 "" 0 0 0 ""> + <-310 270 -310 340 "" 0 0 0 ""> + <-120 480 -70 480 "" 0 0 0 ""> + <-70 270 80 270 "Vbase" 30 220 111 ""> + <-70 480 390 480 "" 0 0 0 ""> + <-70 440 -70 480 "" 0 0 0 ""> + <110 400 140 400 "" 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