diff --git a/media/Pasted image 20241017155312.png b/media/Pasted image 20241017155312.png new file mode 100644 index 00000000..6a1dd316 Binary files /dev/null and b/media/Pasted image 20241017155312.png differ diff --git a/media/Pasted image 20241017162220.png b/media/Pasted image 20241017162220.png new file mode 100644 index 00000000..c4f2e18b Binary files /dev/null and b/media/Pasted image 20241017162220.png differ diff --git a/media/Screenshot 2024-10-29 093228.png b/media/Screenshot 2024-10-29 093228.png new file mode 100644 index 00000000..69cc1ebc Binary files /dev/null and b/media/Screenshot 2024-10-29 093228.png differ diff --git a/media/Screenshot 2024-10-29 094337.png b/media/Screenshot 2024-10-29 094337.png new file mode 100644 index 00000000..f0cb33b5 Binary files /dev/null and b/media/Screenshot 2024-10-29 094337.png differ diff --git a/media/Screenshot 2024-10-29 095117.png b/media/Screenshot 2024-10-29 095117.png new file mode 100644 index 00000000..e72581e6 Binary files /dev/null and b/media/Screenshot 2024-10-29 095117.png differ diff --git a/modules/module_0_foundations/foundations.md b/modules/module_0_foundations/foundations.md index e69de29b..43e6a107 100644 --- a/modules/module_0_foundations/foundations.md +++ b/modules/module_0_foundations/foundations.md @@ -0,0 +1,183 @@ +# Module 0 - Foundations + +Welcome to the first module in the IHP Open PDK analog design course. +Module Overview + +- Setup and Verification of Tools +- Notes on the Design Flow +- Setting Up gm/Id Methodology (Optional) +- Verifying gm/Id Design in Xschem (Optional) + +## Setup and Verification of Tools + +To install and set up the tools for working with the IHP Open PDK, refer to the installation guides in the ReadTheDocs link below: + ``` + https://ihp-open-pdk-docs.readthedocs.io/en/latest/index.html + ``` +After following the installation steps, you should be able to launch Xschem by entering the following command in your terminal: + + xschem + +Upon launching, the initial Xschem window should appear as follows: +

+ +This view includes test cases within the IHP PDK, demonstrating different types of simulations. Below is an overview of each type: + +- DC Analysis: Evaluates steady-state operation of devices, such as operating points and device characterization. +- Transient Analysis: Assesses time-domain behavior, showing device operation over time and response to input changes. +- AC Analysis: Examines frequency response, including cutoff frequencies and phase shift. +- Monte Carlo Analysis: Provides statistical data on device performance variability due to random influences, such as manufacturing deviations. +- S-Parameter Analysis: Focuses on high-frequency behavior, describing network reflection and transmission, useful in RF design. + +The simulation library allows you to explore different designs and understand the simulation setups, which will be covered in detail throughout the course. To get started, try opening dc_lv_nmos by selecting the instance and pressing e. This will open the schematic view. + +From here, navigate to the "netlist" button in the top-right corner, then press "simulate." Your first schematic simulation in Xschem will now be complete. View the results by left-clicking the green arrow while holding down Ctrl. The output should look like this: +

+ +If the dark mode theme is hard to read, you can toggle it by pressing "Shift + O." +## Notes on the Design Flow + +Analog design requires a solid foundation in analog electronics to ensure high-performance, robust designs. In this course, we will focus on the gm/Id methodology rather than traditional small-signal calculations using square-law models. This method uses model parameters to generate lookup tables, enabling a more data-driven approach to design. If you're interested in understanding the circuit design procedures in greater detail, each module includes Jupyter Notebook scripts as references for more advanced IC design using open-source tools. + +For a deeper dive into the gm/Id methodology, consider watching this video by Mastering Microelectronics: https://www.youtube.com/watch?v=dzz4z3ijVts + +Refer to the next section for instructions on setting up the gm/Id tools using pygmid. +## Setting Up gm/Id Methodology (Optional) + +To set up the gm/Id tools, access the pygmid repository: + +Repository URL: https://github.com/dreoilin/pygmid + +Switch to the "Ngspice" branch and clone the repository to a destination of your choice. Follow the installation instructions in the README. To generate the lookup table, create a configuration file specifying parameters. Below is a sample configuration file to sweep the low-voltage devices, sg13_lv_nmos and sg13_lv_pmos, with relevant parameters: + +``` + +[MODEL] +file = /path/to/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt +info = 130nm CMOS, IHP Open Source PDK, SPICE +corner = NOM +temp = 300 +modeln = sg13_lv_nmos +modelp = sg13_lv_pmos +savefilen = 130n1vrvt +savefilep = 130p1vrvt +paramfile = params.lib + +[SWEEP] +VGS = (0, 20e-3, 1.2) +VDS = (0, 25e-3, 1.2) +VSB = (0, 0.2, 1) +LENGTH = [(0.13, 0.987, 10)] +WIDTH = 1 +NFING = 1 + +[SETTINGS] +RAW_INCLUDE = ['pre_osdi ./psp103_nqs.osdi'] +SIMULATOR = ngspice +``` +To run the sweep, execute the following command: + +``` +python -m pygmid --mode sweep --config +``` + +This command will generate a .pkl file that serves as the lookup table. To test the table, navigate to the scripting folder in this module and open gmid_commonsource.ipynb. + +Note: Ensure the paths to sg13g2_nmos_lv and sg13g2_pmos_lv are correctly referenced in your config file, and modify the LUT path in the script to point to the location of your lookup tables. + +## Verifying gm/Id Design in Xschem (Optional) + +To verify the design created using the lookup tables, start by identifying key parameters to validate, such as DC gain and the first pole. This requires creating a frequency analysis simulation to capture both characteristics. Begin by creating a new schematic in some specified folder: + +``` +touch gmid_test.sch +``` + +From here you launch this schematic by typing + +``` +xschem gmid_test.sch +``` + +the first thing we want to do is the instanciate our mosfets. In this example we make a current mirror for biasing our output transistor to the right operation. Therefore we will need to instanciate two MOSFETS. This is done by navigating to the insert symbol botton, with a nandgate as its icon. Or you can press shift+i. Here you want to click the IHP open pdk path, and click on "sg13g2_pr". Here you should select the "sg13_lv_nmos.sym", and press OK. Now you will place it and duplicate it by pressing it and clicking "c". Now you can press shift+f while toggeling the instance for flipping it and place it in a gate to gate configuration as shown in the image: + + +

+select each instance and press Q to change the widht and the length to the parameters found in the gmid script. + + +Now you should conncect the bulk of the devices to the sources with a wire, by pressing "w" and dragging the wire to its location. After this navigate to the symbol library, again by pressing and instanciate the following items: + +- xschem_library/devices -> search: gnd -> gnd.sym +- xschem_library/devices -> search: res -> res.sym +- xschem_library/devices -> search: cap -> capa-2.sym +- xschem_library/devices -> search: isource -> isource.sym +- xschem_library/devices -> search: vsource -> vsource.sym (duplicate this item) +- xschem_library/devices -> search: lab -> lab_pin.sym (duplicate this item 4 times) +- xschem_library/devices -> search: code -> code_shown.sym (duplicate this item) + +From here you should connect the individual components so you have the same setup as seen in the following image: + +

+ +modify each instance in the same way as the transistors so you also have the same values and labels. NOTE the Vin1 source has the following settings for value "value = AC 1". Next up we want to write the code for our simulation. Chose one of the code_shown blocks and press Q. In here change the name to NGSPICE and set only_toplevel to true. In the value section, insert the following code: + +``` +value = " +.control +op +ac dec 20 1 1e12 +save all +let Av = db(v(vout)) +write output_file.raw +.endc +" +``` +- .control ... .endc: This block defines a sequence of commands to control the simulation. + +- op: Runs a DC operating point analysis, which calculates the steady-state (DC) node voltages and currents based on the current sources, voltage sources, and component values. + +- ac dec 20 1 1e12: Runs an AC analysis with the following parameters: + + - dec: Specifies a logarithmic frequency sweep (in decades). + - 20: Defines the number of points per decade. + - 1 and 1e12: Sets the frequency range from 1 Hz to 1 THz. This analysis evaluates the frequency response of the circuit over this range. + +- save all: Instructs Ngspice to save all node voltages and branch currents during the simulation. This allows for detailed data analysis and access to all circuit variables. + +- let Av = db(v(vout)): Defines a new variable Av to store the voltage gain (in decibels) at the node vout. Here: + + - v(vout) retrieves the voltage at the vout node. + - db(...) converts this voltage to decibels (dB) for gain measurement. + +- write output_file.raw: Saves all the collected data and defined variables (Av and phase) to a file named output_file.raw. This output file can be used for post-simulation analysis or plotting in external tools. + +For the second code block we want to include the model for the transistors, which is done by filling the value parameter with the following: + +``` +name=MODEL only_toplevel=true +format="tcleval( @value )" +value=" +.lib cornerMOSlv.lib mos_tt" +``` + +Here we see that the corner of the models is chosen as typical typical. More about this in the later modules.... + + +As the last step before we can simulate we must set the netlisting to spice netlist. For this navigate to options-> Netlist Format/Symbol mode and choose Spice netlist. Now everything is setup and you can click netlist in the top right corner and afterwards Simulate. When this is done, a window should pop up, with a message: binary raw file "output_file.raw". Now write +``` +show all +``` +in the input to display the DC operating points, and here you can verify that the operating points is set as calculated in the gm/id script. If not you can tweek the current source for instance to get a more accurate ids of your output transistor. In order to see the outputs avaliable for plotting, you can write + +``` +display all +``` +For plotting you can use the following commands + +``` +print Av \\ printing the freq response in decibels +print Vout \\ printing the freq response with linear y axis +``` + +From here you can play around with the different displays avaliable or even plot the output of the raw file in python.