diff --git a/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex.md b/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex.md
index c67dd5b9..1b6649ad 100644
--- a/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex.md
+++ b/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex.md
@@ -1,4 +1,4 @@
-Parasitic Extraction (PEX)
+# Parasitic Extraction (PEX)
 
 Parasitic extraction is an important step in the analog design flow, kind of like EM simulation. After you finish the physical layout, this step analyzes how unintended parasitic resistances and capacitances affect your circuit’s behavior.