From c5593a7dc40611d51f4d63affd634e54fa648924 Mon Sep 17 00:00:00 2001 From: PhillipRambo Date: Fri, 11 Apr 2025 09:05:29 +0200 Subject: [PATCH] push changes --- .../switch_array/switch_array_tb.sch | 130 ---- .../part_4_SAR_ADC/sar_adc_tutorial.sch | 593 ++++++++++++++++++ .../part_4_SAR_ADC/scripting/plot_adc.ipynb | 6 +- 3 files changed, 596 insertions(+), 133 deletions(-) delete mode 100644 modules/module_3_8_bit_SAR_ADC/part_3_array_components/switch_array/switch_array_tb.sch create mode 100644 modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc_tutorial.sch diff --git a/modules/module_3_8_bit_SAR_ADC/part_3_array_components/switch_array/switch_array_tb.sch b/modules/module_3_8_bit_SAR_ADC/part_3_array_components/switch_array/switch_array_tb.sch deleted file mode 100644 index a4089f83..00000000 --- a/modules/module_3_8_bit_SAR_ADC/part_3_array_components/switch_array/switch_array_tb.sch +++ /dev/null @@ -1,130 +0,0 @@ -v {xschem version=3.4.6 file_version=1.2} -G {} -K {} -V {} -S {} -E {} -B 2 1960 -1930 2760 -1530 {flags=graph -y1=-0.0024 -y2=0.61 -ypos1=0 -ypos2=2 -divy=5 -subdivy=1 -unity=1 -x1=0 -x2=1e-07 -divx=5 -subdivx=1 -xlabmag=1.0 -ylabmag=1.0 -node="1 -2 -3 -4 -5 -6 -7 -8" -color="8 4 4 4 4 4 4 4" -dataset=-1 -unitx=1 -logx=0 -logy=0 -} -B 2 1950 -1480 2750 -1080 {flags=graph -y1=0 -y2=1.3 -ypos1=0 -ypos2=2 -divy=5 -subdivy=1 -unity=1 -x1=0 -x2=1e-07 -divx=5 -subdivx=1 -xlabmag=1.0 -ylabmag=1.0 -dataset=-1 -unitx=1 -logx=0 -logy=0 -color=4 -node=clk_comp} -N 1480 -1480 1480 -1420 {lab=vref} -N 1270 -1480 1270 -1420 {lab=1} -N 1300 -1480 1300 -1420 {lab=2} -N 1330 -1480 1330 -1420 {lab=3} -N 1360 -1480 1360 -1420 {lab=4} -N 1390 -1480 1390 -1420 {lab=5} -N 1420 -1480 1420 -1420 {lab=6} -N 1450 -1480 1450 -1420 {lab=7} -N 1510 -1600 1550 -1600 {lab=vdd} -N 1490 -1620 1490 -1600 {lab=GND} -N 1490 -1620 1610 -1620 {lab=GND} -N 980 -1730 980 -1710 {lab=clk_comp} -N 980 -1670 980 -1640 {lab=GND} -N 980 -1600 980 -1580 {lab=vdd} -N 980 -1540 980 -1510 {lab=GND} -N 980 -1460 980 -1440 {lab=vref} -N 980 -1400 980 -1370 {lab=GND} -N 1440 -1730 1470 -1730 {lab=clk_comp} -N 1470 -1730 1470 -1600 {lab=clk_comp} -N 1440 -1730 1440 -1600 {lab=clk_comp} -N 1410 -1730 1440 -1730 {lab=clk_comp} -N 1410 -1730 1410 -1600 {lab=clk_comp} -N 1380 -1730 1410 -1730 {lab=clk_comp} -N 1380 -1730 1380 -1600 {lab=clk_comp} -N 1350 -1730 1380 -1730 {lab=clk_comp} -N 1350 -1730 1350 -1600 {lab=clk_comp} -N 1320 -1730 1350 -1730 {lab=clk_comp} -N 1320 -1730 1320 -1600 {lab=clk_comp} -N 1280 -1730 1280 -1600 {lab=clk_comp} -N 1280 -1730 1320 -1730 {lab=clk_comp} -N 980 -1730 1280 -1730 {lab=clk_comp} -N 1190 -1360 1220 -1360 {lab=vdd} -N 1540 -1360 1590 -1360 {lab=vo} -C {devices/lab_pin.sym} 1550 -1600 2 0 {name=p12 sig_type=std_logic lab=vdd} -C {devices/lab_pin.sym} 1480 -1450 2 0 {name=p8 sig_type=std_logic lab=vref} -C {gnd.sym} 1610 -1620 0 0 {name=l1 lab=GND} -C {devices/lab_pin.sym} 1270 -1440 0 0 {name=p77 sig_type=std_logic lab=1} -C {devices/lab_pin.sym} 1300 -1440 0 0 {name=p78 sig_type=std_logic lab=2} -C {devices/lab_pin.sym} 1330 -1440 0 0 {name=p79 sig_type=std_logic lab=3} -C {devices/lab_pin.sym} 1360 -1440 0 0 {name=p80 sig_type=std_logic lab=4} -C {devices/lab_pin.sym} 1390 -1440 0 0 {name=p81 sig_type=std_logic lab=5} -C {devices/lab_pin.sym} 1420 -1440 0 0 {name=p82 sig_type=std_logic lab=6} -C {devices/lab_pin.sym} 1450 -1440 0 0 {name=p83 sig_type=std_logic lab=7} -C {devices/lab_pin.sym} 980 -1730 2 0 {name=p24 sig_type=std_logic lab=clk_comp} -C {devices/gnd.sym} 980 -1640 0 0 {name=l6 lab=GND} -C {devices/vsource.sym} 980 -1680 0 0 {name=V1 value="dc 0 ac 0 PULSE(0 1.2 0 1n 1n 31.25n 62.5n)"} -C {devices/code_shown.sym} 970 -1310 0 0 {name=NGSPICE only_toplevel=true -value=" -.param temp=27 -.control -tran 1n 100n -save all -write switch_array_tb.raw -.endc -"} -C {devices/lab_pin.sym} 980 -1600 2 0 {name=p1 sig_type=std_logic lab=vdd} -C {devices/gnd.sym} 980 -1510 0 0 {name=l2 lab=GND} -C {devices/lab_pin.sym} 980 -1460 2 0 {name=p2 sig_type=std_logic lab=vref} -C {devices/gnd.sym} 980 -1370 0 0 {name=l3 lab=GND} -C {devices/vsource.sym} 980 -1410 0 0 {name=V3 value=0.6} -C {launcher.sym} 2010 -1510 0 0 {name=h5 -descr="load waves" -tclcommand="xschem raw_read $netlist_dir/switch_array_tb.raw tran" -} -C {devices/lab_pin.sym} 980 -1600 2 0 {name=p3 sig_type=std_logic lab=vdd} -C {devices/gnd.sym} 980 -1510 0 0 {name=l4 lab=GND} -C {devices/vsource.sym} 980 -1550 0 0 {name=V4 value=1.2} -C {devices/lab_pin.sym} 1590 -1360 2 0 {name=p4 sig_type=std_logic lab=vo} -C {devices/code_shown.sym} 940 -1060 0 0 {name=MODEL1 only_toplevel=true -format="tcleval( @value )" -value=".lib cornerMOSlv.lib mos_tt -.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ -"} -C {devices/lab_pin.sym} 1190 -1360 2 1 {name=p5 sig_type=std_logic lab=vdd} -C {switch_array.sym} 1380 -1540 2 1 {name=x1} -C {C-DAC.sym} 1370 -1360 2 1 {name=x2} diff --git a/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc_tutorial.sch b/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc_tutorial.sch new file mode 100644 index 00000000..a3bf1628 --- /dev/null +++ b/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc_tutorial.sch @@ -0,0 +1,593 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +B 2 2395 -980 3195 -580 {flags=graph +y1=1.8372 +y2=3.1802 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=2.3254487e-06 +x2=3.0530249e-06 +divx=5 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 +dataset=-1 +unitx=1 +logx=0 +logy=0 +color="12 7" +node="cdac_v+ +cdac_v-" +hilight_wave=0 +hcursor1_y=1.2502139} +B 2 2395 -1390 3195 -990 {flags=graph +y1=0 +y2=1.3 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=2.3254487e-06 +x2=3.0530249e-06 +divx=5 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 +dataset=-1 +unitx=1 +logx=0 +logy=0 +hcursor1_y=1.0065781 +color=11 +node=dac_clk} +B 2 3325 -1680 4125 -1280 {flags=graph +y1=-0.044 +y2=1.3 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=2.3254487e-06 +x2=3.0530249e-06 +divx=5 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 +dataset=-1 +unitx=1 +logx=0 +logy=0 +color="12 7" +node="cdac_v+ +cdac_v-" +hilight_wave=0 +hcursor1_y=1.2502139} +B 2 3335 -950 4135 -550 {flags=graph +y1=-0.0047 +y2=1.3 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=2.3254487e-06 +x2=3.0530249e-06 +divx=5 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 +dataset=-1 +unitx=1 +logx=0 +logy=0 +color=7 +node=clk_algo +} +B 2 3335 -540 4135 -140 {flags=graph +y1=-0.0047 +y2=1.3 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=2.3254487e-06 +x2=3.0530249e-06 +divx=5 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 +dataset=-1 +unitx=1 +logx=0 +logy=0 +color=11 +node=clk_samp} +B 2 4145 -950 4945 -550 {flags=graph +y1=-0.0047 +y2=1.3 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=2.3254487e-06 +x2=3.0530249e-06 +divx=5 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 +dataset=-1 +unitx=1 +logx=0 +logy=0 +color=10 +node=clk_comp +} +B 2 4145 -540 4945 -140 {flags=graph +y1=0 +y2=1.3 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=2.3254487e-06 +x2=3.0530249e-06 +divx=5 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 +dataset=-1 +unitx=1 +logx=0 +logy=0 +color=11 +node=dac_clk} +N -95 -590 -35 -590 { +lab=#net1} +N -175 -590 -155 -590 {lab=clk_samp} +N -175 -610 -155 -610 {lab=Om} +N -175 -630 -155 -630 {lab=vdd} +N -175 -650 -155 -650 {lab=Op} +N 125 -840 175 -840 {lab=#net2} +N 125 -820 175 -820 {lab=#net3} +N 125 -800 175 -800 {lab=#net4} +N 125 -780 175 -780 {lab=#net5} +N 125 -760 175 -760 {lab=#net6} +N 125 -740 175 -740 {lab=#net7} +N 125 -720 175 -720 {lab=#net8} +N 125 -700 175 -700 {lab=#net9} +N 125 -680 175 -680 {lab=#net10} +N 125 -660 175 -660 {lab=#net11} +N 125 -640 175 -640 {lab=#net12} +N 125 -620 175 -620 {lab=#net13} +N 125 -600 175 -600 {lab=#net14} +N 125 -580 175 -580 {lab=#net15} +N 125 -560 175 -560 {lab=#net16} +N 125 -540 175 -540 {lab=#net17} +N 125 -520 175 -520 {lab=#net18} +N 125 -500 175 -500 {lab=#net19} +N 125 -480 175 -480 {lab=#net20} +N 125 -460 175 -460 {lab=#net21} +N 125 -440 175 -440 {lab=#net22} +N 125 -420 175 -420 {lab=#net23} +N 1740 -1190 1790 -1190 {lab=bias} +N 1870 -1090 1870 -1050 {lab=GND} +N 1500 -1490 1540 -1490 {lab=vdd} +N 1480 -1510 1480 -1490 {lab=GND} +N 1480 -1510 1600 -1510 {lab=GND} +N 1270 -890 1270 -870 {lab=BN_MSB} +N 1310 -890 1310 -870 {lab=BN6} +N 1340 -890 1340 -870 {lab=BN5} +N 1370 -890 1370 -870 {lab=BN4} +N 1400 -890 1400 -870 {lab=BN3} +N 1430 -890 1430 -870 {lab=BN2} +N 1460 -890 1460 -870 {lab=BN1} +N 1500 -890 1540 -890 {lab=vdd} +N 1480 -890 1480 -870 {lab=GND} +N 1480 -870 1600 -870 {lab=GND} +N 1270 -1520 1270 -1490 {lab=B_MSB} +N 1310 -1520 1310 -1490 {lab=B6} +N 1340 -1520 1340 -1490 {lab=B5} +N 1370 -1520 1370 -1490 {lab=B4} +N 1400 -1520 1400 -1490 {lab=B3} +N 1430 -1520 1430 -1490 {lab=B2} +N 1460 -1520 1460 -1490 {lab=B1} +N 1090 -1130 1210 -1130 {lab=#net24} +N 950 -1180 950 -1170 {lab=GND} +N 950 -1060 950 -1050 {lab=GND} +N 1010 -1180 1010 -1160 {lab=vdd} +N 1010 -1060 1010 -1040 {lab=vdd} +N 1070 -1180 1070 -1160 {lab=clk_samp} +N 870 -1250 920 -1250 {lab=vin_pos} +N 870 -1130 920 -1130 {lab=vin_neg} +N 1870 -1330 1870 -1290 {lab=vdd} +N 90 -1270 90 -1250 {lab=clk_comp} +N 90 -1210 90 -1180 {lab=GND} +N 50 -1270 50 -1250 {lab=vdd} +N 50 -1190 50 -1180 {lab=GND} +N 1920 -1110 1920 -1080 {lab=clk_comp} +N 50 -1400 50 -1380 {lab=bias} +N 50 -1320 50 -1310 {lab=GND} +N 1070 -1060 1070 -1040 {lab=clk_samp} +N 2070 -1200 2120 -1200 {lab=Op} +N 2070 -1180 2120 -1180 {lab=Om} +N 1090 -1250 1210 -1250 {lab=#net25} +N 1470 -1350 1470 -1310 {lab=vdd} +N 1470 -1350 1540 -1350 {lab=vdd} +N 1470 -1370 1470 -1350 {lab=vdd} +N 1540 -1490 1540 -1350 {lab=vdd} +N 1440 -1370 1440 -1310 {lab=#net26} +N 1410 -1370 1410 -1310 {lab=#net27} +N 1380 -1370 1380 -1310 {lab=#net28} +N 1350 -1370 1350 -1310 {lab=#net29} +N 1320 -1370 1320 -1310 {lab=#net30} +N 1290 -1370 1290 -1310 {lab=#net31} +N 1260 -1370 1260 -1310 {lab=#net32} +N 1260 -1070 1260 -1010 {lab=#net33} +N 1290 -1070 1290 -1010 {lab=#net34} +N 1320 -1070 1320 -1010 {lab=#net35} +N 1350 -1070 1350 -1010 {lab=#net36} +N 1380 -1070 1380 -1010 {lab=#net37} +N 1410 -1070 1410 -1010 {lab=#net38} +N 1440 -1070 1440 -1010 {lab=#net39} +N 1470 -1040 1470 -1010 {lab=vdd} +N 1470 -1040 1540 -1040 {lab=vdd} +N 1470 -1070 1470 -1040 {lab=vdd} +N 1540 -1040 1540 -890 {lab=vdd} +N 1530 -1250 1790 -1250 {lab=CDAC_v+} +N 1530 -1130 1790 -1130 {lab=CDAC_v-} +N 90 -1400 90 -1380 {lab=clk_samp} +N 90 -1340 90 -1310 {lab=GND} +N 90 -1140 90 -1120 {lab=dac_clk} +N 90 -1080 90 -1050 {lab=GND} +N 50 -1015 50 -985 {lab=vin_pos} +N 50 -925 50 -915 {lab=GND} +N 50 -1060 50 -1050 {lab=GND} +N 50 -1140 50 -1120 {lab=vin_neg} +N -180 -670 -155 -670 {lab=clk_algo} +N -95 -670 -35 -670 {lab=#net40} +N -95 -650 -35 -650 {lab=#net41} +N -95 -630 -35 -630 {lab=#net42} +N -95 -610 -35 -610 { +lab=#net43} +N 235 -840 565 -840 { +lab=B1} +N 235 -820 565 -820 {lab=B2} +N 235 -800 565 -800 {lab=B3} +N 235 -780 565 -780 {lab=B4} +N 235 -760 565 -760 {lab=B5} +N 235 -740 565 -740 {lab=B6} +N 235 -720 565 -720 {lab=B_MSB} +N 235 -700 565 -700 {lab=BN1} +N 235 -680 565 -680 {lab=BN2} +N 235 -660 565 -660 {lab=BN3} +N 235 -640 565 -640 {lab=BN4} +N 235 -620 565 -620 {lab=BN5} +N 235 -600 565 -600 {lab=BN6} +N 235 -580 565 -580 {lab=BN_MSB} +N 235 -560 565 -560 {lab=D7} +N 235 -540 565 -540 {lab=D6} +N 235 -520 565 -520 {lab=D5} +N 235 -500 565 -500 {lab=D4} +N 235 -480 565 -480 {lab=D3} +N 235 -460 565 -460 {lab=D2} +N 235 -440 565 -440 {lab=D1} +N 235 -420 565 -420 {lab=D0} +N 770 -1630 790 -1630 {lab=Op} +N 770 -1570 790 -1570 {lab=Om} +N 880 -1710 880 -1680 {lab=vdd} +N 880 -1520 880 -1500 {lab=GND} +N 1030 -1600 1040 -1600 {lab=clk_algo} +N 1030 -1600 1030 -1580 {lab=clk_algo} +N 1020 -1600 1030 -1600 {lab=clk_algo} +N 1030 -1520 1030 -1500 {lab=GND} +N 880 -1500 1030 -1500 {lab=GND} +C {devices/code_shown.sym} 1705 -820 0 0 {name=NGSPICE only_toplevel=true +value=" +.param temp=27 +.param T = 1u +.param T_half = T/2 +.param T_algo = T/16 +.param T_algo_delay = T/10 +.param T_algo_PW = T/32 +.param DAC_delay = 0.99*T +.param DAC_PW = T/20 +.param comparator_delay = 0.328*T + +.control +tran 1u 8u +let vin_diff = v(Vin_pos) - v(Vin_neg) +let comp_diff = v(op)- v(om) +write sar_adc_test.raw +.endc +"} +C {devices/launcher.sym} 2432.5 -520 0 0 {name=h1 +descr="load waves Ctrl + left click" +tclcommand="xschem raw_read $netlist_dir/sar_adc_test.raw tran" +} +C {devices/lab_pin.sym} 90 -1400 2 0 {name=p10 sig_type=std_logic lab=clk_samp} +C {devices/lab_pin.sym} -175 -590 2 1 {name=p2 sig_type=std_logic lab=clk_samp} +C {devices/lab_pin.sym} 1540 -1490 2 0 {name=p12 sig_type=std_logic lab=vdd} +C {devices/lab_pin.sym} -175 -650 2 1 {name=p3 sig_type=std_logic lab=Op} +C {devices/lab_pin.sym} -175 -630 2 1 {name=p13 sig_type=std_logic lab=vdd} +C {devices/lab_pin.sym} -175 -610 2 1 {name=p14 sig_type=std_logic lab=Om} +C {devices/lab_pin.sym} 2120 -1200 2 0 {name=p36 sig_type=std_logic lab=Op} +C {devices/lab_pin.sym} 2120 -1180 2 0 {name=p37 sig_type=std_logic lab=Om} +C {devices/lab_pin.sym} 1740 -1190 2 1 {name=p5 sig_type=std_logic lab=bias} +C {gnd.sym} 1600 -1510 0 0 {name=l1 lab=GND} +C {devices/lab_pin.sym} 1540 -890 0 1 {name=p38 sig_type=std_logic lab=vdd} +C {gnd.sym} 1600 -870 2 1 {name=l2 lab=GND} +C {devices/lab_pin.sym} 1270 -1520 1 0 {name=p40 sig_type=std_logic lab=B_MSB} +C {devices/lab_pin.sym} 1340 -1520 1 0 {name=p41 sig_type=std_logic lab=B5} +C {devices/lab_pin.sym} 1430 -1520 1 0 {name=p42 sig_type=std_logic lab=B2} +C {devices/lab_pin.sym} 1400 -1520 1 0 {name=p43 sig_type=std_logic lab=B3} +C {devices/lab_pin.sym} 1370 -1520 1 0 {name=p44 sig_type=std_logic lab=B4} +C {devices/lab_pin.sym} 1460 -1520 1 0 {name=p46 sig_type=std_logic lab=B1} +C {devices/lab_pin.sym} 1310 -1520 1 0 {name=p45 sig_type=std_logic lab=B6} +C {devices/lab_pin.sym} 1270 -870 1 1 {name=p48 sig_type=std_logic lab=BN_MSB} +C {devices/lab_pin.sym} 1340 -870 1 1 {name=p49 sig_type=std_logic lab=BN5} +C {devices/lab_pin.sym} 1430 -870 1 1 {name=p50 sig_type=std_logic lab=BN2} +C {devices/lab_pin.sym} 1400 -870 1 1 {name=p51 sig_type=std_logic lab=BN3} +C {devices/lab_pin.sym} 1370 -870 1 1 {name=p52 sig_type=std_logic lab=BN4} +C {devices/lab_pin.sym} 1460 -870 1 1 {name=p53 sig_type=std_logic lab=BN1} +C {devices/lab_pin.sym} 1310 -870 1 1 {name=p54 sig_type=std_logic lab=BN6} +C {devices/lab_pin.sym} 565 -740 0 1 {name=p55 sig_type=std_logic lab=B6} +C {devices/lab_pin.sym} 565 -720 0 1 {name=p56 sig_type=std_logic lab=B_MSB} +C {devices/lab_pin.sym} 565 -780 0 1 {name=p57 sig_type=std_logic lab=B4} +C {devices/lab_pin.sym} 565 -840 0 1 {name=p58 sig_type=std_logic lab=B1} +C {devices/lab_pin.sym} 565 -820 0 1 {name=p59 sig_type=std_logic lab=B2} +C {devices/lab_pin.sym} 565 -800 0 1 {name=p60 sig_type=std_logic lab=B3} +C {devices/lab_pin.sym} 565 -760 0 1 {name=p62 sig_type=std_logic lab=B5} +C {devices/lab_pin.sym} 565 -580 0 1 {name=p1 sig_type=std_logic lab=BN_MSB} +C {devices/lab_pin.sym} 565 -620 0 1 {name=p6 sig_type=std_logic lab=BN5} +C {devices/lab_pin.sym} 565 -680 0 1 {name=p7 sig_type=std_logic lab=BN2} +C {devices/lab_pin.sym} 565 -660 0 1 {name=p15 sig_type=std_logic lab=BN3} +C {devices/lab_pin.sym} 565 -640 0 1 {name=p16 sig_type=std_logic lab=BN4} +C {devices/lab_pin.sym} 565 -700 0 1 {name=p18 sig_type=std_logic lab=BN1} +C {devices/lab_pin.sym} 565 -600 0 1 {name=p19 sig_type=std_logic lab=BN6} +C {gnd.sym} 950 -1170 0 1 {name=l3 lab=GND} +C {gnd.sym} 950 -1050 0 1 {name=l4 lab=GND} +C {devices/lab_pin.sym} 1010 -1160 2 0 {name=p20 sig_type=std_logic lab=vdd} +C {devices/lab_pin.sym} 90 -1270 2 0 {name=p24 sig_type=std_logic lab=clk_comp} +C {devices/gnd.sym} 90 -1180 0 0 {name=l6 lab=GND} +C {devices/vsource.sym} 90 -1220 0 0 {name=V1 value="dc 0 ac 0 PULSE(0 1.2 comparator_delay 10p 10p T_algo_PW T_algo)"} +C {devices/vsource.sym} 50 -1220 0 1 {name=V6 value=1.2} +C {devices/gnd.sym} 50 -1180 0 1 {name=l11 lab=GND +value=1.2} +C {devices/lab_pin.sym} 50 -1270 2 1 {name=p26 sig_type=std_logic lab=vdd} +C {devices/lab_pin.sym} 1870 -1330 2 0 {name=p65 sig_type=std_logic lab=vdd} +C {gnd.sym} 1870 -1050 0 1 {name=l12 lab=GND} +C {devices/lab_pin.sym} 1920 -1080 2 0 {name=p66 sig_type=std_logic lab=clk_comp} +C {iopin.sym} 565 -540 0 0 {name=p67 lab=D6} +C {iopin.sym} 565 -520 0 0 {name=p28 lab=D5} +C {iopin.sym} 565 -500 0 0 {name=p29 lab=D4} +C {iopin.sym} 565 -480 0 0 {name=p30 lab=D3} +C {iopin.sym} 565 -460 0 0 {name=p31 lab=D2} +C {iopin.sym} 565 -440 0 0 {name=p32 lab=D1} +C {iopin.sym} 565 -420 0 0 {name=p33 lab=D0} +C {devices/code_shown.sym} -95 -1525 0 0 {name=MODEL only_toplevel=true +format="tcleval( @value )" +value=".lib cornerMOSlv.lib mos_tt +.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ +"} +C {devices/vsource.sym} 50 -1350 0 1 {name=V7 value=0.6} +C {devices/gnd.sym} 50 -1310 0 1 {name=l13 lab=GND +value=1.2} +C {devices/lab_pin.sym} 50 -1400 2 1 {name=p68 sig_type=std_logic lab=bias} +C {devices/lab_pin.sym} 1070 -1160 2 0 {name=p22 sig_type=std_logic lab=clk_samp} +C {devices/lab_pin.sym} 1010 -1040 2 0 {name=p21 sig_type=std_logic lab=vdd} +C {devices/lab_pin.sym} 1070 -1040 2 0 {name=p23 sig_type=std_logic lab=clk_samp} +C {devices/lab_pin.sym} 1570 -1250 3 1 {name=p74 sig_type=std_logic lab=CDAC_v+} +C {devices/lab_pin.sym} 1570 -1130 1 1 {name=p73 sig_type=std_logic lab=CDAC_v-} +C {devices/lab_pin.sym} 870 -1250 2 1 {name=p25 sig_type=std_logic lab=vin_pos} +C {devices/lab_pin.sym} 870 -1130 2 1 {name=p69 sig_type=std_logic lab=vin_neg} +C {devices/lab_pin.sym} 50 -1015 2 1 {name=p75 sig_type=std_logic lab=vin_pos} +C {iopin.sym} 565 -560 0 0 {name=p4 lab=D7} +C {devices/gnd.sym} 90 -1310 0 0 {name=l9 lab=GND} +C {devices/gnd.sym} 90 -1050 0 0 {name=l18 lab=GND} +C {devices/vsource.sym} 90 -1090 0 0 {name=V12 value="dc 0 ac 0 PULSE(0 1.2 DAC_delay 10p 10p DAC_PW T)"} +C {iopin.sym} 90 -1140 0 0 {name=p17 lab=dac_clk +} +C {devices/gnd.sym} 50 -915 0 1 {name=l19 lab=GND} +C {devices/gnd.sym} 50 -1050 0 1 {name=l20 lab=GND} +C {devices/vsource.sym} 50 -955 0 1 {name=V11 value=0.8} +C {devices/vsource.sym} 50 -1090 0 1 {name=V4 value=0.4} +C {devices/lab_pin.sym} -180 -670 2 1 {name=p27 sig_type=std_logic lab=clk_algo} +C {devices/lab_pin.sym} 50 -1140 2 1 {name=p8 sig_type=std_logic lab=vin_neg} +C {devices/vsource.sym} 90 -1350 0 0 {name=V5 value="dc 0 ac 0 PULSE(0 1.2 0 10p 10p T_half T)"} +C {devices/lab_pin.sym} 770 -1630 2 1 {name=p9 sig_type=std_logic lab=Op} +C {devices/lab_pin.sym} 770 -1570 2 1 {name=p11 sig_type=std_logic lab=Om} +C {devices/lab_pin.sym} 880 -1710 2 1 {name=p34 sig_type=std_logic lab=vdd} +C {devices/gnd.sym} 880 -1500 0 1 {name=l7 lab=GND +value=1.2} +C {capa.sym} 1030 -1550 0 0 {name=C3 +m=1 +value=20f +footprint=1206 +device="ceramic capacitor"} +C {devices/lab_pin.sym} 1040 -1600 2 0 {name=p35 sig_type=std_logic lab=clk_algo} +C {sar_logic.sym} 45 -630 0 0 {name=adut +dut=dut +d_cosim_model= d_cosim +model=./sar_logic.so} +C {adc_bridge1.sym} -125 -670 0 0 {name=A6 +adc=adc1 +adc_bridge_model=adc_bridge +in_low=0.2 +in_high=0.8 +} +C {adc_bridge1.sym} -125 -650 0 0 {name=A1 +adc=adc1 +adc_bridge_model=adc_bridge +in_low=0.2 +in_high=0.8 +} +C {adc_bridge1.sym} -125 -630 0 0 {name=A2 +adc=adc1 +adc_bridge_model=adc_bridge +in_low=0.2 +in_high=0.8 +} +C {adc_bridge1.sym} -125 -610 0 0 {name=A3 +adc=adc1 +adc_bridge_model=adc_bridge +in_low=0.2 +in_high=0.8 +} +C {adc_bridge1.sym} -125 -590 0 0 {name=A4 +adc=adc1 +adc_bridge_model=adc_bridge +in_low=0.2 +in_high=0.8 +} +C {dac_bridge1.sym} 205 -840 0 0 {name=A5 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -820 0 0 {name=A7 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -800 0 0 {name=A8 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -780 0 0 {name=A9 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -760 0 0 {name=A10 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -740 0 0 {name=A11 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -720 0 0 {name=A12 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -700 0 0 {name=A13 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -680 0 0 {name=A14 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -660 0 0 {name=A15 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -640 0 0 {name=A16 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -620 0 0 {name=A17 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -600 0 0 {name=A18 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -580 0 0 {name=A19 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -560 0 0 {name=A20 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -540 0 0 {name=A21 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -520 0 0 {name=A22 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -500 0 0 {name=A23 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -480 0 0 {name=A24 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -460 0 0 {name=A25 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -440 0 0 {name=A26 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {dac_bridge1.sym} 205 -420 0 0 {name=A27 +dac=dac1 +dac_bridge_model=dac_bridge +out_low=0 +out_high=1.2 +} +C {switch_array.sym} 1370 -1430 2 1 {name=x4} +C {C-DAC.sym} 1360 -1130 0 0 {name=x2} +C {C-DAC.sym} 1360 -1250 2 1 {name=x3} +C {switch_array.sym} 1370 -950 0 0 {name=x5} +C {bootstrap_switch.sym} 990 -1250 0 0 {name=x6} +C {bootstrap_switch.sym} 990 -1130 0 0 {name=x7} +C {nand_gate.sym} 940 -1590 0 0 {name=x1} +C {dynamic_comparator.sym} 1940 -1190 0 0 {name=x8} diff --git a/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/scripting/plot_adc.ipynb b/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/scripting/plot_adc.ipynb index fa511417..b3f94a2b 100644 --- a/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/scripting/plot_adc.ipynb +++ b/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/scripting/plot_adc.ipynb @@ -254,8 +254,8 @@ "metadata": {}, "outputs": [], "source": [ - "def verilog_a_dac_from_df(df, vmin=-1.2, vmax=1.2, vdd=1.2, vss=0.0,\n", - " thresh=None, dir=1, td=0, tt=0):\n", + "def virtual_dac(df, vmin=-1.2, vmax=1.2, vdd=1.2, vss=0.0,\n", + " thresh=None, dir=1):\n", " if thresh is None:\n", " thresh = (vdd + vss) / 2.0\n", "\n", @@ -291,7 +291,7 @@ "\n", " return output\n", "\n", - "df['dac_out'] = verilog_a_dac_from_df(df)\n" + "df['dac_out'] = virtual_dac(df)\n" ] }, {