From 785cc597b18e3a590617fd6b62ac410352819d3f Mon Sep 17 00:00:00 2001
From: PhillipRambo <93056982+PhillipRambo@users.noreply.github.com>
Date: Fri, 11 Apr 2025 07:37:21 +0200
Subject: [PATCH] Update sar_adc.md

---
 modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc.md | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc.md b/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc.md
index 05c4c524..984390f2 100644
--- a/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc.md
+++ b/modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/sar_adc.md
@@ -8,10 +8,14 @@ In this section, we’ll dive into creating the final schematic for the SAR ADC.
 Before diving into the full ADC schematic, it's essential to check whether the SAR algorithm can be simulated in the testbench. This can be done by copying the schematic from earlier in the module that uses mixed-signal simulation. You can then use this as the starting point for the rest of the schematic.
 
 > ⚠️ **Note:** Make sure to copy the shared object file (`.so`) and place it relative to the testbench, just like we did before. Create a simulation folder and include it there:
-> 
+
+
 ├── SAR_ADC_tb.sch
+
 ├── simulations
+
 │   └── sar_logic.so
+
 └── xschemrc
 
 In this example, the wiring looks like this: