diff --git a/modules/module_0_foundations/lvs_tester/GDS/drc_run_lvs_tester/gallery_lvs_tester_full.lyrdb b/modules/module_0_foundations/lvs_tester/GDS/drc_run_lvs_tester/gallery_lvs_tester_full.lyrdb new file mode 100644 index 00000000..46e90506 --- /dev/null +++ b/modules/module_0_foundations/lvs_tester/GDS/drc_run_lvs_tester/gallery_lvs_tester_full.lyrdb @@ -0,0 +1,3340 @@ + + + Main DRC Run Report at + + drc: script='/home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/klayout/tech/drc/ihp-sg13g2.drc' + lvs_tester + + + + + NW.b + 5.1.NW.b : Min. NWell space or notch (same net). NWell regions separated by less than this value will be merged. is 0.62 um + + + + + NW.b1 + 5.1.NW.b1 : Min. PWell width between NWell regions (different net) is 1.8 um + + + + + PWB.e + 5.2. PWB.e Min. PWell:block space to (N+Activ not inside ThickGateOx) in PWell is 0.31 um + + + + + PWB.e1 + 5.2. PWB.e1 Min. PWell:block space to (N+Activ inside ThickGateOx) in PWell is 0.62 um + + + + + PWB.f + 5.2. PWB.f Min. PWell:block space to (P+Activ not inside ThickGateOx) in PWell is 0.24 um + + + + + PWB.f1 + 5.2. PWB.f1 Min. PWell:block space to (P+Activ inside ThickGateOx) in PWell 0.62 um + + + + + NBL.b + 5.3.NBL.b : Min. nBuLay space or notch (same net) is 1.5 um + + + + + NBL.c + 5.3.NBL.c : Min. PWell width between nBuLay regions (different net) is 3.2 um + + + + + NBL.d + 5.3.NBL.d : Min. PWell width between nBuLay and NWell (different net) is 2.2 um + + + + + NBL.e + 5.3.NBL.e : Min. nBuLay space to unrelated N+Activ is 1.0 um + + + + + NBL.f + 5.3.NBL.f : Min. nBuLay space to unrelated P+Activ is 0.5 um + + + + + Act.a + 5.5. Act.a : Min. Activ width : 0.15 µm + + + + + Act.b + 5.5. Act.b : Min. Activ space or notch: 0.21 µm. + + + + + AFil.c1 + 5.6. AFil.c1 Min. Activ:filler space to Activ is 0.42 um + + + + + AFil.c + 5.6. AFil.c Min. Activ:filler space to Cont, GatPoly is 1.1 um + + + + + AFil.d + 5.6. AFil.d Min. Activ:filler space to NWell, nBuLay is 1.0 um + + + + + AFil.e + 5.6. AFil.e Min. Activ:filler space to TRANS is 1.0 um + + + + + AFil.j + 5.6. AFil.j Min. nSD:block and SalBlock enclosure of Activ:filler inside PWell:block is 0.25 um + + + + + TGO.f + 5.7. TGO.f : Min. ThickGateOx width: 0.86 µm + + + + + Gat.a + 5.8. Gat.a : Min. GatPoly width: 0.13 µm + + + + + Gat.b + 5.8. Gat.b :Min. GatPoly space or notch: 0.18 µm. + + + + + Gat.d + 5.8. Gat.d :Min. GatPoly space to Activ: 0.07 µm. + + + + + Gat.a1 + 5.8. Gat.a1 Min. GatPoly width for channel length of 1.2V NFET is 0.13 um + + + + + Gat.a2 + 5.8. Gat.a2 Min. GatPoly width for channel length of 1.2V PFET is 0.13 um + + + + + Gat.g + 5.8. Gat.g Min. GatPoly width for 45-degree bent shapes if the bend GatPoly,length is > 0.39 µm is 0.16 um + + + + + GFil.d + 5.9. GFil.d : Min. GatPoly:filler space to Activ, GatPoly, Cont, pSD, nSD:block, SalBlock is 1.1 um + + + + + GFil.e + 5.9. GFil.e Min. GatPoly:filler space to NWell, nBuLay is 1.1 um + + + + + GFil.i + 5.9. GFil.i Max. GatPoly:nofill area (µm²) is 400.0 um x 400.0 um + + + + + pSD.c1 + 5.10. pSD.c1 Min. pSD enclosure of P+Activ in PWell is 0.03 um + + + + + Cnt.a + 5.14. Cnt.a : Min. and max. Cont width: 0.16 µm + + + + + Cnt.b + 5.14. Cnt.b : Min. Cont space: 0.18 µm + + + + + Cnt.c + 5.14. Cnt.c Min. Activ enclosure of Cont is 0.07 um + + + + + Cnt.c.digibnd + 8.1.2. Cnt.c.digibnd Min. Activ enclosure of Cont (Inside DigiBnd) is 0.05 um + + + + + Cnt.d + 5.14. Cnt.d Min. GatPoly enclosure of Cont is 0.07 um + + + + + Cnt.e + 5.14. Cnt.e Min. Cont on GatPoly space to Activ is 0.14 um + + + + + Cnt.g1 + 5.14. Cnt.g1 Min. pSD space to Cont on nSD-Activ is 0.09 um + + + + + Cnt.g2 + 5.14. Cnt.g2 Min. pSD overlap of Cont on pSD-Activ is 0.09 um + + + + + CntB.b1 + 5.15. CntB.b1 Min. ContBar space with common run > 5.0 µm is 0.36 um + + + + + CntB.h1 + 5.15. CntB.h1 Min. Metal1 enclosure of ContBar is 0.05 um + + + + + npn13G2.bR + 6.1.3. npn13G2.bR : Max. recommended total number of npn13G2 emitters per chip is 4000 + + + + + npn13G2L.cR + 6.1.3. npn13G2L.cR : Max. recommended total number of npn13G2L emitters per chip is 800 + + + + + npn13G2V.cR + 6.1.3. npn13G2V.cR : Max. recommended total number of npn13G2V emitters per chip is 800 + + + + + Sdiod.d + 6.7. Sdiod.d : Min. and max. ContBar width inside nBuLay is 0.3 um + + + + + Sdiod.e + 6.7. Sdiod.e : Min. and max. ContBar length inside nBuLay is 1.0 um + + + + + LU.b + 7.2. LU.b : Max. space from any portion of N+Activ inside PWell to an pSD-PWell tie is 20.0 um + + + + + M1.a + 5.16. M1.a: Min. Metal1 width: 0.16 μm. + + + + + M1.b + 5.16. M1.b: Min. Metal1 space or notch: 0.18μm. + + + + + M1.e + 5.16. M1.e Min. space of Metal1 lines if, at least one line is wider than 0.15 µm and the parallel run is more than 1.0 µm is 0.22 um + + + + + M1.f + 5.16. M1.f Min. space of Metal1 lines if, at least one line is wider than 5.0 µm and the parallel run is more than 10.0 µm is 0.6 um + + + + + M1.g + 5.16. M1.g Min. 45-degree bent Metal1 width if the bent metal length is > 0.5 µm is 0.2 um + + + + + M1.i + 5.16. M1.i Min. space of Metal1 lines of which at least one is bent by 45-degree is 0.22 um + + + + + M2.a + 5.17. M2.a: Min. Metal2 width: 0.2 μm. + + + + + M2.b + 5.17. M2.b: Min. Metal2 space or notch: 0.21 μm. + + + + + M2.e + 5.17. M2.e Min. space of Metal2 lines if, at least one line is wider than 0.195 µm and the parallel run is more than 1.0 µm is 0.24 um + + + + + M2.f + 5.17. M2.f Min. space of Metal2 lines if, at least one line is wider than 5.0 µm and the parallel run is more than 10.0 µm is 0.6 um + + + + + M2.g + 5.17. M2.g Min. 45-degree bent Metal2 width if the bent metal length is > 0.5 µm is 0.24 um + + + + + M2.i + 5.17. M2.i Min. space of Metal2 lines of which at least one is bent by 45-degree is 0.24 um + + + + + M3.a + 5.17. M3.a: Min. Metal3 width: 0.2 μm. + + + + + M3.b + 5.17. M3.b: Min. Metal3 space or notch: 0.21 μm. + + + + + M3.e + 5.17. M3.e Min. space of Metal3 lines if, at least one line is wider than 0.195 µm and the parallel run is more than 1.0 µm is 0.24 um + + + + + M3.f + 5.17. M3.f Min. space of Metal3 lines if, at least one line is wider than 5.0 µm and the parallel run is more than 10.0 µm is 0.6 um + + + + + M3.g + 5.17. M3.g Min. 45-degree bent Metal3 width if the bent metal length is > 0.5 µm is 0.24 um + + + + + M3.i + 5.17. M3.i Min. space of Metal3 lines of which at least one is bent by 45-degree is 0.24 um + + + + + M4.a + 5.17. M4.a: Min. Metal4 width: 0.2 μm. + + + + + M4.b + 5.17. M4.b: Min. Metal4 space or notch: 0.21 μm. + + + + + M4.e + 5.17. M4.e Min. space of Metal4 lines if, at least one line is wider than 0.195 µm and the parallel run is more than 1.0 µm is 0.24 um + + + + + M4.f + 5.17. M4.f Min. space of Metal4 lines if, at least one line is wider than 5.0 µm and the parallel run is more than 10.0 µm is 0.6 um + + + + + M4.g + 5.17. M4.g Min. 45-degree bent Metal4 width if the bent metal length is > 0.5 µm is 0.24 um + + + + + M4.i + 5.17. M4.i Min. space of Metal4 lines of which at least one is bent by 45-degree is 0.24 um + + + + + M5.a + 5.17. M5.a: Min. Metal5 width: 0.2 μm. + + + + + M5.b + 5.17. M5.b: Min. Metal5 space or notch: 0.21 μm. + + + + + M5.e + 5.17. M5.e Min. space of Metal5 lines if, at least one line is wider than 0.195 µm and the parallel run is more than 1.0 µm is 0.24 um + + + + + M5.f + 5.17. M5.f Min. space of Metal5 lines if, at least one line is wider than 5.0 µm and the parallel run is more than 10.0 µm is 0.6 um + + + + + M5.g + 5.17. M5.g Min. 45-degree bent Metal5 width if the bent metal length is > 0.5 µm is 0.24 um + + + + + M5.i + 5.17. M5.i Min. space of Metal5 lines of which at least one is bent by 45-degree is 0.24 um + + + + + M1Fil.c + 5.18. M1Fil.c : Min. Metal1:filler space to Metal1 is 0.42 um + + + + + M1Fil.a2 + 5.18. M1Fil.a2 : Max. Metal1:filler width is 5.0 um + + + + + M2Fil.c + 5.18. M2Fil.c : Min. Metal2:filler space to Metal2 is 0.42 um + + + + + M2Fil.a2 + 5.18. M2Fil.a2 : Max. Metal2:filler width is 5.0 um + + + + + M3Fil.c + 5.18. M3Fil.c : Min. Metal3:filler space to Metal3 is 0.42 um + + + + + M3Fil.a2 + 5.18. M3Fil.a2 : Max. Metal3:filler width is 5.0 um + + + + + M4Fil.c + 5.18. M4Fil.c : Min. Metal4:filler space to Metal4 is 0.42 um + + + + + M4Fil.a2 + 5.18. M4Fil.a2 : Max. Metal4:filler width is 5.0 um + + + + + M5Fil.c + 5.18. M5Fil.c : Min. Metal5:filler space to Metal5 is 0.42 um + + + + + M5Fil.a2 + 5.18. M5Fil.a2 : Max. Metal5:filler width is 5.0 um + + + + + V1.a + 5.19. V1.a : Min. and max. Via1 width: 0.19 µm + + + + + V1.b + 5.19. V1.b : Min. Via1 space: 0.22 µm + + + + + V1.c + 5.19. V1.c Min. Metal1 enclosure of Via1 is 0.01 um + + + + + V2.a + 5.20. V2.a : Min. and max. Via2 width: 0.19 µm + + + + + V2.b + 5.20. V2.b : Min. Via2 space: 0.22 µm + + + + + V2.c + 5.20. V2.c : Min. Metal2 enclosure of Via2 is 0.005 µm + + + + + V3.a + 5.20. V3.a : Min. and max. Via3 width: 0.19 µm + + + + + V3.b + 5.20. V3.b : Min. Via3 space: 0.22 µm + + + + + V3.c + 5.20. V3.c : Min. Metal3 enclosure of Via3 is 0.005 µm + + + + + V4.a + 5.20. V4.a : Min. and max. Via4 width: 0.19 µm + + + + + V4.b + 5.20. V4.b : Min. Via4 space: 0.22 µm + + + + + V4.c + 5.20. V4.c : Min. Metal4 enclosure of Via4 is 0.005 µm + + + + + TV1.a + 5.21. TV1.a : Min. and max. TopVia1 width: 0.42 µm + + + + + TV1.b + 5.21. TV1.b : Min. TopVia1 space: 0.42 µm + + + + + TV1.c + 5.21. TV1.c : Min. Metal5 enclosure of TopVia1 is 0.1 um + + + + + TV1.d + 5.21. TV1.d : Min. TopMetal1 enclosure of TopVia1 is 0.42 um + + + + + TM1.a + 5.22. TM1.a: Min. TopMetal1 width: 1.64 μm. + + + + + TM1.b + 5.22. TM1.b: Min. TopMetal1 space or notch: 1.64 μm. + + + + + TM1Fil.c + 5.23. TM1Fil.c : Min. TopMetal1:filler space to TopMetal1 is 3.0 um + + + + + TM1Fil.a1 + 5.23. TM1Fil.a1 : Max. TopMetal1:filler width is 10.0 um + + + + + TV2.a + 5.24. TV2.a : Min. and max. TopVia2 width: 0.9 µm + + + + + TV2.b + 5.24. TV2.b : Min. TopVia2 space: 1.06 µm + + + + + TV2.c + 5.24. TV2.c : Min. TopMetal1 enclosure of TopVia2 is 0.5 um + + + + + TV2.d + 5.24. TV2.d : Min. TopMetal2 enclosure of TopVia2 is 0.5 um + + + + + TM2.a + 5.25. TM2.a: Min. TopMetal2 width: 2.0 μm. + + + + + TM2.b + 5.25. TM2.b: Min. TopMetal2 space or notch: 2.0 μm. + + + + + TM2.bR + 5.25. TM2.bR : Min. space of TopMetal2 lines if, at least one line is wider than 2.5 µm + and the parallel run is more than 50.0 µm is 5.0 um + + + + + TM2Fil.c + 5.26. TM2Fil.c : Min. TopMetal2:filler space to TopMetal2 is 3.0 um + + + + + TM2Fil.a1 + 5.26. TM2Fil.a1 : Max. TopMetal2:filler width is 10.0 um + + + + + Pas.a + 5.27. Pas.a:Min. Passiv width: 2.1 µm + + + + + Pas.b + 5.27. Pas.b: Min. Passiv space or notch: 3.5 µm + + + + + Pas.c + 5.27. Pas.c : Min. TopMetal2 enclosure of Passiv [Not checked outside of sealring (edge-seal-passive)] is 2.1 um + + + + + Padc.a + 6.9. Padc.a : CuPillarPad size is 35.0 um + + + + + Padc.b + 6.9. Padc.b : Min. CuPillarPad space is 40.0 um + + + + + Padc.c + 6.9. Padc.c : Min. TopMetal2 (within dfpad) enclosure of CuPillarPad is 7.5 um + + + + + padc.f + 6.9.2. Padc.f: Allowed passivation opening shape Circle + + + + + Pad.m + 6.9. Pad.m : SBumpPad and CuPillarPad in same layout not allowed + + + + + Pad.fR_M1 + 6.9. Pad.fR_M1 : Min. recommended M1 exit length is 7.0 um + + + + + Pad.fR_M2 + 6.9. Pad.fR_M2 : Min. recommended M2 exit length is 7.0 um + + + + + Pad.fR_M3 + 6.9. Pad.fR_M3 : Min. recommended M3 exit length is 7.0 um + + + + + Pad.fR_M4 + 6.9. Pad.fR_M4 : Min. recommended M4 exit length is 7.0 um + + + + + Pad.fR_M5 + 6.9. Pad.fR_M5 : Min. recommended M5 exit length is 7.0 um + + + + + Pad.fR_TM1 + 6.9. Pad.fR_TM1 : Min. recommended TM1 exit length is 7.0 um + + + + + Pad.fR_TM2 + 6.9. Pad.fR_TM2 : Min. recommended TM2 exit length is 7.0 um + + + + + Pad.i + 6.9. Pad.i : dfpad without TopMetal2 not allowed + + + + + Padb.a + 6.9. Padb.a : SBumpPad size is 60.0 um + + + + + Padb.b + 6.9. Padb.b : Min. SBumpPad space is 70.0 um + + + + + Padb.c + 6.9. Padb.c : Min. TopMetal2 (within dfpad) enclosure of SBumpPad is 10.0 um + + + + + padb.f + 6.9. Padb.f: Allowed passivation opening shape Octagon , Circle + + + + + Padb.d + 6.9. Padb.d : Min. SBumpPad space to EdgeSeal is 50.0 um + + + + + Seal.n + 6.10. seal.n : Sealring must be enclosed by an unbroken Passiv ring + + + + + Seal.b_metal1 + 6.10. Seal.b_metal1 : Min. Activ space to EdgeSeal-metal1 is 4.9 um + + + + + Seal.b_metal2 + 6.10. Seal.b_metal2 : Min. Activ space to EdgeSeal-metal2 is 4.9 um + + + + + Seal.b_metal3 + 6.10. Seal.b_metal3 : Min. Activ space to EdgeSeal-metal3 is 4.9 um + + + + + Seal.b_metal4 + 6.10. Seal.b_metal4 : Min. Activ space to EdgeSeal-metal4 is 4.9 um + + + + + Seal.b_metal5 + 6.10. Seal.b_metal5 : Min. Activ space to EdgeSeal-metal5 is 4.9 um + + + + + Seal.b_topmetal1 + 6.10. Seal.b_topmetal1 : Min. Activ space to EdgeSeal-topmetal1 is 4.9 um + + + + + Seal.b_topmetal2 + 6.10. Seal.b_topmetal2 : Min. Activ space to EdgeSeal-topmetal2 is 4.9 um + + + + + Seal.b_activ + 6.10. Seal.b_activ : Min. Activ space to EdgeSeal-activ is 4.9 um + + + + + Seal.b_psd + 6.10. Seal.b_psd : Min. Activ space to EdgeSeal-psd is 4.9 um + + + + + Seal.k + 6.10. Seal.k : Min. EdgeSeal 45-degree corner length is 21.0 um + + + + + Seal.m + 6.10. Seal.m : Only one sealring per chip allowed + + + + + MIM.c + 6.11. MIM.c : Min. Metal5 enclosure of MIM is 0.6 um + + + + + MIM.d + 6.11. MIM.d : Min. MIM enclosure of TopVia1 is 0.36 um + + + + + Slt.e1_M1 + 7.3. Slt.e1_M1 : No M1:slit required on MIM + + + + + Slt.e1_M2 + 7.3. Slt.e1_M2 : No M2:slit required on MIM + + + + + Slt.e1_M3 + 7.3. Slt.e1_M3 : No M3:slit required on MIM + + + + + Slt.e1_M4 + 7.3. Slt.e1_M4 : No M4:slit required on MIM + + + + + Slt.e1_M5 + 7.3. Slt.e1_M5 : No M5:slit required on MIM + + + + + Slt.e1_TM1 + 7.3. Slt.e1_TM1 : No TM1:slit required on MIM + + + + + Slt.e1_TM2 + 7.3. Slt.e1_TM2 : No TM2:slit required on MIM + + + + + LBE.a + 9.1. LBE.a: Min. LBE width: 100.0 µm + + + + + LBE.b + 9.1. LBE.b: Max. LBE width: 1500.0 µm. + + + + + LBE.b1 + 9.1. LBE.b1: Max. LBE area (µm²): 250000.0 .um + + + + + LBE.c + 9.1. LBE.c: Min. LBE space or notch: 100.0 µm + + + + + LBE.d + 9.1. LBE.d: Min. LBE space to inner edge of EdgeSeal: 150.0 µm + + + + + LBE.h + 9.1. LBE.h: No LBE ring allowed. + + + + + Pin.a + Pin.a : 7.4. Pin.a: Min. activ enclosure of activ:pin = 0um + + + + + Pin.b + Pin.b : 7.4. Pin.b: Min. gatpoly enclosure of gatpoly:pin = 0um + + + + + Pin.e + Pin.e : 7.4. Pin.e: Min. metal1 enclosure of metal1:pin = 0um + + + + + Pin.f_M2 + Pin.f_M2 : 7.4. Pin.f_M2: Min. metal2 enclosure of metal2:pin = 0um + + + + + Pin.f_M3 + Pin.f_M3 : 7.4. Pin.f_M3: Min. metal3 enclosure of metal3:pin = 0um + + + + + Pin.f_M4 + Pin.f_M4 : 7.4. Pin.f_M4: Min. metal4 enclosure of metal4:pin = 0um + + + + + Pin.f_M5 + Pin.f_M5 : 7.4. Pin.f_M5: Min. metal5 enclosure of metal5:pin = 0um + + + + + Pin.g + Pin.g : 7.4. Pin.g: Min. topmetal1 enclosure of topmetal1:pin = 0um + + + + + Pin.h + Pin.h : 7.4. Pin.h: Min. topmetal2 enclosure of topmetal2:pin = 0um + + + + + forbidden.biwind + forbidden.biwind : 3.2. biwind is forbidden in designs submitted for all 0.13 um techs. + + + + + forbidden.pemwind + forbidden.pemwind : 3.2. pemwind is forbidden in designs submitted for all 0.13 um techs. + + + + + forbidden.baspoly + forbidden.baspoly : 3.2. baspoly is forbidden in designs submitted for all 0.13 um techs. + + + + + forbidden.deepco + forbidden.deepco : 3.2. deepco is forbidden in designs submitted for all 0.13 um techs. + + + + + forbidden.pempoly + forbidden.pempoly : 3.2. pempoly is forbidden in designs submitted for all 0.13 um techs. + + + + + forbidden.empoly + forbidden.empoly : 3.2. empoly is forbidden in designs submitted for all 0.13 um techs. + + + + + forbidden.ldmos + forbidden.ldmos : 3.2. ldmos is forbidden in designs submitted for all 0.13 um techs. + + + + + forbidden.pbiwind + forbidden.pbiwind : 3.2. pbiwind is forbidden in designs submitted for all 0.13 um techs. + + + + + forbidden.nodrc + forbidden.nodrc : 3.2. nodrc is forbidden in designs submitted for all 0.13 um techs. + + + + + forbidden.flash + forbidden.flash : 3.2. flash is forbidden in designs submitted for all 0.13 um techs. + + + + + forbidden.colwind + forbidden.colwind : 3.2. colwind is forbidden in designs submitted for all 0.13 um techs. + + + + + NW.a + Min. NWell width = 0.62 + + + + + NW.c + Min. NWell enclosure of P+Activ not inside ThickGateOx = 0.31 + + + + + NW.c1 + Min. NWell enclosure of P+Activ inside ThickGateOx = 0.62 + + + + + NW.d + Min. NWell space to external N+Activ not inside ThickGateOx = 0.31 + + + + + NW.d1 + Min. NWell space to external N+Activ inside ThickGateOx = 0.62 + + + + + NW.e + Min. NWell enclosure of NWell tie surrounded entirely by NWell in N+Activ not inside ThickGateOx = 0.24 + + + + + NW.e1 + Min. NWell enclosure of NWell tie surrounded entirely by NWell in N+Activ inside ThickGateOx = 0.62 + + + + + NW.f + Min. NWell space to substrate tie in P+Activ not inside ThickGateOx = 0.24 + + + + + NW.f1 + Min. NWell space to substrate tie in P+Activ inside ThickGateOx = 0.62 + + + + + PWB.a + Min. PWell:block width = 0.62 + + + + + PWB.b + Min. PWell:block space or notch = 0.62 + + + + + PWB.c + Min. PWell:block space to NWell = 0.62 + + + + + NBL.a + Min. nBuLay width = 1.00 + + + + + NBLB.a + Min. nBuLay:block width = 1.50 + + + + + NBLB.b + Min. nBuLay:block space or notch = 1.00 + + + + + NBLB.c + Min. nBuLay enclosure of nBuLay:block = 1.00 + + + + + NBLB.d + Min. nBuLay:block space to unrelated nBuLay = 1.50 + + + + + Act.c + Min. Activ drain/source extension = 0.23 + + + + + Act.d + Min. Activ area (µm²) = 0.122 + + + + + Act.e + Min. Activ enclosed area (µm²) = 0.15 + + + + + AFil.a + Max. Activ:filler width = 5.00 + + + + + AFil.a1 + Min. Activ:filler width = 1.00 + + + + + AFil.b + Min. Activ:filler space = 0.42 + + + + + AFil.i + Min. Activ:filler space to edges of PWell:block = 1.50 + + + + + TGO.a + Min. ThickGateOx extension over Activ = 0.27 + + + + + TGO.b + Min. space between ThickGateOx and Activ outside thick gate oxide region = 0.27 + + + + + TGO.c + Min. ThickGateOx extension over GatPoly over Activ = 0.34 + + + + + TGO.d + Min. space between ThickGateOx and GatPoly over Activ outside thick gate oxide region = 0.34 + + + + + TGO.e + Min. ThickGateOx space (merge if less than this value) = 0.86 + + + + + Gat.a3 + Min. GatPoly width for channel length of 3.3 V NFET = 0.45 + + + + + Gat.a4 + Min. GatPoly width for channel length of 3.3 V PFET = 0.4 + + + + + Gat.b1 + Min. space between unrelated 3.3 V GatPoly over Activ regions = 0.25 + + + + + Gat.c + Min. GatPoly extension over Activ (end cap) = 0.18 + + + + + Gat.e + Min. GatPoly area (µm²) = 0.09 + + + + + Gat.f + 45-degree and 90-degree angles for GatPoly on Activ area are not allowed + + + + + GFil.a + Max. GatPoly:filler width = 5.00 + + + + + GFil.b + Min. GatPoly:filler width = 0.70 + + + + + GFil.c + Min. GatPoly:filler space = 0.80 + + + + + GFil.f + Min. GatPoly:filler space to TRANS = 1.10 + + + + + GFil.j + Min. GatPoly:filler extension over Activ:filler (end cap) = 0.18 + + + + + pSD.a + Min. pSD width = 0.31 + + + + + pSD.b + Min. pSD space or notch (pSD regions separated by less than this value will be merged.) = 0.31 + + + + + pSD.c + Min. pSD enclosure of P+Activ in NWell = 0.18 + + + + + pSD.d + Min. pSD space to unrelated N+Activ in PWell = 0.18 + + + + + pSD.d1 + Min. pSD space to N+Activ in NWell = 0.03 + + + + + pSD.e + Min. pSD overlap of Activ at one position when forming abutted substrate tie (These rules are for abutted ties: An electrical connection from P+Activ to NWell tie (or N+ Activ to P-sub tie) is made through the source/drain silicide. For a good electrical connection rule pSD.g is important together with rule pSD.e or pSD.f (see Fig. 5.10).) = 0.30 + + + + + pSD.f + Min. Activ extension over pSD at one position when forming abutted NWell tie (These rules are for abutted ties: An electrical connection from P+Activ to NWell tie (or N+ Activ to P-sub tie) is made through the source/drain silicide. For a good electrical connection rule pSD.g is important together with rule pSD.e or pSD.f (see Fig. 5.10).) = 0.30 + + + + + pSD.g + Min. N+Activ or P+Activ area (µm²) when forming abutted tie (These rules are for abutted ties: An electrical connection from P+Activ to NWell tie (or N+ Activ to P-sub tie) is made through the source/drain silicide. For a good electrical connection rule pSD.g is important together with rule pSD.e or pSD.f (see Fig. 5.10).) = 0.09 + + + + + pSD.i + Min. pSD enclosure of PFET gate not inside ThickGateOx = 0.30 + + + + + pSD.i1 + Min. pSD enclosure of PFET gate inside ThickGateOx = 0.40 + + + + + pSD.j + Min. pSD space to NFET gate not inside ThickGateOx = 0.30 + + + + + pSD.j1 + Min. pSD space to NFET gate inside ThickGateOx = 0.40 + + + + + pSD.k + Min. pSD area (µm²) = 0.25 + + + + + pSD.l + Min. pSD enclosed area (µm²) = 0.25 + + + + + pSD.m + Min. pSD space to n-type poly resistors = 0.18 + + + + + pSD.n + Min. pSD enclosure of p-type poly resistors = 0.18 + + + + + nSDB.a + Min. nSD:block width = 0.31 + + + + + nSDB.b + Min. nSD:block space or notch = 0.31 + + + + + nSDB.c + Min. nSD:block space to pSD = 0.31 + + + + + nSDB.e + Min. nSD:block space to Cont (nSD:block and Cont do not overlap.) = 0.00 + + + + + EXTB.a + Min. EXTBlock width = 0.31 + + + + + EXTB.b + Min. EXTBlock space or notch = 0.31 + + + + + EXTB.c + Min. EXTBlock space to pSD = 0.31 + + + + + Sal.a + Min. SalBlock width = 0.42 + + + + + Sal.b + Min. SalBlock space or notch = 0.42 + + + + + Sal.c + Min. SalBlock extension over Activ or GatPoly = 0.20 + + + + + Sal.d + Min. SalBlock space to unrelated Activ or GatPoly = 0.20 + + + + + Sal.e + Min. SalBlock space to Cont = 0.20 + + + + + Cnt.b1 + Min. Cont space in a contact array of more than 4 rows and more then 4 columns (Cnt.b1 is only required in one direction. The distance of the other direction must be at least Cnt.b.) = 0.20 + + + + + Cnt.f + Min. Cont on Activ space to GatPoly = 0.11 + + + + + Cnt.g + Cont must be within Activ or GatPoly + + + + + Cnt.h + Cont must be covered with Metal1 + + + + + Cnt.j + Cont on GatPoly over Activ is not allowed + + + + + CntB.a + Min. and max. ContBar width = 0.16 + + + + + CntB.a1 + Min. ContBar length = 0.34 + + + + + CntB.b + Min. ContBar space = 0.28 + + + + + CntB.b2 + Min. ContBar space to Cont = 0.22 + + + + + CntB.c + Min. Activ enclosure of ContBar = 0.07 + + + + + CntB.d + Min. GatPoly enclosure of ContBar = 0.07 + + + + + CntB.e + Min. ContBar on GatPoly space to Activ = 0.14 + + + + + CntB.f + Min. ContBar on Activ space to GatPoly = 0.11 + + + + + CntB.g + ContBar must be within Activ or GatPoly + + + + + CntB.g1 + Min. pSD space to ContBar on nSD-Activ = 0.09 + + + + + CntB.g2 + Min. pSD overlap of ContBar on pSD-Activ = 0.09 + + + + + CntB.h + ContBar must be covered with Metal1 + + + + + CntB.j + ContBar on GatPoly over Activ is not allowed + + + + + M1.c + Min. Metal1 enclosure of Cont = 0.00 + + + + + M1.c1 + Min. Metal1 endcap enclosure of Cont (For contacts at Metal1 corners at least one side must be treated as an endcap and for the other sides rule M1.c can be applied.) = 0.05 + + + + + M1.d + Min. Metal1 area (µm²) = 0.09 + + + + + M2.c + Min. Metal2 enclosure of Via1 = 0.005 + + + + + M2.c1 + Min. Metal2 endcap enclosure of Via1 (For vias at Metal2 corners at least one side must be treated as an endcap and for the other sides rule M2.c can be applied.) = 0.05 + + + + + M2.d + Min. Metal2 area (µm²) = 0.144 + + + + + M3.c + Min. Metal3 enclosure of Via2 = 0.005 + + + + + M3.c1 + Min. Metal3 endcap enclosure of Via2 (For vias at Metal3 corners at least one side must be treated as an endcap and for the other sides rule M3.c can be applied.) = 0.05 + + + + + M3.d + Min. Metal3 area (µm²) = 0.144 + + + + + M4.c + Min. Metal4 enclosure of Via3 = 0.005 + + + + + M4.c1 + Min. Metal4 endcap enclosure of Via3 (For vias at Metal4 corners at least one side must be treated as an endcap and for the other sides rule M4.c can be applied.) = 0.05 + + + + + M4.d + Min. Metal4 area (µm²) = 0.144 + + + + + M5.c + Min. Metal5 enclosure of Via4 = 0.005 + + + + + M5.c1 + Min. Metal5 endcap enclosure of Via4 (For vias at Metal5 corners at least one side must be treated as an endcap and for the other sides rule M5.c can be applied.) = 0.05 + + + + + M5.d + Min. Metal5 area (µm²) = 0.144 + + + + + M1Fil.a1 + Min. Metal1:filler width = 1.00 + + + + + M1Fil.b + Min. Metal1:filler space = 0.42 + + + + + M1Fil.d + Min. Metal1:filler space to TRANS = 1.00 + + + + + M2Fil.a1 + Min. Metal2:filler width = 1.00 + + + + + M2Fil.b + Min. Metal2:filler space = 0.42 + + + + + M2Fil.d + Min. Metal2:filler space to TRANS = 1.00 + + + + + M3Fil.a1 + Min. Metal3:filler width = 1.00 + + + + + M3Fil.b + Min. Metal3:filler space = 0.42 + + + + + M3Fil.d + Min. Metal3:filler space to TRANS = 1.00 + + + + + M4Fil.a1 + Min. Metal4:filler width = 1.00 + + + + + M4Fil.b + Min. Metal4:filler space = 0.42 + + + + + M4Fil.d + Min. Metal4:filler space to TRANS = 1.00 + + + + + M5Fil.a1 + Min. Metal5:filler width = 1.00 + + + + + M5Fil.b + Min. Metal5:filler space = 0.42 + + + + + M5Fil.d + Min. Metal5:filler space to TRANS = 1.00 + + + + + V1.b1 + Min. Via1 space in an array of more than 3 rows and more then 3 columns (V1.b1 is only required in one direction. The distance of the other direction must be at least V1.b.) = 0.29 + + + + + V1.c1 + Min. Metal1 endcap enclosure of Via1 (For Via1 at Metal1 corners at least one side must be treated as an endcap and for the other sides rule V1.c can be applied.) = 0.05 + + + + + V2.b1 + Min. Via2 space in an array of more than 3 rows and more then 3 columns (V2.b1 is only required in one direction. The distance of the other direction must be at least V2.b.) = 0.29 + + + + + V2.c1 + Min. Metal2 endcap enclosure of Via2 (For Via2 at Metal2 corners at least one side must be treated as an endcap and for the other sides rule V2.c can be applied.) = 0.05 + + + + + V3.b1 + Min. Via3 space in an array of more than 3 rows and more then 3 columns (V3.b1 is only required in one direction. The distance of the other direction must be at least V3.b.) = 0.29 + + + + + V3.c1 + Min. Metal3 endcap enclosure of Via3 (For Via3 at Metal3 corners at least one side must be treated as an endcap and for the other sides rule V3.c can be applied.) = 0.05 + + + + + V4.b1 + Min. Via4 space in an array of more than 3 rows and more then 3 columns (V4.b1 is only required in one direction. The distance of the other direction must be at least V4.b.) = 0.29 + + + + + V4.c1 + Min. Metal4 endcap enclosure of Via4 (For Via4 at Metal4 corners at least one side must be treated as an endcap and for the other sides rule V4.c can be applied.) = 0.05 + + + + + TM1Fil.a + Min. TopMetal1:filler width = 5.00 + + + + + TM1Fil.b + Min. TopMetal1:filler space = 3.00 + + + + + TM1Fil.d + Min. TopMetal1:filler space to TRANS = 4.90 + + + + + TM2Fil.a + Min. TopMetal2:filler width = 5.00 + + + + + TM2Fil.b + Min. TopMetal2:filler space = 3.00 + + + + + TM2Fil.d + Min. TopMetal2:filler space to TRANS = 4.90 + + + + + npnG2.b + NPN Substrate-Tie must enclose TRANS + + + + + npnG2.c + pSD enclosure of Activ inside NPN Substrate-Tie = 0.20 + + + + + npnG2.d.N_Activ + Min. unrelated N+Activ space to TRANS = 1.21 + + + + + npnG2.d.NWell + Min. unrelated NWell space to TRANS = 1.21 + + + + + npnG2.d.PWell_block + Min. unrelated PWell:block space to TRANS = 1.21 + + + + + npnG2.d.nBuLay + Min. unrelated nBuLay space to TRANS = 1.21 + + + + + npnG2.d.nSD_block + Min. unrelated nSD:block space to TRANS = 1.21 + + + + + npnG2.d1 + Min. unrelated GatPoly space to TRANS = 0.90 + + + + + npnG2.d2 + Min. unrelated SalBlock space to TRANS = 0.90 + + + + + npnG2.e + Min. unrelated Cont space to TRANS = 0.27 + + + + + npn13G2.a + Min. and max. npn13G2 emitter length = 0.90 + + + + + npn13G2L.a + Min. npn13G2L emitter length = 1.00 + + + + + npn13G2L.b + Max. npn13G2L emitter length = 2.50 + + + + + npn13G2V.a + Min. npn13G2V emitter length = 1.00 + + + + + npn13G2V.b + Max. npn13G2V emitter length = 5.00 + + + + + Rsil.a + Min. GatPoly width = 0.50 + + + + + Rsil.b + Min. RES space to Cont = 0.12 + + + + + Rsil.c + Min. RES extension over GatPoly = 0.00 + + + + + Rsil.d + Min. pSD space to GatPoly = 0.18 + + + + + Rsil.e + Min. EXTBlock enclosure of GatPoly = 0.18 + + + + + Rsil.f + Min. RES length = 0.50 + + + + + Rppd.a + Min. GatPoly width = 0.50 + + + + + Rppd.b + Min. pSD enclosure of GatPoly = 0.18 + + + + + Rppd.c + Min. and max. SalBlock space to Cont = 0.20 + + + + + Rppd.d + Min. EXTBlock enclosure of GatPoly = 0.18 + + + + + Rppd.e + Min. SalBlock length = 0.50 + + + + + Rhi.a + Min. GatPoly width = 0.50 + + + + + Rhi.b + pSD and nSD are identical (nSD:drawing is only permitted within Rhigh resistors. Apart from that, nSD is generated automatically (see section 4.2).) + + + + + Rhi.c + Min. pSD and nSD enclosure of GatPoly = 0.18 + + + + + Rhi.d + Min. and max. SalBlock space to Cont = 0.20 + + + + + Rhi.e + Min. EXTBlock enclosure of GatPoly = 0.18 + + + + + Rhi.f + Min. SalBlock length = 0.50 + + + + + nmosi.b + Min. nBuLay enclosure of Iso-PWell-Activ (Iso-PWell-Activ = Activ AND nBuLay AND PWell) = 1.24 + + + + + nmosi.c + Min. NWell space to Iso-PWell-Activ = 0.39 + + + + + nmosi.d + Min. NWell-nBuLay width forming an unbroken ring around any Iso-PWell-Activ (NWell-nBuLay = NWell AND nBuLay) = 0.62 + + + + + nmosi.f + Min. nSD:block width to separate ptap in nmosi = 0.62 + + + + + nmosi.g + Min. SalBlock overlap of nSD:block over Activ = 0.15 + + + + + Sdiod.a + Min. and max. PWell:block enclosure of ContBar = 0.25 + + + + + Sdiod.b + Min. and max. nSD:block enclosure of ContBar = 0.40 + + + + + Sdiod.c + Min. and max. SalBlock enclosure of ContBar = 0.45 + + + + + Pad.aR + Min. recommended Pad width = 30.00 + + + + + Pad.a1 + Max. Pad width = 150.00 + + + + + Pad.bR + Min. recommended Pad space = 8.40 + + + + + Pad.d + Min. Pad space to EdgeSeal = 7.50 + + + + + Pad.dR + Min. recommended Pad to EdgeSeal space (Distance of Pad opening to EdgeSeal strongly depends on bonding procedure. For flip chip bonding via solder bumps (see section 6.9.1) or copper pillars (see section 6.9.2) or manual bonding a bigger distance may be required. We strongly recommend 25 µm distance for wedge-wedge wire bonding.) = 25.00 + + + + + Pad.d1R + Min. recommended Pad to Activ (inside chip area) space = 11.20 + + + + + Pad.gR + Min. recommended TopMetal1 (within dfpad) enclosure of TopVia2 = 1.40 + + + + + Pad.jR + No devices under Pad allowed (Components under pads can be damaged by mechanical stress.) + + + + + Pad.kR + TopVia2 under Pad not allowed (TopVia2 may be damaged during packaging process, we recommend not to use them below Passiv.) + + + + + Padc.d + Min. CuPillarPad space to EdgeSeal = 30.00 + + + + + Seal.a_Activ + Min. EdgeSeal-Activ width = 3.50 + + + + + Seal.a_pSD + Min. EdgeSeal-pSD width = 3.50 + + + + + Seal.a_Metal1 + Min. EdgeSeal-Metal1 width = 3.50 + + + + + Seal.a_Metal2 + Min. EdgeSeal-Metal2 width = 3.50 + + + + + Seal.a_Metal3 + Min. EdgeSeal-Metal3 width = 3.50 + + + + + Seal.a_Metal4 + Min. EdgeSeal-Metal4 width = 3.50 + + + + + Seal.a_Metal5 + Min. EdgeSeal-Metal5 width = 3.50 + + + + + Seal.a_TopMetal1 + Min. EdgeSeal-TopMetal1 width = 3.50 + + + + + Seal.a_TopMetal2 + Min. EdgeSeal-TopMetal2 width = 3.50 + + + + + Seal.c + EdgeSeal-Cont ring width = 0.16 + + + + + Seal.c1.Via1 + EdgeSeal-Via1 ring width = 0.19 + + + + + Seal.c1.Via2 + EdgeSeal-Via2 ring width = 0.19 + + + + + Seal.c1.Via3 + EdgeSeal-Via3 ring width = 0.19 + + + + + Seal.c1.Via4 + EdgeSeal-Via4 ring width = 0.19 + + + + + Seal.c2 + EdgeSeal-TopVia1 ring width = 0.42 + + + + + Seal.c3 + EdgeSeal-TopVia2 ring width = 0.90 + + + + + Seal.d.Cont + Min. EdgeSeal-Activ enclosure of EdgeSeal-Cont ring = 1.30 + + + + + Seal.d.Via1 + Min. EdgeSeal-Activ enclosure of EdgeSeal-Via1 ring = 1.30 + + + + + Seal.d.Via2 + Min. EdgeSeal-Activ enclosure of EdgeSeal-Via2 ring = 1.30 + + + + + Seal.d.Via3 + Min. EdgeSeal-Activ enclosure of EdgeSeal-Via3 ring = 1.30 + + + + + Seal.d.Via4 + Min. EdgeSeal-Activ enclosure of EdgeSeal-Via4 ring = 1.30 + + + + + Seal.d.TopVia1 + Min. EdgeSeal-Activ enclosure of EdgeSeal-TopVia1 ring = 1.30 + + + + + Seal.d.TopVia2 + Min. EdgeSeal-Activ enclosure of EdgeSeal-TopVia2 ring = 1.30 + + + + + Seal.e + Min. Passiv ring width outside of sealring = 4.20 + + + + + Seal.f.Activ + Min. Passiv ring outside of sealring space to EdgeSeal-Activ = 1.00 + + + + + Seal.f.pSD + Min. Passiv ring outside of sealring space to EdgeSeal-pSD = 1.00 + + + + + Seal.f.Metal1 + Min. Passiv ring outside of sealring space to EdgeSeal-Metal1 = 1.00 + + + + + Seal.f.Metal2 + Min. Passiv ring outside of sealring space to EdgeSeal-Metal2 = 1.00 + + + + + Seal.f.Metal3 + Min. Passiv ring outside of sealring space to EdgeSeal-Metal3 = 1.00 + + + + + Seal.f.Metal4 + Min. Passiv ring outside of sealring space to EdgeSeal-Metal4 = 1.00 + + + + + Seal.f.Metal5 + Min. Passiv ring outside of sealring space to EdgeSeal-Metal5 = 1.00 + + + + + Seal.f.TopMetal1 + Min. Passiv ring outside of sealring space to EdgeSeal-TopMetal1 = 1.00 + + + + + Seal.f.TopMetal2 + Min. Passiv ring outside of sealring space to EdgeSeal-TopMetal2 = 1.00 + + + + + MIM.a + Min. MIM width = 1.14 + + + + + MIM.b + Min. MIM space = 0.60 + + + + + MIM.e + Min. TopMetal1 space to MIM = 0.60 + + + + + MIM.f + Min. MIM area per MIM device (µm²) = 1.30 + + + + + MIM.g + Max. MIM area per MIM device (µm²) = 5625.00 + + + + + MIM.h + TopVia1 must be over MIM + + + + + LU.a + Max. space from any portion of P+Activ inside NWell to an nSD-NWell tie = 20.00 + + + + + LU.c + Max. extension of an abutted NWell tie beyond Cont = 6.00 + + + + + LU.c1 + Max. extension of an abutted substrate tie beyond Cont = 6.00 + + + + + LU.d + Max. extension of NWell tie Activ tie beyond Cont = 6.00 + + + + + LU.d1 + Max. extension of an substrate tie Activ beyond Cont = 6.00 + + + + + Slt.a.M1 + Min. Metal1:slit width = 2.80 + + + + + Slt.b.M1 + Max. Metal1:slit width = 20.00 + + + + + Slt.c.M1 + Max. Metal1 width without requiring a slit = 30.00 + + + + + Slt.e.M1 + No slits required on pads + + + + + Slt.f.M1 + Min. Metal1 enclosure of Metal1:slit = 1.00 + + + + + Slt.h1 + Min. Metal1:slit space to Cont and Via1 = 0.30 + + + + + Slt.a.M2 + Min. Metal2:slit width = 2.80 + + + + + Slt.b.M2 + Max. Metal2:slit width = 20.00 + + + + + Slt.c.M2 + Max. Metal2 width without requiring a slit = 30.00 + + + + + Slt.e.M2 + No slits required on pads + + + + + Slt.f.M2 + Min. Metal2 enclosure of Metal2:slit = 1.00 + + + + + Slt.h2.M2 + Min. Metal2:slit space to Via1 and Via2 = 0.30 + + + + + Slt.a.M3 + Min. Metal3:slit width = 2.80 + + + + + Slt.b.M3 + Max. Metal3:slit width = 20.00 + + + + + Slt.c.M3 + Max. Metal3 width without requiring a slit = 30.00 + + + + + Slt.e.M3 + No slits required on pads + + + + + Slt.f.M3 + Min. Metal3 enclosure of Metal2:slit = 1.00 + + + + + Slt.h2.M3 + Min. Metal3:slit space to Via2 and Via3 = 0.30 + + + + + Slt.a.M4 + Min. Metal4:slit width = 2.80 + + + + + Slt.b.M4 + Max. Metal4:slit width = 20.00 + + + + + Slt.c.M4 + Max. Metal4 width without requiring a slit = 30.00 + + + + + Slt.e.M4 + No slits required on pads + + + + + Slt.f.M4 + Min. Metal4 enclosure of Metal4:slit = 1.00 + + + + + Slt.h2.M4 + Min. Metal4:slit space to Via3 and Via4 = 0.30 + + + + + Slt.a.M5 + Min. Metal5:slit width = 2.80 + + + + + Slt.b.M5 + Max. Metal5:slit width = 20.00 + + + + + Slt.c.M5 + Max. Metal5 width without requiring a slit = 30.00 + + + + + Slt.e.M5 + No slits required on pads + + + + + Slt.f.M5 + Min. Metal5 enclosure of Metal5:slit = 1.00 + + + + + Slt.g.M5 + Min. Metal5:slit and TopMetal1:slit space to MIM = 0.60 + + + + + Slt.h2.M5 + Min. Metal5:slit space to Via4 and Via5 = 0.30 + + + + + Slt.a.TM1 + Min. TopMetal1:slit width = 2.80 + + + + + Slt.b.TM1 + Max. TopMetal1:slit width = 20.00 + + + + + Slt.c.TM1 + Max. TopMetal1 width without requiring a slit = 30.00 + + + + + Slt.e.TM1 + No slits required on pads + + + + + Slt.f.TM1 + Min. TopMetal1 enclosure of TopMetal1:slit = 1.00 + + + + + Slt.g.TM1 + Min. Metal5:slit and TopMetal1:slit space to MIM = 0.60 + + + + + Slt.h3 + Min. TopMetal1:slit space to TopVia1 and TopVia2 = 1.00 + + + + + Slt.a.TM2 + Min. TopMetal2:slit width = 2.80 + + + + + Slt.b.TM2 + Max. TopMetal2:slit width = 20.00 + + + + + Slt.c.TM2 + Max. TopMetal2 width without requiring a slit = 30.00 + + + + + Slt.e.TM2 + No slits required on pads + + + + + Slt.f.TM2 + Min. TopMetal2 enclosure of TopMetal2:slit = 1.00 + + + + + Slt.h4 + Min. TopMetal2:slit space to TopVia2 = 1.00 + + + + + NW.c1.dig + Min. NWell enclosure of P+Activ inside ThickGateOx inside DigiBnd = 0.31 + + + + + NW.d1.dig + Min. NWell space to external N+Activ inside ThickGateOx inside DigiBnd = 0.31 + + + + + NW.e1.dig + Min. NWell enclosure of NWell tie surrounded entirely by NWell in N+Activ inside ThickGateOx inside DigiBnd = 0.24 + + + + + NW.f1.dig + Min. NWell space to substrate tie in P+Activ inside ThickGateOx inside DigiBnd = 0.24 + + + + + Cnt.c.Digi + Min. Activ enclosure of Cont inside DigiBnd = 0.05 + + + + + LBE.b2 + Min. LBE area (µm²) = 30000.00 + + + + + LBE.e.dfPad + Min. LBE space to dfpad and Passiv = 50.00 + + + + + LBE.e.Passiv + Min. LBE space to dfpad and Passiv = 50.00 + + + + + LBE.f + Min. LBE space to Activ = 30.00 + + + + + OffGrid.NWell + NWell is off-grid + + + + + OffGrid.PWell + PWell is off-grid + + + + + OffGrid.PWell_block + PWell_block is off-grid + + + + + OffGrid.nBuLay + nBuLay is off-grid + + + + + OffGrid.nBuLay_block + nBuLay_block is off-grid + + + + + OffGrid.Activ + Activ is off-grid + + + + + OffGrid.ThickGateOx + ThickGateOx is off-grid + + + + + OffGrid.Activ_filler + Activ_filler is off-grid + + + + + OffGrid.GatPoly_filler + GatPoly_filler is off-grid + + + + + OffGrid.GatPoly + GatPoly is off-grid + + + + + OffGrid.pSD + pSD is off-grid + + + + + OffGrid.nSD + nSD is off-grid + + + + + OffGrid.nSD_block + nSD_block is off-grid + + + + + OffGrid.EXTBlock + EXTBlock is off-grid + + + + + OffGrid.SalBlock + SalBlock is off-grid + + + + + OffGrid.Cont + Cont is off-grid + + + + + OffGrid.Activ_nofill + Activ_nofill is off-grid + + + + + OffGrid.GatPoly_nofill + GatPoly_nofill is off-grid + + + + + OffGrid.Metal1 + Metal1 is off-grid + + + + + OffGrid.Via1 + Via1 is off-grid + + + + + OffGrid.Metal2 + Metal2 is off-grid + + + + + OffGrid.Via2 + Via2 is off-grid + + + + + OffGrid.Metal3 + Metal3 is off-grid + + + + + OffGrid.Via3 + Via3 is off-grid + + + + + OffGrid.Metal4 + Metal4 is off-grid + + + + + OffGrid.Via4 + Via4 is off-grid + + + + + OffGrid.Metal5 + Metal5 is off-grid + + + + + OffGrid.MIM + MIM is off-grid + + + + + OffGrid.Vmim + Vmim is off-grid + + + + + OffGrid.TopVia1 + TopVia1 is off-grid + + + + + OffGrid.TopMetal1 + TopMetal1 is off-grid + + + + + OffGrid.TopVia2 + TopVia2 is off-grid + + + + + OffGrid.TopMetal2 + TopMetal2 is off-grid + + + + + OffGrid.Passiv + Passiv is off-grid + + + + + OffGrid.Metal1_filler + Metal1_filler is off-grid + + + + + OffGrid.Metal2_filler + Metal2_filler is off-grid + + + + + OffGrid.Metal3_filler + Metal3_filler is off-grid + + + + + OffGrid.Metal4_filler + Metal4_filler is off-grid + + + + + OffGrid.Metal5_filler + Metal5_filler is off-grid + + + + + OffGrid.TopMetal1_filler + TopMetal1_filler is off-grid + + + + + OffGrid.TopMetal2_filler + TopMetal2_filler is off-grid + + + + + OffGrid.Metal1_nofill + Metal1_nofill is off-grid + + + + + OffGrid.Metal2_nofill + Metal2_nofill is off-grid + + + + + OffGrid.Metal3_nofill + Metal3_nofill is off-grid + + + + + OffGrid.Metal4_nofill + Metal4_nofill is off-grid + + + + + OffGrid.Metal5_nofill + Metal5_nofill is off-grid + + + + + OffGrid.TopMetal1_nofill + TopMetal1_nofill is off-grid + + + + + OffGrid.TopMetal2_nofill + TopMetal2_nofill is off-grid + + + + + OffGrid.NoMetFiller + NoMetFiller is off-grid + + + + + OffGrid.Metal1_slit + Metal1_slit is off-grid + + + + + OffGrid.Metal2_slit + Metal2_slit is off-grid + + + + + OffGrid.Metal3_slit + Metal3_slit is off-grid + + + + + OffGrid.Metal4_slit + Metal4_slit is off-grid + + + + + OffGrid.Metal5_slit + Metal5_slit is off-grid + + + + + OffGrid.TopMetal1_slit + TopMetal1_slit is off-grid + + + + + OffGrid.TopMetal2_slit + TopMetal2_slit is off-grid + + + + + OffGrid.EdgeSeal + EdgeSeal is off-grid + + + + + OffGrid.EmWind + EmWind is off-grid + + + + + OffGrid.dfpad + dfpad is off-grid + + + + + OffGrid.Polimide + Polimide is off-grid + + + + + OffGrid.TRANS + TRANS is off-grid + + + + + OffGrid.IND + IND is off-grid + + + + + OffGrid.RES + RES is off-grid + + + + + OffGrid.RFMEM + RFMEM is off-grid + + + + + OffGrid.Recog_diode + Recog_diode is off-grid + + + + + OffGrid.Recog_esd + Recog_esd is off-grid + + + + + OffGrid.DigiBnd + DigiBnd is off-grid + + + + + OffGrid.DigiSub + DigiSub is off-grid + + + + + OffGrid.SRAM + SRAM is off-grid + + + + + OffGrid.dfpad_pillar + dfpad_pillar is off-grid + + + + + OffGrid.dfpad_sbump + dfpad_sbump is off-grid + + + + + OffGrid.DeepVia + DeepVia is off-grid + + + + + OffGrid.LBE + LBE is off-grid + + + + + OffGrid.PolyRes + PolyRes is off-grid + + + + + + + lvs_tester + + + + + + + nmos$1 + + nmos$1 + + + lvs_tester + r0 *1 2.56,0.1 + + + + + + + + 'Cnt.d' + lvs_tester + false + 1 + + + + edge-pair: (3.215,-0.065;3.055,-0.065)/(3.283,-0.08;2.987,-0.08) + + + + + 'Cnt.e' + lvs_tester + false + 1 + + + + edge-pair: (3.055,0.095;3.215,0.095)/(3.355,0.1;2.915,0.1) + + + + + 'M1.b' + lvs_tester + false + 1 + + + + edge-pair: (2.93,-0.065;2.93,0.095)|(2.79,0.208;2.79,-0.178) + + + + + 'M1.b' + lvs_tester + false + 1 + + + + edge-pair: (3.46,-0.095;3.46,0.208)|(3.32,0.095;3.32,-0.065) + + + + + 'M1.b' + lvs_tester + false + 1 + + + + edge-pair: (3.46,-0.095;3.46,0.1)|(3.32,0.095;3.32,-0.065) + + + + + 'M1.b' + lvs_tester + false + 1 + + + + edge-pair: (2.93,-0.065;2.93,0.095)|(2.79,0.1;2.79,-0.178) + + + + + 'M1.b' + nmos$1 + false + 1 + + + + edge-pair: (0.37,-0.113;0.37,-0.005)|(0.23,0.108;0.23,0) + + + + + 'M1.b' + nmos$1 + false + 1 + + + + edge-pair: (0.76,-0.005;0.76,-0.113)|(0.9,0;0.9,0.108) + + + + + 'M1.d' + lvs_tester + false + 1 + + + + polygon: (2.93,-0.065;2.93,0.095;3.32,0.095;3.32,-0.065) + + + + \ No newline at end of file diff --git a/modules/module_0_foundations/lvs_tester/GDS/lvs_tester_extracted.cir b/modules/module_0_foundations/lvs_tester/GDS/lvs_tester_extracted.cir index 48517d9b..e8033888 100644 --- a/modules/module_0_foundations/lvs_tester/GDS/lvs_tester_extracted.cir +++ b/modules/module_0_foundations/lvs_tester/GDS/lvs_tester_extracted.cir @@ -1,4 +1,4 @@ -* Extracted by KLayout with SG13G2 LVS runset on : 13/02/2026 11:51 +* Extracted by KLayout with SG13G2 LVS runset on : 23/02/2026 16:48 .SUBCKT lvs_tester gnd G D M$1 gnd G D \$1 sg13_lv_nmos L=0.45u W=1u AS=0.34p AD=0.34p PS=2.68u PD=2.68u diff --git a/modules/module_0_foundations/scripting/gmid_test.ipynb b/modules/module_0_foundations/scripting/gmid_test.ipynb index 1b1e1cf4..132572a4 100644 --- a/modules/module_0_foundations/scripting/gmid_test.ipynb +++ b/modules/module_0_foundations/scripting/gmid_test.ipynb @@ -2,7 +2,7 @@ "cells": [ { "cell_type": "code", - "execution_count": 34, + "execution_count": 1, "id": "9f325daf-eb3b-4cf7-8ffe-b9b94e7f66ea", "metadata": {}, "outputs": [], @@ -18,7 +18,7 @@ }, { "cell_type": "code", - "execution_count": 35, + "execution_count": 2, "id": "b5b31aca-47bf-4461-8e50-16c20f03b337", "metadata": {}, "outputs": [], @@ -29,7 +29,7 @@ }, { "cell_type": "code", - "execution_count": 36, + "execution_count": 3, "id": "743dc381-0d35-4aa9-847c-c42c80c17786", "metadata": {}, "outputs": [], @@ -40,7 +40,7 @@ }, { "cell_type": "code", - "execution_count": 37, + "execution_count": 4, "id": "b27d5fca-3436-4df7-895f-f6a4bbd7a80d", "metadata": { "jupyter": { @@ -243,7 +243,7 @@ }, { "cell_type": "code", - "execution_count": 38, + "execution_count": 5, "id": "fc95a0ff-ba36-46ce-9fa1-64d6d2d7770f", "metadata": {}, "outputs": [], @@ -263,14 +263,14 @@ }, { "cell_type": "code", - "execution_count": 39, + "execution_count": 6, "id": "b7cc630f-b385-47a6-a6f9-ac0d10effffe", "metadata": {}, "outputs": [ { "data": { "application/vnd.jupyter.widget-view+json": { - "model_id": "c0d716a395d84be68ee1dbc73a913175", + "model_id": "ffe7b403abd44a54aed0fd72398a9e7d", "version_major": 2, "version_minor": 0 }, @@ -309,14 +309,14 @@ }, { "cell_type": "code", - "execution_count": 40, + "execution_count": 7, "id": "3727c42d-a4bf-4eb0-bc11-6e859ae41324", "metadata": {}, "outputs": [ { "data": { "application/vnd.jupyter.widget-view+json": { - "model_id": "cba5a4c794944ea1900cd54144dad957", + "model_id": "7d74cd77c32c4375988584ce9ecbe123", "version_major": 2, "version_minor": 0 }, @@ -337,6 +337,14 @@ "\n", "plot_data_vs_data(gm_values/id_values, gm_values/gds_values, vgs_values, length_2d_pmos, 'gm/id', 'gm/gds')" ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "8cb46727-5495-4ba9-bc48-b6b672250b45", + "metadata": {}, + "outputs": [], + "source": [] } ], "metadata": { diff --git a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_MC.sch b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_MC.sch index c14c92fb..995ed9de 100644 --- a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_MC.sch +++ b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_MC.sch @@ -189,12 +189,6 @@ value=" .endc "} -C {devices/code_shown.sym} -980 -595 0 0 {name=MODEL only_toplevel=true -format="tcleval( @value )" -value=" -.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ -.lib $::SG13G2_MODELS/cornerRES.lib res_typ -.lib cornerMOSlv.lib mos_tt_stat"} C {sg13g2_pr/sg13_lv_nmos.sym} -700 -765 2 0 {name=M8 l=10u w=150n @@ -335,3 +329,9 @@ w=100.78e-6 l=100.78e-6 } C {sg13g2_pr/sub.sym} 760 -310 0 0 {name=l7 lab=sub!} +C {devices/code_shown.sym} -950 -585 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ +.lib $::SG13G2_MODELS/cornerRES.lib res_typ +.lib cornerMOSlv.lib mos_tt_stat"} diff --git a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/offset_MC_analysis.sch b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/offset_MC_analysis.sch index 9622e2d6..c6511d77 100644 --- a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/offset_MC_analysis.sch +++ b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/offset_MC_analysis.sch @@ -102,10 +102,11 @@ footprint=1206 device="ceramic capacitor"} C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND} C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND} -C {devices/code_shown.sym} -675 -780 0 0 {name=NGSPICE1 only_toplevel=false +C {devices/code_shown.sym} -855 -770 0 0 {name=NGSPICE1 only_toplevel=false value=" -.lib cornerCAP.lib cap_typ -.lib cornerMOSlv.lib mos_tt_stat + +.param mm_ok=1 +.param mc_ok=1 .control let run = 1 @@ -133,8 +134,7 @@ value=" "} C {dynamic_comparator.sym} 270 -220 0 0 {name=x1} -C {devices/code_shown.sym} -5 -580 0 0 {name=MODEL only_toplevel=false +C {devices/code_shown.sym} -180 -755 0 0 {name=MODEL only_toplevel=true format="tcleval( @value )" value=" -.lib cornerMOSlv.lib mos_tt_stat -"} +.lib cornerMOSlv.lib mos_tt_mismatch"} diff --git a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/comparator_tb.save b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/comparator_tb.save deleted file mode 100644 index e390facc..00000000 --- a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/comparator_tb.save +++ /dev/null @@ -1,122 +0,0 @@ -* Place this .save file with a .include line in your testbench - -.save @n.x1.xm13.nsg13_lv_pmos[ids] -.save @n.x1.xm13.nsg13_lv_pmos[gm] -.save @n.x1.xm13.nsg13_lv_pmos[gds] -.save @n.x1.xm13.nsg13_lv_pmos[vth] -.save @n.x1.xm13.nsg13_lv_pmos[vgs] -.save @n.x1.xm13.nsg13_lv_pmos[vdss] -.save @n.x1.xm13.nsg13_lv_pmos[vds] -.save @n.x1.xm13.nsg13_lv_pmos[cgg] -.save @n.x1.xm13.nsg13_lv_pmos[cgsol] -.save @n.x1.xm13.nsg13_lv_pmos[cgdol] -.save @n.x1.xm3.nsg13_lv_pmos[ids] -.save @n.x1.xm3.nsg13_lv_pmos[gm] -.save @n.x1.xm3.nsg13_lv_pmos[gds] -.save @n.x1.xm3.nsg13_lv_pmos[vth] -.save @n.x1.xm3.nsg13_lv_pmos[vgs] -.save @n.x1.xm3.nsg13_lv_pmos[vdss] -.save @n.x1.xm3.nsg13_lv_pmos[vds] -.save @n.x1.xm3.nsg13_lv_pmos[cgg] -.save @n.x1.xm3.nsg13_lv_pmos[cgsol] -.save @n.x1.xm3.nsg13_lv_pmos[cgdol] -.save @n.x1.xm2.nsg13_lv_pmos[ids] -.save @n.x1.xm2.nsg13_lv_pmos[gm] -.save @n.x1.xm2.nsg13_lv_pmos[gds] -.save @n.x1.xm2.nsg13_lv_pmos[vth] -.save @n.x1.xm2.nsg13_lv_pmos[vgs] -.save @n.x1.xm2.nsg13_lv_pmos[vdss] -.save @n.x1.xm2.nsg13_lv_pmos[vds] -.save @n.x1.xm2.nsg13_lv_pmos[cgg] -.save @n.x1.xm2.nsg13_lv_pmos[cgsol] -.save @n.x1.xm2.nsg13_lv_pmos[cgdol] -.save @n.x1.xm1.nsg13_lv_pmos[ids] -.save @n.x1.xm1.nsg13_lv_pmos[gm] -.save @n.x1.xm1.nsg13_lv_pmos[gds] -.save @n.x1.xm1.nsg13_lv_pmos[vth] -.save @n.x1.xm1.nsg13_lv_pmos[vgs] -.save @n.x1.xm1.nsg13_lv_pmos[vdss] -.save @n.x1.xm1.nsg13_lv_pmos[vds] -.save @n.x1.xm1.nsg13_lv_pmos[cgg] -.save @n.x1.xm1.nsg13_lv_pmos[cgsol] -.save @n.x1.xm1.nsg13_lv_pmos[cgdol] -.save @n.x1.xm4.nsg13_lv_pmos[ids] -.save @n.x1.xm4.nsg13_lv_pmos[gm] -.save @n.x1.xm4.nsg13_lv_pmos[gds] -.save @n.x1.xm4.nsg13_lv_pmos[vth] -.save @n.x1.xm4.nsg13_lv_pmos[vgs] -.save @n.x1.xm4.nsg13_lv_pmos[vdss] -.save @n.x1.xm4.nsg13_lv_pmos[vds] -.save @n.x1.xm4.nsg13_lv_pmos[cgg] -.save @n.x1.xm4.nsg13_lv_pmos[cgsol] -.save @n.x1.xm4.nsg13_lv_pmos[cgdol] -.save @n.x1.xm5.nsg13_lv_pmos[ids] -.save @n.x1.xm5.nsg13_lv_pmos[gm] -.save @n.x1.xm5.nsg13_lv_pmos[gds] -.save @n.x1.xm5.nsg13_lv_pmos[vth] -.save @n.x1.xm5.nsg13_lv_pmos[vgs] -.save @n.x1.xm5.nsg13_lv_pmos[vdss] -.save @n.x1.xm5.nsg13_lv_pmos[vds] -.save @n.x1.xm5.nsg13_lv_pmos[cgg] -.save @n.x1.xm5.nsg13_lv_pmos[cgsol] -.save @n.x1.xm5.nsg13_lv_pmos[cgdol] -.save @n.x1.xm11.nsg13_lv_nmos[ids] -.save @n.x1.xm11.nsg13_lv_nmos[gm] -.save @n.x1.xm11.nsg13_lv_nmos[gds] -.save @n.x1.xm11.nsg13_lv_nmos[vth] -.save @n.x1.xm11.nsg13_lv_nmos[vgs] -.save @n.x1.xm11.nsg13_lv_nmos[vdss] -.save @n.x1.xm11.nsg13_lv_nmos[vds] -.save @n.x1.xm11.nsg13_lv_nmos[cgg] -.save @n.x1.xm11.nsg13_lv_nmos[cgsol] -.save @n.x1.xm11.nsg13_lv_nmos[cgdol] -.save @n.x1.xm12.nsg13_lv_nmos[ids] -.save @n.x1.xm12.nsg13_lv_nmos[gm] -.save @n.x1.xm12.nsg13_lv_nmos[gds] -.save @n.x1.xm12.nsg13_lv_nmos[vth] -.save @n.x1.xm12.nsg13_lv_nmos[vgs] -.save @n.x1.xm12.nsg13_lv_nmos[vdss] -.save @n.x1.xm12.nsg13_lv_nmos[vds] -.save @n.x1.xm12.nsg13_lv_nmos[cgg] -.save @n.x1.xm12.nsg13_lv_nmos[cgsol] -.save @n.x1.xm12.nsg13_lv_nmos[cgdol] -.save @n.x1.xm6.nsg13_lv_nmos[ids] -.save @n.x1.xm6.nsg13_lv_nmos[gm] -.save @n.x1.xm6.nsg13_lv_nmos[gds] -.save @n.x1.xm6.nsg13_lv_nmos[vth] -.save @n.x1.xm6.nsg13_lv_nmos[vgs] -.save @n.x1.xm6.nsg13_lv_nmos[vdss] -.save @n.x1.xm6.nsg13_lv_nmos[vds] -.save @n.x1.xm6.nsg13_lv_nmos[cgg] -.save @n.x1.xm6.nsg13_lv_nmos[cgsol] -.save @n.x1.xm6.nsg13_lv_nmos[cgdol] -.save @n.x1.xm10.nsg13_lv_nmos[ids] -.save @n.x1.xm10.nsg13_lv_nmos[gm] -.save @n.x1.xm10.nsg13_lv_nmos[gds] -.save @n.x1.xm10.nsg13_lv_nmos[vth] -.save @n.x1.xm10.nsg13_lv_nmos[vgs] -.save @n.x1.xm10.nsg13_lv_nmos[vdss] -.save @n.x1.xm10.nsg13_lv_nmos[vds] -.save @n.x1.xm10.nsg13_lv_nmos[cgg] -.save @n.x1.xm10.nsg13_lv_nmos[cgsol] -.save @n.x1.xm10.nsg13_lv_nmos[cgdol] -.save @n.x1.xm7.nsg13_lv_nmos[ids] -.save @n.x1.xm7.nsg13_lv_nmos[gm] -.save @n.x1.xm7.nsg13_lv_nmos[gds] -.save @n.x1.xm7.nsg13_lv_nmos[vth] -.save @n.x1.xm7.nsg13_lv_nmos[vgs] -.save @n.x1.xm7.nsg13_lv_nmos[vdss] -.save @n.x1.xm7.nsg13_lv_nmos[vds] -.save @n.x1.xm7.nsg13_lv_nmos[cgg] -.save @n.x1.xm7.nsg13_lv_nmos[cgsol] -.save @n.x1.xm7.nsg13_lv_nmos[cgdol] -.save @n.x1.xm8.nsg13_lv_nmos[ids] -.save @n.x1.xm8.nsg13_lv_nmos[gm] -.save @n.x1.xm8.nsg13_lv_nmos[gds] -.save @n.x1.xm8.nsg13_lv_nmos[vth] -.save @n.x1.xm8.nsg13_lv_nmos[vgs] -.save @n.x1.xm8.nsg13_lv_nmos[vdss] -.save @n.x1.xm8.nsg13_lv_nmos[vds] -.save @n.x1.xm8.nsg13_lv_nmos[cgg] -.save @n.x1.xm8.nsg13_lv_nmos[cgsol] -.save @n.x1.xm8.nsg13_lv_nmos[cgdol] diff --git a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/dc_lv_nmos.save b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/dc_lv_nmos.save deleted file mode 100644 index d41430d0..00000000 --- a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/dc_lv_nmos.save +++ /dev/null @@ -1,12 +0,0 @@ -* Place this .save file with a .include line in your testbench - -.save @n.xm1.nsg13_lv_nmos[ids] -.save @n.xm1.nsg13_lv_nmos[gm] -.save @n.xm1.nsg13_lv_nmos[gds] -.save @n.xm1.nsg13_lv_nmos[vth] -.save @n.xm1.nsg13_lv_nmos[vgs] -.save @n.xm1.nsg13_lv_nmos[vdss] -.save @n.xm1.nsg13_lv_nmos[vds] -.save @n.xm1.nsg13_lv_nmos[cgg] -.save @n.xm1.nsg13_lv_nmos[cgsol] -.save @n.xm1.nsg13_lv_nmos[cgdol] diff --git a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/inv_mc_tb.save b/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/inv_mc_tb.save deleted file mode 100644 index 212ff978..00000000 --- a/modules/module_3_8_bit_SAR_ADC/part_1_comparator/testbench/simulations/inv_mc_tb.save +++ /dev/null @@ -1,32 +0,0 @@ -* Place this .save file with a .include line in your testbench - -.save @n.xm1.nsg13_lv_nmos[ids] -.save @n.xm1.nsg13_lv_nmos[gm] -.save @n.xm1.nsg13_lv_nmos[gds] -.save @n.xm1.nsg13_lv_nmos[vth] -.save @n.xm1.nsg13_lv_nmos[vgs] -.save @n.xm1.nsg13_lv_nmos[vdss] -.save @n.xm1.nsg13_lv_nmos[vds] -.save @n.xm1.nsg13_lv_nmos[cgg] -.save @n.xm1.nsg13_lv_nmos[cgsol] -.save @n.xm1.nsg13_lv_nmos[cgdol] -.save @n.xm2.nsg13_lv_pmos[ids] -.save @n.xm2.nsg13_lv_pmos[gm] -.save @n.xm2.nsg13_lv_pmos[gds] -.save @n.xm2.nsg13_lv_pmos[vth] -.save @n.xm2.nsg13_lv_pmos[vgs] -.save @n.xm2.nsg13_lv_pmos[vdss] -.save @n.xm2.nsg13_lv_pmos[vds] -.save @n.xm2.nsg13_lv_pmos[cgg] -.save @n.xm2.nsg13_lv_pmos[cgsol] -.save @n.xm2.nsg13_lv_pmos[cgdol] -.save @n.xm3.nsg13_lv_nmos[ids] -.save @n.xm3.nsg13_lv_nmos[gm] -.save @n.xm3.nsg13_lv_nmos[gds] -.save @n.xm3.nsg13_lv_nmos[vth] -.save @n.xm3.nsg13_lv_nmos[vgs] -.save @n.xm3.nsg13_lv_nmos[vdss] -.save @n.xm3.nsg13_lv_nmos[vds] -.save @n.xm3.nsg13_lv_nmos[cgg] -.save @n.xm3.nsg13_lv_nmos[cgsol] -.save @n.xm3.nsg13_lv_nmos[cgdol]