diff --git a/modules/module_1_bandgap_reference/part_2_full_bgr/design_of_bgr.md b/modules/module_1_bandgap_reference/part_2_full_bgr/design_of_bgr.md
index 458a83bc..70e1c580 100644
--- a/modules/module_1_bandgap_reference/part_2_full_bgr/design_of_bgr.md
+++ b/modules/module_1_bandgap_reference/part_2_full_bgr/design_of_bgr.md
@@ -1,24 +1,319 @@
-# Selecting the BJT Operating Point
+# Designing the Bandgap Reference
-The first step in designing the bandgap reference in the structure we are working with is to select the appropriate relationship between the transistors Q1 and Q2 to achieve a suitable n-factor, while considering layout constraints. A 1:8 ratio with n = 8 provides favorable conditions for creating a robust common centroid layout, which will be discussed in more detail later.
+In this tutorial, we will design a functional bandgap reference circuit and perform the necessary simulations to evaluate its performance. Our analysis will cover both the DC characteristics and transient behavior of the bandgap reference. Additionally, to understand the effects of mismatch, we will delve into the concept of mismatch analysis and conduct Monte Carlo simulations. Unlike the traditional BJT-based reference discussed in the introduction, the circuit we will design here uses an all-CMOS implementation. This approach leverages transistors M1 and M2 operating in weak inversion to achieve the desired performance.
-For the current bias, we assume a value of:
+ 
-$$I_{D3}=25\mu A$$
-and for the resistor value:
+In the schematic above, we observe an all-CMOS bandgap reference circuit, which we will design in the following tutorial. As previously discussed in the introduction, achieving a temperature-dependent characteristic is essential to generate a CTAT (Complementary to Absolute Temperature) behavior in terms of current.
-$$R_3 = 45k\Omega$$
+For an NMOS transistor operating in the weak inversion (subthreshold) region, the current exhibits an exponential dependence on VGS. This makes the NMOS transistor suitable for generating a CTAT characteristic, particularly because VGS varies with temperature.
-From here lets investigate the resulting change in Vbe as the temperature varies from -30°C to 100°C. For this we create a new schematic given as
+ 
+
+Similarly, by exploiting the voltage difference between the VGS values of transistors M1 and M2, we can generate a PTAT (Proportional to Absolute Temperature).
+
+
+### Challenges of Using Resistors in CMOS Technology
+
+Designing with resistors in CMOS technology involves several challenges that can impact circuit performance. One key issue is **temperature dependence**, as resistors often experience changes in resistance due to temperature variations, which can affect precision in analog and mixed-signal circuits. This is especially problematic in resistors with high temperature coefficients (TCs), leading to variability under different operating conditions.
+
+**Area constraints** are also a concern, as achieving high resistance values requires larger resistor dimensions, consuming valuable chip space. This creates a trade-off between resistance and area efficiency, especially in dense designs. Below we will discuss the resistors available in the SG13G2 PDK
+.
+### **Resistor Types in SG13G2 PDK**
+
+The SG13G2 process provides three primary resistor types, each tailored for specific use cases:
+
+1. **Rsil (Salicided n-doped Polysilicon Resistor)**:
+
+ - **Material**: Salicided, n-doped polysilicon.
+ - **Characteristics**:
+ - Low sheet resistance (7 Ω/□7 \, \Omega/\square7Ω/□).
+ - High temperature coefficient (TC: 3100 ppm/K3100 \, \text{ppm/K}3100ppm/K).
+ - **Applications**:
+ - Suitable for low-resistance paths but not ideal for precision or temperature-sensitive applications.
+2. **Rppd (Unsalicided p-doped Polysilicon Resistor)**:
+
+ - **Material**: Unsalicided, p-doped polysilicon.
+ - **Characteristics**:
+ - Moderate sheet resistance (260 Ω/□260 \, \Omega/\square260Ω/□).
+ - Low temperature coefficient (TC: 170 ppm/K170 \, \text{ppm/K}170ppm/K).
+ - **Applications**:
+ - Ideal for precision applications and temperature-sensitive designs.
+3. **Rhigh (High-Resistance Structures)**:
+
+ - **Material**: Specialized high-resistance structures.
+ - **Characteristics**:
+ - Extremely high sheet resistance (exact values depend on design and material).
+ - Temperature behavior varies with structure.
+ - **Applications**:
+ - Used for high-impedance paths and circuits where area and power constraints allow.
+
+
+| **Resistor Type** | **Material** | **Sheet Resistance** | **Temperature Coefficient (TC)** | **Applications** |
+|-------------------|------------------------------|-------------------------|-----------------------------------|-----------------------------------------|
+| Rsil | Salicided n-doped polysilicon | 7 Ω/□ | 3100 ppm/K | Low-resistance paths, non-precision use |
+| Rppd | Unsalicided p-doped polysilicon | 260 Ω/□ | 170 ppm/K | Precision and temperature-sensitive designs |
+| Rhigh | High-resistance structures | Very high | Variable | High-impedance paths |
+
+Rppd’s low temperature coefficient, good precision, and moderate resistance make it ideal for bandgap reference circuits. It ensures temperature stability, process consistency, and area efficiency. Lets build the schematic
+
+### 1. Building the Schematic
+
+First, we will build the core of the bandgap reference.
+
+ 
+
+As shown here, the setup is quite basic. You can adjust it to your needs, as long as the proper connections are maintained. The new component introduced is the RPPD resistors, which can be found in the components library under the PDK directory. Ensure the device sizes match those shown in the image, and don't forget to add a voltage source to supply VDD.
+
+
+### Verilog-A Model for the Differential Amplifier
+At this point we want to introduce the concept of an ideal amplifier. We will create this in Verilog A. Verilog-A allows for the behavioral modeling of analog circuits, enabling efficient testing and simulation. The `openvaf` compiler is used to convert the Verilog-A description into a format usable by simulation tools.
+
+#### Creating the Verilog-A Model
+
+First, create a `verilog` directory in the repository and define a file named `diff_amp.va`. The following Verilog-A code describes the differential amplifier:
```
- touch vbesim.sch
+// importing libs
+
+`include "discipline.h"
+
+module diff_amp (out, IN1, IN2);
+
+output electrical out;
+
+input electrical IN1, IN2;
+
+parameter real gain = 10; // setting gain to 10 of the differential amplifier
+
+analog begin
+
+ V(out) <+ gain * (V(IN1) - V(IN2));
+
+end
+
+endmodule
+
```
-In this schematic we want to instaciate the following
+**Explanation:**
+
+- The `discipline.h` file provides definitions for electrical signals.
+- The module `diff_amp` has one output (`out`) and two inputs (`IN1` and `IN2`).
+- A parameter `gain` allows the amplifier gain to be specified (default is 10).
+- The `analog` block implements the core behavior, where the output voltage is the product of the gain and the input voltage difference.
+
+#### Verifying the Model with a Testbench
+
+To verify the functionality of the Verilog-A module, create a testbench file (`tb_diff_amp.sch`) and simulate it. Begin by compiling the Verilog-A code using `openvaf`:
+
+```
+openvaf /path/to/verilog/diff_amp.va
+```
+This generates an `.osdi` file that is required for simulation. The symbol for the differential amplifier can be accessed using `diff_amp.sym`, and its properties can be viewed by pressing `q` in the symbol editor. The relevant section includes:
+```
+type=opamp_va
+format="@spiceprefix@name @@OUT @@IN1 @@IN2 @model"
+template="name=U1 model=diff_amp_cell spiceprefix=X"
+
+device_model="tcleval(
+.subckt diff_amp_cell OUT IN1 IN2
+N1 out in1 in2 diff_amp_model
+.ends diff_amp_cell
+.model diff_amp_model diff_amp
+
+.control
+
+* following line specifies the location for the .osdi file so ngspice can use it.
+pre_osdi /IHP-AnalogAcademy/verilog/diff_amp.osdi
+.endc
+
+)"
+
+```
+#### Testbench Creation
+
+Refer to the `tb_diff_amp.sch` file in the repository for an example of how to create a schematic-based testbench using this Verilog-A module. The testbench verifies the module's behavior. Remember to use the openvaf_23_5_0_linux_amd64.tar.gz for compiling the model, otherwise you will face convergence issues.
+
+### 4. Inserting the Amplifier with Startup Circuitry
+
+At this stage, you have two options for proceeding with the bandgap reference design:
+
+1. **Using an Ideal Amplifier**:
+ You can create a bandgap reference with an ideal amplifier, as introduced earlier. This approach allows you to experiment with properties like the power supply rejection ratio (PSRR) and observe the effects of an arbitrarily high-gain amplifier.
+
+2. **Using the OTA Designed in Part 1**:
+ To keep this tutorial concise, we will use the operational transconductance amplifier (OTA) designed in Part 1. This provides a practical implementation..
+
+
+The circuit, including the amplifier and startup circuitry, is shown in the image below. Ensure proper connections as depicted. Refer to the next section for details on setting up the testbench.
+
+ 
+
+
+## Bandgap Reference Testbench
+
+The purpose of the testbench is to evaluate the performance of the bandgap reference circuit under various conditions. The primary goal of a bandgap reference is to maintain a stable voltage across a wide temperature range and respond predictably to changes in supply voltage (VDD). In this section, we will set up a **DC simulation profile** to analyze temperature stability and a **transient simulation profile** to examine the circuit's dynamic behavior.
+
+### Importing Device Models
+
+To perform accurate simulations, we first include the model libraries for resistors, transistors, and capacitors. This ensures that the simulation reflects real-world component behavior. Create and insert the following code block for importing the necessary models:
+```
+name=MODEL only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
+.lib $::SG13G2_MODELS/cornerRES.lib res_typ
+.lib cornerMOSlv.lib mos_tt
+"
+```
+### Setting Up the Simulation Profile
+
+Next, create the simulation profile for the DC analysis. This profile focuses on evaluating the reference voltage's stability across a temperature range from -50°C to 100°C. Insert the following code block to configure the DC simulation:
+
+```
+"
+.control
+.save all
+alter V1 dc 1.2
+op
+dc TEMP -50 100 5
+write bgr_temp.raw
+.endc
+
+```
+### Setting Up the Transient Simulation Profile
+
+Transient simulation evaluates how the circuit reacts to time-varying conditions, such as a ramped supply voltage. This step ensures the bandgap reference circuit stabilizes at the desired voltage in a realistic startup scenario. Use the following code block to define the transient simulation:
+
+```
+.control
+.save all
+tran 1m 2
+write bandgap_transient.raw
+.endc
+
+
+"
+```
+
+- **`tran 1m 2`**: Runs a transient analysis with a 1ms time step for 2ms total.
+- **`write bgr_transient.raw`**: Exports the transient simulation data to a file (`bgr_transient.raw`)
+
+### Voltage Source Configuration
+
+For the transient simulation, the supply voltage source (`V1`) should simulate a realistic ramp-up. Use the following configuration:
+Also the voltage source in the schematic should have the following value
+
+```
+"PULSE(0 1.2 0 1 0 1 2)"
+```
+**`PULSE(0 1.2 0 1 0 1 2)`**: Defines a pulse waveform that starts at 0V, ramps to 1.2V with a 1s rise time, and remains at 1.2V for 1s. This mimics a practical VDD ramp scenario during power-up. The general form of the pulse function is `PULSE(V1 V2 TD TR TF PW PER NP)`. General information about the ngspice simulator can be found in the following link: https://ngspice.sourceforge.io/docs/ngspice-html-manual/manual.xhtml
+
+
+### Final Simulation Profile
+
+Combine the DC and transient simulation profiles into one testbench as shown:
+
+```
+"
+.control
+.save all
+alter V1 dc 1.2
+op
+dc TEMP -50 100 5
+write bgr_temp.raw
+.endc
+
+.control
+.save all
+tran 1m 2
+write bgr_transient.raw
+.endc
+
+"
+```
+### Final Schematic
+
+Ensure the schematic matches the design below:
+ 
+
+
+### Visualizing Results
+
+To visualize the results:
+
+1. Import **two waveform viewers** as described in the previous tutorial.
+2. Add **two launch buttons**, labeling them:
+ - **Load DC** (for `bgr_temp.raw`).
+ - **Load Transient** (for `bgr_transient.raw`).
+3. Arrange the plots:
+ - The top plot should display **VDD**.
+ - The bottom plot should display **VBG** (bandgap reference voltage).
+
+
+Expected results should resemble the following plots:
+
+**Temperature Sweep (DC Simulation)**:
+ 
+**Transient Analysis**:
+ 
+
+
+### Mismatch and Monte Carlo Simulations
+
+In real-world production, semiconductor devices like transistors are subject to variations in manufacturing processes. These variations, often referred to as **mismatch**, result from slight differences in dimensions, doping concentrations, and other fabrication parameters. Mismatch can have a profound impact on circuits that rely on symmetry and precision, such as **differential pairs**.
+
+#### The Impact of Mismatch on Differential Pairs and Bandgap References
+
+For example, in differential pairs, mismatch between the two transistors can result in imbalances in current distribution. This imbalance can compromise the accuracy, stability, and overall design integrity of the circuit if not properly addressed.
+
+For a bandgap reference, mismatched devices can cause the reference voltage to deviate from its intended value. Even a small variation in key components, such as transistors or resistors, can shift the temperature coefficient or the nominal output voltage, leading to performance degradation.
+
+### Why Monte Carlo Simulations Are Essential
+
+To account for mismatch in circuit design, engineers perform **Monte Carlo simulations**, which introduce random variations to model the effects of mismatch statistically. These simulations help:
+
+- Predict the impact of process variations on circuit performance.
+- Identify design weaknesses sensitive to mismatch.
+- Evaluate if the circuit meets specifications under worst-case conditions.
+### Monte Carlo Simulation for Mismatch
+
+In mismatch simulations, the tool generates a large number of circuit instances, each with random variations applied to components like transistors and resistors. For example, the threshold voltage Vth of transistors might vary slightly between runs.
+
+#### Number of Runs: Industry Considerations
+
+The number of runs required for a Monte Carlo simulation depends on several factors, including the desired confidence level and the complexity of the circuit. While **400 runs** is often cited as a typical benchmark in the industry to achieve statistically meaningful results, this number may vary. Smaller circuits or lower confidence requirements might allow for fewer runs, while highly sensitive or complex designs may require significantly more runs to capture outliers and ensure robust trend analysis.
+
+---
+
+### Understanding 3-Sigma Analysis
+
+Monte Carlo simulation results are often evaluated using a **3-sigma (3σ)** approach:
+
+- **1σ (1 standard deviation):** Captures ~68% of the data around the mean.
+- **2σ (2 standard deviations):** Covers ~95% of the data.
+- **3σ (3 standard deviations):** Encompasses ~99.7% of the data.
+
+By analyzing at the 3σ level, designers can ensure that the circuit performs reliably under nearly all manufacturing conditions, even those that result in extreme variations. For example, in a bandgap reference, a 3σ analysis would verify that the reference voltage remains stable for 99.7% of possible mismatch scenarios.
+
+---
+
+### Connecting to Bandgap Reference Design
+
+In the context of bandgap reference design, **Monte Carlo mismatch simulations** play a key role in:
+
+- Assessing how device mismatch impacts the output voltage variation.
+- Verifying that the design adheres to strict accuracy and temperature stability requirements.
+- Determining if trimming or calibration is necessary to compensate for mismatch during production.
+
+When considering the **3-sigma interval**, the focus shifts to evaluating the overall trend of the bandgap voltage across the temperature range. For this design, the critical objective is to ensure that even the most extreme scenarios fall within a stable voltage band, approximately centered around $Vdd/2$
+
+The next section will demonstrate how to set up and perform a Monte Carlo simulation for the bandgap reference. This includes defining mismatch parameters, specifying the number of runs, and analyzing the results to assess robustness.
+
+### Mismatch Monte Carlo simulation in xschem with ngspice (ongoing)
+
+
+
-- res.sym -->> values = 45k
-- sg13g2_pr/pnpMPA.sym -->> $w = 5.0\mu m \ \ l = 5.0\mu m$
-- isource.sym -->> name=I0 value=25e-6
-- vsource.sym -->> name=V1 value=1.2 savecurrent=false
diff --git a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_MC.sch b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_MC.sch
new file mode 100644
index 00000000..aa8f3ba7
--- /dev/null
+++ b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_MC.sch
@@ -0,0 +1,328 @@
+v {xschem version=3.4.5 file_version=1.2
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N -720 -850 -720 -795 {
+lab=#net1}
+N -575 -980 -485 -980 {
+lab=vdd}
+N -645 -930 -615 -930 {
+lab=#net1}
+N -720 -850 -645 -850 {
+lab=#net1}
+N -720 -900 -720 -850 {
+lab=#net1}
+N -645 -930 -645 -850 {
+lab=#net1}
+N -680 -930 -645 -930 {
+lab=#net1}
+N -720 -765 -720 -710 {
+lab=GND}
+N -575 -850 -575 -795 {
+lab=#net2}
+N -720 -710 -575 -710 {
+lab=GND}
+N -575 -735 -575 -710 {
+lab=GND}
+N -680 -765 -485 -765 {
+lab=v-}
+N -485 -980 -485 -850 {
+lab=vdd}
+N -575 -850 -525 -850 {
+lab=#net2}
+N -575 -900 -575 -850 {
+lab=#net2}
+N -485 -765 -485 -650 {
+lab=v-}
+N -485 -820 -485 -765 {
+lab=v-}
+N -110 -695 -80 -695 {
+lab=Vo1}
+N -275 -795 -275 -760 {
+lab=vdd}
+N -350 -610 -350 -595 {
+lab=#net3}
+N -350 -535 -275 -535 {
+lab=GND}
+N -275 -535 -275 -520 {
+lab=GND}
+N -275 -630 -275 -535 {
+lab=GND}
+N -435 -735 -410 -735 {
+lab=v+}
+N -485 -650 -410 -650 {
+lab=v-}
+N -780 -930 -720 -930 {
+lab=vdd}
+N -575 -930 -530 -930 {
+lab=vdd}
+N -575 -980 -575 -960 {
+lab=vdd}
+N -720 -980 -575 -980 {
+lab=vdd}
+N -720 -980 -720 -960 {
+lab=vdd}
+N 890 -405 890 -360 {
+lab=vdd}
+N 890 -300 890 -270 {
+lab=GND}
+N 370 -560 390 -560 {
+lab=#net4}
+N 370 -620 370 -560 {
+lab=#net4}
+N 370 -620 430 -620 {
+lab=#net4}
+N 130 -560 130 -460 {
+lab=GND}
+N 280 -460 430 -460 {
+lab=GND}
+N 130 -740 230 -740 {
+lab=v-}
+N 280 -965 280 -940 {
+lab=vdd}
+N 130 -940 280 -940 {
+lab=vdd}
+N 130 -840 130 -740 {
+lab=v-}
+N 430 -750 430 -740 {
+lab=v+}
+N 430 -740 430 -710 {
+lab=v+}
+N 430 -560 430 -460 {
+lab=GND}
+N 430 -620 430 -590 {
+lab=#net4}
+N 430 -650 430 -620 {
+lab=#net4}
+N 280 -460 280 -430 {
+lab=GND}
+N 130 -460 280 -460 {
+lab=GND}
+N 170 -870 390 -870 {
+lab=Vo1}
+N 595 -900 595 -870 {
+lab=Vo1}
+N 430 -750 595 -750 {
+lab=v+}
+N 980 -770 1030 -770 {
+lab=VBG}
+N 635 -840 635 -770 {
+lab=VBG}
+N 315 -740 430 -740 {
+lab=v+}
+N 430 -840 430 -750 {
+lab=v+}
+N 595 -750 595 -710 {
+lab=v+}
+N 430 -460 595 -460 {
+lab=GND}
+N 595 -650 595 -460 {
+lab=GND}
+N 430 -940 635 -940 {
+lab=vdd}
+N 980 -655 980 -460 {
+lab=GND}
+N 800 -460 980 -460 {
+lab=GND}
+N 980 -770 980 -715 {
+lab=VBG}
+N 800 -770 980 -770 {
+lab=VBG}
+N 635 -940 635 -900 {
+lab=vdd}
+N 635 -870 725 -870 {
+lab=vdd}
+N 430 -940 430 -900 {
+lab=vdd}
+N 280 -940 430 -940 {
+lab=vdd}
+N 430 -870 495 -870 {
+lab=vdd}
+N 130 -940 130 -900 {
+lab=vdd}
+N 70 -870 130 -870 {
+lab=vdd}
+N 130 -740 130 -590 {
+lab=v-}
+N 170 -560 315 -560 {
+lab=v+}
+N 315 -740 315 -560 {
+lab=v+}
+N 800 -770 800 -715 {
+lab=VBG}
+N 635 -770 800 -770 {
+lab=VBG}
+N 800 -655 800 -460 {
+lab=GND}
+N 595 -460 800 -460 {
+lab=GND}
+N -630 -795 -575 -795 {
+lab=#net2}
+N -630 -735 -575 -735 {
+lab=GND}
+C {devices/code_shown.sym} 20 -403.828125 0 0 {name=NGSPICE only_toplevel=false
+value="
+.control
+ let run = 1
+ let mc_runs = 100
+ set curplot = new
+ set scratch = $curplot
+ dowhile run <= mc_runs
+ reset
+ dc temp -50 100 5
+ set run = $&run
+ set dc = $curplot
+ setplot $scratch
+ let off\{$run\} = \{$dc\}.v(VBG)
+ let mytemp\{$run\} = \\"\{$dc\}.temp-sweep\\"
+ setplot $dc
+ let run = run + 1
+ end
+ set nolegend
+ plot \{$scratch\}.allv vs \{$scratch\}.mytemp1
+ write bandgap_testbench_mc_mis.raw \{$scratch\}.allv \{$scratch\}.mytemp1
+.endc
+
+"}
+C {devices/code_shown.sym} -450 -445 0 0 {name=MODEL only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
+.lib $::SG13G2_MODELS/cornerRES.lib res_typ
+.lib cornerMOSlv.lib mos_tt_mismatch
+"}
+C {sg13g2_pr/sg13_lv_nmos.sym} -700 -765 2 0 {name=M8
+l=10u
+w=150n
+ng=1
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} -700 -930 0 1 {name=M6
+l=1u
+w=1u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} -595 -930 0 0 {name=M7
+l=1u
+w=1u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {gnd.sym} -720 -710 0 0 {name=l1 lab=GND}
+C {sg13g2_pr/sg13_lv_pmos.sym} -505 -850 0 0 {name=M9
+l=4u
+w=200n
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} -485 -980 0 1 {name=p5 sig_type=std_logic lab=vdd}
+C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} -260 -695 0 0 {name=x2}
+C {lab_pin.sym} -275 -795 0 1 {name=p1 sig_type=std_logic lab=vdd}
+C {gnd.sym} -275 -520 0 1 {name=l4 lab=GND}
+C {isource.sym} -350 -565 0 1 {name=I1 value=80u}
+C {iopin.sym} -435 -735 0 1 {name=p16 lab=v+}
+C {iopin.sym} -435 -650 3 1 {name=p7 lab=v-}
+C {iopin.sym} -80 -695 0 0 {name=p10 lab=Vo1}
+C {lab_pin.sym} -530 -930 0 1 {name=p4 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -780 -930 0 0 {name=p17 sig_type=std_logic lab=vdd}
+C {vsource.sym} 890 -330 0 0 {name=V1 value="DC 1.2" savecurrent=false}
+C {lab_pin.sym} 890 -405 0 1 {name=p6 sig_type=std_logic lab=vdd}
+C {gnd.sym} 890 -270 0 0 {name=l18 lab=GND}
+C {sg13g2_pr/sg13_lv_nmos.sym} 150 -560 2 0 {name=M1
+l=5u
+w=7.14u
+ng=4
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_nmos.sym} 410 -560 2 1 {name=M2
+l=5u
+w=21u
+ng=8
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {gnd.sym} 280 -430 0 0 {name=l3 lab=GND}
+C {sg13g2_pr/sg13_lv_pmos.sym} 150 -870 0 1 {name=M3
+l=5u
+w=15u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} 410 -870 0 0 {name=M4
+l=5u
+w=15u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 280 -965 0 1 {name=p2 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 230 -740 3 0 {name=p3 sig_type=std_logic lab=v-}
+C {lab_pin.sym} 315 -740 0 0 {name=p8 sig_type=std_logic lab=v+}
+C {lab_pin.sym} 285 -870 1 1 {name=p9 sig_type=std_logic lab=Vo1}
+C {sg13g2_pr/sg13_lv_pmos.sym} 615 -870 0 0 {name=M5
+l=5u
+w=16u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {opin.sym} 1030 -770 0 0 {name=p11 lab=VBG}
+C {lab_pin.sym} 595 -900 2 1 {name=p12 sig_type=std_logic lab=Vo1}
+C {lab_pin.sym} 70 -870 0 0 {name=p13 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 495 -870 0 1 {name=p14 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 725 -870 0 1 {name=p15 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/cap_cmim.sym} 980 -685 0 0 {name=C3
+model=cap_cmim
+w=72.965e-6
+l=72.965e-6
+m=1
+spiceprefix=X}
+C {sg13g2_pr/rppd.sym} 430 -680 0 0 {name=R3
+w=0.5e-6
+l=194.345e-6
+model=rppd
+spiceprefix=X
+b=0
+m=1
+}
+C {sg13g2_pr/rppd.sym} 595 -680 0 0 {name=R1
+w=0.5e-6
+l=194.345e-6
+model=rppd
+spiceprefix=X
+b=0
+m=1.2
+}
+C {sg13g2_pr/rppd.sym} 800 -685 0 0 {name=R2
+w=0.5e-6
+l=192.395e-6
+model=rppd
+spiceprefix=X
+b=0
+m=1
+}
+C {sg13g2_pr/cap_cmim.sym} -630 -765 0 0 {name=C1
+model=cap_cmim
+w=18.195e-6
+l=18.195e-6
+m=1
+spiceprefix=X}
diff --git a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_reference.sch b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_reference.sch
index 33c524b8..891591e9 100644
--- a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_reference.sch
+++ b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_reference.sch
@@ -5,6 +5,50 @@ K {}
V {}
S {}
E {}
+B 2 1345.3515625 -1214.21875 2145.3515625 -814.21875 {flags=graph
+y1=0
+y2=1.3
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+
+x2=2
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+
+
+dataset=-1
+unitx=1
+logx=0
+logy=0
+x1=0
+color=7
+node=vdd}
+B 2 1345.3515625 -804.21875 2145.3515625 -404.21875 {flags=graph
+y1=-2.4e-13
+y2=0.61
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+
+x2=2
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+node=vbg
+color=4
+dataset=-1
+unitx=1
+logx=0
+logy=0
+x1=0}
N -720 -850 -720 -795 {
lab=#net1}
N -575 -980 -485 -980 {
@@ -65,9 +109,9 @@ N -720 -980 -575 -980 {
lab=vdd}
N -720 -980 -720 -960 {
lab=vdd}
-N 1085 -665 1085 -620 {
+N 890 -405 890 -360 {
lab=vdd}
-N 1085 -560 1085 -530 {
+N 890 -300 890 -270 {
lab=GND}
N 370 -560 390 -560 {
lab=#net4}
@@ -159,19 +203,27 @@ N 800 -655 800 -460 {
lab=GND}
N 595 -460 800 -460 {
lab=GND}
-N 1200 -540 1250 -540 {
-lab=sub!}
-N 1200 -480 1200 -465 {
+N -630 -795 -575 -795 {
+lab=#net2}
+N -630 -735 -575 -735 {
lab=GND}
-C {devices/code_shown.sym} -415 -305 0 0 {name=COMMANDS2 only_toplevel=true value="
+C {devices/code_shown.sym} -440 -333.828125 0 0 {name=bandgap only_toplevel=true value="
.control
.save all
+alter V1 dc 1.2
op
dc TEMP -50 100 5
+write bgr_temp.raw
+.endc
+
+.control
+.save all
+tran 1m 2
+write bandgap_transient.raw
.endc
"
}
-C {devices/code_shown.sym} -420 -455 0 0 {name=MODEL only_toplevel=true
+C {devices/code_shown.sym} -450 -445 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value="
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
@@ -203,11 +255,6 @@ model=sg13_lv_pmos
spiceprefix=X
}
C {gnd.sym} -720 -710 0 0 {name=l1 lab=GND}
-C {capa.sym} -575 -765 0 0 {name=C2
-m=1
-value=500e-15
-footprint=1206
-device="ceramic capacitor"}
C {sg13g2_pr/sg13_lv_pmos.sym} -505 -850 0 0 {name=M9
l=4u
w=200n
@@ -226,9 +273,9 @@ C {iopin.sym} -435 -650 3 1 {name=p7 lab=v-}
C {iopin.sym} -80 -695 0 0 {name=p10 lab=Vo1}
C {lab_pin.sym} -530 -930 0 1 {name=p4 sig_type=std_logic lab=vdd}
C {lab_pin.sym} -780 -930 0 0 {name=p17 sig_type=std_logic lab=vdd}
-C {vsource.sym} 1085 -590 0 0 {name=V1 value=1.2 savecurrent=false}
-C {lab_pin.sym} 1085 -665 0 1 {name=p6 sig_type=std_logic lab=vdd}
-C {gnd.sym} 1085 -530 0 0 {name=l18 lab=GND}
+C {vsource.sym} 890 -330 0 0 {name=V1 value="PULSE(0 1.2 0 1 0 1 2)" savecurrent=false}
+C {lab_pin.sym} 890 -405 0 1 {name=p6 sig_type=std_logic lab=vdd}
+C {gnd.sym} 890 -270 0 0 {name=l18 lab=GND}
C {sg13g2_pr/sg13_lv_nmos.sym} 150 -560 2 0 {name=M1
l=5u
w=7.14u
@@ -281,8 +328,8 @@ C {lab_pin.sym} 495 -870 0 1 {name=p14 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 725 -870 0 1 {name=p15 sig_type=std_logic lab=vdd}
C {sg13g2_pr/cap_cmim.sym} 980 -685 0 0 {name=C3
model=cap_cmim
-w=25.8e-6
-l=25.8e-6
+w=72.965e-6
+l=72.965e-6
m=1
spiceprefix=X}
C {sg13g2_pr/rppd.sym} 430 -680 0 0 {name=R3
@@ -309,11 +356,17 @@ spiceprefix=X
b=0
m=1
}
-C {sg13g2_pr/ptap1.sym} 1200 -510 2 0 {name=R4
-model=ptap1
-spiceprefix=X
-R=262.847.0
-Imax=0.3e-6
+C {launcher.sym} 1171.40625 -793.28125 0 0 {name=h5
+descr="load DC"
+tclcommand="xschem raw_read $netlist_dir/bgr_temp.raw dc"
}
-C {lab_pin.sym} 1250 -540 2 0 {name=p18 sig_type=std_logic lab=sub!}
-C {gnd.sym} 1200 -465 0 0 {name=l2 lab=GND}
+C {launcher.sym} 1171.40625 -768.28125 0 0 {name=h1
+descr="load Transient"
+tclcommand="xschem raw_read $netlist_dir/bandgap_transient.raw tran"
+}
+C {sg13g2_pr/cap_cmim.sym} -630 -765 0 0 {name=C1
+model=cap_cmim
+w=18.195e-6
+l=18.195e-6
+m=1
+spiceprefix=X}
diff --git a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_reference_temp.sch b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_reference_temp.sch
new file mode 100644
index 00000000..20d8eb00
--- /dev/null
+++ b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_reference_temp.sch
@@ -0,0 +1,333 @@
+v {xschem version=3.4.5 file_version=1.2
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+B 2 1345.3515625 -1214.21875 2145.3515625 -814.21875 {flags=graph
+y1=0.6
+y2=0.61
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+
+x2=100
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+node=vbg
+color=4
+dataset=-1
+unitx=1
+logx=0
+logy=0
+x1=-50}
+N -720 -850 -720 -795 {
+lab=#net1}
+N -575 -980 -485 -980 {
+lab=vdd}
+N -645 -930 -615 -930 {
+lab=#net1}
+N -720 -850 -645 -850 {
+lab=#net1}
+N -720 -900 -720 -850 {
+lab=#net1}
+N -645 -930 -645 -850 {
+lab=#net1}
+N -680 -930 -645 -930 {
+lab=#net1}
+N -720 -765 -720 -710 {
+lab=GND}
+N -575 -850 -575 -795 {
+lab=#net2}
+N -720 -710 -575 -710 {
+lab=GND}
+N -575 -735 -575 -710 {
+lab=GND}
+N -680 -765 -485 -765 {
+lab=v-}
+N -485 -980 -485 -850 {
+lab=vdd}
+N -575 -850 -525 -850 {
+lab=#net2}
+N -575 -900 -575 -850 {
+lab=#net2}
+N -485 -765 -485 -650 {
+lab=v-}
+N -485 -820 -485 -765 {
+lab=v-}
+N -110 -695 -80 -695 {
+lab=Vo1}
+N -275 -795 -275 -760 {
+lab=vdd}
+N -350 -610 -350 -595 {
+lab=#net3}
+N -350 -535 -275 -535 {
+lab=GND}
+N -275 -535 -275 -520 {
+lab=GND}
+N -275 -630 -275 -535 {
+lab=GND}
+N -435 -735 -410 -735 {
+lab=v+}
+N -485 -650 -410 -650 {
+lab=v-}
+N -780 -930 -720 -930 {
+lab=vdd}
+N -575 -930 -530 -930 {
+lab=vdd}
+N -575 -980 -575 -960 {
+lab=vdd}
+N -720 -980 -575 -980 {
+lab=vdd}
+N -720 -980 -720 -960 {
+lab=vdd}
+N 1085 -665 1085 -620 {
+lab=vdd}
+N 1085 -560 1085 -530 {
+lab=GND}
+N 370 -560 390 -560 {
+lab=#net4}
+N 370 -620 370 -560 {
+lab=#net4}
+N 370 -620 430 -620 {
+lab=#net4}
+N 130 -560 130 -460 {
+lab=GND}
+N 280 -460 430 -460 {
+lab=GND}
+N 130 -740 230 -740 {
+lab=v-}
+N 280 -965 280 -940 {
+lab=vdd}
+N 130 -940 280 -940 {
+lab=vdd}
+N 130 -840 130 -740 {
+lab=v-}
+N 430 -750 430 -740 {
+lab=v+}
+N 430 -740 430 -710 {
+lab=v+}
+N 430 -560 430 -460 {
+lab=GND}
+N 430 -620 430 -590 {
+lab=#net4}
+N 430 -650 430 -620 {
+lab=#net4}
+N 280 -460 280 -430 {
+lab=GND}
+N 130 -460 280 -460 {
+lab=GND}
+N 170 -870 390 -870 {
+lab=Vo1}
+N 595 -900 595 -870 {
+lab=Vo1}
+N 430 -750 595 -750 {
+lab=v+}
+N 980 -770 1030 -770 {
+lab=VBG}
+N 635 -840 635 -770 {
+lab=VBG}
+N 315 -740 430 -740 {
+lab=v+}
+N 430 -840 430 -750 {
+lab=v+}
+N 595 -750 595 -710 {
+lab=v+}
+N 430 -460 595 -460 {
+lab=GND}
+N 595 -650 595 -460 {
+lab=GND}
+N 430 -940 635 -940 {
+lab=vdd}
+N 980 -655 980 -460 {
+lab=GND}
+N 800 -460 980 -460 {
+lab=GND}
+N 980 -770 980 -715 {
+lab=VBG}
+N 800 -770 980 -770 {
+lab=VBG}
+N 635 -940 635 -900 {
+lab=vdd}
+N 635 -870 725 -870 {
+lab=vdd}
+N 430 -940 430 -900 {
+lab=vdd}
+N 280 -940 430 -940 {
+lab=vdd}
+N 430 -870 495 -870 {
+lab=vdd}
+N 130 -940 130 -900 {
+lab=vdd}
+N 70 -870 130 -870 {
+lab=vdd}
+N 130 -740 130 -590 {
+lab=v-}
+N 170 -560 315 -560 {
+lab=v+}
+N 315 -740 315 -560 {
+lab=v+}
+N 800 -770 800 -715 {
+lab=VBG}
+N 635 -770 800 -770 {
+lab=VBG}
+N 800 -655 800 -460 {
+lab=GND}
+N 595 -460 800 -460 {
+lab=GND}
+C {devices/code_shown.sym} -415 -303.828125 0 0 {name=COMMANDS2 only_toplevel=true value="
+.control
+.save all
+op
+dc TEMP -50 100 5
+write bgr_temp.raw
+.endc
+"
+}
+C {devices/code_shown.sym} -420 -455 0 0 {name=MODEL only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
+.lib $::SG13G2_MODELS/cornerRES.lib res_typ
+.lib cornerMOSlv.lib mos_tt
+"}
+C {sg13g2_pr/sg13_lv_nmos.sym} -700 -765 2 0 {name=M8
+l=10u
+w=150n
+ng=1
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} -700 -930 0 1 {name=M6
+l=1u
+w=1u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} -595 -930 0 0 {name=M7
+l=1u
+w=1u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {gnd.sym} -720 -710 0 0 {name=l1 lab=GND}
+C {capa.sym} -575 -765 0 0 {name=C2
+m=1
+value=500e-15
+footprint=1206
+device="ceramic capacitor"}
+C {sg13g2_pr/sg13_lv_pmos.sym} -505 -850 0 0 {name=M9
+l=4u
+w=200n
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} -485 -980 0 1 {name=p5 sig_type=std_logic lab=vdd}
+C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} -260 -695 0 0 {name=x2}
+C {lab_pin.sym} -275 -795 0 1 {name=p1 sig_type=std_logic lab=vdd}
+C {gnd.sym} -275 -520 0 1 {name=l4 lab=GND}
+C {isource.sym} -350 -565 0 1 {name=I1 value=80u}
+C {iopin.sym} -435 -735 0 1 {name=p16 lab=v+}
+C {iopin.sym} -435 -650 3 1 {name=p7 lab=v-}
+C {iopin.sym} -80 -695 0 0 {name=p10 lab=Vo1}
+C {lab_pin.sym} -530 -930 0 1 {name=p4 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -780 -930 0 0 {name=p17 sig_type=std_logic lab=vdd}
+C {vsource.sym} 1085 -590 0 0 {name=V1 value=1.2 savecurrent=false}
+C {lab_pin.sym} 1085 -665 0 1 {name=p6 sig_type=std_logic lab=vdd}
+C {gnd.sym} 1085 -530 0 0 {name=l18 lab=GND}
+C {sg13g2_pr/sg13_lv_nmos.sym} 150 -560 2 0 {name=M1
+l=5u
+w=7.14u
+ng=4
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_nmos.sym} 410 -560 2 1 {name=M2
+l=5u
+w=21u
+ng=8
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {gnd.sym} 280 -430 0 0 {name=l3 lab=GND}
+C {sg13g2_pr/sg13_lv_pmos.sym} 150 -870 0 1 {name=M3
+l=5u
+w=15u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} 410 -870 0 0 {name=M4
+l=5u
+w=15u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 280 -965 0 1 {name=p2 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 230 -740 3 0 {name=p3 sig_type=std_logic lab=v-}
+C {lab_pin.sym} 315 -740 0 0 {name=p8 sig_type=std_logic lab=v+}
+C {lab_pin.sym} 285 -870 1 1 {name=p9 sig_type=std_logic lab=Vo1}
+C {sg13g2_pr/sg13_lv_pmos.sym} 615 -870 0 0 {name=M5
+l=5u
+w=16u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {opin.sym} 1030 -770 0 0 {name=p11 lab=VBG}
+C {lab_pin.sym} 595 -900 2 1 {name=p12 sig_type=std_logic lab=Vo1}
+C {lab_pin.sym} 70 -870 0 0 {name=p13 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 495 -870 0 1 {name=p14 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 725 -870 0 1 {name=p15 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/cap_cmim.sym} 980 -685 0 0 {name=C3
+model=cap_cmim
+w=25.8e-6
+l=25.8e-6
+m=1
+spiceprefix=X}
+C {sg13g2_pr/rppd.sym} 430 -680 0 0 {name=R3
+w=0.5e-6
+l=194.345e-6
+model=rppd
+spiceprefix=X
+b=0
+m=1
+}
+C {sg13g2_pr/rppd.sym} 595 -680 0 0 {name=R1
+w=0.5e-6
+l=194.345e-6
+model=rppd
+spiceprefix=X
+b=0
+m=1.2
+}
+C {sg13g2_pr/rppd.sym} 800 -685 0 0 {name=R2
+w=0.5e-6
+l=192.395e-6
+model=rppd
+spiceprefix=X
+b=0
+m=1
+}
+C {launcher.sym} 1181.40625 -918.28125 0 0 {name=h5
+descr="load waves"
+tclcommand="xschem raw_read $netlist_dir/bgr_temp.raw dc"
+}
diff --git a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp.va b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp.va
index 273ee6a0..01fdca43 100644
--- a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp.va
+++ b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp.va
@@ -8,7 +8,7 @@ output electrical out;
input electrical IN1, IN2;
-parameter real gain = 10000; // setting gain to 10 of the differential amplifier
+parameter real gain = 3500; // setting gain to 10 of the differential amplifier
analog begin
diff --git a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp2.va b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp2.va
deleted file mode 100644
index 273ee6a0..00000000
--- a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp2.va
+++ /dev/null
@@ -1,21 +0,0 @@
-// importing libs
-
-`include "discipline.h"
-
-module diff_amp (out, IN1, IN2);
-
-output electrical out;
-
-input electrical IN1, IN2;
-
-parameter real gain = 10000; // setting gain to 10 of the differential amplifier
-
-analog begin
-
- V(out) <+ gain * (V(IN1) - V(IN2));
-
-end
-
-endmodule
-
-
diff --git a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/veriloga_tbs/diff_amp.sym b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/veriloga_tbs/diff_amp.sym
index 11e18e81..90caf663 100644
--- a/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/veriloga_tbs/diff_amp.sym
+++ b/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/veriloga_tbs/diff_amp.sym
@@ -30,7 +30,7 @@ N1 out in1 in2 diff_amp_model
* following line specifies the location for the .osdi file so ngspice can use it.
-pre_osdi /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp2.osdi
+pre_osdi /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp.osdi
.endc