diff --git a/modules/module_4_type_2_PLL/CML_divider/cace/CML_divider.yaml b/modules/module_4_type_2_PLL/CML_divider/cace/CML_divider.yaml new file mode 100644 index 00000000..e0ce793a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/cace/CML_divider.yaml @@ -0,0 +1,115 @@ +#-------------------------------------------------------------- +# CACE circuit characterization file +#-------------------------------------------------------------- + +name: CML_divider +description: Current mode logic divider +PDK: ihp-sg13g2 + +cace_format: 5.2 + +authorship: + designer: Phillip F. Baade-Pedersen + company: IHP + creation_date: + license: Apache 2.0 + +paths: + root: .. + schematic: xschem/ + netlist: xschem/simulations + documentation: docs + +pins: + VDD: + description: Positive analog power supply + type: power + direction: inout + Vmin: 0.8 + Vmax: 1.6 + Vinplus: + description: Positive Input + type: signal + direction: input + Vinminus: + description: Negative Input + type: signal + direction: input + +default_conditions: + vdd: + description: Analog power supply voltage + display: Vdd + unit: V + typical: 1.2 + corner: + description: Process corner + display: Corner + typical: tt + temperature: + description: Ambient temperature + display: Temp + unit: °C + typical: 27 + +parameters: + ac_params: + description: Frequency characterization of the divider + display: CML divider frequency response + spec: + frequency: + display: Frequency + description: Output frequency of the divider + unit: GHz + minimum: + value: 4.3 + typical: + value: 5.0 + maximum: + value: 5.2 + amplitude: + display: Amplitude + description: Differential output amplitude (half swing) + unit: V + minimum: + value: 0.2 + typical: + value: 0.4 + maximum: + value: 0.6 + voltage_swing: + display: Voltage swing + description: Differential peak-to-peak output swing + unit: V + minimum: + value: 0.4 + typical: + value: 0.8 + maximum: + value: 1.2 + tool: + ngspice: + template: CML_core_tb.sch + format: ascii + suffix: .data + variables: [time, vo_diff] + script: freq.py + script_variables: [frequency, amplitude, voltage_swing] + plot: + vo_diff_vs_time: + type: xyplot + xaxis: time + yaxis: vo_diff + conditions: + vdd: + minimum: 0.8 + typical: 1.2 + maximum: 1.6 + corner: + enumerate: [tt, ff, ss] + temperature: + minimum: -40 + typical: 27 + maximum: 80 + + diff --git a/modules/module_4_type_2_PLL/CML_divider/cace/scripts/__pycache__/freq.cpython-310.pyc b/modules/module_4_type_2_PLL/CML_divider/cace/scripts/__pycache__/freq.cpython-310.pyc new file mode 100644 index 00000000..6523f1ed Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/cace/scripts/__pycache__/freq.cpython-310.pyc differ diff --git a/modules/module_4_type_2_PLL/CML_divider/cace/scripts/freq.py b/modules/module_4_type_2_PLL/CML_divider/cace/scripts/freq.py new file mode 100644 index 00000000..3c457ffe --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/cace/scripts/freq.py @@ -0,0 +1,41 @@ +from typing import Any +import numpy as np + +def postprocess(results: dict[str, list], conditions: dict[str, Any]) -> dict[str, list]: + # Extract waveform + t = np.array(results['time']) + v = np.array(results['vo_diff']) + + if len(t) < 2 or len(v) == 0: + return { + 'frequency': [0.0], + 'amplitude': [0.0], + 'voltage_swing': [0.0] + } + + # --- Compute sampling frequency --- + dt = np.mean(np.diff(t)) + fs = 1.0 / dt + + # --- FFT to find main tone --- + Y = np.fft.fft(v - np.mean(v)) # remove DC + freqs = np.fft.fftfreq(len(Y), d=dt) + + # Use positive frequencies only + mask = freqs > 0 + freqs = freqs[mask] + Y = np.abs(Y[mask]) + + freq_peak = freqs[np.argmax(Y)] + + # --- Compute amplitude and voltage swing --- + v_max = np.max(v) + v_min = np.min(v) + voltage_swing = v_max - v_min + amplitude = voltage_swing / 2.0 + + return { + 'frequency': [freq_peak], + 'amplitude': [amplitude], + 'voltage_swing': [voltage_swing] + } diff --git a/modules/module_4_type_2_PLL/CML_divider/cace/templates/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/cace/templates/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/cace/templates/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/cace/templates/xschemrc b/modules/module_4_type_2_PLL/CML_divider/cace/templates/xschemrc new file mode 100644 index 00000000..36e35c71 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/cace/templates/xschemrc @@ -0,0 +1 @@ +source [file dirname [info script]]/../../xschem/xschemrc diff --git a/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider.md b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider.md new file mode 100644 index 00000000..06216088 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider.md @@ -0,0 +1,54 @@ +# CML_divider + +- Description: Current mode logic divider +- PDK: ihp-sg13g2 + +## Authorship + +- Designer: Phillip F. Baade-Pedersen +- Company: IHP +- Created: None +- License: Apache 2.0 +- Last modified: None + +## Pins + +- VDD + + Description: Positive analog power supply + + Type: power + + Direction: inout + + Vmin: 0.8 + + Vmax: 1.6 +- Vinplus + + Description: Positive Input + + Type: signal + + Direction: input +- Vinminus + + Description: Negative Input + + Type: signal + + Direction: input + +## Default Conditions + +- vdd + + Description: Analog power supply voltage + + Display: Vdd + + Unit: V + + Typical: 1.2 +- corner + + Description: Process corner + + Display: Corner + + Typical: tt +- temperature + + Description: Ambient temperature + + Display: Temp + + Unit: °C + + Typical: 27 + +## Symbol + +![Symbol of CML_divider](CML_divider_symbol.svg) + +## Schematic + +![Schematic of CML_divider](CML_divider_schematic.svg) diff --git a/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider/schematic/frequency.png b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider/schematic/frequency.png new file mode 100644 index 00000000..e4b0a21a Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider/schematic/frequency.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider/schematic/vo_diff_vs_time.png b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider/schematic/vo_diff_vs_time.png new file mode 100644 index 00000000..b3049fae Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider/schematic/vo_diff_vs_time.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider_schematic.md b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider_schematic.md new file mode 100644 index 00000000..51ae9078 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider_schematic.md @@ -0,0 +1,17 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Frequency | ngspice | frequency | 4.3 GHz | 4.722 GHz | 5.0 GHz | 4.722 GHz | 5.2 GHz | 4.722 GHz | Pass ✅ | +| Amplitude | ngspice | amplitude | 0.2 V | 0.315 V | 0.4 V | 0.382 V | 0.6 V | 0.429 V | Pass ✅ | +| Voltage swing | ngspice | voltage_swing | 0.4 V | 0.629 V | 0.8 V | 0.763 V | 1.2 V | 0.857 V | Pass ✅ | + + +## Plots + +## vo_diff_vs_time + +![vo_diff_vs_time](./CML_divider/schematic/vo_diff_vs_time.png) diff --git a/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider_schematic.svg b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider_schematic.svg new file mode 100644 index 00000000..5de9a6fa --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider_schematic.svg @@ -0,0 +1,160 @@ + + + + diff --git a/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider_symbol.svg b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider_symbol.svg new file mode 100644 index 00000000..5de9a6fa --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/docs/CML_divider_symbol.svg @@ -0,0 +1,160 @@ + + + + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/frequency.png new file mode 100644 index 00000000..cfba68b3 Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/CML_core_tb.sch new file mode 100644 index 00000000..85d54eb2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/CML_core_tb_0.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..f3e24e04 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/run_0 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..1bf3ee60 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time,vo_diff,frequency +run_0,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",4.722 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..b1f49411 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time | vo_diff | frequency | +| :-- | ---: | ------: | --------: | +| run_0 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 4.722 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/summary.md new file mode 100644 index 00000000..04de8373 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-12/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | ​ | ​ | ​ | 0.000 GHz | ​ | ​ | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/frequency.png new file mode 100644 index 00000000..cfba68b3 Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/CML_core_tb.sch new file mode 100644 index 00000000..222d7572 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/CML_core_tb_0.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..3df3e27f --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/run_0 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..1bf3ee60 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time,vo_diff,frequency +run_0,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",4.722 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..b1f49411 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time | vo_diff | frequency | +| :-- | ---: | ------: | --------: | +| run_0 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 4.722 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/summary.md new file mode 100644 index 00000000..04de8373 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-37-39/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | ​ | ​ | ​ | 0.000 GHz | ​ | ​ | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/frequency.png new file mode 100644 index 00000000..e3ac31d9 Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/CML_core_tb.sch new file mode 100644 index 00000000..29e3c824 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/CML_core_tb_0.data new file mode 100644 index 00000000..4cb5b399 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.110742996065e-01 + 1.728000000000e-10 -1.869505717284e-01 + 1.828000000000e-10 -3.563037101706e-02 + 1.928000000000e-10 1.056708524540e-01 + 2.028000000000e-10 2.100393804445e-01 + 2.128000000000e-10 2.784249297688e-01 + 2.228000000000e-10 3.224310579067e-01 + 2.328000000000e-10 3.548600651170e-01 + 2.428000000000e-10 3.792482005271e-01 + 2.528000000000e-10 3.740820324036e-01 + 2.628000000000e-10 3.079440308227e-01 + 2.728000000000e-10 1.813826171807e-01 + 2.828000000000e-10 2.923027813912e-02 + 2.928000000000e-10 -1.118282325615e-01 + 3.028000000000e-10 -2.157337068367e-01 + 3.128000000000e-10 -2.829033176767e-01 + 3.228000000000e-10 -3.260714502323e-01 + 3.328000000000e-10 -3.577361248183e-01 + 3.428000000000e-10 -3.819104006606e-01 + 3.528000000000e-10 -3.764730474160e-01 + 3.628000000000e-10 -3.102968359246e-01 + 3.728000000000e-10 -1.832608913655e-01 + 3.828000000000e-10 -3.084931437320e-02 + 3.928000000000e-10 1.106163095990e-01 + 4.028000000000e-10 2.145714971977e-01 + 4.128000000000e-10 2.819937231053e-01 + 4.228000000000e-10 3.251740998910e-01 + 4.328000000000e-10 3.570946969464e-01 + 4.428000000000e-10 3.813004444382e-01 + 4.528000000000e-10 3.761230596147e-01 + 4.628000000000e-10 3.099646053412e-01 + 4.728000000000e-10 1.831473345022e-01 + 4.828000000000e-10 3.069401022130e-02 + 4.928000000000e-10 -1.106258411343e-01 + 5.028000000000e-10 -2.146793601179e-01 + 5.128000000000e-10 -2.820035552799e-01 + 5.228000000000e-10 -3.252909243829e-01 + 5.328000000000e-10 -3.570986338553e-01 + 5.428000000000e-10 -3.813904658256e-01 + 5.528000000000e-10 -3.760889514061e-01 + 5.628000000000e-10 -3.100114096943e-01 + 5.728000000000e-10 -1.830827247194e-01 + 5.828000000000e-10 -3.072480545922e-02 + 5.928000000000e-10 1.106906463094e-01 + 6.028000000000e-10 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8.528000000000e-10 3.761324372121e-01 + 8.628000000000e-10 3.099775475493e-01 + 8.728000000000e-10 1.831274535707e-01 + 8.828000000000e-10 3.069175078476e-02 + 8.928000000000e-10 -1.106491559136e-01 + 9.028000000000e-10 -2.146821655528e-01 + 9.128000000000e-10 -2.820218639330e-01 + 9.228000000000e-10 -3.252864642203e-01 + 9.328000000000e-10 -3.571122611941e-01 + 9.428000000000e-10 -3.813854215351e-01 + 9.528000000000e-10 -3.761024723822e-01 + 9.628000000000e-10 -3.100075395903e-01 + 9.728000000000e-10 -1.830975404653e-01 + 9.828000000000e-10 -3.072097080048e-02 + 9.928000000000e-10 1.106770531472e-01 + 1.000000000000e-09 1.895325033433e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/conditions.yaml new file mode 100644 index 00000000..b67ea4fd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_00 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/CML_core_tb.sch new file mode 100644 index 00000000..e145cc80 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/CML_core_tb_1.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/CML_core_tb_1.data new file mode 100644 index 00000000..b332ca2c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/CML_core_tb_1.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162797108708e-01 + 1.728000000000e-10 -1.875883768906e-01 + 1.828000000000e-10 -3.217177564589e-02 + 1.928000000000e-10 1.118453904517e-01 + 2.028000000000e-10 2.178869753922e-01 + 2.128000000000e-10 2.869187499571e-01 + 2.228000000000e-10 3.311831063176e-01 + 2.328000000000e-10 3.637965093552e-01 + 2.428000000000e-10 3.884475585753e-01 + 2.528000000000e-10 3.831703446637e-01 + 2.628000000000e-10 3.149426000366e-01 + 2.728000000000e-10 1.840825734866e-01 + 2.828000000000e-10 2.786370536806e-02 + 2.928000000000e-10 -1.159899232258e-01 + 3.028000000000e-10 -2.217323928122e-01 + 3.128000000000e-10 -2.897841810826e-01 + 3.228000000000e-10 -3.334256487170e-01 + 3.328000000000e-10 -3.654508602495e-01 + 3.428000000000e-10 -3.900407544937e-01 + 3.528000000000e-10 -3.846189534315e-01 + 3.628000000000e-10 -3.164922452622e-01 + 3.728000000000e-10 -1.853182634851e-01 + 3.828000000000e-10 -2.898615964086e-02 + 3.928000000000e-10 1.151710782521e-01 + 4.028000000000e-10 2.209054309263e-01 + 4.128000000000e-10 2.891817322742e-01 + 4.228000000000e-10 3.328077516782e-01 + 4.328000000000e-10 3.650515838921e-01 + 4.428000000000e-10 3.896233583948e-01 + 4.528000000000e-10 3.844074302627e-01 + 4.628000000000e-10 3.162448842688e-01 + 4.728000000000e-10 1.852475068120e-01 + 4.828000000000e-10 2.884623360652e-02 + 4.928000000000e-10 -1.151788252337e-01 + 5.028000000000e-10 -2.210147130581e-01 + 5.128000000000e-10 -2.891872658193e-01 + 5.228000000000e-10 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7.728000000000e-10 -1.852023753321e-01 + 7.828000000000e-10 -2.888743165850e-02 + 7.928000000000e-10 1.152240030808e-01 + 8.028000000000e-10 2.209771419031e-01 + 8.128000000000e-10 2.892295361788e-01 + 8.228000000000e-10 3.328747680971e-01 + 8.328000000000e-10 3.650871456099e-01 + 8.428000000000e-10 3.896701175780e-01 + 8.528000000000e-10 3.844156912621e-01 + 8.628000000000e-10 3.162637401476e-01 + 8.728000000000e-10 1.852363586492e-01 + 8.828000000000e-10 2.885434112124e-02 + 8.928000000000e-10 -1.151920978903e-01 + 9.028000000000e-10 -2.210084087345e-01 + 9.128000000000e-10 -2.891984388712e-01 + 9.228000000000e-10 -3.329064027155e-01 + 9.328000000000e-10 -3.650560988894e-01 + 9.428000000000e-10 -3.897007143418e-01 + 9.528000000000e-10 -3.843858173814e-01 + 9.628000000000e-10 -3.162935974835e-01 + 9.728000000000e-10 -1.852064424274e-01 + 9.828000000000e-10 -2.888350905479e-02 + 9.928000000000e-10 1.152199079204e-01 + 1.000000000000e-09 1.954791142410e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/conditions.yaml new file mode 100644 index 00000000..4fba8c93 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 1 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_01 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/CML_core_tb.sch new file mode 100644 index 00000000..ce26b8ed --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/CML_core_tb_2.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/CML_core_tb_2.data new file mode 100644 index 00000000..6dccbfd6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/CML_core_tb_2.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.914571027454e-01 + 1.728000000000e-10 -1.780117263272e-01 + 1.828000000000e-10 -3.802564096594e-02 + 1.928000000000e-10 9.479025580261e-02 + 2.028000000000e-10 1.961220444980e-01 + 2.128000000000e-10 2.643669322964e-01 + 2.228000000000e-10 3.071498875260e-01 + 2.328000000000e-10 3.351667250191e-01 + 2.428000000000e-10 3.529478733093e-01 + 2.528000000000e-10 3.439767079911e-01 + 2.628000000000e-10 2.827109934029e-01 + 2.728000000000e-10 1.683025534555e-01 + 2.828000000000e-10 2.843266655337e-02 + 2.928000000000e-10 -1.036223502576e-01 + 3.028000000000e-10 -2.042863713809e-01 + 3.128000000000e-10 -2.713818104821e-01 + 3.228000000000e-10 -3.132717880322e-01 + 3.328000000000e-10 -3.402903477971e-01 + 3.428000000000e-10 -3.574262556597e-01 + 3.528000000000e-10 -3.476240566503e-01 + 3.628000000000e-10 -2.857203755187e-01 + 3.728000000000e-10 -1.703849236420e-01 + 3.828000000000e-10 -2.994825869373e-02 + 3.928000000000e-10 1.026817167876e-01 + 4.028000000000e-10 2.034750084544e-01 + 4.128000000000e-10 2.707812081585e-01 + 4.228000000000e-10 3.126503625184e-01 + 4.328000000000e-10 3.399043734480e-01 + 4.428000000000e-10 3.571021595385e-01 + 4.528000000000e-10 3.475896983741e-01 + 4.628000000000e-10 2.857411927694e-01 + 4.728000000000e-10 1.706053611761e-01 + 4.828000000000e-10 3.010795594348e-02 + 4.928000000000e-10 -1.024135388755e-01 + 5.028000000000e-10 -2.033190471438e-01 + 5.128000000000e-10 -2.705615444577e-01 + 5.228000000000e-10 -3.125558523975e-01 + 5.328000000000e-10 -3.397330193449e-01 + 5.428000000000e-10 -3.570354300338e-01 + 5.528000000000e-10 -3.474353611027e-01 + 5.628000000000e-10 -2.856876769732e-01 + 5.728000000000e-10 -1.704760895977e-01 + 5.828000000000e-10 -3.008641427314e-02 + 5.928000000000e-10 1.025087996136e-01 + 6.028000000000e-10 2.033209986443e-01 + 6.128000000000e-10 2.706412375819e-01 + 6.228000000000e-10 3.125457575810e-01 + 6.328000000000e-10 3.398008382665e-01 + 6.428000000000e-10 3.570145583479e-01 + 6.528000000000e-10 3.474888598072e-01 + 6.628000000000e-10 2.856551852535e-01 + 6.728000000000e-10 1.705188293935e-01 + 6.828000000000e-10 3.004736925580e-02 + 6.928000000000e-10 -1.024728514478e-01 + 7.028000000000e-10 -2.033602328622e-01 + 7.128000000000e-10 -2.706061106716e-01 + 7.228000000000e-10 -3.125843283316e-01 + 7.328000000000e-10 -3.397655433228e-01 + 7.428000000000e-10 -3.570523646632e-01 + 7.528000000000e-10 -3.474554820929e-01 + 7.628000000000e-10 -2.856929985560e-01 + 7.728000000000e-10 -1.704859799650e-01 + 7.828000000000e-10 -3.008383757896e-02 + 7.928000000000e-10 1.025039608177e-01 + 8.028000000000e-10 2.033261442763e-01 + 8.128000000000e-10 2.706371082838e-01 + 8.228000000000e-10 3.125504649737e-01 + 8.328000000000e-10 3.397966066528e-01 + 8.428000000000e-10 3.570198965640e-01 + 8.528000000000e-10 3.474857187206e-01 + 8.628000000000e-10 2.856614378232e-01 + 8.728000000000e-10 1.705164607562e-01 + 8.828000000000e-10 3.005354621749e-02 + 8.928000000000e-10 -1.024749769036e-01 + 9.028000000000e-10 -2.033548454455e-01 + 9.128000000000e-10 -2.706087008930e-01 + 9.228000000000e-10 -3.125792630790e-01 + 9.328000000000e-10 -3.397683901773e-01 + 9.428000000000e-10 -3.570478314069e-01 + 9.528000000000e-10 -3.474583427153e-01 + 9.628000000000e-10 -2.856887110961e-01 + 9.728000000000e-10 -1.704892548593e-01 + 9.828000000000e-10 -3.008001356704e-02 + 9.928000000000e-10 1.025005080892e-01 + 1.000000000000e-09 1.786649040194e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/conditions.yaml new file mode 100644 index 00000000..f674196c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 2 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_02 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/CML_core_tb.sch new file mode 100644 index 00000000..35de4f4a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/CML_core_tb_3.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/CML_core_tb_3.data new file mode 100644 index 00000000..0cc77d23 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/CML_core_tb_3.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.958574299710e-01 + 1.728000000000e-10 -1.791897212785e-01 + 1.828000000000e-10 -3.599075048614e-02 + 1.928000000000e-10 9.946703268478e-02 + 2.028000000000e-10 2.032502871016e-01 + 2.128000000000e-10 2.733994094958e-01 + 2.228000000000e-10 3.172845988123e-01 + 2.328000000000e-10 3.455609123691e-01 + 2.428000000000e-10 3.630923957132e-01 + 2.528000000000e-10 3.534419450967e-01 + 2.628000000000e-10 2.903663934708e-01 + 2.728000000000e-10 1.726743312860e-01 + 2.828000000000e-10 2.930291139472e-02 + 2.928000000000e-10 -1.057514312075e-01 + 3.028000000000e-10 -2.091913834589e-01 + 3.128000000000e-10 -2.784696434768e-01 + 3.228000000000e-10 -3.216873931074e-01 + 3.328000000000e-10 -3.491870426412e-01 + 3.428000000000e-10 -3.662894191498e-01 + 3.528000000000e-10 -3.560374131806e-01 + 3.628000000000e-10 -2.925719059469e-01 + 3.728000000000e-10 -1.742159787839e-01 + 3.828000000000e-10 -3.049391935212e-02 + 3.928000000000e-10 1.049756016137e-01 + 4.028000000000e-10 2.084672065617e-01 + 4.128000000000e-10 2.779301238417e-01 + 4.228000000000e-10 3.211180618030e-01 + 4.328000000000e-10 3.488255023686e-01 + 4.428000000000e-10 3.659572542624e-01 + 4.528000000000e-10 3.559493947967e-01 + 4.628000000000e-10 2.925058094407e-01 + 4.728000000000e-10 1.743267017008e-01 + 4.828000000000e-10 3.054314172764e-02 + 4.928000000000e-10 -1.048175245910e-01 + 5.028000000000e-10 -2.084096499031e-01 + 5.128000000000e-10 -2.777998408986e-01 + 5.228000000000e-10 -3.210985617265e-01 + 5.328000000000e-10 -3.487226120056e-01 + 5.428000000000e-10 -3.659481451181e-01 + 5.528000000000e-10 -3.558482598240e-01 + 5.628000000000e-10 -2.924942070749e-01 + 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2.778603942564e-01 + 8.228000000000e-10 3.210827582845e-01 + 8.328000000000e-10 3.487751488045e-01 + 8.428000000000e-10 3.659266824704e-01 + 8.528000000000e-10 3.558925702991e-01 + 8.628000000000e-10 2.924671830422e-01 + 8.728000000000e-10 1.742711856894e-01 + 8.828000000000e-10 3.051417003050e-02 + 8.928000000000e-10 -1.048591994973e-01 + 9.028000000000e-10 -2.084299430076e-01 + 9.128000000000e-10 -2.778331783696e-01 + 9.228000000000e-10 -3.211104359655e-01 + 9.328000000000e-10 -3.487480244246e-01 + 9.428000000000e-10 -3.659535267111e-01 + 9.528000000000e-10 -3.558663548813e-01 + 9.628000000000e-10 -2.924933270906e-01 + 9.728000000000e-10 -1.742451324195e-01 + 9.828000000000e-10 -3.053963678018e-02 + 9.928000000000e-10 1.048836196344e-01 + 1.000000000000e-09 1.830293824662e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/conditions.yaml new file mode 100644 index 00000000..8bfe7921 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 3 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_03 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/CML_core_tb.sch new file mode 100644 index 00000000..98adc519 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/CML_core_tb_4.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/CML_core_tb_4.data new file mode 100644 index 00000000..38ffd8bf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/CML_core_tb_4.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.689355033953e-01 + 1.728000000000e-10 -1.691728954892e-01 + 1.828000000000e-10 -4.423302134033e-02 + 1.928000000000e-10 7.663444207075e-02 + 2.028000000000e-10 1.714764750752e-01 + 2.128000000000e-10 2.368219567798e-01 + 2.228000000000e-10 2.772768132445e-01 + 2.328000000000e-10 3.013675537348e-01 + 2.428000000000e-10 3.140706479520e-01 + 2.528000000000e-10 3.038549886105e-01 + 2.628000000000e-10 2.508404086347e-01 + 2.728000000000e-10 1.528360605683e-01 + 2.828000000000e-10 3.040034809293e-02 + 2.928000000000e-10 -8.785381094258e-02 + 3.028000000000e-10 -1.808734961109e-01 + 3.128000000000e-10 -2.445795528199e-01 + 3.228000000000e-10 -2.838354337528e-01 + 3.328000000000e-10 -3.065800962400e-01 + 3.428000000000e-10 -3.181767360109e-01 + 3.528000000000e-10 -3.065752663659e-01 + 3.628000000000e-10 -2.523878800401e-01 + 3.728000000000e-10 -1.531173668737e-01 + 3.828000000000e-10 -2.992055538556e-02 + 3.928000000000e-10 8.900435641641e-02 + 4.028000000000e-10 1.821756238512e-01 + 4.128000000000e-10 2.460123650690e-01 + 4.228000000000e-10 2.851182310100e-01 + 4.328000000000e-10 3.079291995556e-01 + 4.428000000000e-10 3.194129911462e-01 + 4.528000000000e-10 3.078915366323e-01 + 4.628000000000e-10 2.535144344421e-01 + 4.728000000000e-10 1.541542026196e-01 + 4.828000000000e-10 3.063651583090e-02 + 4.928000000000e-10 -8.839161491074e-02 + 5.028000000000e-10 -1.817999659778e-01 + 5.128000000000e-10 -2.456456661989e-01 + 5.228000000000e-10 -2.849195350591e-01 + 5.328000000000e-10 -3.077091828990e-01 + 5.428000000000e-10 -3.193505374448e-01 + 5.528000000000e-10 -3.078081521678e-01 + 5.628000000000e-10 -2.535787813503e-01 + 5.728000000000e-10 -1.541764927596e-01 + 5.828000000000e-10 -3.077048554081e-02 + 5.928000000000e-10 8.832790620553e-02 + 6.028000000000e-10 1.816551916875e-01 + 6.128000000000e-10 2.455879975104e-01 + 6.228000000000e-10 2.847911932982e-01 + 6.328000000000e-10 3.076677363016e-01 + 6.428000000000e-10 3.192371229053e-01 + 6.528000000000e-10 3.077778412262e-01 + 6.628000000000e-10 2.534819327505e-01 + 6.728000000000e-10 1.541683138663e-01 + 6.828000000000e-10 3.070155435378e-02 + 6.928000000000e-10 -8.831320560130e-02 + 7.028000000000e-10 -1.817038543937e-01 + 7.128000000000e-10 -2.455619958387e-01 + 7.228000000000e-10 -2.848320347671e-01 + 7.328000000000e-10 -3.076358698550e-01 + 7.428000000000e-10 -3.192710667609e-01 + 7.528000000000e-10 -3.077409972388e-01 + 7.628000000000e-10 -2.535098012890e-01 + 7.728000000000e-10 -1.541282589474e-01 + 7.828000000000e-10 -3.072672689244e-02 + 7.928000000000e-10 8.835148526653e-02 + 8.028000000000e-10 1.816795669555e-01 + 8.128000000000e-10 2.455984246601e-01 + 8.228000000000e-10 2.848062931006e-01 + 8.328000000000e-10 3.076705916890e-01 + 8.428000000000e-10 3.192450073559e-01 + 8.528000000000e-10 3.077736319697e-01 + 8.628000000000e-10 2.534831121829e-01 + 8.728000000000e-10 1.541590953584e-01 + 8.828000000000e-10 3.069946612700e-02 + 8.928000000000e-10 -8.832341199891e-02 + 9.028000000000e-10 -1.817063952021e-01 + 9.128000000000e-10 -2.455714256322e-01 + 9.228000000000e-10 -2.848333922463e-01 + 9.328000000000e-10 -3.076440936715e-01 + 9.428000000000e-10 -3.192716274515e-01 + 9.528000000000e-10 -3.077481608676e-01 + 9.628000000000e-10 -2.535093614867e-01 + 9.728000000000e-10 -1.541340765567e-01 + 9.828000000000e-10 -3.072486745089e-02 + 9.928000000000e-10 8.834711873249e-02 + 1.000000000000e-09 1.586239577417e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/conditions.yaml new file mode 100644 index 00000000..66eb1871 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 4 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_04 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/CML_core_tb.sch new file mode 100644 index 00000000..459472a8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/CML_core_tb_5.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/CML_core_tb_5.data new file mode 100644 index 00000000..b4ed17dd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/CML_core_tb_5.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.722799425151e-01 + 1.728000000000e-10 -1.701277707773e-01 + 1.828000000000e-10 -4.252496989706e-02 + 1.928000000000e-10 8.092536896213e-02 + 2.028000000000e-10 1.785199933375e-01 + 2.128000000000e-10 2.463984181452e-01 + 2.228000000000e-10 2.885755113271e-01 + 2.328000000000e-10 3.131967480955e-01 + 2.428000000000e-10 3.255285716483e-01 + 2.528000000000e-10 3.143820454109e-01 + 2.628000000000e-10 2.595824958850e-01 + 2.728000000000e-10 1.585585813323e-01 + 2.828000000000e-10 3.254606172598e-02 + 2.928000000000e-10 -8.921916265210e-02 + 3.028000000000e-10 -1.857143058967e-01 + 3.128000000000e-10 -2.524588707093e-01 + 3.228000000000e-10 -2.937876617757e-01 + 3.328000000000e-10 -3.173655773168e-01 + 3.428000000000e-10 -3.288566343508e-01 + 3.528000000000e-10 -3.166123605828e-01 + 3.628000000000e-10 -2.609360611345e-01 + 3.728000000000e-10 -1.589355414621e-01 + 3.828000000000e-10 -3.237621747627e-02 + 3.928000000000e-10 8.990939637816e-02 + 4.028000000000e-10 1.864994737191e-01 + 4.128000000000e-10 2.533636311879e-01 + 4.228000000000e-10 2.945633129641e-01 + 4.328000000000e-10 3.182197832362e-01 + 4.428000000000e-10 3.296245618008e-01 + 4.528000000000e-10 3.174841059207e-01 + 4.628000000000e-10 2.616780558587e-01 + 4.728000000000e-10 1.596622360522e-01 + 4.828000000000e-10 3.287681921596e-02 + 4.928000000000e-10 -8.943999963453e-02 + 5.028000000000e-10 -1.862066308093e-01 + 5.128000000000e-10 -2.530527908612e-01 + 5.228000000000e-10 -2.943931136832e-01 + 5.328000000000e-10 -3.180152021024e-01 + 5.428000000000e-10 -3.295545667130e-01 + 5.528000000000e-10 -3.173812952412e-01 + 5.628000000000e-10 -2.617027726155e-01 + 5.728000000000e-10 -1.596411992093e-01 + 5.828000000000e-10 -3.295895028258e-02 + 5.928000000000e-10 8.942267434718e-02 + 6.028000000000e-10 1.861105403656e-01 + 6.128000000000e-10 2.530344325895e-01 + 6.228000000000e-10 2.943051008579e-01 + 6.328000000000e-10 3.180051485103e-01 + 6.428000000000e-10 3.294737915539e-01 + 6.528000000000e-10 3.173744791022e-01 + 6.628000000000e-10 2.616291881364e-01 + 6.728000000000e-10 1.596450333001e-01 + 6.828000000000e-10 3.290088244348e-02 + 6.928000000000e-10 -8.940659470005e-02 + 7.028000000000e-10 -1.861562133447e-01 + 7.128000000000e-10 -2.530116656482e-01 + 7.228000000000e-10 -2.943454309811e-01 + 7.328000000000e-10 -3.179780561670e-01 + 7.428000000000e-10 -3.295087969733e-01 + 7.528000000000e-10 -3.173438661274e-01 + 7.628000000000e-10 -2.616591955397e-01 + 7.728000000000e-10 -1.596115565426e-01 + 7.828000000000e-10 -3.292790237402e-02 + 7.928000000000e-10 8.943927261705e-02 + 8.028000000000e-10 1.861310420114e-01 + 8.128000000000e-10 2.530433655174e-01 + 8.228000000000e-10 2.943195630770e-01 + 8.328000000000e-10 3.180088285378e-01 + 8.428000000000e-10 3.294832118435e-01 + 8.528000000000e-10 3.173732295072e-01 + 8.628000000000e-10 2.616337486722e-01 + 8.728000000000e-10 1.596399004289e-01 + 8.828000000000e-10 3.290244884503e-02 + 8.928000000000e-10 -8.941301350766e-02 + 9.028000000000e-10 -1.861557185261e-01 + 9.128000000000e-10 -2.530180139920e-01 + 9.228000000000e-10 -2.943444772306e-01 + 9.328000000000e-10 -3.179838696148e-01 + 9.428000000000e-10 -3.295076633013e-01 + 9.528000000000e-10 -3.173492560727e-01 + 9.628000000000e-10 -2.616577755083e-01 + 9.728000000000e-10 -1.596163947717e-01 + 9.828000000000e-10 -3.292583900074e-02 + 9.928000000000e-10 8.943518431692e-02 + 1.000000000000e-09 1.621529465729e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/conditions.yaml new file mode 100644 index 00000000..22e861a7 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 5 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_05 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/CML_core_tb.sch new file mode 100644 index 00000000..4e78f7cb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/CML_core_tb_6.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/CML_core_tb_6.data new file mode 100644 index 00000000..6b24d1d6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/CML_core_tb_6.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.622644182692e-01 + 1.728000000000e-10 -1.962653738736e-01 + 1.828000000000e-10 -5.712895575235e-03 + 1.928000000000e-10 1.510345047594e-01 + 2.028000000000e-10 2.432775412534e-01 + 2.128000000000e-10 2.772000132926e-01 + 2.228000000000e-10 3.161630086256e-01 + 2.328000000000e-10 3.654121904616e-01 + 2.428000000000e-10 4.070200809677e-01 + 2.528000000000e-10 4.211809118313e-01 + 2.628000000000e-10 3.552666659990e-01 + 2.728000000000e-10 1.954111420719e-01 + 2.828000000000e-10 7.499275151763e-03 + 2.928000000000e-10 -1.488912332472e-01 + 3.028000000000e-10 -2.420325529570e-01 + 3.128000000000e-10 -2.768171400503e-01 + 3.228000000000e-10 -3.164103191401e-01 + 3.328000000000e-10 -3.656815561297e-01 + 3.428000000000e-10 -4.072561733660e-01 + 3.528000000000e-10 -4.210637971044e-01 + 3.628000000000e-10 -3.548415521036e-01 + 3.728000000000e-10 -1.946286859654e-01 + 3.828000000000e-10 -6.746438981043e-03 + 3.928000000000e-10 1.496127957227e-01 + 4.028000000000e-10 2.425057762271e-01 + 4.128000000000e-10 2.772590268750e-01 + 4.228000000000e-10 3.167075169816e-01 + 4.328000000000e-10 3.660182242119e-01 + 4.428000000000e-10 4.074726111052e-01 + 4.528000000000e-10 4.212975956202e-01 + 4.628000000000e-10 3.549573822535e-01 + 4.728000000000e-10 1.947835560361e-01 + 4.828000000000e-10 6.801482567115e-03 + 4.928000000000e-10 -1.495086456760e-01 + 5.028000000000e-10 -2.424863730465e-01 + 5.128000000000e-10 -2.771744431737e-01 + 5.228000000000e-10 -3.166940000076e-01 + 5.328000000000e-10 -3.659398771497e-01 + 5.428000000000e-10 -4.074689465730e-01 + 5.528000000000e-10 -4.212394549000e-01 + 5.628000000000e-10 -3.549741510035e-01 + 5.728000000000e-10 -1.947436351784e-01 + 5.828000000000e-10 -6.830080160870e-03 + 5.928000000000e-10 1.495407150967e-01 + 6.028000000000e-10 2.424570295697e-01 + 6.128000000000e-10 2.772066160972e-01 + 6.228000000000e-10 3.166654934082e-01 + 6.328000000000e-10 3.659723864247e-01 + 6.428000000000e-10 4.074416211051e-01 + 6.528000000000e-10 4.212697301261e-01 + 6.628000000000e-10 3.549467093259e-01 + 6.728000000000e-10 1.947718238583e-01 + 6.828000000000e-10 6.800951177238e-03 + 6.928000000000e-10 -1.495148390529e-01 + 7.028000000000e-10 -2.424852043575e-01 + 7.128000000000e-10 -2.771809105751e-01 + 7.228000000000e-10 -3.166930947909e-01 + 7.328000000000e-10 -3.659459016360e-01 + 7.428000000000e-10 -4.074677461547e-01 + 7.528000000000e-10 -4.212442717757e-01 + 7.628000000000e-10 -3.549717520551e-01 + 7.728000000000e-10 -1.947463263521e-01 + 7.828000000000e-10 -6.825916545420e-03 + 7.928000000000e-10 1.495385751436e-01 + 8.028000000000e-10 2.424609931904e-01 + 8.128000000000e-10 2.772040406871e-01 + 8.228000000000e-10 3.166687905139e-01 + 8.328000000000e-10 3.659694951712e-01 + 8.428000000000e-10 4.074447010218e-01 + 8.528000000000e-10 4.212671408417e-01 + 8.628000000000e-10 3.549498827484e-01 + 8.728000000000e-10 1.947689363825e-01 + 8.828000000000e-10 6.803756635994e-03 + 8.928000000000e-10 -1.495176738691e-01 + 9.028000000000e-10 -2.424825342063e-01 + 9.128000000000e-10 -2.771836734306e-01 + 9.228000000000e-10 -3.166902103892e-01 + 9.328000000000e-10 -3.659485359213e-01 + 9.428000000000e-10 -4.074650210911e-01 + 9.528000000000e-10 -4.212469657833e-01 + 9.628000000000e-10 -3.549694058275e-01 + 9.728000000000e-10 -1.947487958951e-01 + 9.828000000000e-10 -6.823236278537e-03 + 9.928000000000e-10 1.495363177485e-01 + 1.000000000000e-09 2.250264100511e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/conditions.yaml new file mode 100644 index 00000000..bb1416c2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 6 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_06 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/CML_core_tb.sch new file mode 100644 index 00000000..f2eb2baf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/CML_core_tb_7.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/CML_core_tb_7.data new file mode 100644 index 00000000..1453012b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/CML_core_tb_7.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.668500025046e-01 + 1.728000000000e-10 -1.978704758130e-01 + 1.828000000000e-10 -3.069550951996e-03 + 1.928000000000e-10 1.561389387989e-01 + 2.028000000000e-10 2.488697408913e-01 + 2.128000000000e-10 2.833379270136e-01 + 2.228000000000e-10 3.221467647695e-01 + 2.328000000000e-10 3.723176028273e-01 + 2.428000000000e-10 4.147931582649e-01 + 2.528000000000e-10 4.286646301121e-01 + 2.628000000000e-10 3.614677855799e-01 + 2.728000000000e-10 1.982726052647e-01 + 2.828000000000e-10 5.580533140739e-03 + 2.928000000000e-10 -1.536551403474e-01 + 3.028000000000e-10 -2.474729097395e-01 + 3.128000000000e-10 -2.827981749211e-01 + 3.228000000000e-10 -3.222400643179e-01 + 3.328000000000e-10 -3.724510578191e-01 + 3.428000000000e-10 -4.149487937489e-01 + 3.528000000000e-10 -4.285094572794e-01 + 3.628000000000e-10 -3.610716711123e-01 + 3.728000000000e-10 -1.975613483211e-01 + 3.828000000000e-10 -4.936396792217e-03 + 3.928000000000e-10 1.542720670721e-01 + 4.028000000000e-10 2.478554934965e-01 + 4.128000000000e-10 2.831768205427e-01 + 4.228000000000e-10 3.224764565266e-01 + 4.328000000000e-10 3.727376628527e-01 + 4.428000000000e-10 4.151128450004e-01 + 4.528000000000e-10 4.287030398326e-01 + 4.628000000000e-10 3.611465460996e-01 + 4.728000000000e-10 1.976871290976e-01 + 4.828000000000e-10 4.962067120498e-03 + 4.928000000000e-10 -1.541857483448e-01 + 5.028000000000e-10 -2.478549856990e-01 + 5.128000000000e-10 -2.831031432303e-01 + 5.228000000000e-10 -3.224786212940e-01 + 5.328000000000e-10 -3.726675199031e-01 + 5.428000000000e-10 -4.151222726988e-01 + 5.528000000000e-10 -4.286496175832e-01 + 5.628000000000e-10 -3.611719348809e-01 + 5.728000000000e-10 -1.976471175954e-01 + 5.828000000000e-10 -4.995016715658e-03 + 5.928000000000e-10 1.542195273485e-01 + 6.028000000000e-10 2.478226151197e-01 + 6.128000000000e-10 2.831371441394e-01 + 6.228000000000e-10 3.224465270882e-01 + 6.328000000000e-10 3.727020829784e-01 + 6.428000000000e-10 4.150919188021e-01 + 6.528000000000e-10 4.286821395136e-01 + 6.628000000000e-10 3.611419365066e-01 + 6.728000000000e-10 1.976777927703e-01 + 6.828000000000e-10 4.963507878799e-03 + 6.928000000000e-10 -1.541913949207e-01 + 7.028000000000e-10 -2.478529800499e-01 + 7.128000000000e-10 -2.831092109235e-01 + 7.228000000000e-10 -3.224762894768e-01 + 7.328000000000e-10 -3.726728668334e-01 + 7.428000000000e-10 -4.151201370880e-01 + 7.528000000000e-10 -4.286543531433e-01 + 7.628000000000e-10 -3.611692599178e-01 + 7.728000000000e-10 -1.976499135935e-01 + 7.828000000000e-10 -4.990471824028e-03 + 7.928000000000e-10 1.542171227717e-01 + 8.028000000000e-10 2.478269854332e-01 + 8.128000000000e-10 2.831343470853e-01 + 8.228000000000e-10 3.224500362551e-01 + 8.328000000000e-10 3.726987138014e-01 + 8.428000000000e-10 4.150953468135e-01 + 8.528000000000e-10 4.286792233560e-01 + 8.628000000000e-10 3.611455588852e-01 + 8.728000000000e-10 1.976743961081e-01 + 8.828000000000e-10 4.966432661841e-03 + 8.928000000000e-10 -1.541946484524e-01 + 9.028000000000e-10 -2.478502288236e-01 + 9.128000000000e-10 -2.831123474050e-01 + 9.228000000000e-10 -3.224731331421e-01 + 9.328000000000e-10 -3.726757720747e-01 + 9.428000000000e-10 -4.151172388981e-01 + 9.528000000000e-10 -4.286573581279e-01 + 9.628000000000e-10 -3.611667698498e-01 + 9.728000000000e-10 -1.976525646923e-01 + 9.828000000000e-10 -4.987471597641e-03 + 9.928000000000e-10 1.542147143463e-01 + 1.000000000000e-09 2.301006397866e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/conditions.yaml new file mode 100644 index 00000000..4de32c6f --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 7 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_07 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/CML_core_tb.sch new file mode 100644 index 00000000..49645a4c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/CML_core_tb_8.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/CML_core_tb_8.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/CML_core_tb_8.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/conditions.yaml new file mode 100644 index 00000000..950867e9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 8 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_08 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/CML_core_tb.sch new file mode 100644 index 00000000..87120267 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/CML_core_tb_9.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/CML_core_tb_9.data new file mode 100644 index 00000000..73c31d13 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/CML_core_tb_9.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.445927026449e-01 + 1.728000000000e-10 -1.889320969581e-01 + 1.828000000000e-10 -5.355234564888e-03 + 1.928000000000e-10 1.489911128277e-01 + 2.028000000000e-10 2.434822449071e-01 + 2.128000000000e-10 2.838702060450e-01 + 2.228000000000e-10 3.202156401988e-01 + 2.328000000000e-10 3.629401474789e-01 + 2.428000000000e-10 3.990998051164e-01 + 2.528000000000e-10 4.099063275401e-01 + 2.628000000000e-10 3.477923521709e-01 + 2.728000000000e-10 1.968519788675e-01 + 2.828000000000e-10 1.493750763318e-02 + 2.928000000000e-10 -1.398437743336e-01 + 3.028000000000e-10 -2.362338093992e-01 + 3.128000000000e-10 -2.782887085314e-01 + 3.228000000000e-10 -3.158910292643e-01 + 3.328000000000e-10 -3.590893499920e-01 + 3.428000000000e-10 -3.957248346768e-01 + 3.528000000000e-10 -4.069627998073e-01 + 3.628000000000e-10 -3.454070734708e-01 + 3.728000000000e-10 -1.948243362004e-01 + 3.828000000000e-10 -1.337926088934e-02 + 3.928000000000e-10 1.411472162204e-01 + 4.028000000000e-10 2.372231231196e-01 + 4.128000000000e-10 2.792284454069e-01 + 4.228000000000e-10 3.166817589057e-01 + 4.328000000000e-10 3.598702175634e-01 + 4.428000000000e-10 3.963375250752e-01 + 4.528000000000e-10 4.074753309124e-01 + 4.628000000000e-10 3.456854225481e-01 + 4.728000000000e-10 1.950177434222e-01 + 4.828000000000e-10 1.342430394201e-02 + 4.928000000000e-10 -1.410850608466e-01 + 5.028000000000e-10 -2.372286880899e-01 + 5.128000000000e-10 -2.791659662153e-01 + 5.228000000000e-10 -3.166689293508e-01 + 5.328000000000e-10 -3.598026374101e-01 + 5.428000000000e-10 -3.963331138013e-01 + 5.528000000000e-10 -4.074316676804e-01 + 5.628000000000e-10 -3.457088001737e-01 + 5.728000000000e-10 -1.950000158899e-01 + 5.828000000000e-10 -1.346504722293e-02 + 5.928000000000e-10 1.410957635246e-01 + 6.028000000000e-10 2.371909425038e-01 + 6.128000000000e-10 2.791817404178e-01 + 6.228000000000e-10 3.166356138828e-01 + 6.328000000000e-10 3.598203377806e-01 + 6.428000000000e-10 3.963033609435e-01 + 6.528000000000e-10 4.074499160221e-01 + 6.628000000000e-10 3.456826167292e-01 + 6.728000000000e-10 1.950190841630e-01 + 6.828000000000e-10 1.343803454206e-02 + 6.928000000000e-10 -1.410764950259e-01 + 7.028000000000e-10 -2.372163265848e-01 + 7.128000000000e-10 -2.791624229651e-01 + 7.228000000000e-10 -3.166599225368e-01 + 7.328000000000e-10 -3.598002455584e-01 + 7.428000000000e-10 -3.963259615583e-01 + 7.528000000000e-10 -4.074304662079e-01 + 7.628000000000e-10 -3.457033629648e-01 + 7.728000000000e-10 -1.949983704767e-01 + 7.828000000000e-10 -1.345872104163e-02 + 7.928000000000e-10 1.410962716693e-01 + 8.028000000000e-10 2.371963808526e-01 + 8.128000000000e-10 2.791814500218e-01 + 8.228000000000e-10 3.166396456569e-01 + 8.328000000000e-10 3.598191409746e-01 + 8.428000000000e-10 3.963069790813e-01 + 8.528000000000e-10 4.074488078929e-01 + 8.628000000000e-10 3.456858987705e-01 + 8.728000000000e-10 1.950166421641e-01 + 8.828000000000e-10 1.344025602045e-02 + 8.928000000000e-10 -1.410790665154e-01 + 9.028000000000e-10 -2.372142995262e-01 + 9.128000000000e-10 -2.791649325552e-01 + 9.228000000000e-10 -3.166573514474e-01 + 9.328000000000e-10 -3.598022359716e-01 + 9.428000000000e-10 -3.963236588924e-01 + 9.528000000000e-10 -4.074326778223e-01 + 9.628000000000e-10 -3.457016440453e-01 + 9.728000000000e-10 -1.950001702792e-01 + 9.828000000000e-10 -1.345633761364e-02 + 9.928000000000e-10 1.410945129066e-01 + 1.000000000000e-09 2.176807579100e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/conditions.yaml new file mode 100644 index 00000000..1f4a0c85 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 9 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_09 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/CML_core_tb.sch new file mode 100644 index 00000000..daa6bd55 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/CML_core_tb_10.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/CML_core_tb_10.data new file mode 100644 index 00000000..6f87c434 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/CML_core_tb_10.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.831577979118e-01 + 1.728000000000e-10 -1.548331321524e-01 + 1.828000000000e-10 2.954507991941e-03 + 1.928000000000e-10 1.412083661187e-01 + 2.028000000000e-10 2.303947789211e-01 + 2.128000000000e-10 2.725788032239e-01 + 2.228000000000e-10 3.064646814943e-01 + 2.328000000000e-10 3.412898568956e-01 + 2.428000000000e-10 3.692979025942e-01 + 2.528000000000e-10 3.751979264520e-01 + 2.628000000000e-10 3.186495551608e-01 + 2.728000000000e-10 1.849115684226e-01 + 2.828000000000e-10 2.146912258403e-02 + 2.928000000000e-10 -1.215319416200e-01 + 3.028000000000e-10 -2.147336364713e-01 + 3.128000000000e-10 -2.593628319189e-01 + 3.228000000000e-10 -2.947919001104e-01 + 3.328000000000e-10 -3.306034656465e-01 + 3.428000000000e-10 -3.598903423599e-01 + 3.528000000000e-10 -3.674806029527e-01 + 3.628000000000e-10 -3.131864519443e-01 + 3.728000000000e-10 -1.816607205648e-01 + 3.828000000000e-10 -2.002885045896e-02 + 3.928000000000e-10 1.219326732879e-01 + 4.028000000000e-10 2.146583452252e-01 + 4.128000000000e-10 2.593288859790e-01 + 4.228000000000e-10 2.947836961551e-01 + 4.328000000000e-10 3.305873089453e-01 + 4.428000000000e-10 3.597520160348e-01 + 4.528000000000e-10 3.672634041173e-01 + 4.628000000000e-10 3.128292575731e-01 + 4.728000000000e-10 1.812525079401e-01 + 4.828000000000e-10 1.956255085056e-02 + 4.928000000000e-10 -1.223539241893e-01 + 5.028000000000e-10 -2.150587893921e-01 + 5.128000000000e-10 -2.596440912838e-01 + 5.228000000000e-10 -2.950896959018e-01 + 5.328000000000e-10 -3.308452440946e-01 + 5.428000000000e-10 -3.600168265621e-01 + 5.528000000000e-10 -3.674687038170e-01 + 5.628000000000e-10 -3.130140501398e-01 + 5.728000000000e-10 -1.813584327872e-01 + 5.828000000000e-10 -1.965159115909e-02 + 5.928000000000e-10 1.223212864923e-01 + 6.028000000000e-10 2.150157103205e-01 + 6.128000000000e-10 2.596318060931e-01 + 6.228000000000e-10 2.950524078153e-01 + 6.328000000000e-10 3.308363963911e-01 + 6.428000000000e-10 3.599874022300e-01 + 6.528000000000e-10 3.674690181116e-01 + 6.628000000000e-10 3.129980588961e-01 + 6.728000000000e-10 1.813712653368e-01 + 6.828000000000e-10 1.964491680526e-02 + 6.928000000000e-10 -1.223023112353e-01 + 7.028000000000e-10 -2.150202483004e-01 + 7.128000000000e-10 -2.596144309164e-01 + 7.228000000000e-10 -2.950582886643e-01 + 7.328000000000e-10 -3.308199600200e-01 + 7.428000000000e-10 -3.599931640339e-01 + 7.528000000000e-10 -3.674538095645e-01 + 7.628000000000e-10 -3.130042913922e-01 + 7.728000000000e-10 -1.813570925598e-01 + 7.828000000000e-10 -1.965290666609e-02 + 7.928000000000e-10 1.223145971689e-01 + 8.028000000000e-10 2.150114430495e-01 + 8.128000000000e-10 2.596256780136e-01 + 8.228000000000e-10 2.950490452158e-01 + 8.328000000000e-10 3.308307530718e-01 + 8.428000000000e-10 3.599842799802e-01 + 8.528000000000e-10 3.674639698479e-01 + 8.628000000000e-10 3.129957925611e-01 + 8.728000000000e-10 1.813666711568e-01 + 8.828000000000e-10 1.964348030724e-02 + 8.928000000000e-10 -1.223056361887e-01 + 9.028000000000e-10 -2.150207890100e-01 + 9.128000000000e-10 -2.596171721225e-01 + 9.228000000000e-10 -2.950581404305e-01 + 9.328000000000e-10 -3.308221104591e-01 + 9.428000000000e-10 -3.599929167296e-01 + 9.528000000000e-10 -3.674557320782e-01 + 9.628000000000e-10 -3.130039671541e-01 + 9.728000000000e-10 -1.813582011282e-01 + 9.828000000000e-10 -1.965175786777e-02 + 9.928000000000e-10 1.223137237372e-01 + 1.000000000000e-09 1.953703252853e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/conditions.yaml new file mode 100644 index 00000000..adfee817 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 10 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_10 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/CML_core_tb.sch new file mode 100644 index 00000000..421adbfb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/CML_core_tb_11.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/CML_core_tb_11.data new file mode 100644 index 00000000..1e62d263 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/CML_core_tb_11.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.857852225245e-01 + 1.728000000000e-10 -1.572533595452e-01 + 1.828000000000e-10 2.540381659783e-03 + 1.928000000000e-10 1.434374080790e-01 + 2.028000000000e-10 2.351272809546e-01 + 2.128000000000e-10 2.797956268783e-01 + 2.228000000000e-10 3.144243918962e-01 + 2.328000000000e-10 3.493618787392e-01 + 2.428000000000e-10 3.773715695689e-01 + 2.528000000000e-10 3.831823569325e-01 + 2.628000000000e-10 3.264482498061e-01 + 2.728000000000e-10 1.910530045686e-01 + 2.828000000000e-10 2.436059711742e-02 + 2.928000000000e-10 -1.220220612332e-01 + 3.028000000000e-10 -2.180809390746e-01 + 3.128000000000e-10 -2.653775774444e-01 + 3.228000000000e-10 -3.017848824321e-01 + 3.328000000000e-10 -3.379021858146e-01 + 3.428000000000e-10 -3.673696540777e-01 + 3.528000000000e-10 -3.751149757425e-01 + 3.628000000000e-10 -3.209083740174e-01 + 3.728000000000e-10 -1.878979131572e-01 + 3.828000000000e-10 -2.307531260616e-02 + 3.928000000000e-10 1.222703025101e-01 + 4.028000000000e-10 2.179003509445e-01 + 4.128000000000e-10 2.652908784701e-01 + 4.228000000000e-10 3.017672646237e-01 + 4.328000000000e-10 3.378931599738e-01 + 4.428000000000e-10 3.672390198172e-01 + 4.528000000000e-10 3.748903812400e-01 + 4.628000000000e-10 3.205316331029e-01 + 4.728000000000e-10 1.874647700937e-01 + 4.828000000000e-10 2.258819957166e-02 + 4.928000000000e-10 -1.227112688171e-01 + 5.028000000000e-10 -2.183172764214e-01 + 5.128000000000e-10 -2.656203742551e-01 + 5.228000000000e-10 -3.020800906145e-01 + 5.328000000000e-10 -3.381553362553e-01 + 5.428000000000e-10 -3.675051891202e-01 + 5.528000000000e-10 -3.750972240389e-01 + 5.628000000000e-10 -3.207148935088e-01 + 5.728000000000e-10 -1.875700292984e-01 + 5.828000000000e-10 -2.267596999196e-02 + 5.928000000000e-10 1.226776663562e-01 + 6.028000000000e-10 2.182733434309e-01 + 6.128000000000e-10 2.656053081095e-01 + 6.228000000000e-10 3.020411985396e-01 + 6.328000000000e-10 3.381435634392e-01 + 6.428000000000e-10 3.674743818406e-01 + 6.528000000000e-10 3.750952532513e-01 + 6.628000000000e-10 3.206986438750e-01 + 6.728000000000e-10 1.875816736609e-01 + 6.828000000000e-10 2.266940437016e-02 + 6.928000000000e-10 -1.226596158426e-01 + 7.028000000000e-10 -2.182776851932e-01 + 7.128000000000e-10 -2.655888997029e-01 + 7.228000000000e-10 -3.020470638059e-01 + 7.328000000000e-10 -3.381282771084e-01 + 7.428000000000e-10 -3.674800981492e-01 + 7.528000000000e-10 -3.750811166601e-01 + 7.628000000000e-10 -3.207046174850e-01 + 7.728000000000e-10 -1.875682790354e-01 + 7.828000000000e-10 -2.267703281628e-02 + 7.928000000000e-10 1.226713327530e-01 + 8.028000000000e-10 2.182693863135e-01 + 8.128000000000e-10 2.655996099454e-01 + 8.228000000000e-10 3.020383466326e-01 + 8.328000000000e-10 3.381385294735e-01 + 8.428000000000e-10 3.674717742910e-01 + 8.528000000000e-10 3.750907045119e-01 + 8.628000000000e-10 3.206966644115e-01 + 8.728000000000e-10 1.875773616331e-01 + 8.828000000000e-10 2.266807684955e-02 + 8.928000000000e-10 -1.226628120211e-01 + 9.028000000000e-10 -2.182782381400e-01 + 9.128000000000e-10 -2.655915506047e-01 + 9.228000000000e-10 -3.020469590318e-01 + 9.328000000000e-10 -3.381303351991e-01 + 9.428000000000e-10 -3.674798958779e-01 + 9.528000000000e-10 -3.750829516380e-01 + 9.628000000000e-10 -3.207043265993e-01 + 9.728000000000e-10 -1.875693454762e-01 + 9.828000000000e-10 -2.267594148777e-02 + 9.928000000000e-10 1.226704651969e-01 + 1.000000000000e-09 1.977257563344e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/conditions.yaml new file mode 100644 index 00000000..d808158e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 11 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_11 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/CML_core_tb.sch new file mode 100644 index 00000000..4cb8f529 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/CML_core_tb_12.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/CML_core_tb_12.data new file mode 100644 index 00000000..16422ca1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/CML_core_tb_12.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.213526702696e-01 + 1.728000000000e-10 -1.557909441213e-01 + 1.828000000000e-10 3.476956205809e-02 + 1.928000000000e-10 1.811250151598e-01 + 2.028000000000e-10 2.596166993269e-01 + 2.128000000000e-10 2.853727091731e-01 + 2.228000000000e-10 3.254453264627e-01 + 2.328000000000e-10 3.792799604087e-01 + 2.428000000000e-10 4.176388066249e-01 + 2.528000000000e-10 4.205544301124e-01 + 2.628000000000e-10 3.463528198985e-01 + 2.728000000000e-10 1.792096076204e-01 + 2.828000000000e-10 -1.442396833933e-02 + 2.928000000000e-10 -1.649237711275e-01 + 3.028000000000e-10 -2.471596975948e-01 + 3.128000000000e-10 -2.748735614517e-01 + 3.228000000000e-10 -3.160128767795e-01 + 3.328000000000e-10 -3.707930594343e-01 + 3.428000000000e-10 -4.104823651943e-01 + 3.528000000000e-10 -4.153692056047e-01 + 3.628000000000e-10 -3.427931169871e-01 + 3.728000000000e-10 -1.769552164151e-01 + 3.828000000000e-10 1.590673093360e-02 + 3.928000000000e-10 1.658834812043e-01 + 4.028000000000e-10 2.479775600913e-01 + 4.128000000000e-10 2.756409688001e-01 + 4.228000000000e-10 3.168596600790e-01 + 4.328000000000e-10 3.715133147191e-01 + 4.428000000000e-10 4.111218222953e-01 + 4.528000000000e-10 4.157229971644e-01 + 4.628000000000e-10 3.430019798682e-01 + 4.728000000000e-10 1.769456026445e-01 + 4.828000000000e-10 -1.592886494610e-02 + 4.928000000000e-10 -1.659782283296e-01 + 5.028000000000e-10 -2.479947853664e-01 + 5.128000000000e-10 -2.756931315881e-01 + 5.228000000000e-10 -3.168416717549e-01 + 5.328000000000e-10 -3.715547211919e-01 + 5.428000000000e-10 -4.111034138799e-01 + 5.528000000000e-10 -4.157691346087e-01 + 5.628000000000e-10 -3.429925568898e-01 + 5.728000000000e-10 -1.770024985869e-01 + 5.828000000000e-10 1.592938202906e-02 + 5.928000000000e-10 1.659292038608e-01 + 6.028000000000e-10 2.480043512000e-01 + 6.128000000000e-10 2.756533285421e-01 + 6.228000000000e-10 3.168576585763e-01 + 6.328000000000e-10 3.715156583068e-01 + 6.428000000000e-10 4.111207690964e-01 + 6.528000000000e-10 4.157343976531e-01 + 6.628000000000e-10 3.430135347581e-01 + 6.728000000000e-10 1.769734665185e-01 + 6.828000000000e-10 -1.590652763180e-02 + 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-3.715391180409e-01 + 9.428000000000e-10 -4.111007797151e-01 + 9.528000000000e-10 -4.157556639381e-01 + 9.628000000000e-10 -3.429919881202e-01 + 9.728000000000e-10 -1.769955652012e-01 + 9.828000000000e-10 1.592430721908e-02 + 9.928000000000e-10 1.659331850974e-01 + 1.000000000000e-09 2.332140069758e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/conditions.yaml new file mode 100644 index 00000000..31f821ce --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 12 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_12 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/CML_core_tb.sch new file mode 100644 index 00000000..89253593 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/CML_core_tb_13.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/CML_core_tb_13.data new file mode 100644 index 00000000..3dfcf241 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/CML_core_tb_13.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.365386572536e-01 + 1.728000000000e-10 -1.657072094068e-01 + 1.828000000000e-10 3.099865584261e-02 + 1.928000000000e-10 1.820426436768e-01 + 2.028000000000e-10 2.627018214462e-01 + 2.128000000000e-10 2.893736945719e-01 + 2.228000000000e-10 3.287984169352e-01 + 2.328000000000e-10 3.833334317825e-01 + 2.428000000000e-10 4.238785365972e-01 + 2.528000000000e-10 4.280322768716e-01 + 2.628000000000e-10 3.532409470363e-01 + 2.728000000000e-10 1.834641899168e-01 + 2.828000000000e-10 -1.474496205711e-02 + 2.928000000000e-10 -1.691349612478e-01 + 3.028000000000e-10 -2.530204867896e-01 + 3.128000000000e-10 -2.814070764654e-01 + 3.228000000000e-10 -3.218416847899e-01 + 3.328000000000e-10 -3.771799136100e-01 + 3.428000000000e-10 -4.187055626636e-01 + 3.528000000000e-10 -4.243036771430e-01 + 3.628000000000e-10 -3.506062035467e-01 + 3.728000000000e-10 -1.816763297909e-01 + 3.828000000000e-10 1.601938741723e-02 + 3.928000000000e-10 1.700087907901e-01 + 4.028000000000e-10 2.537596951165e-01 + 4.128000000000e-10 2.820887501770e-01 + 4.228000000000e-10 3.225625541805e-01 + 4.328000000000e-10 3.777928583784e-01 + 4.428000000000e-10 4.192485534625e-01 + 4.528000000000e-10 4.246080285894e-01 + 4.628000000000e-10 3.507916132015e-01 + 4.728000000000e-10 1.816929452641e-01 + 4.828000000000e-10 -1.601075067965e-02 + 4.928000000000e-10 -1.700562644838e-01 + 5.028000000000e-10 -2.537513990380e-01 + 5.128000000000e-10 -2.821086741965e-01 + 5.228000000000e-10 -3.225309737549e-01 + 5.328000000000e-10 -3.778081660132e-01 + 5.428000000000e-10 -4.192196231589e-01 + 5.528000000000e-10 -4.246325132019e-01 + 5.628000000000e-10 -3.507765562578e-01 + 5.728000000000e-10 -1.817315603141e-01 + 5.828000000000e-10 1.601468821266e-02 + 5.928000000000e-10 1.700220210141e-01 + 6.028000000000e-10 2.537612841477e-01 + 6.128000000000e-10 2.820810469197e-01 + 6.228000000000e-10 3.225454957468e-01 + 6.328000000000e-10 3.777800822765e-01 + 6.428000000000e-10 4.192350742948e-01 + 6.528000000000e-10 4.246071005326e-01 + 6.628000000000e-10 3.507940665347e-01 + 6.728000000000e-10 1.817094337521e-01 + 6.828000000000e-10 -1.599736953115e-02 + 6.928000000000e-10 -1.700405869499e-01 + 7.028000000000e-10 -2.537437685408e-01 + 7.128000000000e-10 -2.820988428465e-01 + 7.228000000000e-10 -3.225283133162e-01 + 7.328000000000e-10 -3.778004844844e-01 + 7.428000000000e-10 -4.192180216890e-01 + 7.528000000000e-10 -4.246257635725e-01 + 7.628000000000e-10 -3.507760422929e-01 + 7.728000000000e-10 -1.817278922025e-01 + 7.828000000000e-10 1.601285231965e-02 + 7.928000000000e-10 1.700238629540e-01 + 8.028000000000e-10 2.537592487741e-01 + 8.128000000000e-10 2.820829438407e-01 + 8.228000000000e-10 3.225445511573e-01 + 8.328000000000e-10 3.777829985044e-01 + 8.428000000000e-10 4.192337708379e-01 + 8.528000000000e-10 4.246090234999e-01 + 8.628000000000e-10 3.507916632731e-01 + 8.728000000000e-10 1.817122417436e-01 + 8.828000000000e-10 -1.599824136343e-02 + 8.928000000000e-10 -1.700377849177e-01 + 9.028000000000e-10 -2.537449127629e-01 + 9.128000000000e-10 -2.820965585668e-01 + 9.228000000000e-10 -3.225302446360e-01 + 9.328000000000e-10 -3.777982010874e-01 + 9.428000000000e-10 -4.192199753705e-01 + 9.528000000000e-10 -4.246232587341e-01 + 9.628000000000e-10 -3.507775800865e-01 + 9.728000000000e-10 -1.817263367247e-01 + 9.828000000000e-10 1.601066647660e-02 + 9.928000000000e-10 1.700248857455e-01 + 1.000000000000e-09 2.385375784000e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/conditions.yaml new file mode 100644 index 00000000..21bcab57 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 13 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_13 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/CML_core_tb.sch new file mode 100644 index 00000000..90cc3dc4 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/CML_core_tb_14.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/CML_core_tb_14.data new file mode 100644 index 00000000..86f9b023 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/CML_core_tb_14.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.747912795524e-01 + 1.728000000000e-10 -1.327955908449e-01 + 1.828000000000e-10 3.931332790349e-02 + 1.928000000000e-10 1.782957289495e-01 + 2.028000000000e-10 2.573194188668e-01 + 2.128000000000e-10 2.870254911902e-01 + 2.228000000000e-10 3.228650321442e-01 + 2.328000000000e-10 3.690575149088e-01 + 2.428000000000e-10 4.023791308175e-01 + 2.528000000000e-10 4.034409994944e-01 + 2.628000000000e-10 3.332295993533e-01 + 2.728000000000e-10 1.767123870243e-01 + 2.828000000000e-10 -7.574880255958e-03 + 2.928000000000e-10 -1.550892096227e-01 + 3.028000000000e-10 -2.394679486139e-01 + 3.128000000000e-10 -2.715465054757e-01 + 3.228000000000e-10 -3.085580168164e-01 + 3.328000000000e-10 -3.560821219044e-01 + 3.428000000000e-10 -3.914831036325e-01 + 3.528000000000e-10 -3.956717314322e-01 + 3.628000000000e-10 -3.285929470428e-01 + 3.728000000000e-10 -1.747908753666e-01 + 3.828000000000e-10 7.882784627431e-03 + 3.928000000000e-10 1.545893087045e-01 + 4.028000000000e-10 2.389887597051e-01 + 4.128000000000e-10 2.712307710628e-01 + 4.228000000000e-10 3.085047043395e-01 + 4.328000000000e-10 3.559448484744e-01 + 4.428000000000e-10 3.913507819782e-01 + 4.528000000000e-10 3.953547803018e-01 + 4.628000000000e-10 3.282585464854e-01 + 4.728000000000e-10 1.743078825018e-01 + 4.828000000000e-10 -8.291328068348e-03 + 4.928000000000e-10 -1.550293895867e-01 + 5.028000000000e-10 -2.392804293874e-01 + 5.128000000000e-10 -2.715405217782e-01 + 5.228000000000e-10 -3.087067361985e-01 + 5.328000000000e-10 -3.562070457914e-01 + 5.428000000000e-10 -3.915132320474e-01 + 5.528000000000e-10 -3.955548280332e-01 + 5.628000000000e-10 -3.283427048941e-01 + 5.728000000000e-10 -1.744282326244e-01 + 5.828000000000e-10 8.270645751064e-03 + 5.928000000000e-10 1.549582711486e-01 + 6.028000000000e-10 2.392860039329e-01 + 6.128000000000e-10 2.714820836214e-01 + 6.228000000000e-10 3.087161022039e-01 + 6.328000000000e-10 3.561494137047e-01 + 6.428000000000e-10 3.915273490759e-01 + 6.528000000000e-10 3.955079501007e-01 + 6.628000000000e-10 3.283677191723e-01 + 6.728000000000e-10 1.743944727908e-01 + 6.828000000000e-10 -8.238033211244e-03 + 6.928000000000e-10 -1.549849820320e-01 + 7.028000000000e-10 -2.392533741503e-01 + 7.128000000000e-10 -2.715088112944e-01 + 7.228000000000e-10 -3.086845279612e-01 + 7.328000000000e-10 -3.561786907982e-01 + 7.428000000000e-10 -3.914967682891e-01 + 7.528000000000e-10 -3.955360247734e-01 + 7.628000000000e-10 -3.283379458960e-01 + 7.728000000000e-10 -1.744219452106e-01 + 7.828000000000e-10 8.266285029230e-03 + 7.928000000000e-10 1.549592969714e-01 + 8.028000000000e-10 2.392805186707e-01 + 8.128000000000e-10 2.714837558368e-01 + 8.228000000000e-10 3.087120651005e-01 + 8.328000000000e-10 3.561520690508e-01 + 8.428000000000e-10 3.915233230940e-01 + 8.528000000000e-10 3.955100606400e-01 + 8.628000000000e-10 3.283632493206e-01 + 8.728000000000e-10 1.743968536756e-01 + 8.828000000000e-10 -8.241845610385e-03 + 8.928000000000e-10 -1.549825747228e-01 + 9.028000000000e-10 -2.392568734068e-01 + 9.128000000000e-10 -2.715063119250e-01 + 9.228000000000e-10 -3.086881712182e-01 + 9.328000000000e-10 -3.561760305782e-01 + 9.428000000000e-10 -3.915002731039e-01 + 9.528000000000e-10 -3.955331724158e-01 + 9.628000000000e-10 -3.283409163093e-01 + 9.728000000000e-10 -1.744193777973e-01 + 9.828000000000e-10 8.263272108901e-03 + 9.928000000000e-10 1.549616575981e-01 + 1.000000000000e-09 2.229820050464e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/conditions.yaml new file mode 100644 index 00000000..8c6f06b1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 14 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_14 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/CML_core_tb.sch new file mode 100644 index 00000000..23daa263 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/CML_core_tb_15.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/CML_core_tb_15.data new file mode 100644 index 00000000..7b2e7ab2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/CML_core_tb_15.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.957054612407e-01 + 1.728000000000e-10 -1.475216919691e-01 + 1.828000000000e-10 3.196996632833e-02 + 1.928000000000e-10 1.773696584526e-01 + 2.028000000000e-10 2.602670445343e-01 + 2.128000000000e-10 2.919684489720e-01 + 2.228000000000e-10 3.273690981683e-01 + 2.328000000000e-10 3.736661732429e-01 + 2.428000000000e-10 4.086769482098e-01 + 2.528000000000e-10 4.113258498473e-01 + 2.628000000000e-10 3.414272197123e-01 + 2.728000000000e-10 1.833836328070e-01 + 2.828000000000e-10 -4.501363849837e-03 + 2.928000000000e-10 -1.562318489881e-01 + 3.028000000000e-10 -2.435570784568e-01 + 3.128000000000e-10 -2.775386220390e-01 + 3.228000000000e-10 -3.142878056355e-01 + 3.328000000000e-10 -3.618442790176e-01 + 3.428000000000e-10 -3.986028140213e-01 + 3.528000000000e-10 -4.040381865127e-01 + 3.628000000000e-10 -3.369104214062e-01 + 3.728000000000e-10 -1.811830752063e-01 + 3.828000000000e-10 5.355128083595e-03 + 3.928000000000e-10 1.563630270676e-01 + 4.028000000000e-10 2.436522664355e-01 + 4.128000000000e-10 2.777202130414e-01 + 4.228000000000e-10 3.146716935396e-01 + 4.328000000000e-10 3.621309165835e-01 + 4.428000000000e-10 3.988648293319e-01 + 4.528000000000e-10 4.040567761896e-01 + 4.628000000000e-10 3.368362274946e-01 + 4.728000000000e-10 1.809052635954e-01 + 4.828000000000e-10 -5.606347307292e-03 + 4.928000000000e-10 -1.566747533637e-01 + 5.028000000000e-10 -2.438438929936e-01 + 5.128000000000e-10 -2.779365198916e-01 + 5.228000000000e-10 -3.147868656031e-01 + 5.328000000000e-10 -3.623069078218e-01 + 5.428000000000e-10 -3.989546307961e-01 + 5.528000000000e-10 -4.041975741324e-01 + 5.628000000000e-10 -3.368831845243e-01 + 5.728000000000e-10 -1.810020824460e-01 + 5.828000000000e-10 5.593858826262e-03 + 5.928000000000e-10 1.566090374935e-01 + 6.028000000000e-10 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8.528000000000e-10 4.041558823701e-01 + 8.628000000000e-10 3.369030769235e-01 + 8.728000000000e-10 1.809706945647e-01 + 8.828000000000e-10 -5.568483515763e-03 + 8.928000000000e-10 -1.566340912711e-01 + 9.028000000000e-10 -2.438236181184e-01 + 9.128000000000e-10 -2.779064153414e-01 + 9.228000000000e-10 -3.147718720666e-01 + 9.328000000000e-10 -3.622798572716e-01 + 9.428000000000e-10 -3.989444036153e-01 + 9.528000000000e-10 -4.041778978449e-01 + 9.628000000000e-10 -3.368819513246e-01 + 9.728000000000e-10 -1.809921012276e-01 + 9.828000000000e-10 5.588724287086e-03 + 9.928000000000e-10 1.566143682128e-01 + 1.000000000000e-09 2.267750497136e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/conditions.yaml new file mode 100644 index 00000000..16180f19 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 15 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_15 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/CML_core_tb.sch new file mode 100644 index 00000000..2fc8057c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/CML_core_tb_16.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/CML_core_tb_16.data new file mode 100644 index 00000000..a01deb89 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/CML_core_tb_16.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.908985659112e-01 + 1.728000000000e-10 -9.049079150817e-02 + 1.828000000000e-10 3.945873683219e-02 + 1.928000000000e-10 1.521437177417e-01 + 2.028000000000e-10 2.220068772324e-01 + 2.128000000000e-10 2.535092334052e-01 + 2.228000000000e-10 2.861973397174e-01 + 2.328000000000e-10 3.239843013312e-01 + 2.428000000000e-10 3.520113017607e-01 + 2.528000000000e-10 3.540468115658e-01 + 2.628000000000e-10 2.949447709683e-01 + 2.728000000000e-10 1.587983397866e-01 + 2.828000000000e-10 -6.865354773069e-03 + 2.928000000000e-10 -1.448078480843e-01 + 3.028000000000e-10 -2.275605338030e-01 + 3.128000000000e-10 -2.625604064747e-01 + 3.228000000000e-10 -2.958552078644e-01 + 3.328000000000e-10 -3.351711406638e-01 + 3.428000000000e-10 -3.644984224381e-01 + 3.528000000000e-10 -3.669950471097e-01 + 3.628000000000e-10 -3.072796408874e-01 + 3.728000000000e-10 -1.699866077827e-01 + 3.828000000000e-10 -2.842045316933e-03 + 3.928000000000e-10 1.365086891956e-01 + 4.028000000000e-10 2.207869920157e-01 + 4.128000000000e-10 2.567713461579e-01 + 4.228000000000e-10 2.907030026757e-01 + 4.328000000000e-10 3.302687598301e-01 + 4.428000000000e-10 3.600803190405e-01 + 4.528000000000e-10 3.632331450943e-01 + 4.628000000000e-10 3.045482678871e-01 + 4.728000000000e-10 1.682698274629e-01 + 4.828000000000e-10 2.058504292284e-03 + 4.928000000000e-10 -1.367871396964e-01 + 5.028000000000e-10 -2.207717990252e-01 + 5.128000000000e-10 -2.567684885934e-01 + 5.228000000000e-10 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7.728000000000e-10 -1.681486407544e-01 + 7.828000000000e-10 -1.870004957548e-03 + 7.928000000000e-10 1.369437070838e-01 + 8.028000000000e-10 2.209481957039e-01 + 8.128000000000e-10 2.568879030180e-01 + 8.228000000000e-10 2.908064848389e-01 + 8.328000000000e-10 3.303493303219e-01 + 8.428000000000e-10 3.601006147126e-01 + 8.528000000000e-10 3.632041339109e-01 + 8.628000000000e-10 3.044528281549e-01 + 8.728000000000e-10 1.681322760827e-01 + 8.828000000000e-10 1.883536763259e-03 + 8.928000000000e-10 -1.369582535540e-01 + 9.028000000000e-10 -2.209346296842e-01 + 9.128000000000e-10 -2.569016830366e-01 + 9.228000000000e-10 -2.907925936742e-01 + 9.328000000000e-10 -3.303636164667e-01 + 9.428000000000e-10 -3.600871302257e-01 + 9.528000000000e-10 -3.632178492939e-01 + 9.628000000000e-10 -3.044398392752e-01 + 9.728000000000e-10 -1.681454261603e-01 + 9.828000000000e-10 -1.870628705438e-03 + 9.928000000000e-10 1.369459433541e-01 + 1.000000000000e-09 2.037746084522e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/conditions.yaml new file mode 100644 index 00000000..7b1f789e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 16 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_16 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/CML_core_tb.sch new file mode 100644 index 00000000..a8f0c987 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/CML_core_tb_17.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/CML_core_tb_17.data new file mode 100644 index 00000000..c21b093d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/CML_core_tb_17.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.135873679018e-01 + 1.728000000000e-10 -1.054229355639e-01 + 1.828000000000e-10 3.485798650969e-02 + 1.928000000000e-10 1.569675139767e-01 + 2.028000000000e-10 2.330635404696e-01 + 2.128000000000e-10 2.680443549179e-01 + 2.228000000000e-10 3.014044829899e-01 + 2.328000000000e-10 3.394080314353e-01 + 2.428000000000e-10 3.679529618424e-01 + 2.528000000000e-10 3.700593040123e-01 + 2.628000000000e-10 3.097824620429e-01 + 2.728000000000e-10 1.706514675999e-01 + 2.828000000000e-10 3.558070014658e-04 + 2.928000000000e-10 -1.428409974599e-01 + 3.028000000000e-10 -2.298289579719e-01 + 3.128000000000e-10 -2.678794741753e-01 + 3.228000000000e-10 -3.017454056957e-01 + 3.328000000000e-10 -3.410620518407e-01 + 3.428000000000e-10 -3.712405389398e-01 + 3.528000000000e-10 -3.749327973471e-01 + 3.628000000000e-10 -3.157484466493e-01 + 3.728000000000e-10 -1.773087198166e-01 + 3.828000000000e-10 -7.070252178339e-03 + 3.928000000000e-10 1.364462941621e-01 + 4.028000000000e-10 2.243241068758e-01 + 4.128000000000e-10 2.631279769125e-01 + 4.228000000000e-10 2.976097246349e-01 + 4.328000000000e-10 3.371159716785e-01 + 4.428000000000e-10 3.676405775058e-01 + 4.528000000000e-10 3.717787254056e-01 + 4.628000000000e-10 3.133854979421e-01 + 4.728000000000e-10 1.756870158595e-01 + 4.828000000000e-10 6.171257018760e-03 + 4.928000000000e-10 -1.369680995621e-01 + 5.028000000000e-10 -2.245781248931e-01 + 5.128000000000e-10 -2.633829468620e-01 + 5.228000000000e-10 -2.978042748481e-01 + 5.328000000000e-10 -3.373348877854e-01 + 5.428000000000e-10 -3.677584906255e-01 + 5.528000000000e-10 -3.718812762918e-01 + 5.628000000000e-10 -3.133649557524e-01 + 5.728000000000e-10 -1.756479312047e-01 + 5.828000000000e-10 -6.040608056278e-03 + 5.928000000000e-10 1.370690415770e-01 + 6.028000000000e-10 2.247181767783e-01 + 6.128000000000e-10 2.634617265965e-01 + 6.228000000000e-10 2.979157296699e-01 + 6.328000000000e-10 3.373958940353e-01 + 6.428000000000e-10 3.678612954525e-01 + 6.528000000000e-10 3.719309221475e-01 + 6.628000000000e-10 3.134447453066e-01 + 6.728000000000e-10 1.756687688086e-01 + 6.828000000000e-10 6.090200135509e-03 + 6.928000000000e-10 -1.370702307281e-01 + 7.028000000000e-10 -2.246847420648e-01 + 7.128000000000e-10 -2.634701196121e-01 + 7.228000000000e-10 -2.978849158722e-01 + 7.328000000000e-10 -3.374068878437e-01 + 7.428000000000e-10 -3.678336110941e-01 + 7.528000000000e-10 -3.719446503824e-01 + 7.628000000000e-10 -3.134227431793e-01 + 7.728000000000e-10 -1.756868885858e-01 + 7.828000000000e-10 -6.072676723321e-03 + 7.928000000000e-10 1.370503070743e-01 + 8.028000000000e-10 2.247004966695e-01 + 8.128000000000e-10 2.634509722982e-01 + 8.228000000000e-10 2.979013793804e-01 + 8.328000000000e-10 3.373870921905e-01 + 8.428000000000e-10 3.678495602861e-01 + 8.528000000000e-10 3.719256264749e-01 + 8.628000000000e-10 3.134381864470e-01 + 8.728000000000e-10 1.756688935561e-01 + 8.828000000000e-10 6.088345643719e-03 + 8.928000000000e-10 -1.370666831053e-01 + 9.028000000000e-10 -2.246851372638e-01 + 9.128000000000e-10 -2.634666121684e-01 + 9.228000000000e-10 -2.978856025968e-01 + 9.328000000000e-10 -3.374033621769e-01 + 9.428000000000e-10 -3.678342837151e-01 + 9.528000000000e-10 -3.719412125322e-01 + 9.628000000000e-10 -3.134235677100e-01 + 9.728000000000e-10 -1.756838495744e-01 + 9.828000000000e-10 -6.073781243164e-03 + 9.928000000000e-10 1.370527135588e-01 + 1.000000000000e-09 2.065229990524e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/conditions.yaml new file mode 100644 index 00000000..4836dc98 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 17 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/run_17 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..2b2b1892 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,19 @@ +run,corner,temperature,vdd,time,vo_diff,frequency +run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.111e-01, -1.870e-01, -3.563e-02, …]",4.722 +run_01,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.876e-01, -3.217e-02, …]",4.722 +run_02,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.915e-01, -1.780e-01, -3.803e-02, …]",4.722 +run_03,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.959e-01, -1.792e-01, -3.599e-02, …]",4.722 +run_04,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.689e-01, -1.692e-01, -4.423e-02, …]",4.722 +run_05,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.723e-01, -1.701e-01, -4.252e-02, …]",4.722 +run_06,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.623e-01, -1.963e-01, -5.713e-03, …]",4.722 +run_07,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.669e-01, -1.979e-01, -3.070e-03, …]",4.722 +run_08,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",4.722 +run_09,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.446e-01, -1.889e-01, -5.355e-03, …]",4.722 +run_10,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.832e-01, -1.548e-01, 2.955e-03, …]",4.722 +run_11,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.858e-01, -1.573e-01, 2.540e-03, …]",4.722 +run_12,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.214e-01, -1.558e-01, 3.477e-02, …]",4.722 +run_13,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.365e-01, -1.657e-01, 3.100e-02, …]",4.722 +run_14,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.748e-01, -1.328e-01, 3.931e-02, …]",4.722 +run_15,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.957e-01, -1.475e-01, 3.197e-02, …]",4.722 +run_16,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.909e-01, -9.049e-02, 3.946e-02, …]",4.722 +run_17,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.136e-01, -1.054e-01, 3.486e-02, …]",4.722 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..248ed80a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/parameters/Frequency/simulation_summary.md @@ -0,0 +1,22 @@ +# Simulation Summary for Freq + +| run | corner | temperature | vdd | time | vo_diff | frequency | +| :-- | -----: | ----------: | --: | ---: | ------: | --------: | +| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.111e-01, -1.870e-01, -3.563e-02, …] | 4.722 | +| run_01 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.876e-01, -3.217e-02, …] | 4.722 | +| run_02 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.915e-01, -1.780e-01, -3.803e-02, …] | 4.722 | +| run_03 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.959e-01, -1.792e-01, -3.599e-02, …] | 4.722 | +| run_04 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.689e-01, -1.692e-01, -4.423e-02, …] | 4.722 | +| run_05 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.723e-01, -1.701e-01, -4.252e-02, …] | 4.722 | +| run_06 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.623e-01, -1.963e-01, -5.713e-03, …] | 4.722 | +| run_07 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.669e-01, -1.979e-01, -3.070e-03, …] | 4.722 | +| run_08 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 4.722 | +| run_09 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.446e-01, -1.889e-01, -5.355e-03, …] | 4.722 | +| run_10 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.832e-01, -1.548e-01, 2.955e-03, …] | 4.722 | +| run_11 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.858e-01, -1.573e-01, 2.540e-03, …] | 4.722 | +| run_12 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.214e-01, -1.558e-01, 3.477e-02, …] | 4.722 | +| run_13 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.365e-01, -1.657e-01, 3.100e-02, …] | 4.722 | +| run_14 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.748e-01, -1.328e-01, 3.931e-02, …] | 4.722 | +| run_15 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.957e-01, -1.475e-01, 3.197e-02, …] | 4.722 | +| run_16 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.909e-01, -9.049e-02, 3.946e-02, …] | 4.722 | +| run_17 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.136e-01, -1.054e-01, 3.486e-02, …] | 4.722 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/summary.md new file mode 100644 index 00000000..9177d5db --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-38-36/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | any | 0.000 GHz | any | 0.000 GHz | any | 0.000 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/CML_core_tb.sch new file mode 100644 index 00000000..6495f6cb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/CML_core_tb_0.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..13744412 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/parameters/Frequency/run_0 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/summary.md new file mode 100644 index 00000000..0840f717 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-07/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.2 GHz | ​ | 5.4 GHz | ​ | 7.1 GHz | ​ | Error ❗ | + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/frequency.png new file mode 100644 index 00000000..cfba68b3 Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/CML_core_tb.sch new file mode 100644 index 00000000..1b6d8658 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/CML_core_tb_0.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..c06b16d7 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/run_0 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..1bf3ee60 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time,vo_diff,frequency +run_0,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",4.722 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..b1f49411 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time | vo_diff | frequency | +| :-- | ---: | ------: | --------: | +| run_0 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 4.722 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/summary.md new file mode 100644 index 00000000..04de8373 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-41-30/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | ​ | ​ | ​ | 0.000 GHz | ​ | ​ | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/frequency.png new file mode 100644 index 00000000..cfba68b3 Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/CML_core_tb.sch new file mode 100644 index 00000000..735c2a60 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/CML_core_tb_0.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..2d66ad7f --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/run_0 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..44754347 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time,vo_diff,frequency +run_0,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",4.722e+09 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..10d7dafc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time | vo_diff | frequency | +| :-- | ---: | ------: | --------: | +| run_0 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 4.722e+09 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/summary.md new file mode 100644 index 00000000..91014211 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-02/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | ​ | ​ | ​ | 4.722 GHz | ​ | ​ | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/frequency.png new file mode 100644 index 00000000..e3ac31d9 Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/CML_core_tb.sch new file mode 100644 index 00000000..1af9ac89 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/CML_core_tb_0.data new file mode 100644 index 00000000..4cb5b399 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.110742996065e-01 + 1.728000000000e-10 -1.869505717284e-01 + 1.828000000000e-10 -3.563037101706e-02 + 1.928000000000e-10 1.056708524540e-01 + 2.028000000000e-10 2.100393804445e-01 + 2.128000000000e-10 2.784249297688e-01 + 2.228000000000e-10 3.224310579067e-01 + 2.328000000000e-10 3.548600651170e-01 + 2.428000000000e-10 3.792482005271e-01 + 2.528000000000e-10 3.740820324036e-01 + 2.628000000000e-10 3.079440308227e-01 + 2.728000000000e-10 1.813826171807e-01 + 2.828000000000e-10 2.923027813912e-02 + 2.928000000000e-10 -1.118282325615e-01 + 3.028000000000e-10 -2.157337068367e-01 + 3.128000000000e-10 -2.829033176767e-01 + 3.228000000000e-10 -3.260714502323e-01 + 3.328000000000e-10 -3.577361248183e-01 + 3.428000000000e-10 -3.819104006606e-01 + 3.528000000000e-10 -3.764730474160e-01 + 3.628000000000e-10 -3.102968359246e-01 + 3.728000000000e-10 -1.832608913655e-01 + 3.828000000000e-10 -3.084931437320e-02 + 3.928000000000e-10 1.106163095990e-01 + 4.028000000000e-10 2.145714971977e-01 + 4.128000000000e-10 2.819937231053e-01 + 4.228000000000e-10 3.251740998910e-01 + 4.328000000000e-10 3.570946969464e-01 + 4.428000000000e-10 3.813004444382e-01 + 4.528000000000e-10 3.761230596147e-01 + 4.628000000000e-10 3.099646053412e-01 + 4.728000000000e-10 1.831473345022e-01 + 4.828000000000e-10 3.069401022130e-02 + 4.928000000000e-10 -1.106258411343e-01 + 5.028000000000e-10 -2.146793601179e-01 + 5.128000000000e-10 -2.820035552799e-01 + 5.228000000000e-10 -3.252909243829e-01 + 5.328000000000e-10 -3.570986338553e-01 + 5.428000000000e-10 -3.813904658256e-01 + 5.528000000000e-10 -3.760889514061e-01 + 5.628000000000e-10 -3.100114096943e-01 + 5.728000000000e-10 -1.830827247194e-01 + 5.828000000000e-10 -3.072480545922e-02 + 5.928000000000e-10 1.106906463094e-01 + 6.028000000000e-10 2.146493837568e-01 + 6.128000000000e-10 2.820610673881e-01 + 6.228000000000e-10 3.252525482967e-01 + 6.328000000000e-10 3.571504708749e-01 + 6.428000000000e-10 3.813516648295e-01 + 6.528000000000e-10 3.761390656738e-01 + 6.628000000000e-10 3.099742259389e-01 + 6.728000000000e-10 1.831331110808e-01 + 6.828000000000e-10 3.068765829312e-02 + 6.928000000000e-10 -1.106445812930e-01 + 7.028000000000e-10 -2.146859050297e-01 + 7.128000000000e-10 -2.820172231683e-01 + 7.228000000000e-10 -3.252905125649e-01 + 7.328000000000e-10 -3.571078709926e-01 + 7.428000000000e-10 -3.813893177320e-01 + 7.528000000000e-10 -3.760986555866e-01 + 7.628000000000e-10 -3.100117776476e-01 + 7.728000000000e-10 -1.830935153198e-01 + 7.828000000000e-10 -3.072484475908e-02 + 7.928000000000e-10 1.106810594907e-01 + 8.028000000000e-10 2.146507312123e-01 + 8.128000000000e-10 2.820530370402e-01 + 8.228000000000e-10 3.252547871433e-01 + 8.328000000000e-10 3.571432636036e-01 + 8.428000000000e-10 3.813547544577e-01 + 8.528000000000e-10 3.761324372121e-01 + 8.628000000000e-10 3.099775475493e-01 + 8.728000000000e-10 1.831274535707e-01 + 8.828000000000e-10 3.069175078476e-02 + 8.928000000000e-10 -1.106491559136e-01 + 9.028000000000e-10 -2.146821655528e-01 + 9.128000000000e-10 -2.820218639330e-01 + 9.228000000000e-10 -3.252864642203e-01 + 9.328000000000e-10 -3.571122611941e-01 + 9.428000000000e-10 -3.813854215351e-01 + 9.528000000000e-10 -3.761024723822e-01 + 9.628000000000e-10 -3.100075395903e-01 + 9.728000000000e-10 -1.830975404653e-01 + 9.828000000000e-10 -3.072097080048e-02 + 9.928000000000e-10 1.106770531472e-01 + 1.000000000000e-09 1.895325033433e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/conditions.yaml new file mode 100644 index 00000000..d73bdff9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_00 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/CML_core_tb.sch new file mode 100644 index 00000000..7e7b8738 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/CML_core_tb_1.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/CML_core_tb_1.data new file mode 100644 index 00000000..b332ca2c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/CML_core_tb_1.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162797108708e-01 + 1.728000000000e-10 -1.875883768906e-01 + 1.828000000000e-10 -3.217177564589e-02 + 1.928000000000e-10 1.118453904517e-01 + 2.028000000000e-10 2.178869753922e-01 + 2.128000000000e-10 2.869187499571e-01 + 2.228000000000e-10 3.311831063176e-01 + 2.328000000000e-10 3.637965093552e-01 + 2.428000000000e-10 3.884475585753e-01 + 2.528000000000e-10 3.831703446637e-01 + 2.628000000000e-10 3.149426000366e-01 + 2.728000000000e-10 1.840825734866e-01 + 2.828000000000e-10 2.786370536806e-02 + 2.928000000000e-10 -1.159899232258e-01 + 3.028000000000e-10 -2.217323928122e-01 + 3.128000000000e-10 -2.897841810826e-01 + 3.228000000000e-10 -3.334256487170e-01 + 3.328000000000e-10 -3.654508602495e-01 + 3.428000000000e-10 -3.900407544937e-01 + 3.528000000000e-10 -3.846189534315e-01 + 3.628000000000e-10 -3.164922452622e-01 + 3.728000000000e-10 -1.853182634851e-01 + 3.828000000000e-10 -2.898615964086e-02 + 3.928000000000e-10 1.151710782521e-01 + 4.028000000000e-10 2.209054309263e-01 + 4.128000000000e-10 2.891817322742e-01 + 4.228000000000e-10 3.328077516782e-01 + 4.328000000000e-10 3.650515838921e-01 + 4.428000000000e-10 3.896233583948e-01 + 4.528000000000e-10 3.844074302627e-01 + 4.628000000000e-10 3.162448842688e-01 + 4.728000000000e-10 1.852475068120e-01 + 4.828000000000e-10 2.884623360652e-02 + 4.928000000000e-10 -1.151788252337e-01 + 5.028000000000e-10 -2.210147130581e-01 + 5.128000000000e-10 -2.891872658193e-01 + 5.228000000000e-10 -3.329167168088e-01 + 5.328000000000e-10 -3.650471930963e-01 + 5.428000000000e-10 -3.897100874545e-01 + 5.528000000000e-10 -3.843762306477e-01 + 5.628000000000e-10 -3.163013912188e-01 + 5.728000000000e-10 -1.851950213487e-01 + 5.828000000000e-10 -2.889036873678e-02 + 5.928000000000e-10 1.152312899162e-01 + 6.028000000000e-10 2.209735588305e-01 + 6.128000000000e-10 2.892357416511e-01 + 6.228000000000e-10 3.328707955285e-01 + 6.328000000000e-10 3.650931065031e-01 + 6.428000000000e-10 3.896657987149e-01 + 6.528000000000e-10 3.844215105032e-01 + 6.628000000000e-10 3.162596917265e-01 + 6.728000000000e-10 1.852417351036e-01 + 6.828000000000e-10 2.884992827621e-02 + 6.928000000000e-10 -1.151876679011e-01 + 7.028000000000e-10 -2.210123101756e-01 + 7.128000000000e-10 -2.891938845816e-01 + 7.228000000000e-10 -3.329106389600e-01 + 7.328000000000e-10 -3.650518039465e-01 + 7.428000000000e-10 -3.897047407363e-01 + 7.528000000000e-10 -3.843819858648e-01 + 7.628000000000e-10 -3.162978744015e-01 + 7.728000000000e-10 -1.852023753321e-01 + 7.828000000000e-10 -2.888743165850e-02 + 7.928000000000e-10 1.152240030808e-01 + 8.028000000000e-10 2.209771419031e-01 + 8.128000000000e-10 2.892295361788e-01 + 8.228000000000e-10 3.328747680971e-01 + 8.328000000000e-10 3.650871456099e-01 + 8.428000000000e-10 3.896701175780e-01 + 8.528000000000e-10 3.844156912621e-01 + 8.628000000000e-10 3.162637401476e-01 + 8.728000000000e-10 1.852363586492e-01 + 8.828000000000e-10 2.885434112124e-02 + 8.928000000000e-10 -1.151920978903e-01 + 9.028000000000e-10 -2.210084087345e-01 + 9.128000000000e-10 -2.891984388712e-01 + 9.228000000000e-10 -3.329064027155e-01 + 9.328000000000e-10 -3.650560988894e-01 + 9.428000000000e-10 -3.897007143418e-01 + 9.528000000000e-10 -3.843858173814e-01 + 9.628000000000e-10 -3.162935974835e-01 + 9.728000000000e-10 -1.852064424274e-01 + 9.828000000000e-10 -2.888350905479e-02 + 9.928000000000e-10 1.152199079204e-01 + 1.000000000000e-09 1.954791142410e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/conditions.yaml new file mode 100644 index 00000000..90b469c5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 1 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_01 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/CML_core_tb.sch new file mode 100644 index 00000000..aef5907d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/CML_core_tb_2.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/CML_core_tb_2.data new file mode 100644 index 00000000..6dccbfd6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/CML_core_tb_2.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.914571027454e-01 + 1.728000000000e-10 -1.780117263272e-01 + 1.828000000000e-10 -3.802564096594e-02 + 1.928000000000e-10 9.479025580261e-02 + 2.028000000000e-10 1.961220444980e-01 + 2.128000000000e-10 2.643669322964e-01 + 2.228000000000e-10 3.071498875260e-01 + 2.328000000000e-10 3.351667250191e-01 + 2.428000000000e-10 3.529478733093e-01 + 2.528000000000e-10 3.439767079911e-01 + 2.628000000000e-10 2.827109934029e-01 + 2.728000000000e-10 1.683025534555e-01 + 2.828000000000e-10 2.843266655337e-02 + 2.928000000000e-10 -1.036223502576e-01 + 3.028000000000e-10 -2.042863713809e-01 + 3.128000000000e-10 -2.713818104821e-01 + 3.228000000000e-10 -3.132717880322e-01 + 3.328000000000e-10 -3.402903477971e-01 + 3.428000000000e-10 -3.574262556597e-01 + 3.528000000000e-10 -3.476240566503e-01 + 3.628000000000e-10 -2.857203755187e-01 + 3.728000000000e-10 -1.703849236420e-01 + 3.828000000000e-10 -2.994825869373e-02 + 3.928000000000e-10 1.026817167876e-01 + 4.028000000000e-10 2.034750084544e-01 + 4.128000000000e-10 2.707812081585e-01 + 4.228000000000e-10 3.126503625184e-01 + 4.328000000000e-10 3.399043734480e-01 + 4.428000000000e-10 3.571021595385e-01 + 4.528000000000e-10 3.475896983741e-01 + 4.628000000000e-10 2.857411927694e-01 + 4.728000000000e-10 1.706053611761e-01 + 4.828000000000e-10 3.010795594348e-02 + 4.928000000000e-10 -1.024135388755e-01 + 5.028000000000e-10 -2.033190471438e-01 + 5.128000000000e-10 -2.705615444577e-01 + 5.228000000000e-10 -3.125558523975e-01 + 5.328000000000e-10 -3.397330193449e-01 + 5.428000000000e-10 -3.570354300338e-01 + 5.528000000000e-10 -3.474353611027e-01 + 5.628000000000e-10 -2.856876769732e-01 + 5.728000000000e-10 -1.704760895977e-01 + 5.828000000000e-10 -3.008641427314e-02 + 5.928000000000e-10 1.025087996136e-01 + 6.028000000000e-10 2.033209986443e-01 + 6.128000000000e-10 2.706412375819e-01 + 6.228000000000e-10 3.125457575810e-01 + 6.328000000000e-10 3.398008382665e-01 + 6.428000000000e-10 3.570145583479e-01 + 6.528000000000e-10 3.474888598072e-01 + 6.628000000000e-10 2.856551852535e-01 + 6.728000000000e-10 1.705188293935e-01 + 6.828000000000e-10 3.004736925580e-02 + 6.928000000000e-10 -1.024728514478e-01 + 7.028000000000e-10 -2.033602328622e-01 + 7.128000000000e-10 -2.706061106716e-01 + 7.228000000000e-10 -3.125843283316e-01 + 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-1.704892548593e-01 + 9.828000000000e-10 -3.008001356704e-02 + 9.928000000000e-10 1.025005080892e-01 + 1.000000000000e-09 1.786649040194e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/conditions.yaml new file mode 100644 index 00000000..74221d72 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 2 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_02 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/CML_core_tb.sch new file mode 100644 index 00000000..2d185d5a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/CML_core_tb_3.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/CML_core_tb_3.data new file mode 100644 index 00000000..0cc77d23 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/CML_core_tb_3.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.958574299710e-01 + 1.728000000000e-10 -1.791897212785e-01 + 1.828000000000e-10 -3.599075048614e-02 + 1.928000000000e-10 9.946703268478e-02 + 2.028000000000e-10 2.032502871016e-01 + 2.128000000000e-10 2.733994094958e-01 + 2.228000000000e-10 3.172845988123e-01 + 2.328000000000e-10 3.455609123691e-01 + 2.428000000000e-10 3.630923957132e-01 + 2.528000000000e-10 3.534419450967e-01 + 2.628000000000e-10 2.903663934708e-01 + 2.728000000000e-10 1.726743312860e-01 + 2.828000000000e-10 2.930291139472e-02 + 2.928000000000e-10 -1.057514312075e-01 + 3.028000000000e-10 -2.091913834589e-01 + 3.128000000000e-10 -2.784696434768e-01 + 3.228000000000e-10 -3.216873931074e-01 + 3.328000000000e-10 -3.491870426412e-01 + 3.428000000000e-10 -3.662894191498e-01 + 3.528000000000e-10 -3.560374131806e-01 + 3.628000000000e-10 -2.925719059469e-01 + 3.728000000000e-10 -1.742159787839e-01 + 3.828000000000e-10 -3.049391935212e-02 + 3.928000000000e-10 1.049756016137e-01 + 4.028000000000e-10 2.084672065617e-01 + 4.128000000000e-10 2.779301238417e-01 + 4.228000000000e-10 3.211180618030e-01 + 4.328000000000e-10 3.488255023686e-01 + 4.428000000000e-10 3.659572542624e-01 + 4.528000000000e-10 3.559493947967e-01 + 4.628000000000e-10 2.925058094407e-01 + 4.728000000000e-10 1.743267017008e-01 + 4.828000000000e-10 3.054314172764e-02 + 4.928000000000e-10 -1.048175245910e-01 + 5.028000000000e-10 -2.084096499031e-01 + 5.128000000000e-10 -2.777998408986e-01 + 5.228000000000e-10 -3.210985617265e-01 + 5.328000000000e-10 -3.487226120056e-01 + 5.428000000000e-10 -3.659481451181e-01 + 5.528000000000e-10 -3.558482598240e-01 + 5.628000000000e-10 -2.924942070749e-01 + 5.728000000000e-10 -1.742324941843e-01 + 5.828000000000e-10 -3.054486718364e-02 + 5.928000000000e-10 1.048934295445e-01 + 6.028000000000e-10 2.083991544976e-01 + 6.128000000000e-10 2.778660140822e-01 + 6.228000000000e-10 3.210794561497e-01 + 6.328000000000e-10 3.487805773205e-01 + 6.428000000000e-10 3.659226785140e-01 + 6.528000000000e-10 3.558970058340e-01 + 6.628000000000e-10 2.924624137185e-01 + 6.728000000000e-10 1.742748110039e-01 + 6.828000000000e-10 3.050920657876e-02 + 6.928000000000e-10 -1.048562048812e-01 + 7.028000000000e-10 -2.084343791218e-01 + 7.128000000000e-10 -2.778299623633e-01 + 7.228000000000e-10 -3.211147582115e-01 + 7.328000000000e-10 -3.487447461690e-01 + 7.428000000000e-10 -3.659575085549e-01 + 7.528000000000e-10 -3.558632428052e-01 + 7.628000000000e-10 -2.924972481137e-01 + 7.728000000000e-10 -1.742418088753e-01 + 7.828000000000e-10 -3.054328720193e-02 + 7.928000000000e-10 1.048870377838e-01 + 8.028000000000e-10 2.084024115537e-01 + 8.128000000000e-10 2.778603942564e-01 + 8.228000000000e-10 3.210827582845e-01 + 8.328000000000e-10 3.487751488045e-01 + 8.428000000000e-10 3.659266824704e-01 + 8.528000000000e-10 3.558925702991e-01 + 8.628000000000e-10 2.924671830422e-01 + 8.728000000000e-10 1.742711856894e-01 + 8.828000000000e-10 3.051417003050e-02 + 8.928000000000e-10 -1.048591994973e-01 + 9.028000000000e-10 -2.084299430076e-01 + 9.128000000000e-10 -2.778331783696e-01 + 9.228000000000e-10 -3.211104359655e-01 + 9.328000000000e-10 -3.487480244246e-01 + 9.428000000000e-10 -3.659535267111e-01 + 9.528000000000e-10 -3.558663548813e-01 + 9.628000000000e-10 -2.924933270906e-01 + 9.728000000000e-10 -1.742451324195e-01 + 9.828000000000e-10 -3.053963678018e-02 + 9.928000000000e-10 1.048836196344e-01 + 1.000000000000e-09 1.830293824662e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/conditions.yaml new file mode 100644 index 00000000..40accfeb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 3 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_03 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/CML_core_tb.sch new file mode 100644 index 00000000..28f7c28e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/CML_core_tb_4.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/CML_core_tb_4.data new file mode 100644 index 00000000..38ffd8bf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/CML_core_tb_4.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.689355033953e-01 + 1.728000000000e-10 -1.691728954892e-01 + 1.828000000000e-10 -4.423302134033e-02 + 1.928000000000e-10 7.663444207075e-02 + 2.028000000000e-10 1.714764750752e-01 + 2.128000000000e-10 2.368219567798e-01 + 2.228000000000e-10 2.772768132445e-01 + 2.328000000000e-10 3.013675537348e-01 + 2.428000000000e-10 3.140706479520e-01 + 2.528000000000e-10 3.038549886105e-01 + 2.628000000000e-10 2.508404086347e-01 + 2.728000000000e-10 1.528360605683e-01 + 2.828000000000e-10 3.040034809293e-02 + 2.928000000000e-10 -8.785381094258e-02 + 3.028000000000e-10 -1.808734961109e-01 + 3.128000000000e-10 -2.445795528199e-01 + 3.228000000000e-10 -2.838354337528e-01 + 3.328000000000e-10 -3.065800962400e-01 + 3.428000000000e-10 -3.181767360109e-01 + 3.528000000000e-10 -3.065752663659e-01 + 3.628000000000e-10 -2.523878800401e-01 + 3.728000000000e-10 -1.531173668737e-01 + 3.828000000000e-10 -2.992055538556e-02 + 3.928000000000e-10 8.900435641641e-02 + 4.028000000000e-10 1.821756238512e-01 + 4.128000000000e-10 2.460123650690e-01 + 4.228000000000e-10 2.851182310100e-01 + 4.328000000000e-10 3.079291995556e-01 + 4.428000000000e-10 3.194129911462e-01 + 4.528000000000e-10 3.078915366323e-01 + 4.628000000000e-10 2.535144344421e-01 + 4.728000000000e-10 1.541542026196e-01 + 4.828000000000e-10 3.063651583090e-02 + 4.928000000000e-10 -8.839161491074e-02 + 5.028000000000e-10 -1.817999659778e-01 + 5.128000000000e-10 -2.456456661989e-01 + 5.228000000000e-10 -2.849195350591e-01 + 5.328000000000e-10 -3.077091828990e-01 + 5.428000000000e-10 -3.193505374448e-01 + 5.528000000000e-10 -3.078081521678e-01 + 5.628000000000e-10 -2.535787813503e-01 + 5.728000000000e-10 -1.541764927596e-01 + 5.828000000000e-10 -3.077048554081e-02 + 5.928000000000e-10 8.832790620553e-02 + 6.028000000000e-10 1.816551916875e-01 + 6.128000000000e-10 2.455879975104e-01 + 6.228000000000e-10 2.847911932982e-01 + 6.328000000000e-10 3.076677363016e-01 + 6.428000000000e-10 3.192371229053e-01 + 6.528000000000e-10 3.077778412262e-01 + 6.628000000000e-10 2.534819327505e-01 + 6.728000000000e-10 1.541683138663e-01 + 6.828000000000e-10 3.070155435378e-02 + 6.928000000000e-10 -8.831320560130e-02 + 7.028000000000e-10 -1.817038543937e-01 + 7.128000000000e-10 -2.455619958387e-01 + 7.228000000000e-10 -2.848320347671e-01 + 7.328000000000e-10 -3.076358698550e-01 + 7.428000000000e-10 -3.192710667609e-01 + 7.528000000000e-10 -3.077409972388e-01 + 7.628000000000e-10 -2.535098012890e-01 + 7.728000000000e-10 -1.541282589474e-01 + 7.828000000000e-10 -3.072672689244e-02 + 7.928000000000e-10 8.835148526653e-02 + 8.028000000000e-10 1.816795669555e-01 + 8.128000000000e-10 2.455984246601e-01 + 8.228000000000e-10 2.848062931006e-01 + 8.328000000000e-10 3.076705916890e-01 + 8.428000000000e-10 3.192450073559e-01 + 8.528000000000e-10 3.077736319697e-01 + 8.628000000000e-10 2.534831121829e-01 + 8.728000000000e-10 1.541590953584e-01 + 8.828000000000e-10 3.069946612700e-02 + 8.928000000000e-10 -8.832341199891e-02 + 9.028000000000e-10 -1.817063952021e-01 + 9.128000000000e-10 -2.455714256322e-01 + 9.228000000000e-10 -2.848333922463e-01 + 9.328000000000e-10 -3.076440936715e-01 + 9.428000000000e-10 -3.192716274515e-01 + 9.528000000000e-10 -3.077481608676e-01 + 9.628000000000e-10 -2.535093614867e-01 + 9.728000000000e-10 -1.541340765567e-01 + 9.828000000000e-10 -3.072486745089e-02 + 9.928000000000e-10 8.834711873249e-02 + 1.000000000000e-09 1.586239577417e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/conditions.yaml new file mode 100644 index 00000000..c1562ae5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 4 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_04 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/CML_core_tb.sch new file mode 100644 index 00000000..b143b8ab --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/CML_core_tb_5.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/CML_core_tb_5.data new file mode 100644 index 00000000..b4ed17dd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/CML_core_tb_5.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.722799425151e-01 + 1.728000000000e-10 -1.701277707773e-01 + 1.828000000000e-10 -4.252496989706e-02 + 1.928000000000e-10 8.092536896213e-02 + 2.028000000000e-10 1.785199933375e-01 + 2.128000000000e-10 2.463984181452e-01 + 2.228000000000e-10 2.885755113271e-01 + 2.328000000000e-10 3.131967480955e-01 + 2.428000000000e-10 3.255285716483e-01 + 2.528000000000e-10 3.143820454109e-01 + 2.628000000000e-10 2.595824958850e-01 + 2.728000000000e-10 1.585585813323e-01 + 2.828000000000e-10 3.254606172598e-02 + 2.928000000000e-10 -8.921916265210e-02 + 3.028000000000e-10 -1.857143058967e-01 + 3.128000000000e-10 -2.524588707093e-01 + 3.228000000000e-10 -2.937876617757e-01 + 3.328000000000e-10 -3.173655773168e-01 + 3.428000000000e-10 -3.288566343508e-01 + 3.528000000000e-10 -3.166123605828e-01 + 3.628000000000e-10 -2.609360611345e-01 + 3.728000000000e-10 -1.589355414621e-01 + 3.828000000000e-10 -3.237621747627e-02 + 3.928000000000e-10 8.990939637816e-02 + 4.028000000000e-10 1.864994737191e-01 + 4.128000000000e-10 2.533636311879e-01 + 4.228000000000e-10 2.945633129641e-01 + 4.328000000000e-10 3.182197832362e-01 + 4.428000000000e-10 3.296245618008e-01 + 4.528000000000e-10 3.174841059207e-01 + 4.628000000000e-10 2.616780558587e-01 + 4.728000000000e-10 1.596622360522e-01 + 4.828000000000e-10 3.287681921596e-02 + 4.928000000000e-10 -8.943999963453e-02 + 5.028000000000e-10 -1.862066308093e-01 + 5.128000000000e-10 -2.530527908612e-01 + 5.228000000000e-10 -2.943931136832e-01 + 5.328000000000e-10 -3.180152021024e-01 + 5.428000000000e-10 -3.295545667130e-01 + 5.528000000000e-10 -3.173812952412e-01 + 5.628000000000e-10 -2.617027726155e-01 + 5.728000000000e-10 -1.596411992093e-01 + 5.828000000000e-10 -3.295895028258e-02 + 5.928000000000e-10 8.942267434718e-02 + 6.028000000000e-10 1.861105403656e-01 + 6.128000000000e-10 2.530344325895e-01 + 6.228000000000e-10 2.943051008579e-01 + 6.328000000000e-10 3.180051485103e-01 + 6.428000000000e-10 3.294737915539e-01 + 6.528000000000e-10 3.173744791022e-01 + 6.628000000000e-10 2.616291881364e-01 + 6.728000000000e-10 1.596450333001e-01 + 6.828000000000e-10 3.290088244348e-02 + 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-3.179838696148e-01 + 9.428000000000e-10 -3.295076633013e-01 + 9.528000000000e-10 -3.173492560727e-01 + 9.628000000000e-10 -2.616577755083e-01 + 9.728000000000e-10 -1.596163947717e-01 + 9.828000000000e-10 -3.292583900074e-02 + 9.928000000000e-10 8.943518431692e-02 + 1.000000000000e-09 1.621529465729e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/conditions.yaml new file mode 100644 index 00000000..ae5c0488 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 5 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_05 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/CML_core_tb.sch new file mode 100644 index 00000000..ff91eaf0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/CML_core_tb_6.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/CML_core_tb_6.data new file mode 100644 index 00000000..6b24d1d6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/CML_core_tb_6.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.622644182692e-01 + 1.728000000000e-10 -1.962653738736e-01 + 1.828000000000e-10 -5.712895575235e-03 + 1.928000000000e-10 1.510345047594e-01 + 2.028000000000e-10 2.432775412534e-01 + 2.128000000000e-10 2.772000132926e-01 + 2.228000000000e-10 3.161630086256e-01 + 2.328000000000e-10 3.654121904616e-01 + 2.428000000000e-10 4.070200809677e-01 + 2.528000000000e-10 4.211809118313e-01 + 2.628000000000e-10 3.552666659990e-01 + 2.728000000000e-10 1.954111420719e-01 + 2.828000000000e-10 7.499275151763e-03 + 2.928000000000e-10 -1.488912332472e-01 + 3.028000000000e-10 -2.420325529570e-01 + 3.128000000000e-10 -2.768171400503e-01 + 3.228000000000e-10 -3.164103191401e-01 + 3.328000000000e-10 -3.656815561297e-01 + 3.428000000000e-10 -4.072561733660e-01 + 3.528000000000e-10 -4.210637971044e-01 + 3.628000000000e-10 -3.548415521036e-01 + 3.728000000000e-10 -1.946286859654e-01 + 3.828000000000e-10 -6.746438981043e-03 + 3.928000000000e-10 1.496127957227e-01 + 4.028000000000e-10 2.425057762271e-01 + 4.128000000000e-10 2.772590268750e-01 + 4.228000000000e-10 3.167075169816e-01 + 4.328000000000e-10 3.660182242119e-01 + 4.428000000000e-10 4.074726111052e-01 + 4.528000000000e-10 4.212975956202e-01 + 4.628000000000e-10 3.549573822535e-01 + 4.728000000000e-10 1.947835560361e-01 + 4.828000000000e-10 6.801482567115e-03 + 4.928000000000e-10 -1.495086456760e-01 + 5.028000000000e-10 -2.424863730465e-01 + 5.128000000000e-10 -2.771744431737e-01 + 5.228000000000e-10 -3.166940000076e-01 + 5.328000000000e-10 -3.659398771497e-01 + 5.428000000000e-10 -4.074689465730e-01 + 5.528000000000e-10 -4.212394549000e-01 + 5.628000000000e-10 -3.549741510035e-01 + 5.728000000000e-10 -1.947436351784e-01 + 5.828000000000e-10 -6.830080160870e-03 + 5.928000000000e-10 1.495407150967e-01 + 6.028000000000e-10 2.424570295697e-01 + 6.128000000000e-10 2.772066160972e-01 + 6.228000000000e-10 3.166654934082e-01 + 6.328000000000e-10 3.659723864247e-01 + 6.428000000000e-10 4.074416211051e-01 + 6.528000000000e-10 4.212697301261e-01 + 6.628000000000e-10 3.549467093259e-01 + 6.728000000000e-10 1.947718238583e-01 + 6.828000000000e-10 6.800951177238e-03 + 6.928000000000e-10 -1.495148390529e-01 + 7.028000000000e-10 -2.424852043575e-01 + 7.128000000000e-10 -2.771809105751e-01 + 7.228000000000e-10 -3.166930947909e-01 + 7.328000000000e-10 -3.659459016360e-01 + 7.428000000000e-10 -4.074677461547e-01 + 7.528000000000e-10 -4.212442717757e-01 + 7.628000000000e-10 -3.549717520551e-01 + 7.728000000000e-10 -1.947463263521e-01 + 7.828000000000e-10 -6.825916545420e-03 + 7.928000000000e-10 1.495385751436e-01 + 8.028000000000e-10 2.424609931904e-01 + 8.128000000000e-10 2.772040406871e-01 + 8.228000000000e-10 3.166687905139e-01 + 8.328000000000e-10 3.659694951712e-01 + 8.428000000000e-10 4.074447010218e-01 + 8.528000000000e-10 4.212671408417e-01 + 8.628000000000e-10 3.549498827484e-01 + 8.728000000000e-10 1.947689363825e-01 + 8.828000000000e-10 6.803756635994e-03 + 8.928000000000e-10 -1.495176738691e-01 + 9.028000000000e-10 -2.424825342063e-01 + 9.128000000000e-10 -2.771836734306e-01 + 9.228000000000e-10 -3.166902103892e-01 + 9.328000000000e-10 -3.659485359213e-01 + 9.428000000000e-10 -4.074650210911e-01 + 9.528000000000e-10 -4.212469657833e-01 + 9.628000000000e-10 -3.549694058275e-01 + 9.728000000000e-10 -1.947487958951e-01 + 9.828000000000e-10 -6.823236278537e-03 + 9.928000000000e-10 1.495363177485e-01 + 1.000000000000e-09 2.250264100511e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/conditions.yaml new file mode 100644 index 00000000..e20b175a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 6 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_06 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/CML_core_tb.sch new file mode 100644 index 00000000..f2ee83e7 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/CML_core_tb_7.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/CML_core_tb_7.data new file mode 100644 index 00000000..1453012b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/CML_core_tb_7.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.668500025046e-01 + 1.728000000000e-10 -1.978704758130e-01 + 1.828000000000e-10 -3.069550951996e-03 + 1.928000000000e-10 1.561389387989e-01 + 2.028000000000e-10 2.488697408913e-01 + 2.128000000000e-10 2.833379270136e-01 + 2.228000000000e-10 3.221467647695e-01 + 2.328000000000e-10 3.723176028273e-01 + 2.428000000000e-10 4.147931582649e-01 + 2.528000000000e-10 4.286646301121e-01 + 2.628000000000e-10 3.614677855799e-01 + 2.728000000000e-10 1.982726052647e-01 + 2.828000000000e-10 5.580533140739e-03 + 2.928000000000e-10 -1.536551403474e-01 + 3.028000000000e-10 -2.474729097395e-01 + 3.128000000000e-10 -2.827981749211e-01 + 3.228000000000e-10 -3.222400643179e-01 + 3.328000000000e-10 -3.724510578191e-01 + 3.428000000000e-10 -4.149487937489e-01 + 3.528000000000e-10 -4.285094572794e-01 + 3.628000000000e-10 -3.610716711123e-01 + 3.728000000000e-10 -1.975613483211e-01 + 3.828000000000e-10 -4.936396792217e-03 + 3.928000000000e-10 1.542720670721e-01 + 4.028000000000e-10 2.478554934965e-01 + 4.128000000000e-10 2.831768205427e-01 + 4.228000000000e-10 3.224764565266e-01 + 4.328000000000e-10 3.727376628527e-01 + 4.428000000000e-10 4.151128450004e-01 + 4.528000000000e-10 4.287030398326e-01 + 4.628000000000e-10 3.611465460996e-01 + 4.728000000000e-10 1.976871290976e-01 + 4.828000000000e-10 4.962067120498e-03 + 4.928000000000e-10 -1.541857483448e-01 + 5.028000000000e-10 -2.478549856990e-01 + 5.128000000000e-10 -2.831031432303e-01 + 5.228000000000e-10 -3.224786212940e-01 + 5.328000000000e-10 -3.726675199031e-01 + 5.428000000000e-10 -4.151222726988e-01 + 5.528000000000e-10 -4.286496175832e-01 + 5.628000000000e-10 -3.611719348809e-01 + 5.728000000000e-10 -1.976471175954e-01 + 5.828000000000e-10 -4.995016715658e-03 + 5.928000000000e-10 1.542195273485e-01 + 6.028000000000e-10 2.478226151197e-01 + 6.128000000000e-10 2.831371441394e-01 + 6.228000000000e-10 3.224465270882e-01 + 6.328000000000e-10 3.727020829784e-01 + 6.428000000000e-10 4.150919188021e-01 + 6.528000000000e-10 4.286821395136e-01 + 6.628000000000e-10 3.611419365066e-01 + 6.728000000000e-10 1.976777927703e-01 + 6.828000000000e-10 4.963507878799e-03 + 6.928000000000e-10 -1.541913949207e-01 + 7.028000000000e-10 -2.478529800499e-01 + 7.128000000000e-10 -2.831092109235e-01 + 7.228000000000e-10 -3.224762894768e-01 + 7.328000000000e-10 -3.726728668334e-01 + 7.428000000000e-10 -4.151201370880e-01 + 7.528000000000e-10 -4.286543531433e-01 + 7.628000000000e-10 -3.611692599178e-01 + 7.728000000000e-10 -1.976499135935e-01 + 7.828000000000e-10 -4.990471824028e-03 + 7.928000000000e-10 1.542171227717e-01 + 8.028000000000e-10 2.478269854332e-01 + 8.128000000000e-10 2.831343470853e-01 + 8.228000000000e-10 3.224500362551e-01 + 8.328000000000e-10 3.726987138014e-01 + 8.428000000000e-10 4.150953468135e-01 + 8.528000000000e-10 4.286792233560e-01 + 8.628000000000e-10 3.611455588852e-01 + 8.728000000000e-10 1.976743961081e-01 + 8.828000000000e-10 4.966432661841e-03 + 8.928000000000e-10 -1.541946484524e-01 + 9.028000000000e-10 -2.478502288236e-01 + 9.128000000000e-10 -2.831123474050e-01 + 9.228000000000e-10 -3.224731331421e-01 + 9.328000000000e-10 -3.726757720747e-01 + 9.428000000000e-10 -4.151172388981e-01 + 9.528000000000e-10 -4.286573581279e-01 + 9.628000000000e-10 -3.611667698498e-01 + 9.728000000000e-10 -1.976525646923e-01 + 9.828000000000e-10 -4.987471597641e-03 + 9.928000000000e-10 1.542147143463e-01 + 1.000000000000e-09 2.301006397866e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/conditions.yaml new file mode 100644 index 00000000..a6f6017c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 7 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_07 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/CML_core_tb.sch new file mode 100644 index 00000000..02c1ba11 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/CML_core_tb_8.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/CML_core_tb_8.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/CML_core_tb_8.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 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8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/conditions.yaml new file mode 100644 index 00000000..1d7df575 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 8 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_08 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/CML_core_tb.sch new file mode 100644 index 00000000..bb89ef86 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/CML_core_tb_9.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/CML_core_tb_9.data new file mode 100644 index 00000000..73c31d13 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/CML_core_tb_9.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.445927026449e-01 + 1.728000000000e-10 -1.889320969581e-01 + 1.828000000000e-10 -5.355234564888e-03 + 1.928000000000e-10 1.489911128277e-01 + 2.028000000000e-10 2.434822449071e-01 + 2.128000000000e-10 2.838702060450e-01 + 2.228000000000e-10 3.202156401988e-01 + 2.328000000000e-10 3.629401474789e-01 + 2.428000000000e-10 3.990998051164e-01 + 2.528000000000e-10 4.099063275401e-01 + 2.628000000000e-10 3.477923521709e-01 + 2.728000000000e-10 1.968519788675e-01 + 2.828000000000e-10 1.493750763318e-02 + 2.928000000000e-10 -1.398437743336e-01 + 3.028000000000e-10 -2.362338093992e-01 + 3.128000000000e-10 -2.782887085314e-01 + 3.228000000000e-10 -3.158910292643e-01 + 3.328000000000e-10 -3.590893499920e-01 + 3.428000000000e-10 -3.957248346768e-01 + 3.528000000000e-10 -4.069627998073e-01 + 3.628000000000e-10 -3.454070734708e-01 + 3.728000000000e-10 -1.948243362004e-01 + 3.828000000000e-10 -1.337926088934e-02 + 3.928000000000e-10 1.411472162204e-01 + 4.028000000000e-10 2.372231231196e-01 + 4.128000000000e-10 2.792284454069e-01 + 4.228000000000e-10 3.166817589057e-01 + 4.328000000000e-10 3.598702175634e-01 + 4.428000000000e-10 3.963375250752e-01 + 4.528000000000e-10 4.074753309124e-01 + 4.628000000000e-10 3.456854225481e-01 + 4.728000000000e-10 1.950177434222e-01 + 4.828000000000e-10 1.342430394201e-02 + 4.928000000000e-10 -1.410850608466e-01 + 5.028000000000e-10 -2.372286880899e-01 + 5.128000000000e-10 -2.791659662153e-01 + 5.228000000000e-10 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7.728000000000e-10 -1.949983704767e-01 + 7.828000000000e-10 -1.345872104163e-02 + 7.928000000000e-10 1.410962716693e-01 + 8.028000000000e-10 2.371963808526e-01 + 8.128000000000e-10 2.791814500218e-01 + 8.228000000000e-10 3.166396456569e-01 + 8.328000000000e-10 3.598191409746e-01 + 8.428000000000e-10 3.963069790813e-01 + 8.528000000000e-10 4.074488078929e-01 + 8.628000000000e-10 3.456858987705e-01 + 8.728000000000e-10 1.950166421641e-01 + 8.828000000000e-10 1.344025602045e-02 + 8.928000000000e-10 -1.410790665154e-01 + 9.028000000000e-10 -2.372142995262e-01 + 9.128000000000e-10 -2.791649325552e-01 + 9.228000000000e-10 -3.166573514474e-01 + 9.328000000000e-10 -3.598022359716e-01 + 9.428000000000e-10 -3.963236588924e-01 + 9.528000000000e-10 -4.074326778223e-01 + 9.628000000000e-10 -3.457016440453e-01 + 9.728000000000e-10 -1.950001702792e-01 + 9.828000000000e-10 -1.345633761364e-02 + 9.928000000000e-10 1.410945129066e-01 + 1.000000000000e-09 2.176807579100e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/conditions.yaml new file mode 100644 index 00000000..af466938 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 9 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_09 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/CML_core_tb.sch new file mode 100644 index 00000000..d8afeb55 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/CML_core_tb_10.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/CML_core_tb_10.data new file mode 100644 index 00000000..6f87c434 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/CML_core_tb_10.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.831577979118e-01 + 1.728000000000e-10 -1.548331321524e-01 + 1.828000000000e-10 2.954507991941e-03 + 1.928000000000e-10 1.412083661187e-01 + 2.028000000000e-10 2.303947789211e-01 + 2.128000000000e-10 2.725788032239e-01 + 2.228000000000e-10 3.064646814943e-01 + 2.328000000000e-10 3.412898568956e-01 + 2.428000000000e-10 3.692979025942e-01 + 2.528000000000e-10 3.751979264520e-01 + 2.628000000000e-10 3.186495551608e-01 + 2.728000000000e-10 1.849115684226e-01 + 2.828000000000e-10 2.146912258403e-02 + 2.928000000000e-10 -1.215319416200e-01 + 3.028000000000e-10 -2.147336364713e-01 + 3.128000000000e-10 -2.593628319189e-01 + 3.228000000000e-10 -2.947919001104e-01 + 3.328000000000e-10 -3.306034656465e-01 + 3.428000000000e-10 -3.598903423599e-01 + 3.528000000000e-10 -3.674806029527e-01 + 3.628000000000e-10 -3.131864519443e-01 + 3.728000000000e-10 -1.816607205648e-01 + 3.828000000000e-10 -2.002885045896e-02 + 3.928000000000e-10 1.219326732879e-01 + 4.028000000000e-10 2.146583452252e-01 + 4.128000000000e-10 2.593288859790e-01 + 4.228000000000e-10 2.947836961551e-01 + 4.328000000000e-10 3.305873089453e-01 + 4.428000000000e-10 3.597520160348e-01 + 4.528000000000e-10 3.672634041173e-01 + 4.628000000000e-10 3.128292575731e-01 + 4.728000000000e-10 1.812525079401e-01 + 4.828000000000e-10 1.956255085056e-02 + 4.928000000000e-10 -1.223539241893e-01 + 5.028000000000e-10 -2.150587893921e-01 + 5.128000000000e-10 -2.596440912838e-01 + 5.228000000000e-10 -2.950896959018e-01 + 5.328000000000e-10 -3.308452440946e-01 + 5.428000000000e-10 -3.600168265621e-01 + 5.528000000000e-10 -3.674687038170e-01 + 5.628000000000e-10 -3.130140501398e-01 + 5.728000000000e-10 -1.813584327872e-01 + 5.828000000000e-10 -1.965159115909e-02 + 5.928000000000e-10 1.223212864923e-01 + 6.028000000000e-10 2.150157103205e-01 + 6.128000000000e-10 2.596318060931e-01 + 6.228000000000e-10 2.950524078153e-01 + 6.328000000000e-10 3.308363963911e-01 + 6.428000000000e-10 3.599874022300e-01 + 6.528000000000e-10 3.674690181116e-01 + 6.628000000000e-10 3.129980588961e-01 + 6.728000000000e-10 1.813712653368e-01 + 6.828000000000e-10 1.964491680526e-02 + 6.928000000000e-10 -1.223023112353e-01 + 7.028000000000e-10 -2.150202483004e-01 + 7.128000000000e-10 -2.596144309164e-01 + 7.228000000000e-10 -2.950582886643e-01 + 7.328000000000e-10 -3.308199600200e-01 + 7.428000000000e-10 -3.599931640339e-01 + 7.528000000000e-10 -3.674538095645e-01 + 7.628000000000e-10 -3.130042913922e-01 + 7.728000000000e-10 -1.813570925598e-01 + 7.828000000000e-10 -1.965290666609e-02 + 7.928000000000e-10 1.223145971689e-01 + 8.028000000000e-10 2.150114430495e-01 + 8.128000000000e-10 2.596256780136e-01 + 8.228000000000e-10 2.950490452158e-01 + 8.328000000000e-10 3.308307530718e-01 + 8.428000000000e-10 3.599842799802e-01 + 8.528000000000e-10 3.674639698479e-01 + 8.628000000000e-10 3.129957925611e-01 + 8.728000000000e-10 1.813666711568e-01 + 8.828000000000e-10 1.964348030724e-02 + 8.928000000000e-10 -1.223056361887e-01 + 9.028000000000e-10 -2.150207890100e-01 + 9.128000000000e-10 -2.596171721225e-01 + 9.228000000000e-10 -2.950581404305e-01 + 9.328000000000e-10 -3.308221104591e-01 + 9.428000000000e-10 -3.599929167296e-01 + 9.528000000000e-10 -3.674557320782e-01 + 9.628000000000e-10 -3.130039671541e-01 + 9.728000000000e-10 -1.813582011282e-01 + 9.828000000000e-10 -1.965175786777e-02 + 9.928000000000e-10 1.223137237372e-01 + 1.000000000000e-09 1.953703252853e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/conditions.yaml new file mode 100644 index 00000000..d2d42923 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 10 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_10 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/CML_core_tb.sch new file mode 100644 index 00000000..b8b739db --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/CML_core_tb_11.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/CML_core_tb_11.data new file mode 100644 index 00000000..1e62d263 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/CML_core_tb_11.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.857852225245e-01 + 1.728000000000e-10 -1.572533595452e-01 + 1.828000000000e-10 2.540381659783e-03 + 1.928000000000e-10 1.434374080790e-01 + 2.028000000000e-10 2.351272809546e-01 + 2.128000000000e-10 2.797956268783e-01 + 2.228000000000e-10 3.144243918962e-01 + 2.328000000000e-10 3.493618787392e-01 + 2.428000000000e-10 3.773715695689e-01 + 2.528000000000e-10 3.831823569325e-01 + 2.628000000000e-10 3.264482498061e-01 + 2.728000000000e-10 1.910530045686e-01 + 2.828000000000e-10 2.436059711742e-02 + 2.928000000000e-10 -1.220220612332e-01 + 3.028000000000e-10 -2.180809390746e-01 + 3.128000000000e-10 -2.653775774444e-01 + 3.228000000000e-10 -3.017848824321e-01 + 3.328000000000e-10 -3.379021858146e-01 + 3.428000000000e-10 -3.673696540777e-01 + 3.528000000000e-10 -3.751149757425e-01 + 3.628000000000e-10 -3.209083740174e-01 + 3.728000000000e-10 -1.878979131572e-01 + 3.828000000000e-10 -2.307531260616e-02 + 3.928000000000e-10 1.222703025101e-01 + 4.028000000000e-10 2.179003509445e-01 + 4.128000000000e-10 2.652908784701e-01 + 4.228000000000e-10 3.017672646237e-01 + 4.328000000000e-10 3.378931599738e-01 + 4.428000000000e-10 3.672390198172e-01 + 4.528000000000e-10 3.748903812400e-01 + 4.628000000000e-10 3.205316331029e-01 + 4.728000000000e-10 1.874647700937e-01 + 4.828000000000e-10 2.258819957166e-02 + 4.928000000000e-10 -1.227112688171e-01 + 5.028000000000e-10 -2.183172764214e-01 + 5.128000000000e-10 -2.656203742551e-01 + 5.228000000000e-10 -3.020800906145e-01 + 5.328000000000e-10 -3.381553362553e-01 + 5.428000000000e-10 -3.675051891202e-01 + 5.528000000000e-10 -3.750972240389e-01 + 5.628000000000e-10 -3.207148935088e-01 + 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2.655996099454e-01 + 8.228000000000e-10 3.020383466326e-01 + 8.328000000000e-10 3.381385294735e-01 + 8.428000000000e-10 3.674717742910e-01 + 8.528000000000e-10 3.750907045119e-01 + 8.628000000000e-10 3.206966644115e-01 + 8.728000000000e-10 1.875773616331e-01 + 8.828000000000e-10 2.266807684955e-02 + 8.928000000000e-10 -1.226628120211e-01 + 9.028000000000e-10 -2.182782381400e-01 + 9.128000000000e-10 -2.655915506047e-01 + 9.228000000000e-10 -3.020469590318e-01 + 9.328000000000e-10 -3.381303351991e-01 + 9.428000000000e-10 -3.674798958779e-01 + 9.528000000000e-10 -3.750829516380e-01 + 9.628000000000e-10 -3.207043265993e-01 + 9.728000000000e-10 -1.875693454762e-01 + 9.828000000000e-10 -2.267594148777e-02 + 9.928000000000e-10 1.226704651969e-01 + 1.000000000000e-09 1.977257563344e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/conditions.yaml new file mode 100644 index 00000000..eaf144f1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 11 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_11 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/CML_core_tb.sch new file mode 100644 index 00000000..263af6d1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/CML_core_tb_12.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/CML_core_tb_12.data new file mode 100644 index 00000000..16422ca1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/CML_core_tb_12.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.213526702696e-01 + 1.728000000000e-10 -1.557909441213e-01 + 1.828000000000e-10 3.476956205809e-02 + 1.928000000000e-10 1.811250151598e-01 + 2.028000000000e-10 2.596166993269e-01 + 2.128000000000e-10 2.853727091731e-01 + 2.228000000000e-10 3.254453264627e-01 + 2.328000000000e-10 3.792799604087e-01 + 2.428000000000e-10 4.176388066249e-01 + 2.528000000000e-10 4.205544301124e-01 + 2.628000000000e-10 3.463528198985e-01 + 2.728000000000e-10 1.792096076204e-01 + 2.828000000000e-10 -1.442396833933e-02 + 2.928000000000e-10 -1.649237711275e-01 + 3.028000000000e-10 -2.471596975948e-01 + 3.128000000000e-10 -2.748735614517e-01 + 3.228000000000e-10 -3.160128767795e-01 + 3.328000000000e-10 -3.707930594343e-01 + 3.428000000000e-10 -4.104823651943e-01 + 3.528000000000e-10 -4.153692056047e-01 + 3.628000000000e-10 -3.427931169871e-01 + 3.728000000000e-10 -1.769552164151e-01 + 3.828000000000e-10 1.590673093360e-02 + 3.928000000000e-10 1.658834812043e-01 + 4.028000000000e-10 2.479775600913e-01 + 4.128000000000e-10 2.756409688001e-01 + 4.228000000000e-10 3.168596600790e-01 + 4.328000000000e-10 3.715133147191e-01 + 4.428000000000e-10 4.111218222953e-01 + 4.528000000000e-10 4.157229971644e-01 + 4.628000000000e-10 3.430019798682e-01 + 4.728000000000e-10 1.769456026445e-01 + 4.828000000000e-10 -1.592886494610e-02 + 4.928000000000e-10 -1.659782283296e-01 + 5.028000000000e-10 -2.479947853664e-01 + 5.128000000000e-10 -2.756931315881e-01 + 5.228000000000e-10 -3.168416717549e-01 + 5.328000000000e-10 -3.715547211919e-01 + 5.428000000000e-10 -4.111034138799e-01 + 5.528000000000e-10 -4.157691346087e-01 + 5.628000000000e-10 -3.429925568898e-01 + 5.728000000000e-10 -1.770024985869e-01 + 5.828000000000e-10 1.592938202906e-02 + 5.928000000000e-10 1.659292038608e-01 + 6.028000000000e-10 2.480043512000e-01 + 6.128000000000e-10 2.756533285421e-01 + 6.228000000000e-10 3.168576585763e-01 + 6.328000000000e-10 3.715156583068e-01 + 6.428000000000e-10 4.111207690964e-01 + 6.528000000000e-10 4.157343976531e-01 + 6.628000000000e-10 3.430135347581e-01 + 6.728000000000e-10 1.769734665185e-01 + 6.828000000000e-10 -1.590652763180e-02 + 6.928000000000e-10 -1.659537152419e-01 + 7.028000000000e-10 -2.479812550746e-01 + 7.128000000000e-10 -2.756768834918e-01 + 7.228000000000e-10 -3.168350969677e-01 + 7.328000000000e-10 -3.715419152243e-01 + 7.428000000000e-10 -4.110983779981e-01 + 7.528000000000e-10 -4.157587194411e-01 + 7.628000000000e-10 -3.429901444601e-01 + 7.728000000000e-10 -1.769973775521e-01 + 7.828000000000e-10 1.592723735432e-02 + 7.928000000000e-10 1.659318535084e-01 + 8.028000000000e-10 2.480017799848e-01 + 8.128000000000e-10 2.756559811492e-01 + 8.228000000000e-10 3.168566227283e-01 + 8.328000000000e-10 3.715195500188e-01 + 8.428000000000e-10 4.111190536097e-01 + 8.528000000000e-10 4.157370668569e-01 + 8.628000000000e-10 3.430103710665e-01 + 8.728000000000e-10 1.769771675859e-01 + 8.828000000000e-10 -1.590770493918e-02 + 8.928000000000e-10 -1.659501582149e-01 + 9.028000000000e-10 -2.479827571068e-01 + 9.128000000000e-10 -2.756738772283e-01 + 9.228000000000e-10 -3.168377001445e-01 + 9.328000000000e-10 -3.715391180409e-01 + 9.428000000000e-10 -4.111007797151e-01 + 9.528000000000e-10 -4.157556639381e-01 + 9.628000000000e-10 -3.429919881202e-01 + 9.728000000000e-10 -1.769955652012e-01 + 9.828000000000e-10 1.592430721908e-02 + 9.928000000000e-10 1.659331850974e-01 + 1.000000000000e-09 2.332140069758e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/conditions.yaml new file mode 100644 index 00000000..3b43cbad --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 12 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_12 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/CML_core_tb.sch new file mode 100644 index 00000000..d1cccfba --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/CML_core_tb_13.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/CML_core_tb_13.data new file mode 100644 index 00000000..3dfcf241 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/CML_core_tb_13.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.365386572536e-01 + 1.728000000000e-10 -1.657072094068e-01 + 1.828000000000e-10 3.099865584261e-02 + 1.928000000000e-10 1.820426436768e-01 + 2.028000000000e-10 2.627018214462e-01 + 2.128000000000e-10 2.893736945719e-01 + 2.228000000000e-10 3.287984169352e-01 + 2.328000000000e-10 3.833334317825e-01 + 2.428000000000e-10 4.238785365972e-01 + 2.528000000000e-10 4.280322768716e-01 + 2.628000000000e-10 3.532409470363e-01 + 2.728000000000e-10 1.834641899168e-01 + 2.828000000000e-10 -1.474496205711e-02 + 2.928000000000e-10 -1.691349612478e-01 + 3.028000000000e-10 -2.530204867896e-01 + 3.128000000000e-10 -2.814070764654e-01 + 3.228000000000e-10 -3.218416847899e-01 + 3.328000000000e-10 -3.771799136100e-01 + 3.428000000000e-10 -4.187055626636e-01 + 3.528000000000e-10 -4.243036771430e-01 + 3.628000000000e-10 -3.506062035467e-01 + 3.728000000000e-10 -1.816763297909e-01 + 3.828000000000e-10 1.601938741723e-02 + 3.928000000000e-10 1.700087907901e-01 + 4.028000000000e-10 2.537596951165e-01 + 4.128000000000e-10 2.820887501770e-01 + 4.228000000000e-10 3.225625541805e-01 + 4.328000000000e-10 3.777928583784e-01 + 4.428000000000e-10 4.192485534625e-01 + 4.528000000000e-10 4.246080285894e-01 + 4.628000000000e-10 3.507916132015e-01 + 4.728000000000e-10 1.816929452641e-01 + 4.828000000000e-10 -1.601075067965e-02 + 4.928000000000e-10 -1.700562644838e-01 + 5.028000000000e-10 -2.537513990380e-01 + 5.128000000000e-10 -2.821086741965e-01 + 5.228000000000e-10 -3.225309737549e-01 + 5.328000000000e-10 -3.778081660132e-01 + 5.428000000000e-10 -4.192196231589e-01 + 5.528000000000e-10 -4.246325132019e-01 + 5.628000000000e-10 -3.507765562578e-01 + 5.728000000000e-10 -1.817315603141e-01 + 5.828000000000e-10 1.601468821266e-02 + 5.928000000000e-10 1.700220210141e-01 + 6.028000000000e-10 2.537612841477e-01 + 6.128000000000e-10 2.820810469197e-01 + 6.228000000000e-10 3.225454957468e-01 + 6.328000000000e-10 3.777800822765e-01 + 6.428000000000e-10 4.192350742948e-01 + 6.528000000000e-10 4.246071005326e-01 + 6.628000000000e-10 3.507940665347e-01 + 6.728000000000e-10 1.817094337521e-01 + 6.828000000000e-10 -1.599736953115e-02 + 6.928000000000e-10 -1.700405869499e-01 + 7.028000000000e-10 -2.537437685408e-01 + 7.128000000000e-10 -2.820988428465e-01 + 7.228000000000e-10 -3.225283133162e-01 + 7.328000000000e-10 -3.778004844844e-01 + 7.428000000000e-10 -4.192180216890e-01 + 7.528000000000e-10 -4.246257635725e-01 + 7.628000000000e-10 -3.507760422929e-01 + 7.728000000000e-10 -1.817278922025e-01 + 7.828000000000e-10 1.601285231965e-02 + 7.928000000000e-10 1.700238629540e-01 + 8.028000000000e-10 2.537592487741e-01 + 8.128000000000e-10 2.820829438407e-01 + 8.228000000000e-10 3.225445511573e-01 + 8.328000000000e-10 3.777829985044e-01 + 8.428000000000e-10 4.192337708379e-01 + 8.528000000000e-10 4.246090234999e-01 + 8.628000000000e-10 3.507916632731e-01 + 8.728000000000e-10 1.817122417436e-01 + 8.828000000000e-10 -1.599824136343e-02 + 8.928000000000e-10 -1.700377849177e-01 + 9.028000000000e-10 -2.537449127629e-01 + 9.128000000000e-10 -2.820965585668e-01 + 9.228000000000e-10 -3.225302446360e-01 + 9.328000000000e-10 -3.777982010874e-01 + 9.428000000000e-10 -4.192199753705e-01 + 9.528000000000e-10 -4.246232587341e-01 + 9.628000000000e-10 -3.507775800865e-01 + 9.728000000000e-10 -1.817263367247e-01 + 9.828000000000e-10 1.601066647660e-02 + 9.928000000000e-10 1.700248857455e-01 + 1.000000000000e-09 2.385375784000e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/conditions.yaml new file mode 100644 index 00000000..3b8a7fe4 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 13 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_13 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/CML_core_tb.sch new file mode 100644 index 00000000..65438946 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/CML_core_tb_14.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/CML_core_tb_14.data new file mode 100644 index 00000000..86f9b023 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/CML_core_tb_14.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.747912795524e-01 + 1.728000000000e-10 -1.327955908449e-01 + 1.828000000000e-10 3.931332790349e-02 + 1.928000000000e-10 1.782957289495e-01 + 2.028000000000e-10 2.573194188668e-01 + 2.128000000000e-10 2.870254911902e-01 + 2.228000000000e-10 3.228650321442e-01 + 2.328000000000e-10 3.690575149088e-01 + 2.428000000000e-10 4.023791308175e-01 + 2.528000000000e-10 4.034409994944e-01 + 2.628000000000e-10 3.332295993533e-01 + 2.728000000000e-10 1.767123870243e-01 + 2.828000000000e-10 -7.574880255958e-03 + 2.928000000000e-10 -1.550892096227e-01 + 3.028000000000e-10 -2.394679486139e-01 + 3.128000000000e-10 -2.715465054757e-01 + 3.228000000000e-10 -3.085580168164e-01 + 3.328000000000e-10 -3.560821219044e-01 + 3.428000000000e-10 -3.914831036325e-01 + 3.528000000000e-10 -3.956717314322e-01 + 3.628000000000e-10 -3.285929470428e-01 + 3.728000000000e-10 -1.747908753666e-01 + 3.828000000000e-10 7.882784627431e-03 + 3.928000000000e-10 1.545893087045e-01 + 4.028000000000e-10 2.389887597051e-01 + 4.128000000000e-10 2.712307710628e-01 + 4.228000000000e-10 3.085047043395e-01 + 4.328000000000e-10 3.559448484744e-01 + 4.428000000000e-10 3.913507819782e-01 + 4.528000000000e-10 3.953547803018e-01 + 4.628000000000e-10 3.282585464854e-01 + 4.728000000000e-10 1.743078825018e-01 + 4.828000000000e-10 -8.291328068348e-03 + 4.928000000000e-10 -1.550293895867e-01 + 5.028000000000e-10 -2.392804293874e-01 + 5.128000000000e-10 -2.715405217782e-01 + 5.228000000000e-10 -3.087067361985e-01 + 5.328000000000e-10 -3.562070457914e-01 + 5.428000000000e-10 -3.915132320474e-01 + 5.528000000000e-10 -3.955548280332e-01 + 5.628000000000e-10 -3.283427048941e-01 + 5.728000000000e-10 -1.744282326244e-01 + 5.828000000000e-10 8.270645751064e-03 + 5.928000000000e-10 1.549582711486e-01 + 6.028000000000e-10 2.392860039329e-01 + 6.128000000000e-10 2.714820836214e-01 + 6.228000000000e-10 3.087161022039e-01 + 6.328000000000e-10 3.561494137047e-01 + 6.428000000000e-10 3.915273490759e-01 + 6.528000000000e-10 3.955079501007e-01 + 6.628000000000e-10 3.283677191723e-01 + 6.728000000000e-10 1.743944727908e-01 + 6.828000000000e-10 -8.238033211244e-03 + 6.928000000000e-10 -1.549849820320e-01 + 7.028000000000e-10 -2.392533741503e-01 + 7.128000000000e-10 -2.715088112944e-01 + 7.228000000000e-10 -3.086845279612e-01 + 7.328000000000e-10 -3.561786907982e-01 + 7.428000000000e-10 -3.914967682891e-01 + 7.528000000000e-10 -3.955360247734e-01 + 7.628000000000e-10 -3.283379458960e-01 + 7.728000000000e-10 -1.744219452106e-01 + 7.828000000000e-10 8.266285029230e-03 + 7.928000000000e-10 1.549592969714e-01 + 8.028000000000e-10 2.392805186707e-01 + 8.128000000000e-10 2.714837558368e-01 + 8.228000000000e-10 3.087120651005e-01 + 8.328000000000e-10 3.561520690508e-01 + 8.428000000000e-10 3.915233230940e-01 + 8.528000000000e-10 3.955100606400e-01 + 8.628000000000e-10 3.283632493206e-01 + 8.728000000000e-10 1.743968536756e-01 + 8.828000000000e-10 -8.241845610385e-03 + 8.928000000000e-10 -1.549825747228e-01 + 9.028000000000e-10 -2.392568734068e-01 + 9.128000000000e-10 -2.715063119250e-01 + 9.228000000000e-10 -3.086881712182e-01 + 9.328000000000e-10 -3.561760305782e-01 + 9.428000000000e-10 -3.915002731039e-01 + 9.528000000000e-10 -3.955331724158e-01 + 9.628000000000e-10 -3.283409163093e-01 + 9.728000000000e-10 -1.744193777973e-01 + 9.828000000000e-10 8.263272108901e-03 + 9.928000000000e-10 1.549616575981e-01 + 1.000000000000e-09 2.229820050464e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/conditions.yaml new file mode 100644 index 00000000..13060032 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 14 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_14 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/CML_core_tb.sch new file mode 100644 index 00000000..4440b192 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/CML_core_tb_15.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/CML_core_tb_15.data new file mode 100644 index 00000000..7b2e7ab2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/CML_core_tb_15.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.957054612407e-01 + 1.728000000000e-10 -1.475216919691e-01 + 1.828000000000e-10 3.196996632833e-02 + 1.928000000000e-10 1.773696584526e-01 + 2.028000000000e-10 2.602670445343e-01 + 2.128000000000e-10 2.919684489720e-01 + 2.228000000000e-10 3.273690981683e-01 + 2.328000000000e-10 3.736661732429e-01 + 2.428000000000e-10 4.086769482098e-01 + 2.528000000000e-10 4.113258498473e-01 + 2.628000000000e-10 3.414272197123e-01 + 2.728000000000e-10 1.833836328070e-01 + 2.828000000000e-10 -4.501363849837e-03 + 2.928000000000e-10 -1.562318489881e-01 + 3.028000000000e-10 -2.435570784568e-01 + 3.128000000000e-10 -2.775386220390e-01 + 3.228000000000e-10 -3.142878056355e-01 + 3.328000000000e-10 -3.618442790176e-01 + 3.428000000000e-10 -3.986028140213e-01 + 3.528000000000e-10 -4.040381865127e-01 + 3.628000000000e-10 -3.369104214062e-01 + 3.728000000000e-10 -1.811830752063e-01 + 3.828000000000e-10 5.355128083595e-03 + 3.928000000000e-10 1.563630270676e-01 + 4.028000000000e-10 2.436522664355e-01 + 4.128000000000e-10 2.777202130414e-01 + 4.228000000000e-10 3.146716935396e-01 + 4.328000000000e-10 3.621309165835e-01 + 4.428000000000e-10 3.988648293319e-01 + 4.528000000000e-10 4.040567761896e-01 + 4.628000000000e-10 3.368362274946e-01 + 4.728000000000e-10 1.809052635954e-01 + 4.828000000000e-10 -5.606347307292e-03 + 4.928000000000e-10 -1.566747533637e-01 + 5.028000000000e-10 -2.438438929936e-01 + 5.128000000000e-10 -2.779365198916e-01 + 5.228000000000e-10 -3.147868656031e-01 + 5.328000000000e-10 -3.623069078218e-01 + 5.428000000000e-10 -3.989546307961e-01 + 5.528000000000e-10 -4.041975741324e-01 + 5.628000000000e-10 -3.368831845243e-01 + 5.728000000000e-10 -1.810020824460e-01 + 5.828000000000e-10 5.593858826262e-03 + 5.928000000000e-10 1.566090374935e-01 + 6.028000000000e-10 2.438493522755e-01 + 6.128000000000e-10 2.778818285943e-01 + 6.228000000000e-10 3.147972496077e-01 + 6.328000000000e-10 3.622530927659e-01 + 6.428000000000e-10 3.989689895438e-01 + 6.528000000000e-10 4.041528360847e-01 + 6.628000000000e-10 3.369065350765e-01 + 6.728000000000e-10 1.809679655825e-01 + 6.828000000000e-10 -5.565139497590e-03 + 6.928000000000e-10 -1.566366178225e-01 + 7.028000000000e-10 -2.438204188033e-01 + 7.128000000000e-10 -2.779089356335e-01 + 7.228000000000e-10 -3.147686522157e-01 + 7.328000000000e-10 -3.622826637804e-01 + 7.428000000000e-10 -3.989411843085e-01 + 7.528000000000e-10 -4.041807678845e-01 + 7.628000000000e-10 -3.368790616195e-01 + 7.728000000000e-10 -1.809947630224e-01 + 7.828000000000e-10 5.591512634984e-03 + 7.928000000000e-10 1.566120178189e-01 + 8.028000000000e-10 2.438458933358e-01 + 8.128000000000e-10 2.778849719194e-01 + 8.228000000000e-10 3.147945034671e-01 + 8.328000000000e-10 3.622568751046e-01 + 8.428000000000e-10 3.989662140554e-01 + 8.528000000000e-10 4.041558823701e-01 + 8.628000000000e-10 3.369030769235e-01 + 8.728000000000e-10 1.809706945647e-01 + 8.828000000000e-10 -5.568483515763e-03 + 8.928000000000e-10 -1.566340912711e-01 + 9.028000000000e-10 -2.438236181184e-01 + 9.128000000000e-10 -2.779064153414e-01 + 9.228000000000e-10 -3.147718720666e-01 + 9.328000000000e-10 -3.622798572716e-01 + 9.428000000000e-10 -3.989444036153e-01 + 9.528000000000e-10 -4.041778978449e-01 + 9.628000000000e-10 -3.368819513246e-01 + 9.728000000000e-10 -1.809921012276e-01 + 9.828000000000e-10 5.588724287086e-03 + 9.928000000000e-10 1.566143682128e-01 + 1.000000000000e-09 2.267750497136e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/conditions.yaml new file mode 100644 index 00000000..e707938e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 15 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_15 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/CML_core_tb.sch new file mode 100644 index 00000000..ce179453 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/CML_core_tb_16.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/CML_core_tb_16.data new file mode 100644 index 00000000..a01deb89 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/CML_core_tb_16.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.908985659112e-01 + 1.728000000000e-10 -9.049079150817e-02 + 1.828000000000e-10 3.945873683219e-02 + 1.928000000000e-10 1.521437177417e-01 + 2.028000000000e-10 2.220068772324e-01 + 2.128000000000e-10 2.535092334052e-01 + 2.228000000000e-10 2.861973397174e-01 + 2.328000000000e-10 3.239843013312e-01 + 2.428000000000e-10 3.520113017607e-01 + 2.528000000000e-10 3.540468115658e-01 + 2.628000000000e-10 2.949447709683e-01 + 2.728000000000e-10 1.587983397866e-01 + 2.828000000000e-10 -6.865354773069e-03 + 2.928000000000e-10 -1.448078480843e-01 + 3.028000000000e-10 -2.275605338030e-01 + 3.128000000000e-10 -2.625604064747e-01 + 3.228000000000e-10 -2.958552078644e-01 + 3.328000000000e-10 -3.351711406638e-01 + 3.428000000000e-10 -3.644984224381e-01 + 3.528000000000e-10 -3.669950471097e-01 + 3.628000000000e-10 -3.072796408874e-01 + 3.728000000000e-10 -1.699866077827e-01 + 3.828000000000e-10 -2.842045316933e-03 + 3.928000000000e-10 1.365086891956e-01 + 4.028000000000e-10 2.207869920157e-01 + 4.128000000000e-10 2.567713461579e-01 + 4.228000000000e-10 2.907030026757e-01 + 4.328000000000e-10 3.302687598301e-01 + 4.428000000000e-10 3.600803190405e-01 + 4.528000000000e-10 3.632331450943e-01 + 4.628000000000e-10 3.045482678871e-01 + 4.728000000000e-10 1.682698274629e-01 + 4.828000000000e-10 2.058504292284e-03 + 4.928000000000e-10 -1.367871396964e-01 + 5.028000000000e-10 -2.207717990252e-01 + 5.128000000000e-10 -2.567684885934e-01 + 5.228000000000e-10 -2.906651825463e-01 + 5.328000000000e-10 -3.302494358660e-01 + 5.428000000000e-10 -3.599712284157e-01 + 5.528000000000e-10 -3.631239508150e-01 + 5.628000000000e-10 -3.043584109358e-01 + 5.728000000000e-10 -1.680958385636e-01 + 5.828000000000e-10 -1.834034512727e-03 + 5.928000000000e-10 1.369613450439e-01 + 6.028000000000e-10 2.209618957221e-01 + 6.128000000000e-10 2.568952536478e-01 + 6.228000000000e-10 2.908171185353e-01 + 6.328000000000e-10 3.303549214919e-01 + 6.428000000000e-10 3.601082390759e-01 + 6.528000000000e-10 3.632059905221e-01 + 6.628000000000e-10 3.044557238628e-01 + 6.728000000000e-10 1.681292777859e-01 + 6.828000000000e-10 1.882442241730e-03 + 6.928000000000e-10 -1.369637862409e-01 + 7.028000000000e-10 -2.209363992802e-01 + 7.128000000000e-10 -2.569065829626e-01 + 7.228000000000e-10 -2.907936706940e-01 + 7.328000000000e-10 -3.303682701482e-01 + 7.428000000000e-10 -3.600879594395e-01 + 7.528000000000e-10 -3.632220959958e-01 + 7.628000000000e-10 -3.044401007882e-01 + 7.728000000000e-10 -1.681486407544e-01 + 7.828000000000e-10 -1.870004957548e-03 + 7.928000000000e-10 1.369437070838e-01 + 8.028000000000e-10 2.209481957039e-01 + 8.128000000000e-10 2.568879030180e-01 + 8.228000000000e-10 2.908064848389e-01 + 8.328000000000e-10 3.303493303219e-01 + 8.428000000000e-10 3.601006147126e-01 + 8.528000000000e-10 3.632041339109e-01 + 8.628000000000e-10 3.044528281549e-01 + 8.728000000000e-10 1.681322760827e-01 + 8.828000000000e-10 1.883536763259e-03 + 8.928000000000e-10 -1.369582535540e-01 + 9.028000000000e-10 -2.209346296842e-01 + 9.128000000000e-10 -2.569016830366e-01 + 9.228000000000e-10 -2.907925936742e-01 + 9.328000000000e-10 -3.303636164667e-01 + 9.428000000000e-10 -3.600871302257e-01 + 9.528000000000e-10 -3.632178492939e-01 + 9.628000000000e-10 -3.044398392752e-01 + 9.728000000000e-10 -1.681454261603e-01 + 9.828000000000e-10 -1.870628705438e-03 + 9.928000000000e-10 1.369459433541e-01 + 1.000000000000e-09 2.037746084522e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/conditions.yaml new file mode 100644 index 00000000..fcc6fd72 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 16 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_16 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/CML_core_tb.sch new file mode 100644 index 00000000..e5aa74f9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/CML_core_tb_17.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/CML_core_tb_17.data new file mode 100644 index 00000000..c21b093d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/CML_core_tb_17.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.135873679018e-01 + 1.728000000000e-10 -1.054229355639e-01 + 1.828000000000e-10 3.485798650969e-02 + 1.928000000000e-10 1.569675139767e-01 + 2.028000000000e-10 2.330635404696e-01 + 2.128000000000e-10 2.680443549179e-01 + 2.228000000000e-10 3.014044829899e-01 + 2.328000000000e-10 3.394080314353e-01 + 2.428000000000e-10 3.679529618424e-01 + 2.528000000000e-10 3.700593040123e-01 + 2.628000000000e-10 3.097824620429e-01 + 2.728000000000e-10 1.706514675999e-01 + 2.828000000000e-10 3.558070014658e-04 + 2.928000000000e-10 -1.428409974599e-01 + 3.028000000000e-10 -2.298289579719e-01 + 3.128000000000e-10 -2.678794741753e-01 + 3.228000000000e-10 -3.017454056957e-01 + 3.328000000000e-10 -3.410620518407e-01 + 3.428000000000e-10 -3.712405389398e-01 + 3.528000000000e-10 -3.749327973471e-01 + 3.628000000000e-10 -3.157484466493e-01 + 3.728000000000e-10 -1.773087198166e-01 + 3.828000000000e-10 -7.070252178339e-03 + 3.928000000000e-10 1.364462941621e-01 + 4.028000000000e-10 2.243241068758e-01 + 4.128000000000e-10 2.631279769125e-01 + 4.228000000000e-10 2.976097246349e-01 + 4.328000000000e-10 3.371159716785e-01 + 4.428000000000e-10 3.676405775058e-01 + 4.528000000000e-10 3.717787254056e-01 + 4.628000000000e-10 3.133854979421e-01 + 4.728000000000e-10 1.756870158595e-01 + 4.828000000000e-10 6.171257018760e-03 + 4.928000000000e-10 -1.369680995621e-01 + 5.028000000000e-10 -2.245781248931e-01 + 5.128000000000e-10 -2.633829468620e-01 + 5.228000000000e-10 -2.978042748481e-01 + 5.328000000000e-10 -3.373348877854e-01 + 5.428000000000e-10 -3.677584906255e-01 + 5.528000000000e-10 -3.718812762918e-01 + 5.628000000000e-10 -3.133649557524e-01 + 5.728000000000e-10 -1.756479312047e-01 + 5.828000000000e-10 -6.040608056278e-03 + 5.928000000000e-10 1.370690415770e-01 + 6.028000000000e-10 2.247181767783e-01 + 6.128000000000e-10 2.634617265965e-01 + 6.228000000000e-10 2.979157296699e-01 + 6.328000000000e-10 3.373958940353e-01 + 6.428000000000e-10 3.678612954525e-01 + 6.528000000000e-10 3.719309221475e-01 + 6.628000000000e-10 3.134447453066e-01 + 6.728000000000e-10 1.756687688086e-01 + 6.828000000000e-10 6.090200135509e-03 + 6.928000000000e-10 -1.370702307281e-01 + 7.028000000000e-10 -2.246847420648e-01 + 7.128000000000e-10 -2.634701196121e-01 + 7.228000000000e-10 -2.978849158722e-01 + 7.328000000000e-10 -3.374068878437e-01 + 7.428000000000e-10 -3.678336110941e-01 + 7.528000000000e-10 -3.719446503824e-01 + 7.628000000000e-10 -3.134227431793e-01 + 7.728000000000e-10 -1.756868885858e-01 + 7.828000000000e-10 -6.072676723321e-03 + 7.928000000000e-10 1.370503070743e-01 + 8.028000000000e-10 2.247004966695e-01 + 8.128000000000e-10 2.634509722982e-01 + 8.228000000000e-10 2.979013793804e-01 + 8.328000000000e-10 3.373870921905e-01 + 8.428000000000e-10 3.678495602861e-01 + 8.528000000000e-10 3.719256264749e-01 + 8.628000000000e-10 3.134381864470e-01 + 8.728000000000e-10 1.756688935561e-01 + 8.828000000000e-10 6.088345643719e-03 + 8.928000000000e-10 -1.370666831053e-01 + 9.028000000000e-10 -2.246851372638e-01 + 9.128000000000e-10 -2.634666121684e-01 + 9.228000000000e-10 -2.978856025968e-01 + 9.328000000000e-10 -3.374033621769e-01 + 9.428000000000e-10 -3.678342837151e-01 + 9.528000000000e-10 -3.719412125322e-01 + 9.628000000000e-10 -3.134235677100e-01 + 9.728000000000e-10 -1.756838495744e-01 + 9.828000000000e-10 -6.073781243164e-03 + 9.928000000000e-10 1.370527135588e-01 + 1.000000000000e-09 2.065229990524e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/conditions.yaml new file mode 100644 index 00000000..c97e299d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 17 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/run_17 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..a4eb11a9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,19 @@ +run,corner,temperature,vdd,time,vo_diff,frequency +run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.111e-01, -1.870e-01, -3.563e-02, …]",4.722e+09 +run_01,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.876e-01, -3.217e-02, …]",4.722e+09 +run_02,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.915e-01, -1.780e-01, -3.803e-02, …]",4.722e+09 +run_03,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.959e-01, -1.792e-01, -3.599e-02, …]",4.722e+09 +run_04,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.689e-01, -1.692e-01, -4.423e-02, …]",4.722e+09 +run_05,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.723e-01, -1.701e-01, -4.252e-02, …]",4.722e+09 +run_06,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.623e-01, -1.963e-01, -5.713e-03, …]",4.722e+09 +run_07,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.669e-01, -1.979e-01, -3.070e-03, …]",4.722e+09 +run_08,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",4.722e+09 +run_09,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.446e-01, -1.889e-01, -5.355e-03, …]",4.722e+09 +run_10,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.832e-01, -1.548e-01, 2.955e-03, …]",4.722e+09 +run_11,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.858e-01, -1.573e-01, 2.540e-03, …]",4.722e+09 +run_12,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.214e-01, -1.558e-01, 3.477e-02, …]",4.722e+09 +run_13,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.365e-01, -1.657e-01, 3.100e-02, …]",4.722e+09 +run_14,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.748e-01, -1.328e-01, 3.931e-02, …]",4.722e+09 +run_15,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.957e-01, -1.475e-01, 3.197e-02, …]",4.722e+09 +run_16,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.909e-01, -9.049e-02, 3.946e-02, …]",4.722e+09 +run_17,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.136e-01, -1.054e-01, 3.486e-02, …]",4.722e+09 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..540c8d2a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/parameters/Frequency/simulation_summary.md @@ -0,0 +1,22 @@ +# Simulation Summary for Freq + +| run | corner | temperature | vdd | time | vo_diff | frequency | +| :-- | -----: | ----------: | --: | ---: | ------: | --------: | +| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.111e-01, -1.870e-01, -3.563e-02, …] | 4.722e+09 | +| run_01 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.876e-01, -3.217e-02, …] | 4.722e+09 | +| run_02 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.915e-01, -1.780e-01, -3.803e-02, …] | 4.722e+09 | +| run_03 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.959e-01, -1.792e-01, -3.599e-02, …] | 4.722e+09 | +| run_04 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.689e-01, -1.692e-01, -4.423e-02, …] | 4.722e+09 | +| run_05 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.723e-01, -1.701e-01, -4.252e-02, …] | 4.722e+09 | +| run_06 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.623e-01, -1.963e-01, -5.713e-03, …] | 4.722e+09 | +| run_07 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.669e-01, -1.979e-01, -3.070e-03, …] | 4.722e+09 | +| run_08 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 4.722e+09 | +| run_09 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.446e-01, -1.889e-01, -5.355e-03, …] | 4.722e+09 | +| run_10 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.832e-01, -1.548e-01, 2.955e-03, …] | 4.722e+09 | +| run_11 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.858e-01, -1.573e-01, 2.540e-03, …] | 4.722e+09 | +| run_12 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.214e-01, -1.558e-01, 3.477e-02, …] | 4.722e+09 | +| run_13 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.365e-01, -1.657e-01, 3.100e-02, …] | 4.722e+09 | +| run_14 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.748e-01, -1.328e-01, 3.931e-02, …] | 4.722e+09 | +| run_15 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.957e-01, -1.475e-01, 3.197e-02, …] | 4.722e+09 | +| run_16 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.909e-01, -9.049e-02, 3.946e-02, …] | 4.722e+09 | +| run_17 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.136e-01, -1.054e-01, 3.486e-02, …] | 4.722e+09 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/summary.md new file mode 100644 index 00000000..c08b3edd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-42-24/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | any | 4.722 GHz | any | 4.722 GHz | any | 4.722 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/frequency.png new file mode 100644 index 00000000..e4b0a21a Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/CML_core_tb.sch new file mode 100644 index 00000000..1d13f3f3 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/CML_core_tb_0.data new file mode 100644 index 00000000..4cb5b399 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.110742996065e-01 + 1.728000000000e-10 -1.869505717284e-01 + 1.828000000000e-10 -3.563037101706e-02 + 1.928000000000e-10 1.056708524540e-01 + 2.028000000000e-10 2.100393804445e-01 + 2.128000000000e-10 2.784249297688e-01 + 2.228000000000e-10 3.224310579067e-01 + 2.328000000000e-10 3.548600651170e-01 + 2.428000000000e-10 3.792482005271e-01 + 2.528000000000e-10 3.740820324036e-01 + 2.628000000000e-10 3.079440308227e-01 + 2.728000000000e-10 1.813826171807e-01 + 2.828000000000e-10 2.923027813912e-02 + 2.928000000000e-10 -1.118282325615e-01 + 3.028000000000e-10 -2.157337068367e-01 + 3.128000000000e-10 -2.829033176767e-01 + 3.228000000000e-10 -3.260714502323e-01 + 3.328000000000e-10 -3.577361248183e-01 + 3.428000000000e-10 -3.819104006606e-01 + 3.528000000000e-10 -3.764730474160e-01 + 3.628000000000e-10 -3.102968359246e-01 + 3.728000000000e-10 -1.832608913655e-01 + 3.828000000000e-10 -3.084931437320e-02 + 3.928000000000e-10 1.106163095990e-01 + 4.028000000000e-10 2.145714971977e-01 + 4.128000000000e-10 2.819937231053e-01 + 4.228000000000e-10 3.251740998910e-01 + 4.328000000000e-10 3.570946969464e-01 + 4.428000000000e-10 3.813004444382e-01 + 4.528000000000e-10 3.761230596147e-01 + 4.628000000000e-10 3.099646053412e-01 + 4.728000000000e-10 1.831473345022e-01 + 4.828000000000e-10 3.069401022130e-02 + 4.928000000000e-10 -1.106258411343e-01 + 5.028000000000e-10 -2.146793601179e-01 + 5.128000000000e-10 -2.820035552799e-01 + 5.228000000000e-10 -3.252909243829e-01 + 5.328000000000e-10 -3.570986338553e-01 + 5.428000000000e-10 -3.813904658256e-01 + 5.528000000000e-10 -3.760889514061e-01 + 5.628000000000e-10 -3.100114096943e-01 + 5.728000000000e-10 -1.830827247194e-01 + 5.828000000000e-10 -3.072480545922e-02 + 5.928000000000e-10 1.106906463094e-01 + 6.028000000000e-10 2.146493837568e-01 + 6.128000000000e-10 2.820610673881e-01 + 6.228000000000e-10 3.252525482967e-01 + 6.328000000000e-10 3.571504708749e-01 + 6.428000000000e-10 3.813516648295e-01 + 6.528000000000e-10 3.761390656738e-01 + 6.628000000000e-10 3.099742259389e-01 + 6.728000000000e-10 1.831331110808e-01 + 6.828000000000e-10 3.068765829312e-02 + 6.928000000000e-10 -1.106445812930e-01 + 7.028000000000e-10 -2.146859050297e-01 + 7.128000000000e-10 -2.820172231683e-01 + 7.228000000000e-10 -3.252905125649e-01 + 7.328000000000e-10 -3.571078709926e-01 + 7.428000000000e-10 -3.813893177320e-01 + 7.528000000000e-10 -3.760986555866e-01 + 7.628000000000e-10 -3.100117776476e-01 + 7.728000000000e-10 -1.830935153198e-01 + 7.828000000000e-10 -3.072484475908e-02 + 7.928000000000e-10 1.106810594907e-01 + 8.028000000000e-10 2.146507312123e-01 + 8.128000000000e-10 2.820530370402e-01 + 8.228000000000e-10 3.252547871433e-01 + 8.328000000000e-10 3.571432636036e-01 + 8.428000000000e-10 3.813547544577e-01 + 8.528000000000e-10 3.761324372121e-01 + 8.628000000000e-10 3.099775475493e-01 + 8.728000000000e-10 1.831274535707e-01 + 8.828000000000e-10 3.069175078476e-02 + 8.928000000000e-10 -1.106491559136e-01 + 9.028000000000e-10 -2.146821655528e-01 + 9.128000000000e-10 -2.820218639330e-01 + 9.228000000000e-10 -3.252864642203e-01 + 9.328000000000e-10 -3.571122611941e-01 + 9.428000000000e-10 -3.813854215351e-01 + 9.528000000000e-10 -3.761024723822e-01 + 9.628000000000e-10 -3.100075395903e-01 + 9.728000000000e-10 -1.830975404653e-01 + 9.828000000000e-10 -3.072097080048e-02 + 9.928000000000e-10 1.106770531472e-01 + 1.000000000000e-09 1.895325033433e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/conditions.yaml new file mode 100644 index 00000000..639ef15a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_00 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/CML_core_tb.sch new file mode 100644 index 00000000..331d9825 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/CML_core_tb_1.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/CML_core_tb_1.data new file mode 100644 index 00000000..2b8492c0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/CML_core_tb_1.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.098686002716e-01 + 1.728000000000e-10 -1.894560696460e-01 + 1.828000000000e-10 -4.059695742871e-02 + 1.928000000000e-10 9.940964501315e-02 + 2.028000000000e-10 2.033133834097e-01 + 2.128000000000e-10 2.719620830710e-01 + 2.228000000000e-10 3.163098950569e-01 + 2.328000000000e-10 3.491513279687e-01 + 2.428000000000e-10 3.741332087119e-01 + 2.528000000000e-10 3.700254590965e-01 + 2.628000000000e-10 3.062168938694e-01 + 2.728000000000e-10 1.827341653261e-01 + 2.828000000000e-10 3.280764574542e-02 + 2.928000000000e-10 -1.069769977212e-01 + 3.028000000000e-10 -2.102924295592e-01 + 3.128000000000e-10 -2.774748738503e-01 + 3.228000000000e-10 -3.207751929169e-01 + 3.328000000000e-10 -3.527202709264e-01 + 3.428000000000e-10 -3.774342269369e-01 + 3.528000000000e-10 -3.730540733905e-01 + 3.628000000000e-10 -3.091949741363e-01 + 3.728000000000e-10 -1.851642002832e-01 + 3.828000000000e-10 -3.487935842603e-02 + 3.928000000000e-10 1.053970083053e-01 + 4.028000000000e-10 2.088131472734e-01 + 4.128000000000e-10 2.762908135843e-01 + 4.228000000000e-10 3.196385089100e-01 + 4.328000000000e-10 3.518763575372e-01 + 4.428000000000e-10 3.766558038448e-01 + 4.528000000000e-10 3.725714207051e-01 + 4.628000000000e-10 3.087619830708e-01 + 4.728000000000e-10 1.849833837695e-01 + 4.828000000000e-10 3.467977975354e-02 + 4.928000000000e-10 -1.054340839288e-01 + 5.028000000000e-10 -2.089448612506e-01 + 5.128000000000e-10 -2.763231704068e-01 + 5.228000000000e-10 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7.728000000000e-10 -1.849285593480e-01 + 7.828000000000e-10 -3.470862903587e-02 + 7.928000000000e-10 1.054936381918e-01 + 8.028000000000e-10 2.089186129636e-01 + 8.128000000000e-10 2.763755879874e-01 + 8.228000000000e-10 3.197437164625e-01 + 8.328000000000e-10 3.519463479929e-01 + 8.428000000000e-10 3.767260853907e-01 + 8.528000000000e-10 3.725904126785e-01 + 8.628000000000e-10 3.087783440951e-01 + 8.728000000000e-10 1.849632167070e-01 + 8.828000000000e-10 3.467482549783e-02 + 8.928000000000e-10 -1.054610682584e-01 + 9.028000000000e-10 -2.089507846182e-01 + 9.128000000000e-10 -2.763436586770e-01 + 9.228000000000e-10 -3.197760754687e-01 + 9.328000000000e-10 -3.519146615050e-01 + 9.428000000000e-10 -3.767573997120e-01 + 9.528000000000e-10 -3.725597535055e-01 + 9.628000000000e-10 -3.088090609970e-01 + 9.728000000000e-10 -1.849326628321e-01 + 9.828000000000e-10 -3.470475490247e-02 + 9.928000000000e-10 1.054896146910e-01 + 1.000000000000e-09 1.838520001242e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/conditions.yaml new file mode 100644 index 00000000..130a337f --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 1 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_01 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/CML_core_tb.sch new file mode 100644 index 00000000..8024c6e1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/CML_core_tb_2.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/CML_core_tb_2.data new file mode 100644 index 00000000..b332ca2c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/CML_core_tb_2.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162797108708e-01 + 1.728000000000e-10 -1.875883768906e-01 + 1.828000000000e-10 -3.217177564589e-02 + 1.928000000000e-10 1.118453904517e-01 + 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-3.650560988894e-01 + 9.428000000000e-10 -3.897007143418e-01 + 9.528000000000e-10 -3.843858173814e-01 + 9.628000000000e-10 -3.162935974835e-01 + 9.728000000000e-10 -1.852064424274e-01 + 9.828000000000e-10 -2.888350905479e-02 + 9.928000000000e-10 1.152199079204e-01 + 1.000000000000e-09 1.954791142410e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/conditions.yaml new file mode 100644 index 00000000..1edc2819 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 2 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_02 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/CML_core_tb.sch new file mode 100644 index 00000000..915e81fc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/CML_core_tb_3.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/CML_core_tb_3.data new file mode 100644 index 00000000..6dccbfd6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/CML_core_tb_3.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.914571027454e-01 + 1.728000000000e-10 -1.780117263272e-01 + 1.828000000000e-10 -3.802564096594e-02 + 1.928000000000e-10 9.479025580261e-02 + 2.028000000000e-10 1.961220444980e-01 + 2.128000000000e-10 2.643669322964e-01 + 2.228000000000e-10 3.071498875260e-01 + 2.328000000000e-10 3.351667250191e-01 + 2.428000000000e-10 3.529478733093e-01 + 2.528000000000e-10 3.439767079911e-01 + 2.628000000000e-10 2.827109934029e-01 + 2.728000000000e-10 1.683025534555e-01 + 2.828000000000e-10 2.843266655337e-02 + 2.928000000000e-10 -1.036223502576e-01 + 3.028000000000e-10 -2.042863713809e-01 + 3.128000000000e-10 -2.713818104821e-01 + 3.228000000000e-10 -3.132717880322e-01 + 3.328000000000e-10 -3.402903477971e-01 + 3.428000000000e-10 -3.574262556597e-01 + 3.528000000000e-10 -3.476240566503e-01 + 3.628000000000e-10 -2.857203755187e-01 + 3.728000000000e-10 -1.703849236420e-01 + 3.828000000000e-10 -2.994825869373e-02 + 3.928000000000e-10 1.026817167876e-01 + 4.028000000000e-10 2.034750084544e-01 + 4.128000000000e-10 2.707812081585e-01 + 4.228000000000e-10 3.126503625184e-01 + 4.328000000000e-10 3.399043734480e-01 + 4.428000000000e-10 3.571021595385e-01 + 4.528000000000e-10 3.475896983741e-01 + 4.628000000000e-10 2.857411927694e-01 + 4.728000000000e-10 1.706053611761e-01 + 4.828000000000e-10 3.010795594348e-02 + 4.928000000000e-10 -1.024135388755e-01 + 5.028000000000e-10 -2.033190471438e-01 + 5.128000000000e-10 -2.705615444577e-01 + 5.228000000000e-10 -3.125558523975e-01 + 5.328000000000e-10 -3.397330193449e-01 + 5.428000000000e-10 -3.570354300338e-01 + 5.528000000000e-10 -3.474353611027e-01 + 5.628000000000e-10 -2.856876769732e-01 + 5.728000000000e-10 -1.704760895977e-01 + 5.828000000000e-10 -3.008641427314e-02 + 5.928000000000e-10 1.025087996136e-01 + 6.028000000000e-10 2.033209986443e-01 + 6.128000000000e-10 2.706412375819e-01 + 6.228000000000e-10 3.125457575810e-01 + 6.328000000000e-10 3.398008382665e-01 + 6.428000000000e-10 3.570145583479e-01 + 6.528000000000e-10 3.474888598072e-01 + 6.628000000000e-10 2.856551852535e-01 + 6.728000000000e-10 1.705188293935e-01 + 6.828000000000e-10 3.004736925580e-02 + 6.928000000000e-10 -1.024728514478e-01 + 7.028000000000e-10 -2.033602328622e-01 + 7.128000000000e-10 -2.706061106716e-01 + 7.228000000000e-10 -3.125843283316e-01 + 7.328000000000e-10 -3.397655433228e-01 + 7.428000000000e-10 -3.570523646632e-01 + 7.528000000000e-10 -3.474554820929e-01 + 7.628000000000e-10 -2.856929985560e-01 + 7.728000000000e-10 -1.704859799650e-01 + 7.828000000000e-10 -3.008383757896e-02 + 7.928000000000e-10 1.025039608177e-01 + 8.028000000000e-10 2.033261442763e-01 + 8.128000000000e-10 2.706371082838e-01 + 8.228000000000e-10 3.125504649737e-01 + 8.328000000000e-10 3.397966066528e-01 + 8.428000000000e-10 3.570198965640e-01 + 8.528000000000e-10 3.474857187206e-01 + 8.628000000000e-10 2.856614378232e-01 + 8.728000000000e-10 1.705164607562e-01 + 8.828000000000e-10 3.005354621749e-02 + 8.928000000000e-10 -1.024749769036e-01 + 9.028000000000e-10 -2.033548454455e-01 + 9.128000000000e-10 -2.706087008930e-01 + 9.228000000000e-10 -3.125792630790e-01 + 9.328000000000e-10 -3.397683901773e-01 + 9.428000000000e-10 -3.570478314069e-01 + 9.528000000000e-10 -3.474583427153e-01 + 9.628000000000e-10 -2.856887110961e-01 + 9.728000000000e-10 -1.704892548593e-01 + 9.828000000000e-10 -3.008001356704e-02 + 9.928000000000e-10 1.025005080892e-01 + 1.000000000000e-09 1.786649040194e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/conditions.yaml new file mode 100644 index 00000000..b3b8c73a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 3 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_03 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/CML_core_tb.sch new file mode 100644 index 00000000..1855216a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/CML_core_tb_4.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/CML_core_tb_4.data new file mode 100644 index 00000000..3efc8a54 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/CML_core_tb_4.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908886906683e-01 + 1.728000000000e-10 -1.805890382926e-01 + 1.828000000000e-10 -4.276329247682e-02 + 1.928000000000e-10 8.882407595099e-02 + 2.028000000000e-10 1.894983505466e-01 + 2.128000000000e-10 2.576242567207e-01 + 2.228000000000e-10 3.005212718886e-01 + 2.328000000000e-10 3.289546768723e-01 + 2.428000000000e-10 3.474240530436e-01 + 2.528000000000e-10 3.394794629215e-01 + 2.628000000000e-10 2.802266193594e-01 + 2.728000000000e-10 1.685520573893e-01 + 2.828000000000e-10 3.081792474830e-02 + 2.928000000000e-10 -9.985913249602e-02 + 3.028000000000e-10 -1.996535082954e-01 + 3.128000000000e-10 -2.663519845580e-01 + 3.228000000000e-10 -3.081166100610e-01 + 3.328000000000e-10 -3.353557582557e-01 + 3.428000000000e-10 -3.530339682910e-01 + 3.528000000000e-10 -3.441234226063e-01 + 3.628000000000e-10 -2.840838930007e-01 + 3.728000000000e-10 -1.712890179908e-01 + 3.828000000000e-10 -3.280692441870e-02 + 3.928000000000e-10 9.858702888345e-02 + 4.028000000000e-10 1.985844458095e-01 + 4.128000000000e-10 2.655374220709e-01 + 4.228000000000e-10 3.073092043222e-01 + 4.328000000000e-10 3.348254361967e-01 + 4.428000000000e-10 3.526065806553e-01 + 4.528000000000e-10 3.440384505411e-01 + 4.628000000000e-10 2.840943593119e-01 + 4.728000000000e-10 1.715352376725e-01 + 4.828000000000e-10 3.300625747524e-02 + 4.928000000000e-10 -9.826793525126e-02 + 5.028000000000e-10 -1.983826392696e-01 + 5.128000000000e-10 -2.652748957302e-01 + 5.228000000000e-10 -3.071819372703e-01 + 5.328000000000e-10 -3.346211766496e-01 + 5.428000000000e-10 -3.525115401756e-01 + 5.528000000000e-10 -3.438520776438e-01 + 5.628000000000e-10 -2.840132934403e-01 + 5.728000000000e-10 -1.713783534881e-01 + 5.828000000000e-10 -3.296528839742e-02 + 5.928000000000e-10 9.838210726041e-02 + 6.028000000000e-10 1.983970962128e-01 + 6.128000000000e-10 2.653685996210e-01 + 6.228000000000e-10 3.071805271474e-01 + 6.328000000000e-10 3.346994451143e-01 + 6.428000000000e-10 3.524959527178e-01 + 6.528000000000e-10 3.439124816552e-01 + 6.628000000000e-10 2.839825148385e-01 + 6.728000000000e-10 1.714247364616e-01 + 6.828000000000e-10 3.292536702304e-02 + 6.928000000000e-10 -9.834444145178e-02 + 7.028000000000e-10 -1.984381153623e-01 + 7.128000000000e-10 -2.653318964793e-01 + 7.228000000000e-10 -3.072207693265e-01 + 7.328000000000e-10 -3.346627011511e-01 + 7.428000000000e-10 -3.525355719541e-01 + 7.528000000000e-10 -3.438780517049e-01 + 7.628000000000e-10 -2.840226095914e-01 + 7.728000000000e-10 -1.713910964736e-01 + 7.828000000000e-10 -3.296406429130e-02 + 7.928000000000e-10 9.837645950128e-02 + 8.028000000000e-10 1.984019833998e-01 + 8.128000000000e-10 2.653640104122e-01 + 8.228000000000e-10 3.071850636337e-01 + 8.328000000000e-10 3.346949515146e-01 + 8.428000000000e-10 3.525014052751e-01 + 8.528000000000e-10 3.439095067618e-01 + 8.628000000000e-10 2.839893402731e-01 + 8.728000000000e-10 1.714228569780e-01 + 8.828000000000e-10 3.293222880403e-02 + 8.928000000000e-10 -9.834616516704e-02 + 9.028000000000e-10 -1.984321208293e-01 + 9.128000000000e-10 -2.653341991167e-01 + 9.228000000000e-10 -3.072152380466e-01 + 9.328000000000e-10 -3.346653803170e-01 + 9.428000000000e-10 -3.525306496503e-01 + 9.528000000000e-10 -3.438807929682e-01 + 9.628000000000e-10 -2.840179937834e-01 + 9.728000000000e-10 -1.713943425416e-01 + 9.828000000000e-10 -3.296001530074e-02 + 9.928000000000e-10 9.837298926970e-02 + 1.000000000000e-09 1.738955459088e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/conditions.yaml new file mode 100644 index 00000000..5bab1bb1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 4 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_04 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/CML_core_tb.sch new file mode 100644 index 00000000..1b011749 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/CML_core_tb_5.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/CML_core_tb_5.data new file mode 100644 index 00000000..0cc77d23 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/CML_core_tb_5.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.958574299710e-01 + 1.728000000000e-10 -1.791897212785e-01 + 1.828000000000e-10 -3.599075048614e-02 + 1.928000000000e-10 9.946703268478e-02 + 2.028000000000e-10 2.032502871016e-01 + 2.128000000000e-10 2.733994094958e-01 + 2.228000000000e-10 3.172845988123e-01 + 2.328000000000e-10 3.455609123691e-01 + 2.428000000000e-10 3.630923957132e-01 + 2.528000000000e-10 3.534419450967e-01 + 2.628000000000e-10 2.903663934708e-01 + 2.728000000000e-10 1.726743312860e-01 + 2.828000000000e-10 2.930291139472e-02 + 2.928000000000e-10 -1.057514312075e-01 + 3.028000000000e-10 -2.091913834589e-01 + 3.128000000000e-10 -2.784696434768e-01 + 3.228000000000e-10 -3.216873931074e-01 + 3.328000000000e-10 -3.491870426412e-01 + 3.428000000000e-10 -3.662894191498e-01 + 3.528000000000e-10 -3.560374131806e-01 + 3.628000000000e-10 -2.925719059469e-01 + 3.728000000000e-10 -1.742159787839e-01 + 3.828000000000e-10 -3.049391935212e-02 + 3.928000000000e-10 1.049756016137e-01 + 4.028000000000e-10 2.084672065617e-01 + 4.128000000000e-10 2.779301238417e-01 + 4.228000000000e-10 3.211180618030e-01 + 4.328000000000e-10 3.488255023686e-01 + 4.428000000000e-10 3.659572542624e-01 + 4.528000000000e-10 3.559493947967e-01 + 4.628000000000e-10 2.925058094407e-01 + 4.728000000000e-10 1.743267017008e-01 + 4.828000000000e-10 3.054314172764e-02 + 4.928000000000e-10 -1.048175245910e-01 + 5.028000000000e-10 -2.084096499031e-01 + 5.128000000000e-10 -2.777998408986e-01 + 5.228000000000e-10 -3.210985617265e-01 + 5.328000000000e-10 -3.487226120056e-01 + 5.428000000000e-10 -3.659481451181e-01 + 5.528000000000e-10 -3.558482598240e-01 + 5.628000000000e-10 -2.924942070749e-01 + 5.728000000000e-10 -1.742324941843e-01 + 5.828000000000e-10 -3.054486718364e-02 + 5.928000000000e-10 1.048934295445e-01 + 6.028000000000e-10 2.083991544976e-01 + 6.128000000000e-10 2.778660140822e-01 + 6.228000000000e-10 3.210794561497e-01 + 6.328000000000e-10 3.487805773205e-01 + 6.428000000000e-10 3.659226785140e-01 + 6.528000000000e-10 3.558970058340e-01 + 6.628000000000e-10 2.924624137185e-01 + 6.728000000000e-10 1.742748110039e-01 + 6.828000000000e-10 3.050920657876e-02 + 6.928000000000e-10 -1.048562048812e-01 + 7.028000000000e-10 -2.084343791218e-01 + 7.128000000000e-10 -2.778299623633e-01 + 7.228000000000e-10 -3.211147582115e-01 + 7.328000000000e-10 -3.487447461690e-01 + 7.428000000000e-10 -3.659575085549e-01 + 7.528000000000e-10 -3.558632428052e-01 + 7.628000000000e-10 -2.924972481137e-01 + 7.728000000000e-10 -1.742418088753e-01 + 7.828000000000e-10 -3.054328720193e-02 + 7.928000000000e-10 1.048870377838e-01 + 8.028000000000e-10 2.084024115537e-01 + 8.128000000000e-10 2.778603942564e-01 + 8.228000000000e-10 3.210827582845e-01 + 8.328000000000e-10 3.487751488045e-01 + 8.428000000000e-10 3.659266824704e-01 + 8.528000000000e-10 3.558925702991e-01 + 8.628000000000e-10 2.924671830422e-01 + 8.728000000000e-10 1.742711856894e-01 + 8.828000000000e-10 3.051417003050e-02 + 8.928000000000e-10 -1.048591994973e-01 + 9.028000000000e-10 -2.084299430076e-01 + 9.128000000000e-10 -2.778331783696e-01 + 9.228000000000e-10 -3.211104359655e-01 + 9.328000000000e-10 -3.487480244246e-01 + 9.428000000000e-10 -3.659535267111e-01 + 9.528000000000e-10 -3.558663548813e-01 + 9.628000000000e-10 -2.924933270906e-01 + 9.728000000000e-10 -1.742451324195e-01 + 9.828000000000e-10 -3.053963678018e-02 + 9.928000000000e-10 1.048836196344e-01 + 1.000000000000e-09 1.830293824662e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/conditions.yaml new file mode 100644 index 00000000..280b26f2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 5 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_05 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/CML_core_tb.sch new file mode 100644 index 00000000..99556bb5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/CML_core_tb_6.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/CML_core_tb_6.data new file mode 100644 index 00000000..38ffd8bf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/CML_core_tb_6.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.689355033953e-01 + 1.728000000000e-10 -1.691728954892e-01 + 1.828000000000e-10 -4.423302134033e-02 + 1.928000000000e-10 7.663444207075e-02 + 2.028000000000e-10 1.714764750752e-01 + 2.128000000000e-10 2.368219567798e-01 + 2.228000000000e-10 2.772768132445e-01 + 2.328000000000e-10 3.013675537348e-01 + 2.428000000000e-10 3.140706479520e-01 + 2.528000000000e-10 3.038549886105e-01 + 2.628000000000e-10 2.508404086347e-01 + 2.728000000000e-10 1.528360605683e-01 + 2.828000000000e-10 3.040034809293e-02 + 2.928000000000e-10 -8.785381094258e-02 + 3.028000000000e-10 -1.808734961109e-01 + 3.128000000000e-10 -2.445795528199e-01 + 3.228000000000e-10 -2.838354337528e-01 + 3.328000000000e-10 -3.065800962400e-01 + 3.428000000000e-10 -3.181767360109e-01 + 3.528000000000e-10 -3.065752663659e-01 + 3.628000000000e-10 -2.523878800401e-01 + 3.728000000000e-10 -1.531173668737e-01 + 3.828000000000e-10 -2.992055538556e-02 + 3.928000000000e-10 8.900435641641e-02 + 4.028000000000e-10 1.821756238512e-01 + 4.128000000000e-10 2.460123650690e-01 + 4.228000000000e-10 2.851182310100e-01 + 4.328000000000e-10 3.079291995556e-01 + 4.428000000000e-10 3.194129911462e-01 + 4.528000000000e-10 3.078915366323e-01 + 4.628000000000e-10 2.535144344421e-01 + 4.728000000000e-10 1.541542026196e-01 + 4.828000000000e-10 3.063651583090e-02 + 4.928000000000e-10 -8.839161491074e-02 + 5.028000000000e-10 -1.817999659778e-01 + 5.128000000000e-10 -2.456456661989e-01 + 5.228000000000e-10 -2.849195350591e-01 + 5.328000000000e-10 -3.077091828990e-01 + 5.428000000000e-10 -3.193505374448e-01 + 5.528000000000e-10 -3.078081521678e-01 + 5.628000000000e-10 -2.535787813503e-01 + 5.728000000000e-10 -1.541764927596e-01 + 5.828000000000e-10 -3.077048554081e-02 + 5.928000000000e-10 8.832790620553e-02 + 6.028000000000e-10 1.816551916875e-01 + 6.128000000000e-10 2.455879975104e-01 + 6.228000000000e-10 2.847911932982e-01 + 6.328000000000e-10 3.076677363016e-01 + 6.428000000000e-10 3.192371229053e-01 + 6.528000000000e-10 3.077778412262e-01 + 6.628000000000e-10 2.534819327505e-01 + 6.728000000000e-10 1.541683138663e-01 + 6.828000000000e-10 3.070155435378e-02 + 6.928000000000e-10 -8.831320560130e-02 + 7.028000000000e-10 -1.817038543937e-01 + 7.128000000000e-10 -2.455619958387e-01 + 7.228000000000e-10 -2.848320347671e-01 + 7.328000000000e-10 -3.076358698550e-01 + 7.428000000000e-10 -3.192710667609e-01 + 7.528000000000e-10 -3.077409972388e-01 + 7.628000000000e-10 -2.535098012890e-01 + 7.728000000000e-10 -1.541282589474e-01 + 7.828000000000e-10 -3.072672689244e-02 + 7.928000000000e-10 8.835148526653e-02 + 8.028000000000e-10 1.816795669555e-01 + 8.128000000000e-10 2.455984246601e-01 + 8.228000000000e-10 2.848062931006e-01 + 8.328000000000e-10 3.076705916890e-01 + 8.428000000000e-10 3.192450073559e-01 + 8.528000000000e-10 3.077736319697e-01 + 8.628000000000e-10 2.534831121829e-01 + 8.728000000000e-10 1.541590953584e-01 + 8.828000000000e-10 3.069946612700e-02 + 8.928000000000e-10 -8.832341199891e-02 + 9.028000000000e-10 -1.817063952021e-01 + 9.128000000000e-10 -2.455714256322e-01 + 9.228000000000e-10 -2.848333922463e-01 + 9.328000000000e-10 -3.076440936715e-01 + 9.428000000000e-10 -3.192716274515e-01 + 9.528000000000e-10 -3.077481608676e-01 + 9.628000000000e-10 -2.535093614867e-01 + 9.728000000000e-10 -1.541340765567e-01 + 9.828000000000e-10 -3.072486745089e-02 + 9.928000000000e-10 8.834711873249e-02 + 1.000000000000e-09 1.586239577417e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/conditions.yaml new file mode 100644 index 00000000..08d6dff9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 6 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_06 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/CML_core_tb.sch new file mode 100644 index 00000000..138d869d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/CML_core_tb_7.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/CML_core_tb_7.data new file mode 100644 index 00000000..1cfe87b5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/CML_core_tb_7.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.694477874818e-01 + 1.728000000000e-10 -1.721829739194e-01 + 1.828000000000e-10 -4.906833766415e-02 + 1.928000000000e-10 7.069743134728e-02 + 2.028000000000e-10 1.648418946330e-01 + 2.128000000000e-10 2.298765389610e-01 + 2.228000000000e-10 2.702802052070e-01 + 2.328000000000e-10 2.947129455777e-01 + 2.428000000000e-10 3.081296602318e-01 + 2.528000000000e-10 2.990063012040e-01 + 2.628000000000e-10 2.478884705263e-01 + 2.728000000000e-10 1.524230846398e-01 + 2.828000000000e-10 3.216725009037e-02 + 2.928000000000e-10 -8.452884553171e-02 + 3.028000000000e-10 -1.764495371150e-01 + 3.128000000000e-10 -2.394951663999e-01 + 3.228000000000e-10 -2.784178156025e-01 + 3.328000000000e-10 -3.012580547427e-01 + 3.428000000000e-10 -3.133510931360e-01 + 3.528000000000e-10 -3.026055002423e-01 + 3.628000000000e-10 -2.500554574282e-01 + 3.728000000000e-10 -1.530444893437e-01 + 3.828000000000e-10 -3.179895766292e-02 + 3.928000000000e-10 8.573594509971e-02 + 4.028000000000e-10 1.778922744476e-01 + 4.128000000000e-10 2.411102030583e-01 + 4.228000000000e-10 2.798967112063e-01 + 4.328000000000e-10 3.028156837380e-01 + 4.428000000000e-10 3.148075876296e-01 + 4.528000000000e-10 3.041758344829e-01 + 4.628000000000e-10 2.514478797306e-01 + 4.728000000000e-10 1.543354303295e-01 + 4.828000000000e-10 3.272908827542e-02 + 4.928000000000e-10 -8.494488064942e-02 + 5.028000000000e-10 -1.773750790235e-01 + 5.128000000000e-10 -2.406241070550e-01 + 5.228000000000e-10 -2.796032327906e-01 + 5.328000000000e-10 -3.025154625175e-01 + 5.428000000000e-10 -3.146850050735e-01 + 5.528000000000e-10 -3.040456856306e-01 + 5.628000000000e-10 -2.514865398019e-01 + 5.728000000000e-10 -1.543455010081e-01 + 5.828000000000e-10 -3.286780649422e-02 + 5.928000000000e-10 8.487071769529e-02 + 6.028000000000e-10 1.772120847555e-01 + 6.128000000000e-10 2.405506532865e-01 + 6.228000000000e-10 2.794557736074e-01 + 6.328000000000e-10 3.024581955274e-01 + 6.428000000000e-10 3.145521515255e-01 + 6.528000000000e-10 3.039990633934e-01 + 6.628000000000e-10 2.513709142203e-01 + 6.728000000000e-10 1.543241408079e-01 + 6.828000000000e-10 3.278555364704e-02 + 6.928000000000e-10 -8.486327141666e-02 + 7.028000000000e-10 -1.772689800248e-01 + 7.128000000000e-10 -2.405282060865e-01 + 7.228000000000e-10 -2.795021370136e-01 + 7.328000000000e-10 -3.024278022377e-01 + 7.428000000000e-10 -3.145896170200e-01 + 7.528000000000e-10 -3.039617953787e-01 + 7.628000000000e-10 -2.514004690324e-01 + 7.728000000000e-10 -1.542820043229e-01 + 7.828000000000e-10 -3.281110337775e-02 + 7.928000000000e-10 8.490436306023e-02 + 8.028000000000e-10 1.772446330839e-01 + 8.128000000000e-10 2.405674335146e-01 + 8.228000000000e-10 2.794761963085e-01 + 8.328000000000e-10 3.024650976088e-01 + 8.428000000000e-10 3.145632644585e-01 + 8.528000000000e-10 3.039968961590e-01 + 8.628000000000e-10 2.513733111446e-01 + 8.728000000000e-10 1.543150179356e-01 + 8.828000000000e-10 3.278304586331e-02 + 8.928000000000e-10 -8.487456857602e-02 + 9.028000000000e-10 -1.772725618584e-01 + 9.128000000000e-10 -2.405389250041e-01 + 9.228000000000e-10 -2.795045102279e-01 + 9.328000000000e-10 -3.024372521320e-01 + 9.428000000000e-10 -3.145911572553e-01 + 9.528000000000e-10 -3.039701598993e-01 + 9.628000000000e-10 -2.514009218164e-01 + 9.728000000000e-10 -1.542887967264e-01 + 9.828000000000e-10 -3.280979517783e-02 + 9.928000000000e-10 8.489941508642e-02 + 1.000000000000e-09 1.544118489485e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/conditions.yaml new file mode 100644 index 00000000..41505a5d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 7 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_07 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/CML_core_tb.sch new file mode 100644 index 00000000..fcd09006 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/CML_core_tb_8.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/CML_core_tb_8.data new file mode 100644 index 00000000..b4ed17dd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/CML_core_tb_8.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.722799425151e-01 + 1.728000000000e-10 -1.701277707773e-01 + 1.828000000000e-10 -4.252496989706e-02 + 1.928000000000e-10 8.092536896213e-02 + 2.028000000000e-10 1.785199933375e-01 + 2.128000000000e-10 2.463984181452e-01 + 2.228000000000e-10 2.885755113271e-01 + 2.328000000000e-10 3.131967480955e-01 + 2.428000000000e-10 3.255285716483e-01 + 2.528000000000e-10 3.143820454109e-01 + 2.628000000000e-10 2.595824958850e-01 + 2.728000000000e-10 1.585585813323e-01 + 2.828000000000e-10 3.254606172598e-02 + 2.928000000000e-10 -8.921916265210e-02 + 3.028000000000e-10 -1.857143058967e-01 + 3.128000000000e-10 -2.524588707093e-01 + 3.228000000000e-10 -2.937876617757e-01 + 3.328000000000e-10 -3.173655773168e-01 + 3.428000000000e-10 -3.288566343508e-01 + 3.528000000000e-10 -3.166123605828e-01 + 3.628000000000e-10 -2.609360611345e-01 + 3.728000000000e-10 -1.589355414621e-01 + 3.828000000000e-10 -3.237621747627e-02 + 3.928000000000e-10 8.990939637816e-02 + 4.028000000000e-10 1.864994737191e-01 + 4.128000000000e-10 2.533636311879e-01 + 4.228000000000e-10 2.945633129641e-01 + 4.328000000000e-10 3.182197832362e-01 + 4.428000000000e-10 3.296245618008e-01 + 4.528000000000e-10 3.174841059207e-01 + 4.628000000000e-10 2.616780558587e-01 + 4.728000000000e-10 1.596622360522e-01 + 4.828000000000e-10 3.287681921596e-02 + 4.928000000000e-10 -8.943999963453e-02 + 5.028000000000e-10 -1.862066308093e-01 + 5.128000000000e-10 -2.530527908612e-01 + 5.228000000000e-10 -2.943931136832e-01 + 5.328000000000e-10 -3.180152021024e-01 + 5.428000000000e-10 -3.295545667130e-01 + 5.528000000000e-10 -3.173812952412e-01 + 5.628000000000e-10 -2.617027726155e-01 + 5.728000000000e-10 -1.596411992093e-01 + 5.828000000000e-10 -3.295895028258e-02 + 5.928000000000e-10 8.942267434718e-02 + 6.028000000000e-10 1.861105403656e-01 + 6.128000000000e-10 2.530344325895e-01 + 6.228000000000e-10 2.943051008579e-01 + 6.328000000000e-10 3.180051485103e-01 + 6.428000000000e-10 3.294737915539e-01 + 6.528000000000e-10 3.173744791022e-01 + 6.628000000000e-10 2.616291881364e-01 + 6.728000000000e-10 1.596450333001e-01 + 6.828000000000e-10 3.290088244348e-02 + 6.928000000000e-10 -8.940659470005e-02 + 7.028000000000e-10 -1.861562133447e-01 + 7.128000000000e-10 -2.530116656482e-01 + 7.228000000000e-10 -2.943454309811e-01 + 7.328000000000e-10 -3.179780561670e-01 + 7.428000000000e-10 -3.295087969733e-01 + 7.528000000000e-10 -3.173438661274e-01 + 7.628000000000e-10 -2.616591955397e-01 + 7.728000000000e-10 -1.596115565426e-01 + 7.828000000000e-10 -3.292790237402e-02 + 7.928000000000e-10 8.943927261705e-02 + 8.028000000000e-10 1.861310420114e-01 + 8.128000000000e-10 2.530433655174e-01 + 8.228000000000e-10 2.943195630770e-01 + 8.328000000000e-10 3.180088285378e-01 + 8.428000000000e-10 3.294832118435e-01 + 8.528000000000e-10 3.173732295072e-01 + 8.628000000000e-10 2.616337486722e-01 + 8.728000000000e-10 1.596399004289e-01 + 8.828000000000e-10 3.290244884503e-02 + 8.928000000000e-10 -8.941301350766e-02 + 9.028000000000e-10 -1.861557185261e-01 + 9.128000000000e-10 -2.530180139920e-01 + 9.228000000000e-10 -2.943444772306e-01 + 9.328000000000e-10 -3.179838696148e-01 + 9.428000000000e-10 -3.295076633013e-01 + 9.528000000000e-10 -3.173492560727e-01 + 9.628000000000e-10 -2.616577755083e-01 + 9.728000000000e-10 -1.596163947717e-01 + 9.828000000000e-10 -3.292583900074e-02 + 9.928000000000e-10 8.943518431692e-02 + 1.000000000000e-09 1.621529465729e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/conditions.yaml new file mode 100644 index 00000000..19f53193 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 8 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_08 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/CML_core_tb.sch new file mode 100644 index 00000000..96bf1a1b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/CML_core_tb_9.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/CML_core_tb_9.data new file mode 100644 index 00000000..6b24d1d6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/CML_core_tb_9.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.622644182692e-01 + 1.728000000000e-10 -1.962653738736e-01 + 1.828000000000e-10 -5.712895575235e-03 + 1.928000000000e-10 1.510345047594e-01 + 2.028000000000e-10 2.432775412534e-01 + 2.128000000000e-10 2.772000132926e-01 + 2.228000000000e-10 3.161630086256e-01 + 2.328000000000e-10 3.654121904616e-01 + 2.428000000000e-10 4.070200809677e-01 + 2.528000000000e-10 4.211809118313e-01 + 2.628000000000e-10 3.552666659990e-01 + 2.728000000000e-10 1.954111420719e-01 + 2.828000000000e-10 7.499275151763e-03 + 2.928000000000e-10 -1.488912332472e-01 + 3.028000000000e-10 -2.420325529570e-01 + 3.128000000000e-10 -2.768171400503e-01 + 3.228000000000e-10 -3.164103191401e-01 + 3.328000000000e-10 -3.656815561297e-01 + 3.428000000000e-10 -4.072561733660e-01 + 3.528000000000e-10 -4.210637971044e-01 + 3.628000000000e-10 -3.548415521036e-01 + 3.728000000000e-10 -1.946286859654e-01 + 3.828000000000e-10 -6.746438981043e-03 + 3.928000000000e-10 1.496127957227e-01 + 4.028000000000e-10 2.425057762271e-01 + 4.128000000000e-10 2.772590268750e-01 + 4.228000000000e-10 3.167075169816e-01 + 4.328000000000e-10 3.660182242119e-01 + 4.428000000000e-10 4.074726111052e-01 + 4.528000000000e-10 4.212975956202e-01 + 4.628000000000e-10 3.549573822535e-01 + 4.728000000000e-10 1.947835560361e-01 + 4.828000000000e-10 6.801482567115e-03 + 4.928000000000e-10 -1.495086456760e-01 + 5.028000000000e-10 -2.424863730465e-01 + 5.128000000000e-10 -2.771744431737e-01 + 5.228000000000e-10 -3.166940000076e-01 + 5.328000000000e-10 -3.659398771497e-01 + 5.428000000000e-10 -4.074689465730e-01 + 5.528000000000e-10 -4.212394549000e-01 + 5.628000000000e-10 -3.549741510035e-01 + 5.728000000000e-10 -1.947436351784e-01 + 5.828000000000e-10 -6.830080160870e-03 + 5.928000000000e-10 1.495407150967e-01 + 6.028000000000e-10 2.424570295697e-01 + 6.128000000000e-10 2.772066160972e-01 + 6.228000000000e-10 3.166654934082e-01 + 6.328000000000e-10 3.659723864247e-01 + 6.428000000000e-10 4.074416211051e-01 + 6.528000000000e-10 4.212697301261e-01 + 6.628000000000e-10 3.549467093259e-01 + 6.728000000000e-10 1.947718238583e-01 + 6.828000000000e-10 6.800951177238e-03 + 6.928000000000e-10 -1.495148390529e-01 + 7.028000000000e-10 -2.424852043575e-01 + 7.128000000000e-10 -2.771809105751e-01 + 7.228000000000e-10 -3.166930947909e-01 + 7.328000000000e-10 -3.659459016360e-01 + 7.428000000000e-10 -4.074677461547e-01 + 7.528000000000e-10 -4.212442717757e-01 + 7.628000000000e-10 -3.549717520551e-01 + 7.728000000000e-10 -1.947463263521e-01 + 7.828000000000e-10 -6.825916545420e-03 + 7.928000000000e-10 1.495385751436e-01 + 8.028000000000e-10 2.424609931904e-01 + 8.128000000000e-10 2.772040406871e-01 + 8.228000000000e-10 3.166687905139e-01 + 8.328000000000e-10 3.659694951712e-01 + 8.428000000000e-10 4.074447010218e-01 + 8.528000000000e-10 4.212671408417e-01 + 8.628000000000e-10 3.549498827484e-01 + 8.728000000000e-10 1.947689363825e-01 + 8.828000000000e-10 6.803756635994e-03 + 8.928000000000e-10 -1.495176738691e-01 + 9.028000000000e-10 -2.424825342063e-01 + 9.128000000000e-10 -2.771836734306e-01 + 9.228000000000e-10 -3.166902103892e-01 + 9.328000000000e-10 -3.659485359213e-01 + 9.428000000000e-10 -4.074650210911e-01 + 9.528000000000e-10 -4.212469657833e-01 + 9.628000000000e-10 -3.549694058275e-01 + 9.728000000000e-10 -1.947487958951e-01 + 9.828000000000e-10 -6.823236278537e-03 + 9.928000000000e-10 1.495363177485e-01 + 1.000000000000e-09 2.250264100511e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/conditions.yaml new file mode 100644 index 00000000..561e7f4b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 9 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_09 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/CML_core_tb.sch new file mode 100644 index 00000000..f48bc806 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/CML_core_tb_10.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/CML_core_tb_10.data new file mode 100644 index 00000000..f64d27bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/CML_core_tb_10.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.621881537650e-01 + 1.728000000000e-10 -1.984429143572e-01 + 1.828000000000e-10 -1.024381876325e-02 + 1.928000000000e-10 1.456486678579e-01 + 2.028000000000e-10 2.379497773075e-01 + 2.128000000000e-10 2.714724605336e-01 + 2.228000000000e-10 3.108042897090e-01 + 2.328000000000e-10 3.600441003378e-01 + 2.428000000000e-10 4.020596908788e-01 + 2.528000000000e-10 4.176332246346e-01 + 2.628000000000e-10 3.534480183483e-01 + 2.728000000000e-10 1.957884716864e-01 + 2.828000000000e-10 1.048070619246e-02 + 2.928000000000e-10 -1.446967472000e-01 + 3.028000000000e-10 -2.375576326508e-01 + 3.128000000000e-10 -2.717915022579e-01 + 3.228000000000e-10 -3.116603869888e-01 + 3.328000000000e-10 -3.608573425706e-01 + 3.428000000000e-10 -4.027490548925e-01 + 3.528000000000e-10 -4.178578104758e-01 + 3.628000000000e-10 -3.532507313188e-01 + 3.728000000000e-10 -1.951536666098e-01 + 3.828000000000e-10 -9.813336101525e-03 + 3.928000000000e-10 1.453604720604e-01 + 4.028000000000e-10 2.379857130154e-01 + 4.128000000000e-10 2.721818635676e-01 + 4.228000000000e-10 3.119088225778e-01 + 4.328000000000e-10 3.611475798924e-01 + 4.428000000000e-10 4.029304727738e-01 + 4.528000000000e-10 4.180700216423e-01 + 4.628000000000e-10 3.533627988360e-01 + 4.728000000000e-10 1.953149158213e-01 + 4.828000000000e-10 9.881134950277e-03 + 4.928000000000e-10 -1.452466419838e-01 + 5.028000000000e-10 -2.379576224969e-01 + 5.128000000000e-10 -2.720935242692e-01 + 5.228000000000e-10 -3.118909714313e-01 + 5.328000000000e-10 -3.610674239906e-01 + 5.428000000000e-10 -4.029229661263e-01 + 5.528000000000e-10 -4.180098057029e-01 + 5.628000000000e-10 -3.533753449283e-01 + 5.728000000000e-10 -1.952727841385e-01 + 5.828000000000e-10 -9.906008920915e-03 + 5.928000000000e-10 1.452800172029e-01 + 6.028000000000e-10 2.379306740359e-01 + 6.128000000000e-10 2.721261300904e-01 + 6.228000000000e-10 3.118646486801e-01 + 6.328000000000e-10 3.611003417151e-01 + 6.428000000000e-10 4.028972890619e-01 + 6.528000000000e-10 4.180401129989e-01 + 6.628000000000e-10 3.533488930459e-01 + 6.728000000000e-10 1.953007885397e-01 + 6.828000000000e-10 9.878072761317e-03 + 6.928000000000e-10 -1.452545395230e-01 + 7.028000000000e-10 -2.379578117562e-01 + 7.128000000000e-10 -2.721008877684e-01 + 7.228000000000e-10 -3.118914026492e-01 + 7.328000000000e-10 -3.610744602697e-01 + 7.428000000000e-10 -4.029226014194e-01 + 7.528000000000e-10 -4.180151483436e-01 + 7.628000000000e-10 -3.533732531474e-01 + 7.728000000000e-10 -1.952759500525e-01 + 7.828000000000e-10 -9.902411226855e-03 + 7.928000000000e-10 1.452776462046e-01 + 8.028000000000e-10 2.379341379884e-01 + 8.128000000000e-10 2.721234101956e-01 + 8.228000000000e-10 3.118677116052e-01 + 8.328000000000e-10 3.610975209728e-01 + 8.428000000000e-10 4.029000595077e-01 + 8.528000000000e-10 4.180375331400e-01 + 8.628000000000e-10 3.533517750284e-01 + 8.728000000000e-10 1.952981248182e-01 + 8.828000000000e-10 9.880873061622e-03 + 8.928000000000e-10 -1.452571579233e-01 + 9.028000000000e-10 -2.379551078725e-01 + 9.128000000000e-10 -2.721034614056e-01 + 9.228000000000e-10 -3.118886463518e-01 + 9.328000000000e-10 -3.610770519544e-01 + 9.428000000000e-10 -4.029199107687e-01 + 9.528000000000e-10 -4.180177452829e-01 + 9.628000000000e-10 -3.533708821878e-01 + 9.728000000000e-10 -1.952784134813e-01 + 9.828000000000e-10 -9.899898542678e-03 + 9.928000000000e-10 1.452754037376e-01 + 1.000000000000e-09 2.207322871295e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/conditions.yaml new file mode 100644 index 00000000..7768d786 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 10 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_10 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/CML_core_tb.sch new file mode 100644 index 00000000..5cba2556 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/CML_core_tb_11.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/CML_core_tb_11.data new file mode 100644 index 00000000..1453012b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/CML_core_tb_11.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.668500025046e-01 + 1.728000000000e-10 -1.978704758130e-01 + 1.828000000000e-10 -3.069550951996e-03 + 1.928000000000e-10 1.561389387989e-01 + 2.028000000000e-10 2.488697408913e-01 + 2.128000000000e-10 2.833379270136e-01 + 2.228000000000e-10 3.221467647695e-01 + 2.328000000000e-10 3.723176028273e-01 + 2.428000000000e-10 4.147931582649e-01 + 2.528000000000e-10 4.286646301121e-01 + 2.628000000000e-10 3.614677855799e-01 + 2.728000000000e-10 1.982726052647e-01 + 2.828000000000e-10 5.580533140739e-03 + 2.928000000000e-10 -1.536551403474e-01 + 3.028000000000e-10 -2.474729097395e-01 + 3.128000000000e-10 -2.827981749211e-01 + 3.228000000000e-10 -3.222400643179e-01 + 3.328000000000e-10 -3.724510578191e-01 + 3.428000000000e-10 -4.149487937489e-01 + 3.528000000000e-10 -4.285094572794e-01 + 3.628000000000e-10 -3.610716711123e-01 + 3.728000000000e-10 -1.975613483211e-01 + 3.828000000000e-10 -4.936396792217e-03 + 3.928000000000e-10 1.542720670721e-01 + 4.028000000000e-10 2.478554934965e-01 + 4.128000000000e-10 2.831768205427e-01 + 4.228000000000e-10 3.224764565266e-01 + 4.328000000000e-10 3.727376628527e-01 + 4.428000000000e-10 4.151128450004e-01 + 4.528000000000e-10 4.287030398326e-01 + 4.628000000000e-10 3.611465460996e-01 + 4.728000000000e-10 1.976871290976e-01 + 4.828000000000e-10 4.962067120498e-03 + 4.928000000000e-10 -1.541857483448e-01 + 5.028000000000e-10 -2.478549856990e-01 + 5.128000000000e-10 -2.831031432303e-01 + 5.228000000000e-10 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7.728000000000e-10 -1.976499135935e-01 + 7.828000000000e-10 -4.990471824028e-03 + 7.928000000000e-10 1.542171227717e-01 + 8.028000000000e-10 2.478269854332e-01 + 8.128000000000e-10 2.831343470853e-01 + 8.228000000000e-10 3.224500362551e-01 + 8.328000000000e-10 3.726987138014e-01 + 8.428000000000e-10 4.150953468135e-01 + 8.528000000000e-10 4.286792233560e-01 + 8.628000000000e-10 3.611455588852e-01 + 8.728000000000e-10 1.976743961081e-01 + 8.828000000000e-10 4.966432661841e-03 + 8.928000000000e-10 -1.541946484524e-01 + 9.028000000000e-10 -2.478502288236e-01 + 9.128000000000e-10 -2.831123474050e-01 + 9.228000000000e-10 -3.224731331421e-01 + 9.328000000000e-10 -3.726757720747e-01 + 9.428000000000e-10 -4.151172388981e-01 + 9.528000000000e-10 -4.286573581279e-01 + 9.628000000000e-10 -3.611667698498e-01 + 9.728000000000e-10 -1.976525646923e-01 + 9.828000000000e-10 -4.987471597641e-03 + 9.928000000000e-10 1.542147143463e-01 + 1.000000000000e-09 2.301006397866e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/conditions.yaml new file mode 100644 index 00000000..b38c5caf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 11 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_11 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/CML_core_tb.sch new file mode 100644 index 00000000..db264c8b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/CML_core_tb_12.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/CML_core_tb_12.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/CML_core_tb_12.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/conditions.yaml new file mode 100644 index 00000000..4928cb28 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 12 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_12 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/CML_core_tb.sch new file mode 100644 index 00000000..c09405b7 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/CML_core_tb_13.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/CML_core_tb_13.data new file mode 100644 index 00000000..36de6040 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/CML_core_tb_13.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.406999838743e-01 + 1.728000000000e-10 -1.879936990253e-01 + 1.828000000000e-10 -9.262901303246e-03 + 1.928000000000e-10 1.413611635485e-01 + 2.028000000000e-10 2.336775345801e-01 + 2.128000000000e-10 2.717294842894e-01 + 2.228000000000e-10 3.082620487639e-01 + 2.328000000000e-10 3.509422339502e-01 + 2.428000000000e-10 3.871053596645e-01 + 2.528000000000e-10 3.988940820744e-01 + 2.628000000000e-10 3.384312270542e-01 + 2.728000000000e-10 1.913281233779e-01 + 2.828000000000e-10 1.537343295661e-02 + 2.928000000000e-10 -1.347916275204e-01 + 3.028000000000e-10 -2.283419665374e-01 + 3.128000000000e-10 -2.677291408127e-01 + 3.228000000000e-10 -3.052231075401e-01 + 3.328000000000e-10 -3.481601477547e-01 + 3.428000000000e-10 -3.845854123080e-01 + 3.528000000000e-10 -3.965379624605e-01 + 3.628000000000e-10 -3.363314255870e-01 + 3.728000000000e-10 -1.893723794407e-01 + 3.828000000000e-10 -1.375643865463e-02 + 3.928000000000e-10 1.361849816757e-01 + 4.028000000000e-10 2.294005939140e-01 + 4.128000000000e-10 2.686949729273e-01 + 4.228000000000e-10 3.060328157788e-01 + 4.328000000000e-10 3.489590274886e-01 + 4.428000000000e-10 3.852266672724e-01 + 4.528000000000e-10 3.970921187630e-01 + 4.628000000000e-10 3.366736237881e-01 + 4.728000000000e-10 1.896320772426e-01 + 4.828000000000e-10 1.386475371506e-02 + 4.928000000000e-10 -1.360753156283e-01 + 5.028000000000e-10 -2.293675908871e-01 + 5.128000000000e-10 -2.686062530832e-01 + 5.228000000000e-10 -3.059945800423e-01 + 5.328000000000e-10 -3.488729675224e-01 + 5.428000000000e-10 -3.852026785029e-01 + 5.528000000000e-10 -3.970350594993e-01 + 5.628000000000e-10 -3.366834486256e-01 + 5.728000000000e-10 -1.896077423819e-01 + 5.828000000000e-10 -1.389840122586e-02 + 5.928000000000e-10 1.360876217327e-01 + 6.028000000000e-10 2.293336021557e-01 + 6.128000000000e-10 2.686225622920e-01 + 6.228000000000e-10 3.059648098566e-01 + 6.328000000000e-10 3.488907093130e-01 + 6.428000000000e-10 3.851753633828e-01 + 6.528000000000e-10 3.970526526302e-01 + 6.628000000000e-10 3.366583891048e-01 + 6.728000000000e-10 1.896251667832e-01 + 6.828000000000e-10 1.387242911077e-02 + 6.928000000000e-10 -1.360702314024e-01 + 7.028000000000e-10 -2.293580006158e-01 + 7.128000000000e-10 -2.686047945045e-01 + 7.228000000000e-10 -3.059879182353e-01 + 7.328000000000e-10 -3.488722408399e-01 + 7.428000000000e-10 -3.851969589401e-01 + 7.528000000000e-10 -3.970345404264e-01 + 7.628000000000e-10 -3.366782708831e-01 + 7.728000000000e-10 -1.896058621860e-01 + 7.828000000000e-10 -1.389192450355e-02 + 7.928000000000e-10 1.360888260036e-01 + 8.028000000000e-10 2.293391038565e-01 + 8.128000000000e-10 2.686227634282e-01 + 8.228000000000e-10 3.059688096850e-01 + 8.328000000000e-10 3.488900661997e-01 + 8.428000000000e-10 3.851789257250e-01 + 8.528000000000e-10 3.970519764807e-01 + 8.628000000000e-10 3.366616134215e-01 + 8.728000000000e-10 1.896231972496e-01 + 8.828000000000e-10 1.387461571983e-02 + 8.928000000000e-10 -1.360724758723e-01 + 9.028000000000e-10 -2.293560182270e-01 + 9.128000000000e-10 -2.686070528237e-01 + 9.228000000000e-10 -3.059854790954e-01 + 9.328000000000e-10 -3.488740842624e-01 + 9.428000000000e-10 -3.851947329758e-01 + 9.528000000000e-10 -3.970365843841e-01 + 9.628000000000e-10 -3.366766115599e-01 + 9.728000000000e-10 -1.896075309897e-01 + 9.828000000000e-10 -1.388973786858e-02 + 9.928000000000e-10 1.360872156510e-01 + 1.000000000000e-09 2.108297225004e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/conditions.yaml new file mode 100644 index 00000000..24d6b9db --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 13 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_13 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/CML_core_tb.sch new file mode 100644 index 00000000..83f5a899 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/CML_core_tb_14.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/CML_core_tb_14.data new file mode 100644 index 00000000..73c31d13 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/CML_core_tb_14.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.445927026449e-01 + 1.728000000000e-10 -1.889320969581e-01 + 1.828000000000e-10 -5.355234564888e-03 + 1.928000000000e-10 1.489911128277e-01 + 2.028000000000e-10 2.434822449071e-01 + 2.128000000000e-10 2.838702060450e-01 + 2.228000000000e-10 3.202156401988e-01 + 2.328000000000e-10 3.629401474789e-01 + 2.428000000000e-10 3.990998051164e-01 + 2.528000000000e-10 4.099063275401e-01 + 2.628000000000e-10 3.477923521709e-01 + 2.728000000000e-10 1.968519788675e-01 + 2.828000000000e-10 1.493750763318e-02 + 2.928000000000e-10 -1.398437743336e-01 + 3.028000000000e-10 -2.362338093992e-01 + 3.128000000000e-10 -2.782887085314e-01 + 3.228000000000e-10 -3.158910292643e-01 + 3.328000000000e-10 -3.590893499920e-01 + 3.428000000000e-10 -3.957248346768e-01 + 3.528000000000e-10 -4.069627998073e-01 + 3.628000000000e-10 -3.454070734708e-01 + 3.728000000000e-10 -1.948243362004e-01 + 3.828000000000e-10 -1.337926088934e-02 + 3.928000000000e-10 1.411472162204e-01 + 4.028000000000e-10 2.372231231196e-01 + 4.128000000000e-10 2.792284454069e-01 + 4.228000000000e-10 3.166817589057e-01 + 4.328000000000e-10 3.598702175634e-01 + 4.428000000000e-10 3.963375250752e-01 + 4.528000000000e-10 4.074753309124e-01 + 4.628000000000e-10 3.456854225481e-01 + 4.728000000000e-10 1.950177434222e-01 + 4.828000000000e-10 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7.328000000000e-10 -3.598002455584e-01 + 7.428000000000e-10 -3.963259615583e-01 + 7.528000000000e-10 -4.074304662079e-01 + 7.628000000000e-10 -3.457033629648e-01 + 7.728000000000e-10 -1.949983704767e-01 + 7.828000000000e-10 -1.345872104163e-02 + 7.928000000000e-10 1.410962716693e-01 + 8.028000000000e-10 2.371963808526e-01 + 8.128000000000e-10 2.791814500218e-01 + 8.228000000000e-10 3.166396456569e-01 + 8.328000000000e-10 3.598191409746e-01 + 8.428000000000e-10 3.963069790813e-01 + 8.528000000000e-10 4.074488078929e-01 + 8.628000000000e-10 3.456858987705e-01 + 8.728000000000e-10 1.950166421641e-01 + 8.828000000000e-10 1.344025602045e-02 + 8.928000000000e-10 -1.410790665154e-01 + 9.028000000000e-10 -2.372142995262e-01 + 9.128000000000e-10 -2.791649325552e-01 + 9.228000000000e-10 -3.166573514474e-01 + 9.328000000000e-10 -3.598022359716e-01 + 9.428000000000e-10 -3.963236588924e-01 + 9.528000000000e-10 -4.074326778223e-01 + 9.628000000000e-10 -3.457016440453e-01 + 9.728000000000e-10 -1.950001702792e-01 + 9.828000000000e-10 -1.345633761364e-02 + 9.928000000000e-10 1.410945129066e-01 + 1.000000000000e-09 2.176807579100e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/conditions.yaml new file mode 100644 index 00000000..42b6b28f --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 14 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_14 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/CML_core_tb.sch new file mode 100644 index 00000000..05004060 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/CML_core_tb_15.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/CML_core_tb_15.data new file mode 100644 index 00000000..6f87c434 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/CML_core_tb_15.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.831577979118e-01 + 1.728000000000e-10 -1.548331321524e-01 + 1.828000000000e-10 2.954507991941e-03 + 1.928000000000e-10 1.412083661187e-01 + 2.028000000000e-10 2.303947789211e-01 + 2.128000000000e-10 2.725788032239e-01 + 2.228000000000e-10 3.064646814943e-01 + 2.328000000000e-10 3.412898568956e-01 + 2.428000000000e-10 3.692979025942e-01 + 2.528000000000e-10 3.751979264520e-01 + 2.628000000000e-10 3.186495551608e-01 + 2.728000000000e-10 1.849115684226e-01 + 2.828000000000e-10 2.146912258403e-02 + 2.928000000000e-10 -1.215319416200e-01 + 3.028000000000e-10 -2.147336364713e-01 + 3.128000000000e-10 -2.593628319189e-01 + 3.228000000000e-10 -2.947919001104e-01 + 3.328000000000e-10 -3.306034656465e-01 + 3.428000000000e-10 -3.598903423599e-01 + 3.528000000000e-10 -3.674806029527e-01 + 3.628000000000e-10 -3.131864519443e-01 + 3.728000000000e-10 -1.816607205648e-01 + 3.828000000000e-10 -2.002885045896e-02 + 3.928000000000e-10 1.219326732879e-01 + 4.028000000000e-10 2.146583452252e-01 + 4.128000000000e-10 2.593288859790e-01 + 4.228000000000e-10 2.947836961551e-01 + 4.328000000000e-10 3.305873089453e-01 + 4.428000000000e-10 3.597520160348e-01 + 4.528000000000e-10 3.672634041173e-01 + 4.628000000000e-10 3.128292575731e-01 + 4.728000000000e-10 1.812525079401e-01 + 4.828000000000e-10 1.956255085056e-02 + 4.928000000000e-10 -1.223539241893e-01 + 5.028000000000e-10 -2.150587893921e-01 + 5.128000000000e-10 -2.596440912838e-01 + 5.228000000000e-10 -2.950896959018e-01 + 5.328000000000e-10 -3.308452440946e-01 + 5.428000000000e-10 -3.600168265621e-01 + 5.528000000000e-10 -3.674687038170e-01 + 5.628000000000e-10 -3.130140501398e-01 + 5.728000000000e-10 -1.813584327872e-01 + 5.828000000000e-10 -1.965159115909e-02 + 5.928000000000e-10 1.223212864923e-01 + 6.028000000000e-10 2.150157103205e-01 + 6.128000000000e-10 2.596318060931e-01 + 6.228000000000e-10 2.950524078153e-01 + 6.328000000000e-10 3.308363963911e-01 + 6.428000000000e-10 3.599874022300e-01 + 6.528000000000e-10 3.674690181116e-01 + 6.628000000000e-10 3.129980588961e-01 + 6.728000000000e-10 1.813712653368e-01 + 6.828000000000e-10 1.964491680526e-02 + 6.928000000000e-10 -1.223023112353e-01 + 7.028000000000e-10 -2.150202483004e-01 + 7.128000000000e-10 -2.596144309164e-01 + 7.228000000000e-10 -2.950582886643e-01 + 7.328000000000e-10 -3.308199600200e-01 + 7.428000000000e-10 -3.599931640339e-01 + 7.528000000000e-10 -3.674538095645e-01 + 7.628000000000e-10 -3.130042913922e-01 + 7.728000000000e-10 -1.813570925598e-01 + 7.828000000000e-10 -1.965290666609e-02 + 7.928000000000e-10 1.223145971689e-01 + 8.028000000000e-10 2.150114430495e-01 + 8.128000000000e-10 2.596256780136e-01 + 8.228000000000e-10 2.950490452158e-01 + 8.328000000000e-10 3.308307530718e-01 + 8.428000000000e-10 3.599842799802e-01 + 8.528000000000e-10 3.674639698479e-01 + 8.628000000000e-10 3.129957925611e-01 + 8.728000000000e-10 1.813666711568e-01 + 8.828000000000e-10 1.964348030724e-02 + 8.928000000000e-10 -1.223056361887e-01 + 9.028000000000e-10 -2.150207890100e-01 + 9.128000000000e-10 -2.596171721225e-01 + 9.228000000000e-10 -2.950581404305e-01 + 9.328000000000e-10 -3.308221104591e-01 + 9.428000000000e-10 -3.599929167296e-01 + 9.528000000000e-10 -3.674557320782e-01 + 9.628000000000e-10 -3.130039671541e-01 + 9.728000000000e-10 -1.813582011282e-01 + 9.828000000000e-10 -1.965175786777e-02 + 9.928000000000e-10 1.223137237372e-01 + 1.000000000000e-09 1.953703252853e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/conditions.yaml new file mode 100644 index 00000000..f60efffa --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 15 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_15 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/CML_core_tb.sch new file mode 100644 index 00000000..e55a8b0d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/CML_core_tb_16.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/CML_core_tb_16.data new file mode 100644 index 00000000..c0c44c66 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/CML_core_tb_16.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908214410229e-01 + 1.728000000000e-10 -1.609006026552e-01 + 1.828000000000e-10 -2.321243117629e-03 + 1.928000000000e-10 1.363185315112e-01 + 2.028000000000e-10 2.253864999197e-01 + 2.128000000000e-10 2.667546328680e-01 + 2.228000000000e-10 3.007016001191e-01 + 2.328000000000e-10 3.359037685855e-01 + 2.428000000000e-10 3.646369081917e-01 + 2.528000000000e-10 3.717564842409e-01 + 2.628000000000e-10 3.164681086559e-01 + 2.728000000000e-10 1.842122200319e-01 + 2.828000000000e-10 2.261788955655e-02 + 2.928000000000e-10 -1.190364341005e-01 + 3.028000000000e-10 -2.112326750882e-01 + 3.128000000000e-10 -2.547832728498e-01 + 3.228000000000e-10 -2.901354995194e-01 + 3.328000000000e-10 -3.261256516764e-01 + 3.428000000000e-10 -3.558916364396e-01 + 3.528000000000e-10 -3.643768878587e-01 + 3.628000000000e-10 -3.109660871267e-01 + 3.728000000000e-10 -1.806005122430e-01 + 3.828000000000e-10 -2.063463882859e-02 + 3.928000000000e-10 1.200417121301e-01 + 4.028000000000e-10 2.117115066678e-01 + 4.128000000000e-10 2.552245954862e-01 + 4.228000000000e-10 2.905358174314e-01 + 4.328000000000e-10 3.264964127076e-01 + 4.428000000000e-10 3.561164409890e-01 + 4.528000000000e-10 3.644937527082e-01 + 4.628000000000e-10 3.108863598347e-01 + 4.728000000000e-10 1.804066968471e-01 + 4.828000000000e-10 2.031749353463e-02 + 4.928000000000e-10 -1.203543467152e-01 + 5.028000000000e-10 -2.120338656010e-01 + 5.128000000000e-10 -2.554694201182e-01 + 5.228000000000e-10 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7.728000000000e-10 -1.804978632753e-01 + 7.828000000000e-10 -2.040852410596e-02 + 7.928000000000e-10 1.203110667878e-01 + 8.028000000000e-10 2.119781439274e-01 + 8.128000000000e-10 2.554465105638e-01 + 8.228000000000e-10 2.907345088651e-01 + 8.328000000000e-10 3.266793442083e-01 + 8.428000000000e-10 3.562962712815e-01 + 8.528000000000e-10 3.646525269207e-01 + 8.628000000000e-10 3.110264147595e-01 + 8.728000000000e-10 1.805087495738e-01 + 8.828000000000e-10 2.039807927138e-02 + 8.928000000000e-10 -1.203008828088e-01 + 9.028000000000e-10 -2.119885143169e-01 + 9.128000000000e-10 -2.554368509477e-01 + 9.228000000000e-10 -2.907446372900e-01 + 9.328000000000e-10 -3.266695427412e-01 + 9.428000000000e-10 -3.563059183968e-01 + 9.528000000000e-10 -3.646431522847e-01 + 9.628000000000e-10 -3.110356032735e-01 + 9.728000000000e-10 -1.804991631480e-01 + 9.828000000000e-10 -2.040735001275e-02 + 9.928000000000e-10 1.203099974113e-01 + 1.000000000000e-09 1.927324868168e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/conditions.yaml new file mode 100644 index 00000000..560a31d3 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 16 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_16 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/CML_core_tb.sch new file mode 100644 index 00000000..15eda3fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/CML_core_tb_17.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/CML_core_tb_17.data new file mode 100644 index 00000000..1e62d263 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/CML_core_tb_17.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.857852225245e-01 + 1.728000000000e-10 -1.572533595452e-01 + 1.828000000000e-10 2.540381659783e-03 + 1.928000000000e-10 1.434374080790e-01 + 2.028000000000e-10 2.351272809546e-01 + 2.128000000000e-10 2.797956268783e-01 + 2.228000000000e-10 3.144243918962e-01 + 2.328000000000e-10 3.493618787392e-01 + 2.428000000000e-10 3.773715695689e-01 + 2.528000000000e-10 3.831823569325e-01 + 2.628000000000e-10 3.264482498061e-01 + 2.728000000000e-10 1.910530045686e-01 + 2.828000000000e-10 2.436059711742e-02 + 2.928000000000e-10 -1.220220612332e-01 + 3.028000000000e-10 -2.180809390746e-01 + 3.128000000000e-10 -2.653775774444e-01 + 3.228000000000e-10 -3.017848824321e-01 + 3.328000000000e-10 -3.379021858146e-01 + 3.428000000000e-10 -3.673696540777e-01 + 3.528000000000e-10 -3.751149757425e-01 + 3.628000000000e-10 -3.209083740174e-01 + 3.728000000000e-10 -1.878979131572e-01 + 3.828000000000e-10 -2.307531260616e-02 + 3.928000000000e-10 1.222703025101e-01 + 4.028000000000e-10 2.179003509445e-01 + 4.128000000000e-10 2.652908784701e-01 + 4.228000000000e-10 3.017672646237e-01 + 4.328000000000e-10 3.378931599738e-01 + 4.428000000000e-10 3.672390198172e-01 + 4.528000000000e-10 3.748903812400e-01 + 4.628000000000e-10 3.205316331029e-01 + 4.728000000000e-10 1.874647700937e-01 + 4.828000000000e-10 2.258819957166e-02 + 4.928000000000e-10 -1.227112688171e-01 + 5.028000000000e-10 -2.183172764214e-01 + 5.128000000000e-10 -2.656203742551e-01 + 5.228000000000e-10 -3.020800906145e-01 + 5.328000000000e-10 -3.381553362553e-01 + 5.428000000000e-10 -3.675051891202e-01 + 5.528000000000e-10 -3.750972240389e-01 + 5.628000000000e-10 -3.207148935088e-01 + 5.728000000000e-10 -1.875700292984e-01 + 5.828000000000e-10 -2.267596999196e-02 + 5.928000000000e-10 1.226776663562e-01 + 6.028000000000e-10 2.182733434309e-01 + 6.128000000000e-10 2.656053081095e-01 + 6.228000000000e-10 3.020411985396e-01 + 6.328000000000e-10 3.381435634392e-01 + 6.428000000000e-10 3.674743818406e-01 + 6.528000000000e-10 3.750952532513e-01 + 6.628000000000e-10 3.206986438750e-01 + 6.728000000000e-10 1.875816736609e-01 + 6.828000000000e-10 2.266940437016e-02 + 6.928000000000e-10 -1.226596158426e-01 + 7.028000000000e-10 -2.182776851932e-01 + 7.128000000000e-10 -2.655888997029e-01 + 7.228000000000e-10 -3.020470638059e-01 + 7.328000000000e-10 -3.381282771084e-01 + 7.428000000000e-10 -3.674800981492e-01 + 7.528000000000e-10 -3.750811166601e-01 + 7.628000000000e-10 -3.207046174850e-01 + 7.728000000000e-10 -1.875682790354e-01 + 7.828000000000e-10 -2.267703281628e-02 + 7.928000000000e-10 1.226713327530e-01 + 8.028000000000e-10 2.182693863135e-01 + 8.128000000000e-10 2.655996099454e-01 + 8.228000000000e-10 3.020383466326e-01 + 8.328000000000e-10 3.381385294735e-01 + 8.428000000000e-10 3.674717742910e-01 + 8.528000000000e-10 3.750907045119e-01 + 8.628000000000e-10 3.206966644115e-01 + 8.728000000000e-10 1.875773616331e-01 + 8.828000000000e-10 2.266807684955e-02 + 8.928000000000e-10 -1.226628120211e-01 + 9.028000000000e-10 -2.182782381400e-01 + 9.128000000000e-10 -2.655915506047e-01 + 9.228000000000e-10 -3.020469590318e-01 + 9.328000000000e-10 -3.381303351991e-01 + 9.428000000000e-10 -3.674798958779e-01 + 9.528000000000e-10 -3.750829516380e-01 + 9.628000000000e-10 -3.207043265993e-01 + 9.728000000000e-10 -1.875693454762e-01 + 9.828000000000e-10 -2.267594148777e-02 + 9.928000000000e-10 1.226704651969e-01 + 1.000000000000e-09 1.977257563344e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/conditions.yaml new file mode 100644 index 00000000..e78f9667 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 17 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_17 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/CML_core_tb.sch new file mode 100644 index 00000000..747c1e7c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/CML_core_tb_18.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/CML_core_tb_18.data new file mode 100644 index 00000000..16422ca1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/CML_core_tb_18.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.213526702696e-01 + 1.728000000000e-10 -1.557909441213e-01 + 1.828000000000e-10 3.476956205809e-02 + 1.928000000000e-10 1.811250151598e-01 + 2.028000000000e-10 2.596166993269e-01 + 2.128000000000e-10 2.853727091731e-01 + 2.228000000000e-10 3.254453264627e-01 + 2.328000000000e-10 3.792799604087e-01 + 2.428000000000e-10 4.176388066249e-01 + 2.528000000000e-10 4.205544301124e-01 + 2.628000000000e-10 3.463528198985e-01 + 2.728000000000e-10 1.792096076204e-01 + 2.828000000000e-10 -1.442396833933e-02 + 2.928000000000e-10 -1.649237711275e-01 + 3.028000000000e-10 -2.471596975948e-01 + 3.128000000000e-10 -2.748735614517e-01 + 3.228000000000e-10 -3.160128767795e-01 + 3.328000000000e-10 -3.707930594343e-01 + 3.428000000000e-10 -4.104823651943e-01 + 3.528000000000e-10 -4.153692056047e-01 + 3.628000000000e-10 -3.427931169871e-01 + 3.728000000000e-10 -1.769552164151e-01 + 3.828000000000e-10 1.590673093360e-02 + 3.928000000000e-10 1.658834812043e-01 + 4.028000000000e-10 2.479775600913e-01 + 4.128000000000e-10 2.756409688001e-01 + 4.228000000000e-10 3.168596600790e-01 + 4.328000000000e-10 3.715133147191e-01 + 4.428000000000e-10 4.111218222953e-01 + 4.528000000000e-10 4.157229971644e-01 + 4.628000000000e-10 3.430019798682e-01 + 4.728000000000e-10 1.769456026445e-01 + 4.828000000000e-10 -1.592886494610e-02 + 4.928000000000e-10 -1.659782283296e-01 + 5.028000000000e-10 -2.479947853664e-01 + 5.128000000000e-10 -2.756931315881e-01 + 5.228000000000e-10 -3.168416717549e-01 + 5.328000000000e-10 -3.715547211919e-01 + 5.428000000000e-10 -4.111034138799e-01 + 5.528000000000e-10 -4.157691346087e-01 + 5.628000000000e-10 -3.429925568898e-01 + 5.728000000000e-10 -1.770024985869e-01 + 5.828000000000e-10 1.592938202906e-02 + 5.928000000000e-10 1.659292038608e-01 + 6.028000000000e-10 2.480043512000e-01 + 6.128000000000e-10 2.756533285421e-01 + 6.228000000000e-10 3.168576585763e-01 + 6.328000000000e-10 3.715156583068e-01 + 6.428000000000e-10 4.111207690964e-01 + 6.528000000000e-10 4.157343976531e-01 + 6.628000000000e-10 3.430135347581e-01 + 6.728000000000e-10 1.769734665185e-01 + 6.828000000000e-10 -1.590652763180e-02 + 6.928000000000e-10 -1.659537152419e-01 + 7.028000000000e-10 -2.479812550746e-01 + 7.128000000000e-10 -2.756768834918e-01 + 7.228000000000e-10 -3.168350969677e-01 + 7.328000000000e-10 -3.715419152243e-01 + 7.428000000000e-10 -4.110983779981e-01 + 7.528000000000e-10 -4.157587194411e-01 + 7.628000000000e-10 -3.429901444601e-01 + 7.728000000000e-10 -1.769973775521e-01 + 7.828000000000e-10 1.592723735432e-02 + 7.928000000000e-10 1.659318535084e-01 + 8.028000000000e-10 2.480017799848e-01 + 8.128000000000e-10 2.756559811492e-01 + 8.228000000000e-10 3.168566227283e-01 + 8.328000000000e-10 3.715195500188e-01 + 8.428000000000e-10 4.111190536097e-01 + 8.528000000000e-10 4.157370668569e-01 + 8.628000000000e-10 3.430103710665e-01 + 8.728000000000e-10 1.769771675859e-01 + 8.828000000000e-10 -1.590770493918e-02 + 8.928000000000e-10 -1.659501582149e-01 + 9.028000000000e-10 -2.479827571068e-01 + 9.128000000000e-10 -2.756738772283e-01 + 9.228000000000e-10 -3.168377001445e-01 + 9.328000000000e-10 -3.715391180409e-01 + 9.428000000000e-10 -4.111007797151e-01 + 9.528000000000e-10 -4.157556639381e-01 + 9.628000000000e-10 -3.429919881202e-01 + 9.728000000000e-10 -1.769955652012e-01 + 9.828000000000e-10 1.592430721908e-02 + 9.928000000000e-10 1.659331850974e-01 + 1.000000000000e-09 2.332140069758e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/conditions.yaml new file mode 100644 index 00000000..ed935822 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 18 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_18 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/CML_core_tb.sch new file mode 100644 index 00000000..bd39eaa5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/CML_core_tb_19.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/CML_core_tb_19.data new file mode 100644 index 00000000..6e384890 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/CML_core_tb_19.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162777317791e-01 + 1.728000000000e-10 -1.528661974147e-01 + 1.828000000000e-10 3.474832458294e-02 + 1.928000000000e-10 1.787124308466e-01 + 2.028000000000e-10 2.559986610902e-01 + 2.128000000000e-10 2.810767408313e-01 + 2.228000000000e-10 3.219404824571e-01 + 2.328000000000e-10 3.760375868322e-01 + 2.428000000000e-10 4.141294975409e-01 + 2.528000000000e-10 4.175370858756e-01 + 2.628000000000e-10 3.443891646085e-01 + 2.728000000000e-10 1.786024667409e-01 + 2.828000000000e-10 -1.272368439666e-02 + 2.928000000000e-10 -1.612661145276e-01 + 3.028000000000e-10 -2.425558656005e-01 + 3.128000000000e-10 -2.696709375544e-01 + 3.228000000000e-10 -3.115976016931e-01 + 3.328000000000e-10 -3.666762080522e-01 + 3.428000000000e-10 -4.062269757432e-01 + 3.528000000000e-10 -4.117682170104e-01 + 3.628000000000e-10 -3.403932990270e-01 + 3.728000000000e-10 -1.760595961534e-01 + 3.828000000000e-10 1.438676142530e-02 + 3.928000000000e-10 1.623380571180e-01 + 4.028000000000e-10 2.434588647096e-01 + 4.128000000000e-10 2.705169080514e-01 + 4.228000000000e-10 3.125303134845e-01 + 4.328000000000e-10 3.674735521527e-01 + 4.428000000000e-10 4.069324770669e-01 + 4.528000000000e-10 4.121668816011e-01 + 4.628000000000e-10 3.406314536055e-01 + 4.728000000000e-10 1.760592839129e-01 + 4.828000000000e-10 -1.440702618479e-02 + 4.928000000000e-10 -1.624387020945e-01 + 5.028000000000e-10 -2.434775787799e-01 + 5.128000000000e-10 -2.705727170369e-01 + 5.228000000000e-10 -3.125119373252e-01 + 5.328000000000e-10 -3.675184828947e-01 + 5.428000000000e-10 -4.069140356329e-01 + 5.528000000000e-10 -4.122173977207e-01 + 5.628000000000e-10 -3.406230488723e-01 + 5.728000000000e-10 -1.761225643375e-01 + 5.828000000000e-10 1.440482600394e-02 + 5.928000000000e-10 1.623840500109e-01 + 6.028000000000e-10 2.434858819416e-01 + 6.128000000000e-10 2.705285901327e-01 + 6.228000000000e-10 3.125279242462e-01 + 6.328000000000e-10 3.674758375852e-01 + 6.428000000000e-10 4.069313048189e-01 + 6.528000000000e-10 4.121794941223e-01 + 6.628000000000e-10 3.406442721772e-01 + 6.728000000000e-10 1.760913923029e-01 + 6.828000000000e-10 -1.438048626859e-02 + 6.928000000000e-10 -1.624102913298e-01 + 7.028000000000e-10 -2.434611919520e-01 + 7.128000000000e-10 -2.705537859875e-01 + 7.228000000000e-10 -3.125040211699e-01 + 7.328000000000e-10 -3.675038904367e-01 + 7.428000000000e-10 -4.069074652851e-01 + 7.528000000000e-10 -4.122054838885e-01 + 7.628000000000e-10 -3.406192567768e-01 + 7.728000000000e-10 -1.761170868219e-01 + 7.828000000000e-10 1.440247036537e-02 + 7.928000000000e-10 1.623867436405e-01 + 8.028000000000e-10 2.434830143217e-01 + 8.128000000000e-10 2.705312548291e-01 + 8.228000000000e-10 3.125271394700e-01 + 8.328000000000e-10 3.674800931307e-01 + 8.428000000000e-10 4.069295144266e-01 + 8.528000000000e-10 4.121823557439e-01 + 8.628000000000e-10 3.406407407456e-01 + 8.728000000000e-10 1.760956573916e-01 + 8.828000000000e-10 -1.438135361500e-02 + 8.928000000000e-10 -1.624062315135e-01 + 9.028000000000e-10 -2.434625084707e-01 + 9.128000000000e-10 -2.705503455528e-01 + 9.228000000000e-10 -3.125068466958e-01 + 9.328000000000e-10 -3.675009271833e-01 + 9.428000000000e-10 -4.069098943042e-01 + 9.528000000000e-10 -4.122022218921e-01 + 9.628000000000e-10 -3.406210058100e-01 + 9.728000000000e-10 -1.761154015725e-01 + 9.828000000000e-10 1.439913133121e-02 + 9.928000000000e-10 1.623879640093e-01 + 1.000000000000e-09 2.290402036537e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/conditions.yaml new file mode 100644 index 00000000..ded425b2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 19 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_19 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/CML_core_tb.sch new file mode 100644 index 00000000..d8d0b2b6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/CML_core_tb_20.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/CML_core_tb_20.data new file mode 100644 index 00000000..3dfcf241 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/CML_core_tb_20.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.365386572536e-01 + 1.728000000000e-10 -1.657072094068e-01 + 1.828000000000e-10 3.099865584261e-02 + 1.928000000000e-10 1.820426436768e-01 + 2.028000000000e-10 2.627018214462e-01 + 2.128000000000e-10 2.893736945719e-01 + 2.228000000000e-10 3.287984169352e-01 + 2.328000000000e-10 3.833334317825e-01 + 2.428000000000e-10 4.238785365972e-01 + 2.528000000000e-10 4.280322768716e-01 + 2.628000000000e-10 3.532409470363e-01 + 2.728000000000e-10 1.834641899168e-01 + 2.828000000000e-10 -1.474496205711e-02 + 2.928000000000e-10 -1.691349612478e-01 + 3.028000000000e-10 -2.530204867896e-01 + 3.128000000000e-10 -2.814070764654e-01 + 3.228000000000e-10 -3.218416847899e-01 + 3.328000000000e-10 -3.771799136100e-01 + 3.428000000000e-10 -4.187055626636e-01 + 3.528000000000e-10 -4.243036771430e-01 + 3.628000000000e-10 -3.506062035467e-01 + 3.728000000000e-10 -1.816763297909e-01 + 3.828000000000e-10 1.601938741723e-02 + 3.928000000000e-10 1.700087907901e-01 + 4.028000000000e-10 2.537596951165e-01 + 4.128000000000e-10 2.820887501770e-01 + 4.228000000000e-10 3.225625541805e-01 + 4.328000000000e-10 3.777928583784e-01 + 4.428000000000e-10 4.192485534625e-01 + 4.528000000000e-10 4.246080285894e-01 + 4.628000000000e-10 3.507916132015e-01 + 4.728000000000e-10 1.816929452641e-01 + 4.828000000000e-10 -1.601075067965e-02 + 4.928000000000e-10 -1.700562644838e-01 + 5.028000000000e-10 -2.537513990380e-01 + 5.128000000000e-10 -2.821086741965e-01 + 5.228000000000e-10 -3.225309737549e-01 + 5.328000000000e-10 -3.778081660132e-01 + 5.428000000000e-10 -4.192196231589e-01 + 5.528000000000e-10 -4.246325132019e-01 + 5.628000000000e-10 -3.507765562578e-01 + 5.728000000000e-10 -1.817315603141e-01 + 5.828000000000e-10 1.601468821266e-02 + 5.928000000000e-10 1.700220210141e-01 + 6.028000000000e-10 2.537612841477e-01 + 6.128000000000e-10 2.820810469197e-01 + 6.228000000000e-10 3.225454957468e-01 + 6.328000000000e-10 3.777800822765e-01 + 6.428000000000e-10 4.192350742948e-01 + 6.528000000000e-10 4.246071005326e-01 + 6.628000000000e-10 3.507940665347e-01 + 6.728000000000e-10 1.817094337521e-01 + 6.828000000000e-10 -1.599736953115e-02 + 6.928000000000e-10 -1.700405869499e-01 + 7.028000000000e-10 -2.537437685408e-01 + 7.128000000000e-10 -2.820988428465e-01 + 7.228000000000e-10 -3.225283133162e-01 + 7.328000000000e-10 -3.778004844844e-01 + 7.428000000000e-10 -4.192180216890e-01 + 7.528000000000e-10 -4.246257635725e-01 + 7.628000000000e-10 -3.507760422929e-01 + 7.728000000000e-10 -1.817278922025e-01 + 7.828000000000e-10 1.601285231965e-02 + 7.928000000000e-10 1.700238629540e-01 + 8.028000000000e-10 2.537592487741e-01 + 8.128000000000e-10 2.820829438407e-01 + 8.228000000000e-10 3.225445511573e-01 + 8.328000000000e-10 3.777829985044e-01 + 8.428000000000e-10 4.192337708379e-01 + 8.528000000000e-10 4.246090234999e-01 + 8.628000000000e-10 3.507916632731e-01 + 8.728000000000e-10 1.817122417436e-01 + 8.828000000000e-10 -1.599824136343e-02 + 8.928000000000e-10 -1.700377849177e-01 + 9.028000000000e-10 -2.537449127629e-01 + 9.128000000000e-10 -2.820965585668e-01 + 9.228000000000e-10 -3.225302446360e-01 + 9.328000000000e-10 -3.777982010874e-01 + 9.428000000000e-10 -4.192199753705e-01 + 9.528000000000e-10 -4.246232587341e-01 + 9.628000000000e-10 -3.507775800865e-01 + 9.728000000000e-10 -1.817263367247e-01 + 9.828000000000e-10 1.601066647660e-02 + 9.928000000000e-10 1.700248857455e-01 + 1.000000000000e-09 2.385375784000e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/conditions.yaml new file mode 100644 index 00000000..3304573d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 20 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_20 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/CML_core_tb.sch new file mode 100644 index 00000000..e693f6be --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/CML_core_tb_21.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/CML_core_tb_21.data new file mode 100644 index 00000000..86f9b023 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/CML_core_tb_21.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.747912795524e-01 + 1.728000000000e-10 -1.327955908449e-01 + 1.828000000000e-10 3.931332790349e-02 + 1.928000000000e-10 1.782957289495e-01 + 2.028000000000e-10 2.573194188668e-01 + 2.128000000000e-10 2.870254911902e-01 + 2.228000000000e-10 3.228650321442e-01 + 2.328000000000e-10 3.690575149088e-01 + 2.428000000000e-10 4.023791308175e-01 + 2.528000000000e-10 4.034409994944e-01 + 2.628000000000e-10 3.332295993533e-01 + 2.728000000000e-10 1.767123870243e-01 + 2.828000000000e-10 -7.574880255958e-03 + 2.928000000000e-10 -1.550892096227e-01 + 3.028000000000e-10 -2.394679486139e-01 + 3.128000000000e-10 -2.715465054757e-01 + 3.228000000000e-10 -3.085580168164e-01 + 3.328000000000e-10 -3.560821219044e-01 + 3.428000000000e-10 -3.914831036325e-01 + 3.528000000000e-10 -3.956717314322e-01 + 3.628000000000e-10 -3.285929470428e-01 + 3.728000000000e-10 -1.747908753666e-01 + 3.828000000000e-10 7.882784627431e-03 + 3.928000000000e-10 1.545893087045e-01 + 4.028000000000e-10 2.389887597051e-01 + 4.128000000000e-10 2.712307710628e-01 + 4.228000000000e-10 3.085047043395e-01 + 4.328000000000e-10 3.559448484744e-01 + 4.428000000000e-10 3.913507819782e-01 + 4.528000000000e-10 3.953547803018e-01 + 4.628000000000e-10 3.282585464854e-01 + 4.728000000000e-10 1.743078825018e-01 + 4.828000000000e-10 -8.291328068348e-03 + 4.928000000000e-10 -1.550293895867e-01 + 5.028000000000e-10 -2.392804293874e-01 + 5.128000000000e-10 -2.715405217782e-01 + 5.228000000000e-10 -3.087067361985e-01 + 5.328000000000e-10 -3.562070457914e-01 + 5.428000000000e-10 -3.915132320474e-01 + 5.528000000000e-10 -3.955548280332e-01 + 5.628000000000e-10 -3.283427048941e-01 + 5.728000000000e-10 -1.744282326244e-01 + 5.828000000000e-10 8.270645751064e-03 + 5.928000000000e-10 1.549582711486e-01 + 6.028000000000e-10 2.392860039329e-01 + 6.128000000000e-10 2.714820836214e-01 + 6.228000000000e-10 3.087161022039e-01 + 6.328000000000e-10 3.561494137047e-01 + 6.428000000000e-10 3.915273490759e-01 + 6.528000000000e-10 3.955079501007e-01 + 6.628000000000e-10 3.283677191723e-01 + 6.728000000000e-10 1.743944727908e-01 + 6.828000000000e-10 -8.238033211244e-03 + 6.928000000000e-10 -1.549849820320e-01 + 7.028000000000e-10 -2.392533741503e-01 + 7.128000000000e-10 -2.715088112944e-01 + 7.228000000000e-10 -3.086845279612e-01 + 7.328000000000e-10 -3.561786907982e-01 + 7.428000000000e-10 -3.914967682891e-01 + 7.528000000000e-10 -3.955360247734e-01 + 7.628000000000e-10 -3.283379458960e-01 + 7.728000000000e-10 -1.744219452106e-01 + 7.828000000000e-10 8.266285029230e-03 + 7.928000000000e-10 1.549592969714e-01 + 8.028000000000e-10 2.392805186707e-01 + 8.128000000000e-10 2.714837558368e-01 + 8.228000000000e-10 3.087120651005e-01 + 8.328000000000e-10 3.561520690508e-01 + 8.428000000000e-10 3.915233230940e-01 + 8.528000000000e-10 3.955100606400e-01 + 8.628000000000e-10 3.283632493206e-01 + 8.728000000000e-10 1.743968536756e-01 + 8.828000000000e-10 -8.241845610385e-03 + 8.928000000000e-10 -1.549825747228e-01 + 9.028000000000e-10 -2.392568734068e-01 + 9.128000000000e-10 -2.715063119250e-01 + 9.228000000000e-10 -3.086881712182e-01 + 9.328000000000e-10 -3.561760305782e-01 + 9.428000000000e-10 -3.915002731039e-01 + 9.528000000000e-10 -3.955331724158e-01 + 9.628000000000e-10 -3.283409163093e-01 + 9.728000000000e-10 -1.744193777973e-01 + 9.828000000000e-10 8.263272108901e-03 + 9.928000000000e-10 1.549616575981e-01 + 1.000000000000e-09 2.229820050464e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/conditions.yaml new file mode 100644 index 00000000..0f905c49 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 21 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_21 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/CML_core_tb.sch new file mode 100644 index 00000000..145b2a64 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/CML_core_tb_22.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/CML_core_tb_22.data new file mode 100644 index 00000000..ef0e6c8e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/CML_core_tb_22.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.701426652476e-01 + 1.728000000000e-10 -1.295079168872e-01 + 1.828000000000e-10 4.028305902420e-02 + 1.928000000000e-10 1.769160181627e-01 + 2.028000000000e-10 2.543038782058e-01 + 2.128000000000e-10 2.828787064062e-01 + 2.228000000000e-10 3.193333275112e-01 + 2.328000000000e-10 3.660596632426e-01 + 2.428000000000e-10 3.993599084345e-01 + 2.528000000000e-10 4.007883413226e-01 + 2.628000000000e-10 3.312419521143e-01 + 2.728000000000e-10 1.754810620333e-01 + 2.828000000000e-10 -7.142746942805e-03 + 2.928000000000e-10 -1.527779354444e-01 + 3.028000000000e-10 -2.358001938178e-01 + 3.128000000000e-10 -2.668485168237e-01 + 3.228000000000e-10 -3.044746718514e-01 + 3.328000000000e-10 -3.525545062341e-01 + 3.428000000000e-10 -3.880254364838e-01 + 3.528000000000e-10 -3.926522183008e-01 + 3.628000000000e-10 -3.262954780243e-01 + 3.728000000000e-10 -1.733443838482e-01 + 3.828000000000e-10 7.573790689709e-03 + 3.928000000000e-10 1.523487073311e-01 + 4.028000000000e-10 2.353677758316e-01 + 4.128000000000e-10 2.665695097895e-01 + 4.228000000000e-10 3.044490522149e-01 + 4.328000000000e-10 3.524353166192e-01 + 4.428000000000e-10 3.879041587545e-01 + 4.528000000000e-10 3.923389296672e-01 + 4.628000000000e-10 3.259554596391e-01 + 4.728000000000e-10 1.728458619818e-01 + 4.828000000000e-10 -8.002573892585e-03 + 4.928000000000e-10 -1.528088090159e-01 + 5.028000000000e-10 -2.356747724378e-01 + 5.128000000000e-10 -2.668925685814e-01 + 5.228000000000e-10 -3.046638401901e-01 + 5.328000000000e-10 -3.527112223433e-01 + 5.428000000000e-10 -3.880786380631e-01 + 5.528000000000e-10 -3.925506229445e-01 + 5.628000000000e-10 -3.260495799326e-01 + 5.728000000000e-10 -1.729761662154e-01 + 5.828000000000e-10 7.974498187451e-03 + 5.928000000000e-10 1.527311696558e-01 + 6.028000000000e-10 2.356760074325e-01 + 6.128000000000e-10 2.668297167568e-01 + 6.228000000000e-10 3.046702367069e-01 + 6.328000000000e-10 3.526500635637e-01 + 6.428000000000e-10 3.880902250634e-01 + 6.528000000000e-10 3.925010528185e-01 + 6.628000000000e-10 3.260730653917e-01 + 6.728000000000e-10 1.729410953112e-01 + 6.828000000000e-10 -7.941970684065e-03 + 6.928000000000e-10 -1.527585341072e-01 + 7.028000000000e-10 -2.356430884825e-01 + 7.128000000000e-10 -2.668569558480e-01 + 7.228000000000e-10 -3.046384985761e-01 + 7.328000000000e-10 -3.526798341051e-01 + 7.428000000000e-10 -3.880593641809e-01 + 7.528000000000e-10 -3.925295324367e-01 + 7.628000000000e-10 -3.260427874257e-01 + 7.728000000000e-10 -1.729689796013e-01 + 7.828000000000e-10 7.970639231343e-03 + 7.928000000000e-10 1.527324506408e-01 + 8.028000000000e-10 2.356706370408e-01 + 8.128000000000e-10 2.668314718812e-01 + 8.228000000000e-10 3.046665550415e-01 + 8.328000000000e-10 3.526529348742e-01 + 8.428000000000e-10 3.880863283995e-01 + 8.528000000000e-10 3.925032166540e-01 + 8.628000000000e-10 3.260684590033e-01 + 8.728000000000e-10 1.729436324779e-01 + 8.828000000000e-10 -7.945691115533e-03 + 8.928000000000e-10 -1.527560420249e-01 + 9.028000000000e-10 -2.356465048672e-01 + 9.128000000000e-10 -2.668543449819e-01 + 9.228000000000e-10 -3.046422495200e-01 + 9.328000000000e-10 -3.526772110923e-01 + 9.428000000000e-10 -3.880628732866e-01 + 9.528000000000e-10 -3.925266759429e-01 + 9.628000000000e-10 -3.260456785141e-01 + 9.728000000000e-10 -1.729665660062e-01 + 9.828000000000e-10 7.967487161613e-03 + 9.928000000000e-10 1.527347010769e-01 + 1.000000000000e-09 2.198236907112e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/conditions.yaml new file mode 100644 index 00000000..be2ca052 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 22 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_22 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/CML_core_tb.sch new file mode 100644 index 00000000..3b38e8ea --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/CML_core_tb_23.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/CML_core_tb_23.data new file mode 100644 index 00000000..7b2e7ab2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/CML_core_tb_23.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.957054612407e-01 + 1.728000000000e-10 -1.475216919691e-01 + 1.828000000000e-10 3.196996632833e-02 + 1.928000000000e-10 1.773696584526e-01 + 2.028000000000e-10 2.602670445343e-01 + 2.128000000000e-10 2.919684489720e-01 + 2.228000000000e-10 3.273690981683e-01 + 2.328000000000e-10 3.736661732429e-01 + 2.428000000000e-10 4.086769482098e-01 + 2.528000000000e-10 4.113258498473e-01 + 2.628000000000e-10 3.414272197123e-01 + 2.728000000000e-10 1.833836328070e-01 + 2.828000000000e-10 -4.501363849837e-03 + 2.928000000000e-10 -1.562318489881e-01 + 3.028000000000e-10 -2.435570784568e-01 + 3.128000000000e-10 -2.775386220390e-01 + 3.228000000000e-10 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2.778849719194e-01 + 8.228000000000e-10 3.147945034671e-01 + 8.328000000000e-10 3.622568751046e-01 + 8.428000000000e-10 3.989662140554e-01 + 8.528000000000e-10 4.041558823701e-01 + 8.628000000000e-10 3.369030769235e-01 + 8.728000000000e-10 1.809706945647e-01 + 8.828000000000e-10 -5.568483515763e-03 + 8.928000000000e-10 -1.566340912711e-01 + 9.028000000000e-10 -2.438236181184e-01 + 9.128000000000e-10 -2.779064153414e-01 + 9.228000000000e-10 -3.147718720666e-01 + 9.328000000000e-10 -3.622798572716e-01 + 9.428000000000e-10 -3.989444036153e-01 + 9.528000000000e-10 -4.041778978449e-01 + 9.628000000000e-10 -3.368819513246e-01 + 9.728000000000e-10 -1.809921012276e-01 + 9.828000000000e-10 5.588724287086e-03 + 9.928000000000e-10 1.566143682128e-01 + 1.000000000000e-09 2.267750497136e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/conditions.yaml new file mode 100644 index 00000000..0f176bd5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 23 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_23 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/CML_core_tb.sch new file mode 100644 index 00000000..1f05f444 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/CML_core_tb_24.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/CML_core_tb_24.data new file mode 100644 index 00000000..a01deb89 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/CML_core_tb_24.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.908985659112e-01 + 1.728000000000e-10 -9.049079150817e-02 + 1.828000000000e-10 3.945873683219e-02 + 1.928000000000e-10 1.521437177417e-01 + 2.028000000000e-10 2.220068772324e-01 + 2.128000000000e-10 2.535092334052e-01 + 2.228000000000e-10 2.861973397174e-01 + 2.328000000000e-10 3.239843013312e-01 + 2.428000000000e-10 3.520113017607e-01 + 2.528000000000e-10 3.540468115658e-01 + 2.628000000000e-10 2.949447709683e-01 + 2.728000000000e-10 1.587983397866e-01 + 2.828000000000e-10 -6.865354773069e-03 + 2.928000000000e-10 -1.448078480843e-01 + 3.028000000000e-10 -2.275605338030e-01 + 3.128000000000e-10 -2.625604064747e-01 + 3.228000000000e-10 -2.958552078644e-01 + 3.328000000000e-10 -3.351711406638e-01 + 3.428000000000e-10 -3.644984224381e-01 + 3.528000000000e-10 -3.669950471097e-01 + 3.628000000000e-10 -3.072796408874e-01 + 3.728000000000e-10 -1.699866077827e-01 + 3.828000000000e-10 -2.842045316933e-03 + 3.928000000000e-10 1.365086891956e-01 + 4.028000000000e-10 2.207869920157e-01 + 4.128000000000e-10 2.567713461579e-01 + 4.228000000000e-10 2.907030026757e-01 + 4.328000000000e-10 3.302687598301e-01 + 4.428000000000e-10 3.600803190405e-01 + 4.528000000000e-10 3.632331450943e-01 + 4.628000000000e-10 3.045482678871e-01 + 4.728000000000e-10 1.682698274629e-01 + 4.828000000000e-10 2.058504292284e-03 + 4.928000000000e-10 -1.367871396964e-01 + 5.028000000000e-10 -2.207717990252e-01 + 5.128000000000e-10 -2.567684885934e-01 + 5.228000000000e-10 -2.906651825463e-01 + 5.328000000000e-10 -3.302494358660e-01 + 5.428000000000e-10 -3.599712284157e-01 + 5.528000000000e-10 -3.631239508150e-01 + 5.628000000000e-10 -3.043584109358e-01 + 5.728000000000e-10 -1.680958385636e-01 + 5.828000000000e-10 -1.834034512727e-03 + 5.928000000000e-10 1.369613450439e-01 + 6.028000000000e-10 2.209618957221e-01 + 6.128000000000e-10 2.568952536478e-01 + 6.228000000000e-10 2.908171185353e-01 + 6.328000000000e-10 3.303549214919e-01 + 6.428000000000e-10 3.601082390759e-01 + 6.528000000000e-10 3.632059905221e-01 + 6.628000000000e-10 3.044557238628e-01 + 6.728000000000e-10 1.681292777859e-01 + 6.828000000000e-10 1.882442241730e-03 + 6.928000000000e-10 -1.369637862409e-01 + 7.028000000000e-10 -2.209363992802e-01 + 7.128000000000e-10 -2.569065829626e-01 + 7.228000000000e-10 -2.907936706940e-01 + 7.328000000000e-10 -3.303682701482e-01 + 7.428000000000e-10 -3.600879594395e-01 + 7.528000000000e-10 -3.632220959958e-01 + 7.628000000000e-10 -3.044401007882e-01 + 7.728000000000e-10 -1.681486407544e-01 + 7.828000000000e-10 -1.870004957548e-03 + 7.928000000000e-10 1.369437070838e-01 + 8.028000000000e-10 2.209481957039e-01 + 8.128000000000e-10 2.568879030180e-01 + 8.228000000000e-10 2.908064848389e-01 + 8.328000000000e-10 3.303493303219e-01 + 8.428000000000e-10 3.601006147126e-01 + 8.528000000000e-10 3.632041339109e-01 + 8.628000000000e-10 3.044528281549e-01 + 8.728000000000e-10 1.681322760827e-01 + 8.828000000000e-10 1.883536763259e-03 + 8.928000000000e-10 -1.369582535540e-01 + 9.028000000000e-10 -2.209346296842e-01 + 9.128000000000e-10 -2.569016830366e-01 + 9.228000000000e-10 -2.907925936742e-01 + 9.328000000000e-10 -3.303636164667e-01 + 9.428000000000e-10 -3.600871302257e-01 + 9.528000000000e-10 -3.632178492939e-01 + 9.628000000000e-10 -3.044398392752e-01 + 9.728000000000e-10 -1.681454261603e-01 + 9.828000000000e-10 -1.870628705438e-03 + 9.928000000000e-10 1.369459433541e-01 + 1.000000000000e-09 2.037746084522e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/conditions.yaml new file mode 100644 index 00000000..0e0ae605 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 24 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_24 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/CML_core_tb.sch new file mode 100644 index 00000000..4d823c30 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/CML_core_tb_25.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/CML_core_tb_25.data new file mode 100644 index 00000000..182746dc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/CML_core_tb_25.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.878715792581e-01 + 1.728000000000e-10 -8.812036120597e-02 + 1.828000000000e-10 4.046526586524e-02 + 1.928000000000e-10 1.515705626527e-01 + 2.028000000000e-10 2.200566198342e-01 + 2.128000000000e-10 2.503583455541e-01 + 2.228000000000e-10 2.832914205797e-01 + 2.328000000000e-10 3.216696186231e-01 + 2.428000000000e-10 3.500303926946e-01 + 2.528000000000e-10 3.524815741411e-01 + 2.628000000000e-10 2.936462106779e-01 + 2.728000000000e-10 1.576219496242e-01 + 2.828000000000e-10 -7.121462127754e-03 + 2.928000000000e-10 -1.436071598858e-01 + 3.028000000000e-10 -2.249496922999e-01 + 3.128000000000e-10 -2.586592240194e-01 + 3.228000000000e-10 -2.922419569702e-01 + 3.328000000000e-10 -3.321983211521e-01 + 3.428000000000e-10 -3.618684381611e-01 + 3.528000000000e-10 -3.648249016007e-01 + 3.628000000000e-10 -3.055379959953e-01 + 3.728000000000e-10 -1.686105488568e-01 + 3.828000000000e-10 -2.582643774162e-03 + 3.928000000000e-10 1.352182085241e-01 + 4.028000000000e-10 2.180702244722e-01 + 4.128000000000e-10 2.527783389641e-01 + 4.228000000000e-10 2.869845016096e-01 + 4.328000000000e-10 3.271697550530e-01 + 4.428000000000e-10 3.573213651505e-01 + 4.528000000000e-10 3.609341509143e-01 + 4.628000000000e-10 3.026708512688e-01 + 4.728000000000e-10 1.667591862946e-01 + 4.828000000000e-10 1.676053368052e-03 + 4.928000000000e-10 -1.356064331336e-01 + 5.028000000000e-10 -2.181494577446e-01 + 5.128000000000e-10 -2.528581012316e-01 + 5.228000000000e-10 -2.870203472690e-01 + 5.328000000000e-10 -3.272198972187e-01 + 5.428000000000e-10 -3.572767955086e-01 + 5.528000000000e-10 -3.608816832152e-01 + 5.628000000000e-10 -3.025243774497e-01 + 5.728000000000e-10 -1.666129730216e-01 + 5.828000000000e-10 -1.465204057357e-03 + 5.928000000000e-10 1.357749931272e-01 + 6.028000000000e-10 2.183376260095e-01 + 6.128000000000e-10 2.529831758691e-01 + 6.228000000000e-10 2.871716452249e-01 + 6.328000000000e-10 3.273254918206e-01 + 6.428000000000e-10 3.574148326524e-01 + 6.528000000000e-10 3.609652866209e-01 + 6.628000000000e-10 3.026246199120e-01 + 6.728000000000e-10 1.666502220733e-01 + 6.828000000000e-10 1.518129196282e-03 + 6.928000000000e-10 -1.357732099566e-01 + 7.028000000000e-10 -2.183080403425e-01 + 7.128000000000e-10 -2.529912058397e-01 + 7.228000000000e-10 -2.871450109118e-01 + 7.328000000000e-10 -3.273360198503e-01 + 7.428000000000e-10 -3.573916245859e-01 + 7.528000000000e-10 -3.609790664977e-01 + 7.628000000000e-10 -3.026068066478e-01 + 7.728000000000e-10 -1.666683959674e-01 + 7.828000000000e-10 -1.504711775466e-03 + 7.928000000000e-10 1.357534602326e-01 + 8.028000000000e-10 2.183202914392e-01 + 8.128000000000e-10 2.529726082081e-01 + 8.228000000000e-10 2.871582302084e-01 + 8.328000000000e-10 3.273171284192e-01 + 8.428000000000e-10 3.574045685766e-01 + 8.528000000000e-10 3.609610284998e-01 + 8.628000000000e-10 3.026196909841e-01 + 8.728000000000e-10 1.666518528053e-01 + 8.828000000000e-10 1.518315117290e-03 + 8.928000000000e-10 -1.357682747942e-01 + 9.028000000000e-10 -2.183066580359e-01 + 9.128000000000e-10 -2.529866332266e-01 + 9.228000000000e-10 -2.871442829871e-01 + 9.328000000000e-10 -3.273316607928e-01 + 9.428000000000e-10 -3.573910212469e-01 + 9.528000000000e-10 -3.609749965926e-01 + 9.628000000000e-10 -3.026065830591e-01 + 9.728000000000e-10 -1.666652414066e-01 + 9.828000000000e-10 -1.505286118034e-03 + 9.928000000000e-10 1.357557668798e-01 + 1.000000000000e-09 2.016242513907e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/conditions.yaml new file mode 100644 index 00000000..26495c93 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 25 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_25 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/CML_core_tb.sch new file mode 100644 index 00000000..932ad888 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/CML_core_tb_26.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/CML_core_tb_26.data new file mode 100644 index 00000000..c21b093d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/CML_core_tb_26.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.135873679018e-01 + 1.728000000000e-10 -1.054229355639e-01 + 1.828000000000e-10 3.485798650969e-02 + 1.928000000000e-10 1.569675139767e-01 + 2.028000000000e-10 2.330635404696e-01 + 2.128000000000e-10 2.680443549179e-01 + 2.228000000000e-10 3.014044829899e-01 + 2.328000000000e-10 3.394080314353e-01 + 2.428000000000e-10 3.679529618424e-01 + 2.528000000000e-10 3.700593040123e-01 + 2.628000000000e-10 3.097824620429e-01 + 2.728000000000e-10 1.706514675999e-01 + 2.828000000000e-10 3.558070014658e-04 + 2.928000000000e-10 -1.428409974599e-01 + 3.028000000000e-10 -2.298289579719e-01 + 3.128000000000e-10 -2.678794741753e-01 + 3.228000000000e-10 -3.017454056957e-01 + 3.328000000000e-10 -3.410620518407e-01 + 3.428000000000e-10 -3.712405389398e-01 + 3.528000000000e-10 -3.749327973471e-01 + 3.628000000000e-10 -3.157484466493e-01 + 3.728000000000e-10 -1.773087198166e-01 + 3.828000000000e-10 -7.070252178339e-03 + 3.928000000000e-10 1.364462941621e-01 + 4.028000000000e-10 2.243241068758e-01 + 4.128000000000e-10 2.631279769125e-01 + 4.228000000000e-10 2.976097246349e-01 + 4.328000000000e-10 3.371159716785e-01 + 4.428000000000e-10 3.676405775058e-01 + 4.528000000000e-10 3.717787254056e-01 + 4.628000000000e-10 3.133854979421e-01 + 4.728000000000e-10 1.756870158595e-01 + 4.828000000000e-10 6.171257018760e-03 + 4.928000000000e-10 -1.369680995621e-01 + 5.028000000000e-10 -2.245781248931e-01 + 5.128000000000e-10 -2.633829468620e-01 + 5.228000000000e-10 -2.978042748481e-01 + 5.328000000000e-10 -3.373348877854e-01 + 5.428000000000e-10 -3.677584906255e-01 + 5.528000000000e-10 -3.718812762918e-01 + 5.628000000000e-10 -3.133649557524e-01 + 5.728000000000e-10 -1.756479312047e-01 + 5.828000000000e-10 -6.040608056278e-03 + 5.928000000000e-10 1.370690415770e-01 + 6.028000000000e-10 2.247181767783e-01 + 6.128000000000e-10 2.634617265965e-01 + 6.228000000000e-10 2.979157296699e-01 + 6.328000000000e-10 3.373958940353e-01 + 6.428000000000e-10 3.678612954525e-01 + 6.528000000000e-10 3.719309221475e-01 + 6.628000000000e-10 3.134447453066e-01 + 6.728000000000e-10 1.756687688086e-01 + 6.828000000000e-10 6.090200135509e-03 + 6.928000000000e-10 -1.370702307281e-01 + 7.028000000000e-10 -2.246847420648e-01 + 7.128000000000e-10 -2.634701196121e-01 + 7.228000000000e-10 -2.978849158722e-01 + 7.328000000000e-10 -3.374068878437e-01 + 7.428000000000e-10 -3.678336110941e-01 + 7.528000000000e-10 -3.719446503824e-01 + 7.628000000000e-10 -3.134227431793e-01 + 7.728000000000e-10 -1.756868885858e-01 + 7.828000000000e-10 -6.072676723321e-03 + 7.928000000000e-10 1.370503070743e-01 + 8.028000000000e-10 2.247004966695e-01 + 8.128000000000e-10 2.634509722982e-01 + 8.228000000000e-10 2.979013793804e-01 + 8.328000000000e-10 3.373870921905e-01 + 8.428000000000e-10 3.678495602861e-01 + 8.528000000000e-10 3.719256264749e-01 + 8.628000000000e-10 3.134381864470e-01 + 8.728000000000e-10 1.756688935561e-01 + 8.828000000000e-10 6.088345643719e-03 + 8.928000000000e-10 -1.370666831053e-01 + 9.028000000000e-10 -2.246851372638e-01 + 9.128000000000e-10 -2.634666121684e-01 + 9.228000000000e-10 -2.978856025968e-01 + 9.328000000000e-10 -3.374033621769e-01 + 9.428000000000e-10 -3.678342837151e-01 + 9.528000000000e-10 -3.719412125322e-01 + 9.628000000000e-10 -3.134235677100e-01 + 9.728000000000e-10 -1.756838495744e-01 + 9.828000000000e-10 -6.073781243164e-03 + 9.928000000000e-10 1.370527135588e-01 + 1.000000000000e-09 2.065229990524e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/conditions.yaml new file mode 100644 index 00000000..17737255 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 26 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/run_26 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..1c9074b8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,28 @@ +run,corner,temperature,vdd,time,vo_diff,frequency +run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.111e-01, -1.870e-01, -3.563e-02, …]",4.722e+09 +run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.099e-01, -1.895e-01, -4.060e-02, …]",4.722e+09 +run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.876e-01, -3.217e-02, …]",4.722e+09 +run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.915e-01, -1.780e-01, -3.803e-02, …]",4.722e+09 +run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.909e-01, -1.806e-01, -4.276e-02, …]",4.722e+09 +run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.959e-01, -1.792e-01, -3.599e-02, …]",4.722e+09 +run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.689e-01, -1.692e-01, -4.423e-02, …]",4.722e+09 +run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.694e-01, -1.722e-01, -4.907e-02, …]",4.722e+09 +run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.723e-01, -1.701e-01, -4.252e-02, …]",4.722e+09 +run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.623e-01, -1.963e-01, -5.713e-03, …]",4.722e+09 +run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.622e-01, -1.984e-01, -1.024e-02, …]",4.722e+09 +run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.669e-01, -1.979e-01, -3.070e-03, …]",4.722e+09 +run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",4.722e+09 +run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.407e-01, -1.880e-01, -9.263e-03, …]",4.722e+09 +run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.446e-01, -1.889e-01, -5.355e-03, …]",4.722e+09 +run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.832e-01, -1.548e-01, 2.955e-03, …]",4.722e+09 +run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.908e-01, -1.609e-01, -2.321e-03, …]",4.722e+09 +run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.858e-01, -1.573e-01, 2.540e-03, …]",4.722e+09 +run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.214e-01, -1.558e-01, 3.477e-02, …]",4.722e+09 +run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.529e-01, 3.475e-02, …]",4.722e+09 +run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.365e-01, -1.657e-01, 3.100e-02, …]",4.722e+09 +run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.748e-01, -1.328e-01, 3.931e-02, …]",4.722e+09 +run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.701e-01, -1.295e-01, 4.028e-02, …]",4.722e+09 +run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.957e-01, -1.475e-01, 3.197e-02, …]",4.722e+09 +run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.909e-01, -9.049e-02, 3.946e-02, …]",4.722e+09 +run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.879e-01, -8.812e-02, 4.047e-02, …]",4.722e+09 +run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.136e-01, -1.054e-01, 3.486e-02, …]",4.722e+09 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..31c8cc54 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-46-18/parameters/Frequency/simulation_summary.md @@ -0,0 +1,31 @@ +# Simulation Summary for Freq + +| run | corner | temperature | vdd | time | vo_diff | frequency | +| :-- | -----: | ----------: | --: | ---: | ------: | --------: | +| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.111e-01, -1.870e-01, -3.563e-02, …] | 4.722e+09 | +| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.099e-01, -1.895e-01, -4.060e-02, …] | 4.722e+09 | +| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.876e-01, -3.217e-02, …] | 4.722e+09 | +| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.915e-01, -1.780e-01, -3.803e-02, …] | 4.722e+09 | +| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.909e-01, -1.806e-01, -4.276e-02, …] | 4.722e+09 | +| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.959e-01, -1.792e-01, -3.599e-02, …] | 4.722e+09 | +| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.689e-01, -1.692e-01, -4.423e-02, …] | 4.722e+09 | +| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.694e-01, -1.722e-01, -4.907e-02, …] | 4.722e+09 | +| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.723e-01, -1.701e-01, -4.252e-02, …] | 4.722e+09 | +| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.623e-01, -1.963e-01, -5.713e-03, …] | 4.722e+09 | +| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.622e-01, -1.984e-01, -1.024e-02, …] | 4.722e+09 | +| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.669e-01, -1.979e-01, -3.070e-03, …] | 4.722e+09 | +| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 4.722e+09 | +| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.407e-01, -1.880e-01, -9.263e-03, …] | 4.722e+09 | +| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.446e-01, -1.889e-01, -5.355e-03, …] | 4.722e+09 | +| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.832e-01, -1.548e-01, 2.955e-03, …] | 4.722e+09 | +| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.908e-01, -1.609e-01, -2.321e-03, …] | 4.722e+09 | +| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.858e-01, -1.573e-01, 2.540e-03, …] | 4.722e+09 | +| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.214e-01, -1.558e-01, 3.477e-02, …] | 4.722e+09 | +| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.529e-01, 3.475e-02, …] | 4.722e+09 | +| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.365e-01, -1.657e-01, 3.100e-02, …] | 4.722e+09 | +| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.748e-01, -1.328e-01, 3.931e-02, …] | 4.722e+09 | +| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.701e-01, -1.295e-01, 4.028e-02, …] | 4.722e+09 | +| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.957e-01, -1.475e-01, 3.197e-02, …] | 4.722e+09 | +| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.909e-01, -9.049e-02, 3.946e-02, …] | 4.722e+09 | +| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.879e-01, -8.812e-02, 4.047e-02, …] | 4.722e+09 | +| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.136e-01, -1.054e-01, 3.486e-02, …] | 4.722e+09 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/frequency.png new file mode 100644 index 00000000..e4b0a21a Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/CML_core_tb.sch new file mode 100644 index 00000000..f594c8b5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/CML_core_tb_0.data new file mode 100644 index 00000000..4cb5b399 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.110742996065e-01 + 1.728000000000e-10 -1.869505717284e-01 + 1.828000000000e-10 -3.563037101706e-02 + 1.928000000000e-10 1.056708524540e-01 + 2.028000000000e-10 2.100393804445e-01 + 2.128000000000e-10 2.784249297688e-01 + 2.228000000000e-10 3.224310579067e-01 + 2.328000000000e-10 3.548600651170e-01 + 2.428000000000e-10 3.792482005271e-01 + 2.528000000000e-10 3.740820324036e-01 + 2.628000000000e-10 3.079440308227e-01 + 2.728000000000e-10 1.813826171807e-01 + 2.828000000000e-10 2.923027813912e-02 + 2.928000000000e-10 -1.118282325615e-01 + 3.028000000000e-10 -2.157337068367e-01 + 3.128000000000e-10 -2.829033176767e-01 + 3.228000000000e-10 -3.260714502323e-01 + 3.328000000000e-10 -3.577361248183e-01 + 3.428000000000e-10 -3.819104006606e-01 + 3.528000000000e-10 -3.764730474160e-01 + 3.628000000000e-10 -3.102968359246e-01 + 3.728000000000e-10 -1.832608913655e-01 + 3.828000000000e-10 -3.084931437320e-02 + 3.928000000000e-10 1.106163095990e-01 + 4.028000000000e-10 2.145714971977e-01 + 4.128000000000e-10 2.819937231053e-01 + 4.228000000000e-10 3.251740998910e-01 + 4.328000000000e-10 3.570946969464e-01 + 4.428000000000e-10 3.813004444382e-01 + 4.528000000000e-10 3.761230596147e-01 + 4.628000000000e-10 3.099646053412e-01 + 4.728000000000e-10 1.831473345022e-01 + 4.828000000000e-10 3.069401022130e-02 + 4.928000000000e-10 -1.106258411343e-01 + 5.028000000000e-10 -2.146793601179e-01 + 5.128000000000e-10 -2.820035552799e-01 + 5.228000000000e-10 -3.252909243829e-01 + 5.328000000000e-10 -3.570986338553e-01 + 5.428000000000e-10 -3.813904658256e-01 + 5.528000000000e-10 -3.760889514061e-01 + 5.628000000000e-10 -3.100114096943e-01 + 5.728000000000e-10 -1.830827247194e-01 + 5.828000000000e-10 -3.072480545922e-02 + 5.928000000000e-10 1.106906463094e-01 + 6.028000000000e-10 2.146493837568e-01 + 6.128000000000e-10 2.820610673881e-01 + 6.228000000000e-10 3.252525482967e-01 + 6.328000000000e-10 3.571504708749e-01 + 6.428000000000e-10 3.813516648295e-01 + 6.528000000000e-10 3.761390656738e-01 + 6.628000000000e-10 3.099742259389e-01 + 6.728000000000e-10 1.831331110808e-01 + 6.828000000000e-10 3.068765829312e-02 + 6.928000000000e-10 -1.106445812930e-01 + 7.028000000000e-10 -2.146859050297e-01 + 7.128000000000e-10 -2.820172231683e-01 + 7.228000000000e-10 -3.252905125649e-01 + 7.328000000000e-10 -3.571078709926e-01 + 7.428000000000e-10 -3.813893177320e-01 + 7.528000000000e-10 -3.760986555866e-01 + 7.628000000000e-10 -3.100117776476e-01 + 7.728000000000e-10 -1.830935153198e-01 + 7.828000000000e-10 -3.072484475908e-02 + 7.928000000000e-10 1.106810594907e-01 + 8.028000000000e-10 2.146507312123e-01 + 8.128000000000e-10 2.820530370402e-01 + 8.228000000000e-10 3.252547871433e-01 + 8.328000000000e-10 3.571432636036e-01 + 8.428000000000e-10 3.813547544577e-01 + 8.528000000000e-10 3.761324372121e-01 + 8.628000000000e-10 3.099775475493e-01 + 8.728000000000e-10 1.831274535707e-01 + 8.828000000000e-10 3.069175078476e-02 + 8.928000000000e-10 -1.106491559136e-01 + 9.028000000000e-10 -2.146821655528e-01 + 9.128000000000e-10 -2.820218639330e-01 + 9.228000000000e-10 -3.252864642203e-01 + 9.328000000000e-10 -3.571122611941e-01 + 9.428000000000e-10 -3.813854215351e-01 + 9.528000000000e-10 -3.761024723822e-01 + 9.628000000000e-10 -3.100075395903e-01 + 9.728000000000e-10 -1.830975404653e-01 + 9.828000000000e-10 -3.072097080048e-02 + 9.928000000000e-10 1.106770531472e-01 + 1.000000000000e-09 1.895325033433e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/conditions.yaml new file mode 100644 index 00000000..de36aa6b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_00 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/CML_core_tb.sch new file mode 100644 index 00000000..55050413 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/CML_core_tb_1.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/CML_core_tb_1.data new file mode 100644 index 00000000..2b8492c0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/CML_core_tb_1.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.098686002716e-01 + 1.728000000000e-10 -1.894560696460e-01 + 1.828000000000e-10 -4.059695742871e-02 + 1.928000000000e-10 9.940964501315e-02 + 2.028000000000e-10 2.033133834097e-01 + 2.128000000000e-10 2.719620830710e-01 + 2.228000000000e-10 3.163098950569e-01 + 2.328000000000e-10 3.491513279687e-01 + 2.428000000000e-10 3.741332087119e-01 + 2.528000000000e-10 3.700254590965e-01 + 2.628000000000e-10 3.062168938694e-01 + 2.728000000000e-10 1.827341653261e-01 + 2.828000000000e-10 3.280764574542e-02 + 2.928000000000e-10 -1.069769977212e-01 + 3.028000000000e-10 -2.102924295592e-01 + 3.128000000000e-10 -2.774748738503e-01 + 3.228000000000e-10 -3.207751929169e-01 + 3.328000000000e-10 -3.527202709264e-01 + 3.428000000000e-10 -3.774342269369e-01 + 3.528000000000e-10 -3.730540733905e-01 + 3.628000000000e-10 -3.091949741363e-01 + 3.728000000000e-10 -1.851642002832e-01 + 3.828000000000e-10 -3.487935842603e-02 + 3.928000000000e-10 1.053970083053e-01 + 4.028000000000e-10 2.088131472734e-01 + 4.128000000000e-10 2.762908135843e-01 + 4.228000000000e-10 3.196385089100e-01 + 4.328000000000e-10 3.518763575372e-01 + 4.428000000000e-10 3.766558038448e-01 + 4.528000000000e-10 3.725714207051e-01 + 4.628000000000e-10 3.087619830708e-01 + 4.728000000000e-10 1.849833837695e-01 + 4.828000000000e-10 3.467977975354e-02 + 4.928000000000e-10 -1.054340839288e-01 + 5.028000000000e-10 -2.089448612506e-01 + 5.128000000000e-10 -2.763231704068e-01 + 5.228000000000e-10 -3.197791718821e-01 + 5.328000000000e-10 -3.518998659973e-01 + 5.428000000000e-10 -3.767613178326e-01 + 5.528000000000e-10 -3.725445308461e-01 + 5.628000000000e-10 -3.088109693961e-01 + 5.728000000000e-10 -1.849155432321e-01 + 5.828000000000e-10 -3.470667341543e-02 + 5.928000000000e-10 1.055048847061e-01 + 6.028000000000e-10 2.089187592091e-01 + 6.128000000000e-10 2.763849186823e-01 + 6.228000000000e-10 3.197425041182e-01 + 6.328000000000e-10 3.519544114659e-01 + 6.428000000000e-10 3.767237647599e-01 + 6.528000000000e-10 3.725977061828e-01 + 6.628000000000e-10 3.087755728399e-01 + 6.728000000000e-10 1.849692271918e-01 + 6.828000000000e-10 3.467099374312e-02 + 6.928000000000e-10 -1.054562384013e-01 + 7.028000000000e-10 -2.089544093361e-01 + 7.128000000000e-10 -2.763388509076e-01 + 7.228000000000e-10 -3.197800091948e-01 + 7.328000000000e-10 -3.519101110125e-01 + 7.428000000000e-10 -3.767612419697e-01 + 7.528000000000e-10 -3.725558598664e-01 + 7.628000000000e-10 -3.088133010441e-01 + 7.728000000000e-10 -1.849285593480e-01 + 7.828000000000e-10 -3.470862903587e-02 + 7.928000000000e-10 1.054936381918e-01 + 8.028000000000e-10 2.089186129636e-01 + 8.128000000000e-10 2.763755879874e-01 + 8.228000000000e-10 3.197437164625e-01 + 8.328000000000e-10 3.519463479929e-01 + 8.428000000000e-10 3.767260853907e-01 + 8.528000000000e-10 3.725904126785e-01 + 8.628000000000e-10 3.087783440951e-01 + 8.728000000000e-10 1.849632167070e-01 + 8.828000000000e-10 3.467482549783e-02 + 8.928000000000e-10 -1.054610682584e-01 + 9.028000000000e-10 -2.089507846182e-01 + 9.128000000000e-10 -2.763436586770e-01 + 9.228000000000e-10 -3.197760754687e-01 + 9.328000000000e-10 -3.519146615050e-01 + 9.428000000000e-10 -3.767573997120e-01 + 9.528000000000e-10 -3.725597535055e-01 + 9.628000000000e-10 -3.088090609970e-01 + 9.728000000000e-10 -1.849326628321e-01 + 9.828000000000e-10 -3.470475490247e-02 + 9.928000000000e-10 1.054896146910e-01 + 1.000000000000e-09 1.838520001242e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/conditions.yaml new file mode 100644 index 00000000..d1dfdfa9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 1 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_01 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/CML_core_tb.sch new file mode 100644 index 00000000..f6084e58 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/CML_core_tb_2.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/CML_core_tb_2.data new file mode 100644 index 00000000..b332ca2c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/CML_core_tb_2.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162797108708e-01 + 1.728000000000e-10 -1.875883768906e-01 + 1.828000000000e-10 -3.217177564589e-02 + 1.928000000000e-10 1.118453904517e-01 + 2.028000000000e-10 2.178869753922e-01 + 2.128000000000e-10 2.869187499571e-01 + 2.228000000000e-10 3.311831063176e-01 + 2.328000000000e-10 3.637965093552e-01 + 2.428000000000e-10 3.884475585753e-01 + 2.528000000000e-10 3.831703446637e-01 + 2.628000000000e-10 3.149426000366e-01 + 2.728000000000e-10 1.840825734866e-01 + 2.828000000000e-10 2.786370536806e-02 + 2.928000000000e-10 -1.159899232258e-01 + 3.028000000000e-10 -2.217323928122e-01 + 3.128000000000e-10 -2.897841810826e-01 + 3.228000000000e-10 -3.334256487170e-01 + 3.328000000000e-10 -3.654508602495e-01 + 3.428000000000e-10 -3.900407544937e-01 + 3.528000000000e-10 -3.846189534315e-01 + 3.628000000000e-10 -3.164922452622e-01 + 3.728000000000e-10 -1.853182634851e-01 + 3.828000000000e-10 -2.898615964086e-02 + 3.928000000000e-10 1.151710782521e-01 + 4.028000000000e-10 2.209054309263e-01 + 4.128000000000e-10 2.891817322742e-01 + 4.228000000000e-10 3.328077516782e-01 + 4.328000000000e-10 3.650515838921e-01 + 4.428000000000e-10 3.896233583948e-01 + 4.528000000000e-10 3.844074302627e-01 + 4.628000000000e-10 3.162448842688e-01 + 4.728000000000e-10 1.852475068120e-01 + 4.828000000000e-10 2.884623360652e-02 + 4.928000000000e-10 -1.151788252337e-01 + 5.028000000000e-10 -2.210147130581e-01 + 5.128000000000e-10 -2.891872658193e-01 + 5.228000000000e-10 -3.329167168088e-01 + 5.328000000000e-10 -3.650471930963e-01 + 5.428000000000e-10 -3.897100874545e-01 + 5.528000000000e-10 -3.843762306477e-01 + 5.628000000000e-10 -3.163013912188e-01 + 5.728000000000e-10 -1.851950213487e-01 + 5.828000000000e-10 -2.889036873678e-02 + 5.928000000000e-10 1.152312899162e-01 + 6.028000000000e-10 2.209735588305e-01 + 6.128000000000e-10 2.892357416511e-01 + 6.228000000000e-10 3.328707955285e-01 + 6.328000000000e-10 3.650931065031e-01 + 6.428000000000e-10 3.896657987149e-01 + 6.528000000000e-10 3.844215105032e-01 + 6.628000000000e-10 3.162596917265e-01 + 6.728000000000e-10 1.852417351036e-01 + 6.828000000000e-10 2.884992827621e-02 + 6.928000000000e-10 -1.151876679011e-01 + 7.028000000000e-10 -2.210123101756e-01 + 7.128000000000e-10 -2.891938845816e-01 + 7.228000000000e-10 -3.329106389600e-01 + 7.328000000000e-10 -3.650518039465e-01 + 7.428000000000e-10 -3.897047407363e-01 + 7.528000000000e-10 -3.843819858648e-01 + 7.628000000000e-10 -3.162978744015e-01 + 7.728000000000e-10 -1.852023753321e-01 + 7.828000000000e-10 -2.888743165850e-02 + 7.928000000000e-10 1.152240030808e-01 + 8.028000000000e-10 2.209771419031e-01 + 8.128000000000e-10 2.892295361788e-01 + 8.228000000000e-10 3.328747680971e-01 + 8.328000000000e-10 3.650871456099e-01 + 8.428000000000e-10 3.896701175780e-01 + 8.528000000000e-10 3.844156912621e-01 + 8.628000000000e-10 3.162637401476e-01 + 8.728000000000e-10 1.852363586492e-01 + 8.828000000000e-10 2.885434112124e-02 + 8.928000000000e-10 -1.151920978903e-01 + 9.028000000000e-10 -2.210084087345e-01 + 9.128000000000e-10 -2.891984388712e-01 + 9.228000000000e-10 -3.329064027155e-01 + 9.328000000000e-10 -3.650560988894e-01 + 9.428000000000e-10 -3.897007143418e-01 + 9.528000000000e-10 -3.843858173814e-01 + 9.628000000000e-10 -3.162935974835e-01 + 9.728000000000e-10 -1.852064424274e-01 + 9.828000000000e-10 -2.888350905479e-02 + 9.928000000000e-10 1.152199079204e-01 + 1.000000000000e-09 1.954791142410e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/conditions.yaml new file mode 100644 index 00000000..ba5c3aa0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 2 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_02 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/CML_core_tb.sch new file mode 100644 index 00000000..6ac65fea --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/CML_core_tb_3.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/CML_core_tb_3.data new file mode 100644 index 00000000..6dccbfd6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/CML_core_tb_3.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.914571027454e-01 + 1.728000000000e-10 -1.780117263272e-01 + 1.828000000000e-10 -3.802564096594e-02 + 1.928000000000e-10 9.479025580261e-02 + 2.028000000000e-10 1.961220444980e-01 + 2.128000000000e-10 2.643669322964e-01 + 2.228000000000e-10 3.071498875260e-01 + 2.328000000000e-10 3.351667250191e-01 + 2.428000000000e-10 3.529478733093e-01 + 2.528000000000e-10 3.439767079911e-01 + 2.628000000000e-10 2.827109934029e-01 + 2.728000000000e-10 1.683025534555e-01 + 2.828000000000e-10 2.843266655337e-02 + 2.928000000000e-10 -1.036223502576e-01 + 3.028000000000e-10 -2.042863713809e-01 + 3.128000000000e-10 -2.713818104821e-01 + 3.228000000000e-10 -3.132717880322e-01 + 3.328000000000e-10 -3.402903477971e-01 + 3.428000000000e-10 -3.574262556597e-01 + 3.528000000000e-10 -3.476240566503e-01 + 3.628000000000e-10 -2.857203755187e-01 + 3.728000000000e-10 -1.703849236420e-01 + 3.828000000000e-10 -2.994825869373e-02 + 3.928000000000e-10 1.026817167876e-01 + 4.028000000000e-10 2.034750084544e-01 + 4.128000000000e-10 2.707812081585e-01 + 4.228000000000e-10 3.126503625184e-01 + 4.328000000000e-10 3.399043734480e-01 + 4.428000000000e-10 3.571021595385e-01 + 4.528000000000e-10 3.475896983741e-01 + 4.628000000000e-10 2.857411927694e-01 + 4.728000000000e-10 1.706053611761e-01 + 4.828000000000e-10 3.010795594348e-02 + 4.928000000000e-10 -1.024135388755e-01 + 5.028000000000e-10 -2.033190471438e-01 + 5.128000000000e-10 -2.705615444577e-01 + 5.228000000000e-10 -3.125558523975e-01 + 5.328000000000e-10 -3.397330193449e-01 + 5.428000000000e-10 -3.570354300338e-01 + 5.528000000000e-10 -3.474353611027e-01 + 5.628000000000e-10 -2.856876769732e-01 + 5.728000000000e-10 -1.704760895977e-01 + 5.828000000000e-10 -3.008641427314e-02 + 5.928000000000e-10 1.025087996136e-01 + 6.028000000000e-10 2.033209986443e-01 + 6.128000000000e-10 2.706412375819e-01 + 6.228000000000e-10 3.125457575810e-01 + 6.328000000000e-10 3.398008382665e-01 + 6.428000000000e-10 3.570145583479e-01 + 6.528000000000e-10 3.474888598072e-01 + 6.628000000000e-10 2.856551852535e-01 + 6.728000000000e-10 1.705188293935e-01 + 6.828000000000e-10 3.004736925580e-02 + 6.928000000000e-10 -1.024728514478e-01 + 7.028000000000e-10 -2.033602328622e-01 + 7.128000000000e-10 -2.706061106716e-01 + 7.228000000000e-10 -3.125843283316e-01 + 7.328000000000e-10 -3.397655433228e-01 + 7.428000000000e-10 -3.570523646632e-01 + 7.528000000000e-10 -3.474554820929e-01 + 7.628000000000e-10 -2.856929985560e-01 + 7.728000000000e-10 -1.704859799650e-01 + 7.828000000000e-10 -3.008383757896e-02 + 7.928000000000e-10 1.025039608177e-01 + 8.028000000000e-10 2.033261442763e-01 + 8.128000000000e-10 2.706371082838e-01 + 8.228000000000e-10 3.125504649737e-01 + 8.328000000000e-10 3.397966066528e-01 + 8.428000000000e-10 3.570198965640e-01 + 8.528000000000e-10 3.474857187206e-01 + 8.628000000000e-10 2.856614378232e-01 + 8.728000000000e-10 1.705164607562e-01 + 8.828000000000e-10 3.005354621749e-02 + 8.928000000000e-10 -1.024749769036e-01 + 9.028000000000e-10 -2.033548454455e-01 + 9.128000000000e-10 -2.706087008930e-01 + 9.228000000000e-10 -3.125792630790e-01 + 9.328000000000e-10 -3.397683901773e-01 + 9.428000000000e-10 -3.570478314069e-01 + 9.528000000000e-10 -3.474583427153e-01 + 9.628000000000e-10 -2.856887110961e-01 + 9.728000000000e-10 -1.704892548593e-01 + 9.828000000000e-10 -3.008001356704e-02 + 9.928000000000e-10 1.025005080892e-01 + 1.000000000000e-09 1.786649040194e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/conditions.yaml new file mode 100644 index 00000000..e8f17db4 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 3 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_03 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/CML_core_tb.sch new file mode 100644 index 00000000..d049f138 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/CML_core_tb_4.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/CML_core_tb_4.data new file mode 100644 index 00000000..3efc8a54 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/CML_core_tb_4.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908886906683e-01 + 1.728000000000e-10 -1.805890382926e-01 + 1.828000000000e-10 -4.276329247682e-02 + 1.928000000000e-10 8.882407595099e-02 + 2.028000000000e-10 1.894983505466e-01 + 2.128000000000e-10 2.576242567207e-01 + 2.228000000000e-10 3.005212718886e-01 + 2.328000000000e-10 3.289546768723e-01 + 2.428000000000e-10 3.474240530436e-01 + 2.528000000000e-10 3.394794629215e-01 + 2.628000000000e-10 2.802266193594e-01 + 2.728000000000e-10 1.685520573893e-01 + 2.828000000000e-10 3.081792474830e-02 + 2.928000000000e-10 -9.985913249602e-02 + 3.028000000000e-10 -1.996535082954e-01 + 3.128000000000e-10 -2.663519845580e-01 + 3.228000000000e-10 -3.081166100610e-01 + 3.328000000000e-10 -3.353557582557e-01 + 3.428000000000e-10 -3.530339682910e-01 + 3.528000000000e-10 -3.441234226063e-01 + 3.628000000000e-10 -2.840838930007e-01 + 3.728000000000e-10 -1.712890179908e-01 + 3.828000000000e-10 -3.280692441870e-02 + 3.928000000000e-10 9.858702888345e-02 + 4.028000000000e-10 1.985844458095e-01 + 4.128000000000e-10 2.655374220709e-01 + 4.228000000000e-10 3.073092043222e-01 + 4.328000000000e-10 3.348254361967e-01 + 4.428000000000e-10 3.526065806553e-01 + 4.528000000000e-10 3.440384505411e-01 + 4.628000000000e-10 2.840943593119e-01 + 4.728000000000e-10 1.715352376725e-01 + 4.828000000000e-10 3.300625747524e-02 + 4.928000000000e-10 -9.826793525126e-02 + 5.028000000000e-10 -1.983826392696e-01 + 5.128000000000e-10 -2.652748957302e-01 + 5.228000000000e-10 -3.071819372703e-01 + 5.328000000000e-10 -3.346211766496e-01 + 5.428000000000e-10 -3.525115401756e-01 + 5.528000000000e-10 -3.438520776438e-01 + 5.628000000000e-10 -2.840132934403e-01 + 5.728000000000e-10 -1.713783534881e-01 + 5.828000000000e-10 -3.296528839742e-02 + 5.928000000000e-10 9.838210726041e-02 + 6.028000000000e-10 1.983970962128e-01 + 6.128000000000e-10 2.653685996210e-01 + 6.228000000000e-10 3.071805271474e-01 + 6.328000000000e-10 3.346994451143e-01 + 6.428000000000e-10 3.524959527178e-01 + 6.528000000000e-10 3.439124816552e-01 + 6.628000000000e-10 2.839825148385e-01 + 6.728000000000e-10 1.714247364616e-01 + 6.828000000000e-10 3.292536702304e-02 + 6.928000000000e-10 -9.834444145178e-02 + 7.028000000000e-10 -1.984381153623e-01 + 7.128000000000e-10 -2.653318964793e-01 + 7.228000000000e-10 -3.072207693265e-01 + 7.328000000000e-10 -3.346627011511e-01 + 7.428000000000e-10 -3.525355719541e-01 + 7.528000000000e-10 -3.438780517049e-01 + 7.628000000000e-10 -2.840226095914e-01 + 7.728000000000e-10 -1.713910964736e-01 + 7.828000000000e-10 -3.296406429130e-02 + 7.928000000000e-10 9.837645950128e-02 + 8.028000000000e-10 1.984019833998e-01 + 8.128000000000e-10 2.653640104122e-01 + 8.228000000000e-10 3.071850636337e-01 + 8.328000000000e-10 3.346949515146e-01 + 8.428000000000e-10 3.525014052751e-01 + 8.528000000000e-10 3.439095067618e-01 + 8.628000000000e-10 2.839893402731e-01 + 8.728000000000e-10 1.714228569780e-01 + 8.828000000000e-10 3.293222880403e-02 + 8.928000000000e-10 -9.834616516704e-02 + 9.028000000000e-10 -1.984321208293e-01 + 9.128000000000e-10 -2.653341991167e-01 + 9.228000000000e-10 -3.072152380466e-01 + 9.328000000000e-10 -3.346653803170e-01 + 9.428000000000e-10 -3.525306496503e-01 + 9.528000000000e-10 -3.438807929682e-01 + 9.628000000000e-10 -2.840179937834e-01 + 9.728000000000e-10 -1.713943425416e-01 + 9.828000000000e-10 -3.296001530074e-02 + 9.928000000000e-10 9.837298926970e-02 + 1.000000000000e-09 1.738955459088e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/conditions.yaml new file mode 100644 index 00000000..5df8815a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 4 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_04 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/CML_core_tb.sch new file mode 100644 index 00000000..ac517bac --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/CML_core_tb_5.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/CML_core_tb_5.data new file mode 100644 index 00000000..0cc77d23 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/CML_core_tb_5.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.958574299710e-01 + 1.728000000000e-10 -1.791897212785e-01 + 1.828000000000e-10 -3.599075048614e-02 + 1.928000000000e-10 9.946703268478e-02 + 2.028000000000e-10 2.032502871016e-01 + 2.128000000000e-10 2.733994094958e-01 + 2.228000000000e-10 3.172845988123e-01 + 2.328000000000e-10 3.455609123691e-01 + 2.428000000000e-10 3.630923957132e-01 + 2.528000000000e-10 3.534419450967e-01 + 2.628000000000e-10 2.903663934708e-01 + 2.728000000000e-10 1.726743312860e-01 + 2.828000000000e-10 2.930291139472e-02 + 2.928000000000e-10 -1.057514312075e-01 + 3.028000000000e-10 -2.091913834589e-01 + 3.128000000000e-10 -2.784696434768e-01 + 3.228000000000e-10 -3.216873931074e-01 + 3.328000000000e-10 -3.491870426412e-01 + 3.428000000000e-10 -3.662894191498e-01 + 3.528000000000e-10 -3.560374131806e-01 + 3.628000000000e-10 -2.925719059469e-01 + 3.728000000000e-10 -1.742159787839e-01 + 3.828000000000e-10 -3.049391935212e-02 + 3.928000000000e-10 1.049756016137e-01 + 4.028000000000e-10 2.084672065617e-01 + 4.128000000000e-10 2.779301238417e-01 + 4.228000000000e-10 3.211180618030e-01 + 4.328000000000e-10 3.488255023686e-01 + 4.428000000000e-10 3.659572542624e-01 + 4.528000000000e-10 3.559493947967e-01 + 4.628000000000e-10 2.925058094407e-01 + 4.728000000000e-10 1.743267017008e-01 + 4.828000000000e-10 3.054314172764e-02 + 4.928000000000e-10 -1.048175245910e-01 + 5.028000000000e-10 -2.084096499031e-01 + 5.128000000000e-10 -2.777998408986e-01 + 5.228000000000e-10 -3.210985617265e-01 + 5.328000000000e-10 -3.487226120056e-01 + 5.428000000000e-10 -3.659481451181e-01 + 5.528000000000e-10 -3.558482598240e-01 + 5.628000000000e-10 -2.924942070749e-01 + 5.728000000000e-10 -1.742324941843e-01 + 5.828000000000e-10 -3.054486718364e-02 + 5.928000000000e-10 1.048934295445e-01 + 6.028000000000e-10 2.083991544976e-01 + 6.128000000000e-10 2.778660140822e-01 + 6.228000000000e-10 3.210794561497e-01 + 6.328000000000e-10 3.487805773205e-01 + 6.428000000000e-10 3.659226785140e-01 + 6.528000000000e-10 3.558970058340e-01 + 6.628000000000e-10 2.924624137185e-01 + 6.728000000000e-10 1.742748110039e-01 + 6.828000000000e-10 3.050920657876e-02 + 6.928000000000e-10 -1.048562048812e-01 + 7.028000000000e-10 -2.084343791218e-01 + 7.128000000000e-10 -2.778299623633e-01 + 7.228000000000e-10 -3.211147582115e-01 + 7.328000000000e-10 -3.487447461690e-01 + 7.428000000000e-10 -3.659575085549e-01 + 7.528000000000e-10 -3.558632428052e-01 + 7.628000000000e-10 -2.924972481137e-01 + 7.728000000000e-10 -1.742418088753e-01 + 7.828000000000e-10 -3.054328720193e-02 + 7.928000000000e-10 1.048870377838e-01 + 8.028000000000e-10 2.084024115537e-01 + 8.128000000000e-10 2.778603942564e-01 + 8.228000000000e-10 3.210827582845e-01 + 8.328000000000e-10 3.487751488045e-01 + 8.428000000000e-10 3.659266824704e-01 + 8.528000000000e-10 3.558925702991e-01 + 8.628000000000e-10 2.924671830422e-01 + 8.728000000000e-10 1.742711856894e-01 + 8.828000000000e-10 3.051417003050e-02 + 8.928000000000e-10 -1.048591994973e-01 + 9.028000000000e-10 -2.084299430076e-01 + 9.128000000000e-10 -2.778331783696e-01 + 9.228000000000e-10 -3.211104359655e-01 + 9.328000000000e-10 -3.487480244246e-01 + 9.428000000000e-10 -3.659535267111e-01 + 9.528000000000e-10 -3.558663548813e-01 + 9.628000000000e-10 -2.924933270906e-01 + 9.728000000000e-10 -1.742451324195e-01 + 9.828000000000e-10 -3.053963678018e-02 + 9.928000000000e-10 1.048836196344e-01 + 1.000000000000e-09 1.830293824662e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/conditions.yaml new file mode 100644 index 00000000..e65c52d5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 5 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_05 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/CML_core_tb.sch new file mode 100644 index 00000000..27fcf26c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/CML_core_tb_6.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/CML_core_tb_6.data new file mode 100644 index 00000000..38ffd8bf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/CML_core_tb_6.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.689355033953e-01 + 1.728000000000e-10 -1.691728954892e-01 + 1.828000000000e-10 -4.423302134033e-02 + 1.928000000000e-10 7.663444207075e-02 + 2.028000000000e-10 1.714764750752e-01 + 2.128000000000e-10 2.368219567798e-01 + 2.228000000000e-10 2.772768132445e-01 + 2.328000000000e-10 3.013675537348e-01 + 2.428000000000e-10 3.140706479520e-01 + 2.528000000000e-10 3.038549886105e-01 + 2.628000000000e-10 2.508404086347e-01 + 2.728000000000e-10 1.528360605683e-01 + 2.828000000000e-10 3.040034809293e-02 + 2.928000000000e-10 -8.785381094258e-02 + 3.028000000000e-10 -1.808734961109e-01 + 3.128000000000e-10 -2.445795528199e-01 + 3.228000000000e-10 -2.838354337528e-01 + 3.328000000000e-10 -3.065800962400e-01 + 3.428000000000e-10 -3.181767360109e-01 + 3.528000000000e-10 -3.065752663659e-01 + 3.628000000000e-10 -2.523878800401e-01 + 3.728000000000e-10 -1.531173668737e-01 + 3.828000000000e-10 -2.992055538556e-02 + 3.928000000000e-10 8.900435641641e-02 + 4.028000000000e-10 1.821756238512e-01 + 4.128000000000e-10 2.460123650690e-01 + 4.228000000000e-10 2.851182310100e-01 + 4.328000000000e-10 3.079291995556e-01 + 4.428000000000e-10 3.194129911462e-01 + 4.528000000000e-10 3.078915366323e-01 + 4.628000000000e-10 2.535144344421e-01 + 4.728000000000e-10 1.541542026196e-01 + 4.828000000000e-10 3.063651583090e-02 + 4.928000000000e-10 -8.839161491074e-02 + 5.028000000000e-10 -1.817999659778e-01 + 5.128000000000e-10 -2.456456661989e-01 + 5.228000000000e-10 -2.849195350591e-01 + 5.328000000000e-10 -3.077091828990e-01 + 5.428000000000e-10 -3.193505374448e-01 + 5.528000000000e-10 -3.078081521678e-01 + 5.628000000000e-10 -2.535787813503e-01 + 5.728000000000e-10 -1.541764927596e-01 + 5.828000000000e-10 -3.077048554081e-02 + 5.928000000000e-10 8.832790620553e-02 + 6.028000000000e-10 1.816551916875e-01 + 6.128000000000e-10 2.455879975104e-01 + 6.228000000000e-10 2.847911932982e-01 + 6.328000000000e-10 3.076677363016e-01 + 6.428000000000e-10 3.192371229053e-01 + 6.528000000000e-10 3.077778412262e-01 + 6.628000000000e-10 2.534819327505e-01 + 6.728000000000e-10 1.541683138663e-01 + 6.828000000000e-10 3.070155435378e-02 + 6.928000000000e-10 -8.831320560130e-02 + 7.028000000000e-10 -1.817038543937e-01 + 7.128000000000e-10 -2.455619958387e-01 + 7.228000000000e-10 -2.848320347671e-01 + 7.328000000000e-10 -3.076358698550e-01 + 7.428000000000e-10 -3.192710667609e-01 + 7.528000000000e-10 -3.077409972388e-01 + 7.628000000000e-10 -2.535098012890e-01 + 7.728000000000e-10 -1.541282589474e-01 + 7.828000000000e-10 -3.072672689244e-02 + 7.928000000000e-10 8.835148526653e-02 + 8.028000000000e-10 1.816795669555e-01 + 8.128000000000e-10 2.455984246601e-01 + 8.228000000000e-10 2.848062931006e-01 + 8.328000000000e-10 3.076705916890e-01 + 8.428000000000e-10 3.192450073559e-01 + 8.528000000000e-10 3.077736319697e-01 + 8.628000000000e-10 2.534831121829e-01 + 8.728000000000e-10 1.541590953584e-01 + 8.828000000000e-10 3.069946612700e-02 + 8.928000000000e-10 -8.832341199891e-02 + 9.028000000000e-10 -1.817063952021e-01 + 9.128000000000e-10 -2.455714256322e-01 + 9.228000000000e-10 -2.848333922463e-01 + 9.328000000000e-10 -3.076440936715e-01 + 9.428000000000e-10 -3.192716274515e-01 + 9.528000000000e-10 -3.077481608676e-01 + 9.628000000000e-10 -2.535093614867e-01 + 9.728000000000e-10 -1.541340765567e-01 + 9.828000000000e-10 -3.072486745089e-02 + 9.928000000000e-10 8.834711873249e-02 + 1.000000000000e-09 1.586239577417e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/conditions.yaml new file mode 100644 index 00000000..5afc1722 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 6 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_06 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/CML_core_tb.sch new file mode 100644 index 00000000..519d1c35 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/CML_core_tb_7.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/CML_core_tb_7.data new file mode 100644 index 00000000..1cfe87b5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/CML_core_tb_7.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.694477874818e-01 + 1.728000000000e-10 -1.721829739194e-01 + 1.828000000000e-10 -4.906833766415e-02 + 1.928000000000e-10 7.069743134728e-02 + 2.028000000000e-10 1.648418946330e-01 + 2.128000000000e-10 2.298765389610e-01 + 2.228000000000e-10 2.702802052070e-01 + 2.328000000000e-10 2.947129455777e-01 + 2.428000000000e-10 3.081296602318e-01 + 2.528000000000e-10 2.990063012040e-01 + 2.628000000000e-10 2.478884705263e-01 + 2.728000000000e-10 1.524230846398e-01 + 2.828000000000e-10 3.216725009037e-02 + 2.928000000000e-10 -8.452884553171e-02 + 3.028000000000e-10 -1.764495371150e-01 + 3.128000000000e-10 -2.394951663999e-01 + 3.228000000000e-10 -2.784178156025e-01 + 3.328000000000e-10 -3.012580547427e-01 + 3.428000000000e-10 -3.133510931360e-01 + 3.528000000000e-10 -3.026055002423e-01 + 3.628000000000e-10 -2.500554574282e-01 + 3.728000000000e-10 -1.530444893437e-01 + 3.828000000000e-10 -3.179895766292e-02 + 3.928000000000e-10 8.573594509971e-02 + 4.028000000000e-10 1.778922744476e-01 + 4.128000000000e-10 2.411102030583e-01 + 4.228000000000e-10 2.798967112063e-01 + 4.328000000000e-10 3.028156837380e-01 + 4.428000000000e-10 3.148075876296e-01 + 4.528000000000e-10 3.041758344829e-01 + 4.628000000000e-10 2.514478797306e-01 + 4.728000000000e-10 1.543354303295e-01 + 4.828000000000e-10 3.272908827542e-02 + 4.928000000000e-10 -8.494488064942e-02 + 5.028000000000e-10 -1.773750790235e-01 + 5.128000000000e-10 -2.406241070550e-01 + 5.228000000000e-10 -2.796032327906e-01 + 5.328000000000e-10 -3.025154625175e-01 + 5.428000000000e-10 -3.146850050735e-01 + 5.528000000000e-10 -3.040456856306e-01 + 5.628000000000e-10 -2.514865398019e-01 + 5.728000000000e-10 -1.543455010081e-01 + 5.828000000000e-10 -3.286780649422e-02 + 5.928000000000e-10 8.487071769529e-02 + 6.028000000000e-10 1.772120847555e-01 + 6.128000000000e-10 2.405506532865e-01 + 6.228000000000e-10 2.794557736074e-01 + 6.328000000000e-10 3.024581955274e-01 + 6.428000000000e-10 3.145521515255e-01 + 6.528000000000e-10 3.039990633934e-01 + 6.628000000000e-10 2.513709142203e-01 + 6.728000000000e-10 1.543241408079e-01 + 6.828000000000e-10 3.278555364704e-02 + 6.928000000000e-10 -8.486327141666e-02 + 7.028000000000e-10 -1.772689800248e-01 + 7.128000000000e-10 -2.405282060865e-01 + 7.228000000000e-10 -2.795021370136e-01 + 7.328000000000e-10 -3.024278022377e-01 + 7.428000000000e-10 -3.145896170200e-01 + 7.528000000000e-10 -3.039617953787e-01 + 7.628000000000e-10 -2.514004690324e-01 + 7.728000000000e-10 -1.542820043229e-01 + 7.828000000000e-10 -3.281110337775e-02 + 7.928000000000e-10 8.490436306023e-02 + 8.028000000000e-10 1.772446330839e-01 + 8.128000000000e-10 2.405674335146e-01 + 8.228000000000e-10 2.794761963085e-01 + 8.328000000000e-10 3.024650976088e-01 + 8.428000000000e-10 3.145632644585e-01 + 8.528000000000e-10 3.039968961590e-01 + 8.628000000000e-10 2.513733111446e-01 + 8.728000000000e-10 1.543150179356e-01 + 8.828000000000e-10 3.278304586331e-02 + 8.928000000000e-10 -8.487456857602e-02 + 9.028000000000e-10 -1.772725618584e-01 + 9.128000000000e-10 -2.405389250041e-01 + 9.228000000000e-10 -2.795045102279e-01 + 9.328000000000e-10 -3.024372521320e-01 + 9.428000000000e-10 -3.145911572553e-01 + 9.528000000000e-10 -3.039701598993e-01 + 9.628000000000e-10 -2.514009218164e-01 + 9.728000000000e-10 -1.542887967264e-01 + 9.828000000000e-10 -3.280979517783e-02 + 9.928000000000e-10 8.489941508642e-02 + 1.000000000000e-09 1.544118489485e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/conditions.yaml new file mode 100644 index 00000000..7e83d801 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 7 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_07 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/CML_core_tb.sch new file mode 100644 index 00000000..8cd2f767 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/CML_core_tb_8.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/CML_core_tb_8.data new file mode 100644 index 00000000..b4ed17dd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/CML_core_tb_8.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.722799425151e-01 + 1.728000000000e-10 -1.701277707773e-01 + 1.828000000000e-10 -4.252496989706e-02 + 1.928000000000e-10 8.092536896213e-02 + 2.028000000000e-10 1.785199933375e-01 + 2.128000000000e-10 2.463984181452e-01 + 2.228000000000e-10 2.885755113271e-01 + 2.328000000000e-10 3.131967480955e-01 + 2.428000000000e-10 3.255285716483e-01 + 2.528000000000e-10 3.143820454109e-01 + 2.628000000000e-10 2.595824958850e-01 + 2.728000000000e-10 1.585585813323e-01 + 2.828000000000e-10 3.254606172598e-02 + 2.928000000000e-10 -8.921916265210e-02 + 3.028000000000e-10 -1.857143058967e-01 + 3.128000000000e-10 -2.524588707093e-01 + 3.228000000000e-10 -2.937876617757e-01 + 3.328000000000e-10 -3.173655773168e-01 + 3.428000000000e-10 -3.288566343508e-01 + 3.528000000000e-10 -3.166123605828e-01 + 3.628000000000e-10 -2.609360611345e-01 + 3.728000000000e-10 -1.589355414621e-01 + 3.828000000000e-10 -3.237621747627e-02 + 3.928000000000e-10 8.990939637816e-02 + 4.028000000000e-10 1.864994737191e-01 + 4.128000000000e-10 2.533636311879e-01 + 4.228000000000e-10 2.945633129641e-01 + 4.328000000000e-10 3.182197832362e-01 + 4.428000000000e-10 3.296245618008e-01 + 4.528000000000e-10 3.174841059207e-01 + 4.628000000000e-10 2.616780558587e-01 + 4.728000000000e-10 1.596622360522e-01 + 4.828000000000e-10 3.287681921596e-02 + 4.928000000000e-10 -8.943999963453e-02 + 5.028000000000e-10 -1.862066308093e-01 + 5.128000000000e-10 -2.530527908612e-01 + 5.228000000000e-10 -2.943931136832e-01 + 5.328000000000e-10 -3.180152021024e-01 + 5.428000000000e-10 -3.295545667130e-01 + 5.528000000000e-10 -3.173812952412e-01 + 5.628000000000e-10 -2.617027726155e-01 + 5.728000000000e-10 -1.596411992093e-01 + 5.828000000000e-10 -3.295895028258e-02 + 5.928000000000e-10 8.942267434718e-02 + 6.028000000000e-10 1.861105403656e-01 + 6.128000000000e-10 2.530344325895e-01 + 6.228000000000e-10 2.943051008579e-01 + 6.328000000000e-10 3.180051485103e-01 + 6.428000000000e-10 3.294737915539e-01 + 6.528000000000e-10 3.173744791022e-01 + 6.628000000000e-10 2.616291881364e-01 + 6.728000000000e-10 1.596450333001e-01 + 6.828000000000e-10 3.290088244348e-02 + 6.928000000000e-10 -8.940659470005e-02 + 7.028000000000e-10 -1.861562133447e-01 + 7.128000000000e-10 -2.530116656482e-01 + 7.228000000000e-10 -2.943454309811e-01 + 7.328000000000e-10 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9.828000000000e-10 -3.292583900074e-02 + 9.928000000000e-10 8.943518431692e-02 + 1.000000000000e-09 1.621529465729e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/conditions.yaml new file mode 100644 index 00000000..894a7d5c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 8 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_08 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/CML_core_tb.sch new file mode 100644 index 00000000..f4080d0b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/CML_core_tb_9.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/CML_core_tb_9.data new file mode 100644 index 00000000..6b24d1d6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/CML_core_tb_9.data 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4.028000000000e-10 2.425057762271e-01 + 4.128000000000e-10 2.772590268750e-01 + 4.228000000000e-10 3.167075169816e-01 + 4.328000000000e-10 3.660182242119e-01 + 4.428000000000e-10 4.074726111052e-01 + 4.528000000000e-10 4.212975956202e-01 + 4.628000000000e-10 3.549573822535e-01 + 4.728000000000e-10 1.947835560361e-01 + 4.828000000000e-10 6.801482567115e-03 + 4.928000000000e-10 -1.495086456760e-01 + 5.028000000000e-10 -2.424863730465e-01 + 5.128000000000e-10 -2.771744431737e-01 + 5.228000000000e-10 -3.166940000076e-01 + 5.328000000000e-10 -3.659398771497e-01 + 5.428000000000e-10 -4.074689465730e-01 + 5.528000000000e-10 -4.212394549000e-01 + 5.628000000000e-10 -3.549741510035e-01 + 5.728000000000e-10 -1.947436351784e-01 + 5.828000000000e-10 -6.830080160870e-03 + 5.928000000000e-10 1.495407150967e-01 + 6.028000000000e-10 2.424570295697e-01 + 6.128000000000e-10 2.772066160972e-01 + 6.228000000000e-10 3.166654934082e-01 + 6.328000000000e-10 3.659723864247e-01 + 6.428000000000e-10 4.074416211051e-01 + 6.528000000000e-10 4.212697301261e-01 + 6.628000000000e-10 3.549467093259e-01 + 6.728000000000e-10 1.947718238583e-01 + 6.828000000000e-10 6.800951177238e-03 + 6.928000000000e-10 -1.495148390529e-01 + 7.028000000000e-10 -2.424852043575e-01 + 7.128000000000e-10 -2.771809105751e-01 + 7.228000000000e-10 -3.166930947909e-01 + 7.328000000000e-10 -3.659459016360e-01 + 7.428000000000e-10 -4.074677461547e-01 + 7.528000000000e-10 -4.212442717757e-01 + 7.628000000000e-10 -3.549717520551e-01 + 7.728000000000e-10 -1.947463263521e-01 + 7.828000000000e-10 -6.825916545420e-03 + 7.928000000000e-10 1.495385751436e-01 + 8.028000000000e-10 2.424609931904e-01 + 8.128000000000e-10 2.772040406871e-01 + 8.228000000000e-10 3.166687905139e-01 + 8.328000000000e-10 3.659694951712e-01 + 8.428000000000e-10 4.074447010218e-01 + 8.528000000000e-10 4.212671408417e-01 + 8.628000000000e-10 3.549498827484e-01 + 8.728000000000e-10 1.947689363825e-01 + 8.828000000000e-10 6.803756635994e-03 + 8.928000000000e-10 -1.495176738691e-01 + 9.028000000000e-10 -2.424825342063e-01 + 9.128000000000e-10 -2.771836734306e-01 + 9.228000000000e-10 -3.166902103892e-01 + 9.328000000000e-10 -3.659485359213e-01 + 9.428000000000e-10 -4.074650210911e-01 + 9.528000000000e-10 -4.212469657833e-01 + 9.628000000000e-10 -3.549694058275e-01 + 9.728000000000e-10 -1.947487958951e-01 + 9.828000000000e-10 -6.823236278537e-03 + 9.928000000000e-10 1.495363177485e-01 + 1.000000000000e-09 2.250264100511e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/conditions.yaml new file mode 100644 index 00000000..d6f97f74 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 9 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_09 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/CML_core_tb.sch new file mode 100644 index 00000000..520e88c8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/CML_core_tb_10.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/CML_core_tb_10.data new file mode 100644 index 00000000..f64d27bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/CML_core_tb_10.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.621881537650e-01 + 1.728000000000e-10 -1.984429143572e-01 + 1.828000000000e-10 -1.024381876325e-02 + 1.928000000000e-10 1.456486678579e-01 + 2.028000000000e-10 2.379497773075e-01 + 2.128000000000e-10 2.714724605336e-01 + 2.228000000000e-10 3.108042897090e-01 + 2.328000000000e-10 3.600441003378e-01 + 2.428000000000e-10 4.020596908788e-01 + 2.528000000000e-10 4.176332246346e-01 + 2.628000000000e-10 3.534480183483e-01 + 2.728000000000e-10 1.957884716864e-01 + 2.828000000000e-10 1.048070619246e-02 + 2.928000000000e-10 -1.446967472000e-01 + 3.028000000000e-10 -2.375576326508e-01 + 3.128000000000e-10 -2.717915022579e-01 + 3.228000000000e-10 -3.116603869888e-01 + 3.328000000000e-10 -3.608573425706e-01 + 3.428000000000e-10 -4.027490548925e-01 + 3.528000000000e-10 -4.178578104758e-01 + 3.628000000000e-10 -3.532507313188e-01 + 3.728000000000e-10 -1.951536666098e-01 + 3.828000000000e-10 -9.813336101525e-03 + 3.928000000000e-10 1.453604720604e-01 + 4.028000000000e-10 2.379857130154e-01 + 4.128000000000e-10 2.721818635676e-01 + 4.228000000000e-10 3.119088225778e-01 + 4.328000000000e-10 3.611475798924e-01 + 4.428000000000e-10 4.029304727738e-01 + 4.528000000000e-10 4.180700216423e-01 + 4.628000000000e-10 3.533627988360e-01 + 4.728000000000e-10 1.953149158213e-01 + 4.828000000000e-10 9.881134950277e-03 + 4.928000000000e-10 -1.452466419838e-01 + 5.028000000000e-10 -2.379576224969e-01 + 5.128000000000e-10 -2.720935242692e-01 + 5.228000000000e-10 -3.118909714313e-01 + 5.328000000000e-10 -3.610674239906e-01 + 5.428000000000e-10 -4.029229661263e-01 + 5.528000000000e-10 -4.180098057029e-01 + 5.628000000000e-10 -3.533753449283e-01 + 5.728000000000e-10 -1.952727841385e-01 + 5.828000000000e-10 -9.906008920915e-03 + 5.928000000000e-10 1.452800172029e-01 + 6.028000000000e-10 2.379306740359e-01 + 6.128000000000e-10 2.721261300904e-01 + 6.228000000000e-10 3.118646486801e-01 + 6.328000000000e-10 3.611003417151e-01 + 6.428000000000e-10 4.028972890619e-01 + 6.528000000000e-10 4.180401129989e-01 + 6.628000000000e-10 3.533488930459e-01 + 6.728000000000e-10 1.953007885397e-01 + 6.828000000000e-10 9.878072761317e-03 + 6.928000000000e-10 -1.452545395230e-01 + 7.028000000000e-10 -2.379578117562e-01 + 7.128000000000e-10 -2.721008877684e-01 + 7.228000000000e-10 -3.118914026492e-01 + 7.328000000000e-10 -3.610744602697e-01 + 7.428000000000e-10 -4.029226014194e-01 + 7.528000000000e-10 -4.180151483436e-01 + 7.628000000000e-10 -3.533732531474e-01 + 7.728000000000e-10 -1.952759500525e-01 + 7.828000000000e-10 -9.902411226855e-03 + 7.928000000000e-10 1.452776462046e-01 + 8.028000000000e-10 2.379341379884e-01 + 8.128000000000e-10 2.721234101956e-01 + 8.228000000000e-10 3.118677116052e-01 + 8.328000000000e-10 3.610975209728e-01 + 8.428000000000e-10 4.029000595077e-01 + 8.528000000000e-10 4.180375331400e-01 + 8.628000000000e-10 3.533517750284e-01 + 8.728000000000e-10 1.952981248182e-01 + 8.828000000000e-10 9.880873061622e-03 + 8.928000000000e-10 -1.452571579233e-01 + 9.028000000000e-10 -2.379551078725e-01 + 9.128000000000e-10 -2.721034614056e-01 + 9.228000000000e-10 -3.118886463518e-01 + 9.328000000000e-10 -3.610770519544e-01 + 9.428000000000e-10 -4.029199107687e-01 + 9.528000000000e-10 -4.180177452829e-01 + 9.628000000000e-10 -3.533708821878e-01 + 9.728000000000e-10 -1.952784134813e-01 + 9.828000000000e-10 -9.899898542678e-03 + 9.928000000000e-10 1.452754037376e-01 + 1.000000000000e-09 2.207322871295e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/conditions.yaml new file mode 100644 index 00000000..c386d0fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 10 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_10 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/CML_core_tb.sch new file mode 100644 index 00000000..43cda8c8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/CML_core_tb_11.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/CML_core_tb_11.data new file mode 100644 index 00000000..1453012b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/CML_core_tb_11.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.668500025046e-01 + 1.728000000000e-10 -1.978704758130e-01 + 1.828000000000e-10 -3.069550951996e-03 + 1.928000000000e-10 1.561389387989e-01 + 2.028000000000e-10 2.488697408913e-01 + 2.128000000000e-10 2.833379270136e-01 + 2.228000000000e-10 3.221467647695e-01 + 2.328000000000e-10 3.723176028273e-01 + 2.428000000000e-10 4.147931582649e-01 + 2.528000000000e-10 4.286646301121e-01 + 2.628000000000e-10 3.614677855799e-01 + 2.728000000000e-10 1.982726052647e-01 + 2.828000000000e-10 5.580533140739e-03 + 2.928000000000e-10 -1.536551403474e-01 + 3.028000000000e-10 -2.474729097395e-01 + 3.128000000000e-10 -2.827981749211e-01 + 3.228000000000e-10 -3.222400643179e-01 + 3.328000000000e-10 -3.724510578191e-01 + 3.428000000000e-10 -4.149487937489e-01 + 3.528000000000e-10 -4.285094572794e-01 + 3.628000000000e-10 -3.610716711123e-01 + 3.728000000000e-10 -1.975613483211e-01 + 3.828000000000e-10 -4.936396792217e-03 + 3.928000000000e-10 1.542720670721e-01 + 4.028000000000e-10 2.478554934965e-01 + 4.128000000000e-10 2.831768205427e-01 + 4.228000000000e-10 3.224764565266e-01 + 4.328000000000e-10 3.727376628527e-01 + 4.428000000000e-10 4.151128450004e-01 + 4.528000000000e-10 4.287030398326e-01 + 4.628000000000e-10 3.611465460996e-01 + 4.728000000000e-10 1.976871290976e-01 + 4.828000000000e-10 4.962067120498e-03 + 4.928000000000e-10 -1.541857483448e-01 + 5.028000000000e-10 -2.478549856990e-01 + 5.128000000000e-10 -2.831031432303e-01 + 5.228000000000e-10 -3.224786212940e-01 + 5.328000000000e-10 -3.726675199031e-01 + 5.428000000000e-10 -4.151222726988e-01 + 5.528000000000e-10 -4.286496175832e-01 + 5.628000000000e-10 -3.611719348809e-01 + 5.728000000000e-10 -1.976471175954e-01 + 5.828000000000e-10 -4.995016715658e-03 + 5.928000000000e-10 1.542195273485e-01 + 6.028000000000e-10 2.478226151197e-01 + 6.128000000000e-10 2.831371441394e-01 + 6.228000000000e-10 3.224465270882e-01 + 6.328000000000e-10 3.727020829784e-01 + 6.428000000000e-10 4.150919188021e-01 + 6.528000000000e-10 4.286821395136e-01 + 6.628000000000e-10 3.611419365066e-01 + 6.728000000000e-10 1.976777927703e-01 + 6.828000000000e-10 4.963507878799e-03 + 6.928000000000e-10 -1.541913949207e-01 + 7.028000000000e-10 -2.478529800499e-01 + 7.128000000000e-10 -2.831092109235e-01 + 7.228000000000e-10 -3.224762894768e-01 + 7.328000000000e-10 -3.726728668334e-01 + 7.428000000000e-10 -4.151201370880e-01 + 7.528000000000e-10 -4.286543531433e-01 + 7.628000000000e-10 -3.611692599178e-01 + 7.728000000000e-10 -1.976499135935e-01 + 7.828000000000e-10 -4.990471824028e-03 + 7.928000000000e-10 1.542171227717e-01 + 8.028000000000e-10 2.478269854332e-01 + 8.128000000000e-10 2.831343470853e-01 + 8.228000000000e-10 3.224500362551e-01 + 8.328000000000e-10 3.726987138014e-01 + 8.428000000000e-10 4.150953468135e-01 + 8.528000000000e-10 4.286792233560e-01 + 8.628000000000e-10 3.611455588852e-01 + 8.728000000000e-10 1.976743961081e-01 + 8.828000000000e-10 4.966432661841e-03 + 8.928000000000e-10 -1.541946484524e-01 + 9.028000000000e-10 -2.478502288236e-01 + 9.128000000000e-10 -2.831123474050e-01 + 9.228000000000e-10 -3.224731331421e-01 + 9.328000000000e-10 -3.726757720747e-01 + 9.428000000000e-10 -4.151172388981e-01 + 9.528000000000e-10 -4.286573581279e-01 + 9.628000000000e-10 -3.611667698498e-01 + 9.728000000000e-10 -1.976525646923e-01 + 9.828000000000e-10 -4.987471597641e-03 + 9.928000000000e-10 1.542147143463e-01 + 1.000000000000e-09 2.301006397866e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/conditions.yaml new file mode 100644 index 00000000..fdf0598a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 11 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_11 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/CML_core_tb.sch new file mode 100644 index 00000000..6024b729 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/CML_core_tb_12.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/CML_core_tb_12.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/CML_core_tb_12.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/conditions.yaml new file mode 100644 index 00000000..191d932a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 12 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_12 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/CML_core_tb.sch new file mode 100644 index 00000000..fb3f44f9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/CML_core_tb_13.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/CML_core_tb_13.data new file mode 100644 index 00000000..36de6040 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/CML_core_tb_13.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.406999838743e-01 + 1.728000000000e-10 -1.879936990253e-01 + 1.828000000000e-10 -9.262901303246e-03 + 1.928000000000e-10 1.413611635485e-01 + 2.028000000000e-10 2.336775345801e-01 + 2.128000000000e-10 2.717294842894e-01 + 2.228000000000e-10 3.082620487639e-01 + 2.328000000000e-10 3.509422339502e-01 + 2.428000000000e-10 3.871053596645e-01 + 2.528000000000e-10 3.988940820744e-01 + 2.628000000000e-10 3.384312270542e-01 + 2.728000000000e-10 1.913281233779e-01 + 2.828000000000e-10 1.537343295661e-02 + 2.928000000000e-10 -1.347916275204e-01 + 3.028000000000e-10 -2.283419665374e-01 + 3.128000000000e-10 -2.677291408127e-01 + 3.228000000000e-10 -3.052231075401e-01 + 3.328000000000e-10 -3.481601477547e-01 + 3.428000000000e-10 -3.845854123080e-01 + 3.528000000000e-10 -3.965379624605e-01 + 3.628000000000e-10 -3.363314255870e-01 + 3.728000000000e-10 -1.893723794407e-01 + 3.828000000000e-10 -1.375643865463e-02 + 3.928000000000e-10 1.361849816757e-01 + 4.028000000000e-10 2.294005939140e-01 + 4.128000000000e-10 2.686949729273e-01 + 4.228000000000e-10 3.060328157788e-01 + 4.328000000000e-10 3.489590274886e-01 + 4.428000000000e-10 3.852266672724e-01 + 4.528000000000e-10 3.970921187630e-01 + 4.628000000000e-10 3.366736237881e-01 + 4.728000000000e-10 1.896320772426e-01 + 4.828000000000e-10 1.386475371506e-02 + 4.928000000000e-10 -1.360753156283e-01 + 5.028000000000e-10 -2.293675908871e-01 + 5.128000000000e-10 -2.686062530832e-01 + 5.228000000000e-10 -3.059945800423e-01 + 5.328000000000e-10 -3.488729675224e-01 + 5.428000000000e-10 -3.852026785029e-01 + 5.528000000000e-10 -3.970350594993e-01 + 5.628000000000e-10 -3.366834486256e-01 + 5.728000000000e-10 -1.896077423819e-01 + 5.828000000000e-10 -1.389840122586e-02 + 5.928000000000e-10 1.360876217327e-01 + 6.028000000000e-10 2.293336021557e-01 + 6.128000000000e-10 2.686225622920e-01 + 6.228000000000e-10 3.059648098566e-01 + 6.328000000000e-10 3.488907093130e-01 + 6.428000000000e-10 3.851753633828e-01 + 6.528000000000e-10 3.970526526302e-01 + 6.628000000000e-10 3.366583891048e-01 + 6.728000000000e-10 1.896251667832e-01 + 6.828000000000e-10 1.387242911077e-02 + 6.928000000000e-10 -1.360702314024e-01 + 7.028000000000e-10 -2.293580006158e-01 + 7.128000000000e-10 -2.686047945045e-01 + 7.228000000000e-10 -3.059879182353e-01 + 7.328000000000e-10 -3.488722408399e-01 + 7.428000000000e-10 -3.851969589401e-01 + 7.528000000000e-10 -3.970345404264e-01 + 7.628000000000e-10 -3.366782708831e-01 + 7.728000000000e-10 -1.896058621860e-01 + 7.828000000000e-10 -1.389192450355e-02 + 7.928000000000e-10 1.360888260036e-01 + 8.028000000000e-10 2.293391038565e-01 + 8.128000000000e-10 2.686227634282e-01 + 8.228000000000e-10 3.059688096850e-01 + 8.328000000000e-10 3.488900661997e-01 + 8.428000000000e-10 3.851789257250e-01 + 8.528000000000e-10 3.970519764807e-01 + 8.628000000000e-10 3.366616134215e-01 + 8.728000000000e-10 1.896231972496e-01 + 8.828000000000e-10 1.387461571983e-02 + 8.928000000000e-10 -1.360724758723e-01 + 9.028000000000e-10 -2.293560182270e-01 + 9.128000000000e-10 -2.686070528237e-01 + 9.228000000000e-10 -3.059854790954e-01 + 9.328000000000e-10 -3.488740842624e-01 + 9.428000000000e-10 -3.851947329758e-01 + 9.528000000000e-10 -3.970365843841e-01 + 9.628000000000e-10 -3.366766115599e-01 + 9.728000000000e-10 -1.896075309897e-01 + 9.828000000000e-10 -1.388973786858e-02 + 9.928000000000e-10 1.360872156510e-01 + 1.000000000000e-09 2.108297225004e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/conditions.yaml new file mode 100644 index 00000000..1d848f4a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 13 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_13 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/CML_core_tb.sch new file mode 100644 index 00000000..5b3a2a18 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/CML_core_tb_14.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/CML_core_tb_14.data new file mode 100644 index 00000000..73c31d13 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/CML_core_tb_14.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.445927026449e-01 + 1.728000000000e-10 -1.889320969581e-01 + 1.828000000000e-10 -5.355234564888e-03 + 1.928000000000e-10 1.489911128277e-01 + 2.028000000000e-10 2.434822449071e-01 + 2.128000000000e-10 2.838702060450e-01 + 2.228000000000e-10 3.202156401988e-01 + 2.328000000000e-10 3.629401474789e-01 + 2.428000000000e-10 3.990998051164e-01 + 2.528000000000e-10 4.099063275401e-01 + 2.628000000000e-10 3.477923521709e-01 + 2.728000000000e-10 1.968519788675e-01 + 2.828000000000e-10 1.493750763318e-02 + 2.928000000000e-10 -1.398437743336e-01 + 3.028000000000e-10 -2.362338093992e-01 + 3.128000000000e-10 -2.782887085314e-01 + 3.228000000000e-10 -3.158910292643e-01 + 3.328000000000e-10 -3.590893499920e-01 + 3.428000000000e-10 -3.957248346768e-01 + 3.528000000000e-10 -4.069627998073e-01 + 3.628000000000e-10 -3.454070734708e-01 + 3.728000000000e-10 -1.948243362004e-01 + 3.828000000000e-10 -1.337926088934e-02 + 3.928000000000e-10 1.411472162204e-01 + 4.028000000000e-10 2.372231231196e-01 + 4.128000000000e-10 2.792284454069e-01 + 4.228000000000e-10 3.166817589057e-01 + 4.328000000000e-10 3.598702175634e-01 + 4.428000000000e-10 3.963375250752e-01 + 4.528000000000e-10 4.074753309124e-01 + 4.628000000000e-10 3.456854225481e-01 + 4.728000000000e-10 1.950177434222e-01 + 4.828000000000e-10 1.342430394201e-02 + 4.928000000000e-10 -1.410850608466e-01 + 5.028000000000e-10 -2.372286880899e-01 + 5.128000000000e-10 -2.791659662153e-01 + 5.228000000000e-10 -3.166689293508e-01 + 5.328000000000e-10 -3.598026374101e-01 + 5.428000000000e-10 -3.963331138013e-01 + 5.528000000000e-10 -4.074316676804e-01 + 5.628000000000e-10 -3.457088001737e-01 + 5.728000000000e-10 -1.950000158899e-01 + 5.828000000000e-10 -1.346504722293e-02 + 5.928000000000e-10 1.410957635246e-01 + 6.028000000000e-10 2.371909425038e-01 + 6.128000000000e-10 2.791817404178e-01 + 6.228000000000e-10 3.166356138828e-01 + 6.328000000000e-10 3.598203377806e-01 + 6.428000000000e-10 3.963033609435e-01 + 6.528000000000e-10 4.074499160221e-01 + 6.628000000000e-10 3.456826167292e-01 + 6.728000000000e-10 1.950190841630e-01 + 6.828000000000e-10 1.343803454206e-02 + 6.928000000000e-10 -1.410764950259e-01 + 7.028000000000e-10 -2.372163265848e-01 + 7.128000000000e-10 -2.791624229651e-01 + 7.228000000000e-10 -3.166599225368e-01 + 7.328000000000e-10 -3.598002455584e-01 + 7.428000000000e-10 -3.963259615583e-01 + 7.528000000000e-10 -4.074304662079e-01 + 7.628000000000e-10 -3.457033629648e-01 + 7.728000000000e-10 -1.949983704767e-01 + 7.828000000000e-10 -1.345872104163e-02 + 7.928000000000e-10 1.410962716693e-01 + 8.028000000000e-10 2.371963808526e-01 + 8.128000000000e-10 2.791814500218e-01 + 8.228000000000e-10 3.166396456569e-01 + 8.328000000000e-10 3.598191409746e-01 + 8.428000000000e-10 3.963069790813e-01 + 8.528000000000e-10 4.074488078929e-01 + 8.628000000000e-10 3.456858987705e-01 + 8.728000000000e-10 1.950166421641e-01 + 8.828000000000e-10 1.344025602045e-02 + 8.928000000000e-10 -1.410790665154e-01 + 9.028000000000e-10 -2.372142995262e-01 + 9.128000000000e-10 -2.791649325552e-01 + 9.228000000000e-10 -3.166573514474e-01 + 9.328000000000e-10 -3.598022359716e-01 + 9.428000000000e-10 -3.963236588924e-01 + 9.528000000000e-10 -4.074326778223e-01 + 9.628000000000e-10 -3.457016440453e-01 + 9.728000000000e-10 -1.950001702792e-01 + 9.828000000000e-10 -1.345633761364e-02 + 9.928000000000e-10 1.410945129066e-01 + 1.000000000000e-09 2.176807579100e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/conditions.yaml new file mode 100644 index 00000000..d86ee2b6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 14 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_14 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/CML_core_tb.sch new file mode 100644 index 00000000..7ad944e0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/CML_core_tb_15.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/CML_core_tb_15.data new file mode 100644 index 00000000..6f87c434 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/CML_core_tb_15.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.831577979118e-01 + 1.728000000000e-10 -1.548331321524e-01 + 1.828000000000e-10 2.954507991941e-03 + 1.928000000000e-10 1.412083661187e-01 + 2.028000000000e-10 2.303947789211e-01 + 2.128000000000e-10 2.725788032239e-01 + 2.228000000000e-10 3.064646814943e-01 + 2.328000000000e-10 3.412898568956e-01 + 2.428000000000e-10 3.692979025942e-01 + 2.528000000000e-10 3.751979264520e-01 + 2.628000000000e-10 3.186495551608e-01 + 2.728000000000e-10 1.849115684226e-01 + 2.828000000000e-10 2.146912258403e-02 + 2.928000000000e-10 -1.215319416200e-01 + 3.028000000000e-10 -2.147336364713e-01 + 3.128000000000e-10 -2.593628319189e-01 + 3.228000000000e-10 -2.947919001104e-01 + 3.328000000000e-10 -3.306034656465e-01 + 3.428000000000e-10 -3.598903423599e-01 + 3.528000000000e-10 -3.674806029527e-01 + 3.628000000000e-10 -3.131864519443e-01 + 3.728000000000e-10 -1.816607205648e-01 + 3.828000000000e-10 -2.002885045896e-02 + 3.928000000000e-10 1.219326732879e-01 + 4.028000000000e-10 2.146583452252e-01 + 4.128000000000e-10 2.593288859790e-01 + 4.228000000000e-10 2.947836961551e-01 + 4.328000000000e-10 3.305873089453e-01 + 4.428000000000e-10 3.597520160348e-01 + 4.528000000000e-10 3.672634041173e-01 + 4.628000000000e-10 3.128292575731e-01 + 4.728000000000e-10 1.812525079401e-01 + 4.828000000000e-10 1.956255085056e-02 + 4.928000000000e-10 -1.223539241893e-01 + 5.028000000000e-10 -2.150587893921e-01 + 5.128000000000e-10 -2.596440912838e-01 + 5.228000000000e-10 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7.728000000000e-10 -1.813570925598e-01 + 7.828000000000e-10 -1.965290666609e-02 + 7.928000000000e-10 1.223145971689e-01 + 8.028000000000e-10 2.150114430495e-01 + 8.128000000000e-10 2.596256780136e-01 + 8.228000000000e-10 2.950490452158e-01 + 8.328000000000e-10 3.308307530718e-01 + 8.428000000000e-10 3.599842799802e-01 + 8.528000000000e-10 3.674639698479e-01 + 8.628000000000e-10 3.129957925611e-01 + 8.728000000000e-10 1.813666711568e-01 + 8.828000000000e-10 1.964348030724e-02 + 8.928000000000e-10 -1.223056361887e-01 + 9.028000000000e-10 -2.150207890100e-01 + 9.128000000000e-10 -2.596171721225e-01 + 9.228000000000e-10 -2.950581404305e-01 + 9.328000000000e-10 -3.308221104591e-01 + 9.428000000000e-10 -3.599929167296e-01 + 9.528000000000e-10 -3.674557320782e-01 + 9.628000000000e-10 -3.130039671541e-01 + 9.728000000000e-10 -1.813582011282e-01 + 9.828000000000e-10 -1.965175786777e-02 + 9.928000000000e-10 1.223137237372e-01 + 1.000000000000e-09 1.953703252853e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/conditions.yaml new file mode 100644 index 00000000..b5e73849 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 15 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_15 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/CML_core_tb.sch new file mode 100644 index 00000000..bc0e2451 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/CML_core_tb_16.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/CML_core_tb_16.data new file mode 100644 index 00000000..c0c44c66 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/CML_core_tb_16.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908214410229e-01 + 1.728000000000e-10 -1.609006026552e-01 + 1.828000000000e-10 -2.321243117629e-03 + 1.928000000000e-10 1.363185315112e-01 + 2.028000000000e-10 2.253864999197e-01 + 2.128000000000e-10 2.667546328680e-01 + 2.228000000000e-10 3.007016001191e-01 + 2.328000000000e-10 3.359037685855e-01 + 2.428000000000e-10 3.646369081917e-01 + 2.528000000000e-10 3.717564842409e-01 + 2.628000000000e-10 3.164681086559e-01 + 2.728000000000e-10 1.842122200319e-01 + 2.828000000000e-10 2.261788955655e-02 + 2.928000000000e-10 -1.190364341005e-01 + 3.028000000000e-10 -2.112326750882e-01 + 3.128000000000e-10 -2.547832728498e-01 + 3.228000000000e-10 -2.901354995194e-01 + 3.328000000000e-10 -3.261256516764e-01 + 3.428000000000e-10 -3.558916364396e-01 + 3.528000000000e-10 -3.643768878587e-01 + 3.628000000000e-10 -3.109660871267e-01 + 3.728000000000e-10 -1.806005122430e-01 + 3.828000000000e-10 -2.063463882859e-02 + 3.928000000000e-10 1.200417121301e-01 + 4.028000000000e-10 2.117115066678e-01 + 4.128000000000e-10 2.552245954862e-01 + 4.228000000000e-10 2.905358174314e-01 + 4.328000000000e-10 3.264964127076e-01 + 4.428000000000e-10 3.561164409890e-01 + 4.528000000000e-10 3.644937527082e-01 + 4.628000000000e-10 3.108863598347e-01 + 4.728000000000e-10 1.804066968471e-01 + 4.828000000000e-10 2.031749353463e-02 + 4.928000000000e-10 -1.203543467152e-01 + 5.028000000000e-10 -2.120338656010e-01 + 5.128000000000e-10 -2.554694201182e-01 + 5.228000000000e-10 -2.907816217466e-01 + 5.328000000000e-10 -3.266973931907e-01 + 5.428000000000e-10 -3.563354715244e-01 + 5.528000000000e-10 -3.646612654323e-01 + 5.628000000000e-10 -3.110514282819e-01 + 5.728000000000e-10 -1.805042989376e-01 + 5.828000000000e-10 -2.041198102925e-02 + 5.928000000000e-10 1.203139122453e-01 + 6.028000000000e-10 2.119789678115e-01 + 6.128000000000e-10 2.554499136191e-01 + 6.228000000000e-10 2.907352766216e-01 + 6.328000000000e-10 3.266827936599e-01 + 6.428000000000e-10 3.562972261563e-01 + 6.528000000000e-10 3.646559193667e-01 + 6.628000000000e-10 3.110272539685e-01 + 6.728000000000e-10 1.805126920434e-01 + 6.828000000000e-10 2.039901072518e-02 + 6.928000000000e-10 -1.202975671206e-01 + 7.028000000000e-10 -2.119881389434e-01 + 7.128000000000e-10 -2.554339974826e-01 + 7.228000000000e-10 -2.907449786827e-01 + 7.328000000000e-10 -3.266672756474e-01 + 7.428000000000e-10 -3.563063206496e-01 + 7.528000000000e-10 -3.646410588059e-01 + 7.628000000000e-10 -3.110359790738e-01 + 7.728000000000e-10 -1.804978632753e-01 + 7.828000000000e-10 -2.040852410596e-02 + 7.928000000000e-10 1.203110667878e-01 + 8.028000000000e-10 2.119781439274e-01 + 8.128000000000e-10 2.554465105638e-01 + 8.228000000000e-10 2.907345088651e-01 + 8.328000000000e-10 3.266793442083e-01 + 8.428000000000e-10 3.562962712815e-01 + 8.528000000000e-10 3.646525269207e-01 + 8.628000000000e-10 3.110264147595e-01 + 8.728000000000e-10 1.805087495738e-01 + 8.828000000000e-10 2.039807927138e-02 + 8.928000000000e-10 -1.203008828088e-01 + 9.028000000000e-10 -2.119885143169e-01 + 9.128000000000e-10 -2.554368509477e-01 + 9.228000000000e-10 -2.907446372900e-01 + 9.328000000000e-10 -3.266695427412e-01 + 9.428000000000e-10 -3.563059183968e-01 + 9.528000000000e-10 -3.646431522847e-01 + 9.628000000000e-10 -3.110356032735e-01 + 9.728000000000e-10 -1.804991631480e-01 + 9.828000000000e-10 -2.040735001275e-02 + 9.928000000000e-10 1.203099974113e-01 + 1.000000000000e-09 1.927324868168e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/conditions.yaml new file mode 100644 index 00000000..35779b70 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 16 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_16 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/CML_core_tb.sch new file mode 100644 index 00000000..f53966aa --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/CML_core_tb_17.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/CML_core_tb_17.data new file mode 100644 index 00000000..1e62d263 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/CML_core_tb_17.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.857852225245e-01 + 1.728000000000e-10 -1.572533595452e-01 + 1.828000000000e-10 2.540381659783e-03 + 1.928000000000e-10 1.434374080790e-01 + 2.028000000000e-10 2.351272809546e-01 + 2.128000000000e-10 2.797956268783e-01 + 2.228000000000e-10 3.144243918962e-01 + 2.328000000000e-10 3.493618787392e-01 + 2.428000000000e-10 3.773715695689e-01 + 2.528000000000e-10 3.831823569325e-01 + 2.628000000000e-10 3.264482498061e-01 + 2.728000000000e-10 1.910530045686e-01 + 2.828000000000e-10 2.436059711742e-02 + 2.928000000000e-10 -1.220220612332e-01 + 3.028000000000e-10 -2.180809390746e-01 + 3.128000000000e-10 -2.653775774444e-01 + 3.228000000000e-10 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5.728000000000e-10 -1.875700292984e-01 + 5.828000000000e-10 -2.267596999196e-02 + 5.928000000000e-10 1.226776663562e-01 + 6.028000000000e-10 2.182733434309e-01 + 6.128000000000e-10 2.656053081095e-01 + 6.228000000000e-10 3.020411985396e-01 + 6.328000000000e-10 3.381435634392e-01 + 6.428000000000e-10 3.674743818406e-01 + 6.528000000000e-10 3.750952532513e-01 + 6.628000000000e-10 3.206986438750e-01 + 6.728000000000e-10 1.875816736609e-01 + 6.828000000000e-10 2.266940437016e-02 + 6.928000000000e-10 -1.226596158426e-01 + 7.028000000000e-10 -2.182776851932e-01 + 7.128000000000e-10 -2.655888997029e-01 + 7.228000000000e-10 -3.020470638059e-01 + 7.328000000000e-10 -3.381282771084e-01 + 7.428000000000e-10 -3.674800981492e-01 + 7.528000000000e-10 -3.750811166601e-01 + 7.628000000000e-10 -3.207046174850e-01 + 7.728000000000e-10 -1.875682790354e-01 + 7.828000000000e-10 -2.267703281628e-02 + 7.928000000000e-10 1.226713327530e-01 + 8.028000000000e-10 2.182693863135e-01 + 8.128000000000e-10 2.655996099454e-01 + 8.228000000000e-10 3.020383466326e-01 + 8.328000000000e-10 3.381385294735e-01 + 8.428000000000e-10 3.674717742910e-01 + 8.528000000000e-10 3.750907045119e-01 + 8.628000000000e-10 3.206966644115e-01 + 8.728000000000e-10 1.875773616331e-01 + 8.828000000000e-10 2.266807684955e-02 + 8.928000000000e-10 -1.226628120211e-01 + 9.028000000000e-10 -2.182782381400e-01 + 9.128000000000e-10 -2.655915506047e-01 + 9.228000000000e-10 -3.020469590318e-01 + 9.328000000000e-10 -3.381303351991e-01 + 9.428000000000e-10 -3.674798958779e-01 + 9.528000000000e-10 -3.750829516380e-01 + 9.628000000000e-10 -3.207043265993e-01 + 9.728000000000e-10 -1.875693454762e-01 + 9.828000000000e-10 -2.267594148777e-02 + 9.928000000000e-10 1.226704651969e-01 + 1.000000000000e-09 1.977257563344e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/conditions.yaml new file mode 100644 index 00000000..b8e15375 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 17 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_17 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/CML_core_tb.sch new file mode 100644 index 00000000..c3d414d1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/CML_core_tb_18.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/CML_core_tb_18.data new file mode 100644 index 00000000..16422ca1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/CML_core_tb_18.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.213526702696e-01 + 1.728000000000e-10 -1.557909441213e-01 + 1.828000000000e-10 3.476956205809e-02 + 1.928000000000e-10 1.811250151598e-01 + 2.028000000000e-10 2.596166993269e-01 + 2.128000000000e-10 2.853727091731e-01 + 2.228000000000e-10 3.254453264627e-01 + 2.328000000000e-10 3.792799604087e-01 + 2.428000000000e-10 4.176388066249e-01 + 2.528000000000e-10 4.205544301124e-01 + 2.628000000000e-10 3.463528198985e-01 + 2.728000000000e-10 1.792096076204e-01 + 2.828000000000e-10 -1.442396833933e-02 + 2.928000000000e-10 -1.649237711275e-01 + 3.028000000000e-10 -2.471596975948e-01 + 3.128000000000e-10 -2.748735614517e-01 + 3.228000000000e-10 -3.160128767795e-01 + 3.328000000000e-10 -3.707930594343e-01 + 3.428000000000e-10 -4.104823651943e-01 + 3.528000000000e-10 -4.153692056047e-01 + 3.628000000000e-10 -3.427931169871e-01 + 3.728000000000e-10 -1.769552164151e-01 + 3.828000000000e-10 1.590673093360e-02 + 3.928000000000e-10 1.658834812043e-01 + 4.028000000000e-10 2.479775600913e-01 + 4.128000000000e-10 2.756409688001e-01 + 4.228000000000e-10 3.168596600790e-01 + 4.328000000000e-10 3.715133147191e-01 + 4.428000000000e-10 4.111218222953e-01 + 4.528000000000e-10 4.157229971644e-01 + 4.628000000000e-10 3.430019798682e-01 + 4.728000000000e-10 1.769456026445e-01 + 4.828000000000e-10 -1.592886494610e-02 + 4.928000000000e-10 -1.659782283296e-01 + 5.028000000000e-10 -2.479947853664e-01 + 5.128000000000e-10 -2.756931315881e-01 + 5.228000000000e-10 -3.168416717549e-01 + 5.328000000000e-10 -3.715547211919e-01 + 5.428000000000e-10 -4.111034138799e-01 + 5.528000000000e-10 -4.157691346087e-01 + 5.628000000000e-10 -3.429925568898e-01 + 5.728000000000e-10 -1.770024985869e-01 + 5.828000000000e-10 1.592938202906e-02 + 5.928000000000e-10 1.659292038608e-01 + 6.028000000000e-10 2.480043512000e-01 + 6.128000000000e-10 2.756533285421e-01 + 6.228000000000e-10 3.168576585763e-01 + 6.328000000000e-10 3.715156583068e-01 + 6.428000000000e-10 4.111207690964e-01 + 6.528000000000e-10 4.157343976531e-01 + 6.628000000000e-10 3.430135347581e-01 + 6.728000000000e-10 1.769734665185e-01 + 6.828000000000e-10 -1.590652763180e-02 + 6.928000000000e-10 -1.659537152419e-01 + 7.028000000000e-10 -2.479812550746e-01 + 7.128000000000e-10 -2.756768834918e-01 + 7.228000000000e-10 -3.168350969677e-01 + 7.328000000000e-10 -3.715419152243e-01 + 7.428000000000e-10 -4.110983779981e-01 + 7.528000000000e-10 -4.157587194411e-01 + 7.628000000000e-10 -3.429901444601e-01 + 7.728000000000e-10 -1.769973775521e-01 + 7.828000000000e-10 1.592723735432e-02 + 7.928000000000e-10 1.659318535084e-01 + 8.028000000000e-10 2.480017799848e-01 + 8.128000000000e-10 2.756559811492e-01 + 8.228000000000e-10 3.168566227283e-01 + 8.328000000000e-10 3.715195500188e-01 + 8.428000000000e-10 4.111190536097e-01 + 8.528000000000e-10 4.157370668569e-01 + 8.628000000000e-10 3.430103710665e-01 + 8.728000000000e-10 1.769771675859e-01 + 8.828000000000e-10 -1.590770493918e-02 + 8.928000000000e-10 -1.659501582149e-01 + 9.028000000000e-10 -2.479827571068e-01 + 9.128000000000e-10 -2.756738772283e-01 + 9.228000000000e-10 -3.168377001445e-01 + 9.328000000000e-10 -3.715391180409e-01 + 9.428000000000e-10 -4.111007797151e-01 + 9.528000000000e-10 -4.157556639381e-01 + 9.628000000000e-10 -3.429919881202e-01 + 9.728000000000e-10 -1.769955652012e-01 + 9.828000000000e-10 1.592430721908e-02 + 9.928000000000e-10 1.659331850974e-01 + 1.000000000000e-09 2.332140069758e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/conditions.yaml new file mode 100644 index 00000000..bb42c54d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 18 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_18 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/CML_core_tb.sch new file mode 100644 index 00000000..769e4cd5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/CML_core_tb_19.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/CML_core_tb_19.data new file mode 100644 index 00000000..6e384890 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/CML_core_tb_19.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162777317791e-01 + 1.728000000000e-10 -1.528661974147e-01 + 1.828000000000e-10 3.474832458294e-02 + 1.928000000000e-10 1.787124308466e-01 + 2.028000000000e-10 2.559986610902e-01 + 2.128000000000e-10 2.810767408313e-01 + 2.228000000000e-10 3.219404824571e-01 + 2.328000000000e-10 3.760375868322e-01 + 2.428000000000e-10 4.141294975409e-01 + 2.528000000000e-10 4.175370858756e-01 + 2.628000000000e-10 3.443891646085e-01 + 2.728000000000e-10 1.786024667409e-01 + 2.828000000000e-10 -1.272368439666e-02 + 2.928000000000e-10 -1.612661145276e-01 + 3.028000000000e-10 -2.425558656005e-01 + 3.128000000000e-10 -2.696709375544e-01 + 3.228000000000e-10 -3.115976016931e-01 + 3.328000000000e-10 -3.666762080522e-01 + 3.428000000000e-10 -4.062269757432e-01 + 3.528000000000e-10 -4.117682170104e-01 + 3.628000000000e-10 -3.403932990270e-01 + 3.728000000000e-10 -1.760595961534e-01 + 3.828000000000e-10 1.438676142530e-02 + 3.928000000000e-10 1.623380571180e-01 + 4.028000000000e-10 2.434588647096e-01 + 4.128000000000e-10 2.705169080514e-01 + 4.228000000000e-10 3.125303134845e-01 + 4.328000000000e-10 3.674735521527e-01 + 4.428000000000e-10 4.069324770669e-01 + 4.528000000000e-10 4.121668816011e-01 + 4.628000000000e-10 3.406314536055e-01 + 4.728000000000e-10 1.760592839129e-01 + 4.828000000000e-10 -1.440702618479e-02 + 4.928000000000e-10 -1.624387020945e-01 + 5.028000000000e-10 -2.434775787799e-01 + 5.128000000000e-10 -2.705727170369e-01 + 5.228000000000e-10 -3.125119373252e-01 + 5.328000000000e-10 -3.675184828947e-01 + 5.428000000000e-10 -4.069140356329e-01 + 5.528000000000e-10 -4.122173977207e-01 + 5.628000000000e-10 -3.406230488723e-01 + 5.728000000000e-10 -1.761225643375e-01 + 5.828000000000e-10 1.440482600394e-02 + 5.928000000000e-10 1.623840500109e-01 + 6.028000000000e-10 2.434858819416e-01 + 6.128000000000e-10 2.705285901327e-01 + 6.228000000000e-10 3.125279242462e-01 + 6.328000000000e-10 3.674758375852e-01 + 6.428000000000e-10 4.069313048189e-01 + 6.528000000000e-10 4.121794941223e-01 + 6.628000000000e-10 3.406442721772e-01 + 6.728000000000e-10 1.760913923029e-01 + 6.828000000000e-10 -1.438048626859e-02 + 6.928000000000e-10 -1.624102913298e-01 + 7.028000000000e-10 -2.434611919520e-01 + 7.128000000000e-10 -2.705537859875e-01 + 7.228000000000e-10 -3.125040211699e-01 + 7.328000000000e-10 -3.675038904367e-01 + 7.428000000000e-10 -4.069074652851e-01 + 7.528000000000e-10 -4.122054838885e-01 + 7.628000000000e-10 -3.406192567768e-01 + 7.728000000000e-10 -1.761170868219e-01 + 7.828000000000e-10 1.440247036537e-02 + 7.928000000000e-10 1.623867436405e-01 + 8.028000000000e-10 2.434830143217e-01 + 8.128000000000e-10 2.705312548291e-01 + 8.228000000000e-10 3.125271394700e-01 + 8.328000000000e-10 3.674800931307e-01 + 8.428000000000e-10 4.069295144266e-01 + 8.528000000000e-10 4.121823557439e-01 + 8.628000000000e-10 3.406407407456e-01 + 8.728000000000e-10 1.760956573916e-01 + 8.828000000000e-10 -1.438135361500e-02 + 8.928000000000e-10 -1.624062315135e-01 + 9.028000000000e-10 -2.434625084707e-01 + 9.128000000000e-10 -2.705503455528e-01 + 9.228000000000e-10 -3.125068466958e-01 + 9.328000000000e-10 -3.675009271833e-01 + 9.428000000000e-10 -4.069098943042e-01 + 9.528000000000e-10 -4.122022218921e-01 + 9.628000000000e-10 -3.406210058100e-01 + 9.728000000000e-10 -1.761154015725e-01 + 9.828000000000e-10 1.439913133121e-02 + 9.928000000000e-10 1.623879640093e-01 + 1.000000000000e-09 2.290402036537e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/conditions.yaml new file mode 100644 index 00000000..6236e59b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 19 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_19 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/CML_core_tb.sch new file mode 100644 index 00000000..71fb2193 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/CML_core_tb_20.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/CML_core_tb_20.data new file mode 100644 index 00000000..3dfcf241 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/CML_core_tb_20.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.365386572536e-01 + 1.728000000000e-10 -1.657072094068e-01 + 1.828000000000e-10 3.099865584261e-02 + 1.928000000000e-10 1.820426436768e-01 + 2.028000000000e-10 2.627018214462e-01 + 2.128000000000e-10 2.893736945719e-01 + 2.228000000000e-10 3.287984169352e-01 + 2.328000000000e-10 3.833334317825e-01 + 2.428000000000e-10 4.238785365972e-01 + 2.528000000000e-10 4.280322768716e-01 + 2.628000000000e-10 3.532409470363e-01 + 2.728000000000e-10 1.834641899168e-01 + 2.828000000000e-10 -1.474496205711e-02 + 2.928000000000e-10 -1.691349612478e-01 + 3.028000000000e-10 -2.530204867896e-01 + 3.128000000000e-10 -2.814070764654e-01 + 3.228000000000e-10 -3.218416847899e-01 + 3.328000000000e-10 -3.771799136100e-01 + 3.428000000000e-10 -4.187055626636e-01 + 3.528000000000e-10 -4.243036771430e-01 + 3.628000000000e-10 -3.506062035467e-01 + 3.728000000000e-10 -1.816763297909e-01 + 3.828000000000e-10 1.601938741723e-02 + 3.928000000000e-10 1.700087907901e-01 + 4.028000000000e-10 2.537596951165e-01 + 4.128000000000e-10 2.820887501770e-01 + 4.228000000000e-10 3.225625541805e-01 + 4.328000000000e-10 3.777928583784e-01 + 4.428000000000e-10 4.192485534625e-01 + 4.528000000000e-10 4.246080285894e-01 + 4.628000000000e-10 3.507916132015e-01 + 4.728000000000e-10 1.816929452641e-01 + 4.828000000000e-10 -1.601075067965e-02 + 4.928000000000e-10 -1.700562644838e-01 + 5.028000000000e-10 -2.537513990380e-01 + 5.128000000000e-10 -2.821086741965e-01 + 5.228000000000e-10 -3.225309737549e-01 + 5.328000000000e-10 -3.778081660132e-01 + 5.428000000000e-10 -4.192196231589e-01 + 5.528000000000e-10 -4.246325132019e-01 + 5.628000000000e-10 -3.507765562578e-01 + 5.728000000000e-10 -1.817315603141e-01 + 5.828000000000e-10 1.601468821266e-02 + 5.928000000000e-10 1.700220210141e-01 + 6.028000000000e-10 2.537612841477e-01 + 6.128000000000e-10 2.820810469197e-01 + 6.228000000000e-10 3.225454957468e-01 + 6.328000000000e-10 3.777800822765e-01 + 6.428000000000e-10 4.192350742948e-01 + 6.528000000000e-10 4.246071005326e-01 + 6.628000000000e-10 3.507940665347e-01 + 6.728000000000e-10 1.817094337521e-01 + 6.828000000000e-10 -1.599736953115e-02 + 6.928000000000e-10 -1.700405869499e-01 + 7.028000000000e-10 -2.537437685408e-01 + 7.128000000000e-10 -2.820988428465e-01 + 7.228000000000e-10 -3.225283133162e-01 + 7.328000000000e-10 -3.778004844844e-01 + 7.428000000000e-10 -4.192180216890e-01 + 7.528000000000e-10 -4.246257635725e-01 + 7.628000000000e-10 -3.507760422929e-01 + 7.728000000000e-10 -1.817278922025e-01 + 7.828000000000e-10 1.601285231965e-02 + 7.928000000000e-10 1.700238629540e-01 + 8.028000000000e-10 2.537592487741e-01 + 8.128000000000e-10 2.820829438407e-01 + 8.228000000000e-10 3.225445511573e-01 + 8.328000000000e-10 3.777829985044e-01 + 8.428000000000e-10 4.192337708379e-01 + 8.528000000000e-10 4.246090234999e-01 + 8.628000000000e-10 3.507916632731e-01 + 8.728000000000e-10 1.817122417436e-01 + 8.828000000000e-10 -1.599824136343e-02 + 8.928000000000e-10 -1.700377849177e-01 + 9.028000000000e-10 -2.537449127629e-01 + 9.128000000000e-10 -2.820965585668e-01 + 9.228000000000e-10 -3.225302446360e-01 + 9.328000000000e-10 -3.777982010874e-01 + 9.428000000000e-10 -4.192199753705e-01 + 9.528000000000e-10 -4.246232587341e-01 + 9.628000000000e-10 -3.507775800865e-01 + 9.728000000000e-10 -1.817263367247e-01 + 9.828000000000e-10 1.601066647660e-02 + 9.928000000000e-10 1.700248857455e-01 + 1.000000000000e-09 2.385375784000e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/conditions.yaml new file mode 100644 index 00000000..3519aa6d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 20 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_20 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/CML_core_tb.sch new file mode 100644 index 00000000..0e56b96e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/CML_core_tb_21.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/CML_core_tb_21.data new file mode 100644 index 00000000..86f9b023 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/CML_core_tb_21.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.747912795524e-01 + 1.728000000000e-10 -1.327955908449e-01 + 1.828000000000e-10 3.931332790349e-02 + 1.928000000000e-10 1.782957289495e-01 + 2.028000000000e-10 2.573194188668e-01 + 2.128000000000e-10 2.870254911902e-01 + 2.228000000000e-10 3.228650321442e-01 + 2.328000000000e-10 3.690575149088e-01 + 2.428000000000e-10 4.023791308175e-01 + 2.528000000000e-10 4.034409994944e-01 + 2.628000000000e-10 3.332295993533e-01 + 2.728000000000e-10 1.767123870243e-01 + 2.828000000000e-10 -7.574880255958e-03 + 2.928000000000e-10 -1.550892096227e-01 + 3.028000000000e-10 -2.394679486139e-01 + 3.128000000000e-10 -2.715465054757e-01 + 3.228000000000e-10 -3.085580168164e-01 + 3.328000000000e-10 -3.560821219044e-01 + 3.428000000000e-10 -3.914831036325e-01 + 3.528000000000e-10 -3.956717314322e-01 + 3.628000000000e-10 -3.285929470428e-01 + 3.728000000000e-10 -1.747908753666e-01 + 3.828000000000e-10 7.882784627431e-03 + 3.928000000000e-10 1.545893087045e-01 + 4.028000000000e-10 2.389887597051e-01 + 4.128000000000e-10 2.712307710628e-01 + 4.228000000000e-10 3.085047043395e-01 + 4.328000000000e-10 3.559448484744e-01 + 4.428000000000e-10 3.913507819782e-01 + 4.528000000000e-10 3.953547803018e-01 + 4.628000000000e-10 3.282585464854e-01 + 4.728000000000e-10 1.743078825018e-01 + 4.828000000000e-10 -8.291328068348e-03 + 4.928000000000e-10 -1.550293895867e-01 + 5.028000000000e-10 -2.392804293874e-01 + 5.128000000000e-10 -2.715405217782e-01 + 5.228000000000e-10 -3.087067361985e-01 + 5.328000000000e-10 -3.562070457914e-01 + 5.428000000000e-10 -3.915132320474e-01 + 5.528000000000e-10 -3.955548280332e-01 + 5.628000000000e-10 -3.283427048941e-01 + 5.728000000000e-10 -1.744282326244e-01 + 5.828000000000e-10 8.270645751064e-03 + 5.928000000000e-10 1.549582711486e-01 + 6.028000000000e-10 2.392860039329e-01 + 6.128000000000e-10 2.714820836214e-01 + 6.228000000000e-10 3.087161022039e-01 + 6.328000000000e-10 3.561494137047e-01 + 6.428000000000e-10 3.915273490759e-01 + 6.528000000000e-10 3.955079501007e-01 + 6.628000000000e-10 3.283677191723e-01 + 6.728000000000e-10 1.743944727908e-01 + 6.828000000000e-10 -8.238033211244e-03 + 6.928000000000e-10 -1.549849820320e-01 + 7.028000000000e-10 -2.392533741503e-01 + 7.128000000000e-10 -2.715088112944e-01 + 7.228000000000e-10 -3.086845279612e-01 + 7.328000000000e-10 -3.561786907982e-01 + 7.428000000000e-10 -3.914967682891e-01 + 7.528000000000e-10 -3.955360247734e-01 + 7.628000000000e-10 -3.283379458960e-01 + 7.728000000000e-10 -1.744219452106e-01 + 7.828000000000e-10 8.266285029230e-03 + 7.928000000000e-10 1.549592969714e-01 + 8.028000000000e-10 2.392805186707e-01 + 8.128000000000e-10 2.714837558368e-01 + 8.228000000000e-10 3.087120651005e-01 + 8.328000000000e-10 3.561520690508e-01 + 8.428000000000e-10 3.915233230940e-01 + 8.528000000000e-10 3.955100606400e-01 + 8.628000000000e-10 3.283632493206e-01 + 8.728000000000e-10 1.743968536756e-01 + 8.828000000000e-10 -8.241845610385e-03 + 8.928000000000e-10 -1.549825747228e-01 + 9.028000000000e-10 -2.392568734068e-01 + 9.128000000000e-10 -2.715063119250e-01 + 9.228000000000e-10 -3.086881712182e-01 + 9.328000000000e-10 -3.561760305782e-01 + 9.428000000000e-10 -3.915002731039e-01 + 9.528000000000e-10 -3.955331724158e-01 + 9.628000000000e-10 -3.283409163093e-01 + 9.728000000000e-10 -1.744193777973e-01 + 9.828000000000e-10 8.263272108901e-03 + 9.928000000000e-10 1.549616575981e-01 + 1.000000000000e-09 2.229820050464e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/conditions.yaml new file mode 100644 index 00000000..1bcabd93 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 21 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_21 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/CML_core_tb.sch new file mode 100644 index 00000000..9c3ed2de --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/CML_core_tb_22.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/CML_core_tb_22.data new file mode 100644 index 00000000..ef0e6c8e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/CML_core_tb_22.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.701426652476e-01 + 1.728000000000e-10 -1.295079168872e-01 + 1.828000000000e-10 4.028305902420e-02 + 1.928000000000e-10 1.769160181627e-01 + 2.028000000000e-10 2.543038782058e-01 + 2.128000000000e-10 2.828787064062e-01 + 2.228000000000e-10 3.193333275112e-01 + 2.328000000000e-10 3.660596632426e-01 + 2.428000000000e-10 3.993599084345e-01 + 2.528000000000e-10 4.007883413226e-01 + 2.628000000000e-10 3.312419521143e-01 + 2.728000000000e-10 1.754810620333e-01 + 2.828000000000e-10 -7.142746942805e-03 + 2.928000000000e-10 -1.527779354444e-01 + 3.028000000000e-10 -2.358001938178e-01 + 3.128000000000e-10 -2.668485168237e-01 + 3.228000000000e-10 -3.044746718514e-01 + 3.328000000000e-10 -3.525545062341e-01 + 3.428000000000e-10 -3.880254364838e-01 + 3.528000000000e-10 -3.926522183008e-01 + 3.628000000000e-10 -3.262954780243e-01 + 3.728000000000e-10 -1.733443838482e-01 + 3.828000000000e-10 7.573790689709e-03 + 3.928000000000e-10 1.523487073311e-01 + 4.028000000000e-10 2.353677758316e-01 + 4.128000000000e-10 2.665695097895e-01 + 4.228000000000e-10 3.044490522149e-01 + 4.328000000000e-10 3.524353166192e-01 + 4.428000000000e-10 3.879041587545e-01 + 4.528000000000e-10 3.923389296672e-01 + 4.628000000000e-10 3.259554596391e-01 + 4.728000000000e-10 1.728458619818e-01 + 4.828000000000e-10 -8.002573892585e-03 + 4.928000000000e-10 -1.528088090159e-01 + 5.028000000000e-10 -2.356747724378e-01 + 5.128000000000e-10 -2.668925685814e-01 + 5.228000000000e-10 -3.046638401901e-01 + 5.328000000000e-10 -3.527112223433e-01 + 5.428000000000e-10 -3.880786380631e-01 + 5.528000000000e-10 -3.925506229445e-01 + 5.628000000000e-10 -3.260495799326e-01 + 5.728000000000e-10 -1.729761662154e-01 + 5.828000000000e-10 7.974498187451e-03 + 5.928000000000e-10 1.527311696558e-01 + 6.028000000000e-10 2.356760074325e-01 + 6.128000000000e-10 2.668297167568e-01 + 6.228000000000e-10 3.046702367069e-01 + 6.328000000000e-10 3.526500635637e-01 + 6.428000000000e-10 3.880902250634e-01 + 6.528000000000e-10 3.925010528185e-01 + 6.628000000000e-10 3.260730653917e-01 + 6.728000000000e-10 1.729410953112e-01 + 6.828000000000e-10 -7.941970684065e-03 + 6.928000000000e-10 -1.527585341072e-01 + 7.028000000000e-10 -2.356430884825e-01 + 7.128000000000e-10 -2.668569558480e-01 + 7.228000000000e-10 -3.046384985761e-01 + 7.328000000000e-10 -3.526798341051e-01 + 7.428000000000e-10 -3.880593641809e-01 + 7.528000000000e-10 -3.925295324367e-01 + 7.628000000000e-10 -3.260427874257e-01 + 7.728000000000e-10 -1.729689796013e-01 + 7.828000000000e-10 7.970639231343e-03 + 7.928000000000e-10 1.527324506408e-01 + 8.028000000000e-10 2.356706370408e-01 + 8.128000000000e-10 2.668314718812e-01 + 8.228000000000e-10 3.046665550415e-01 + 8.328000000000e-10 3.526529348742e-01 + 8.428000000000e-10 3.880863283995e-01 + 8.528000000000e-10 3.925032166540e-01 + 8.628000000000e-10 3.260684590033e-01 + 8.728000000000e-10 1.729436324779e-01 + 8.828000000000e-10 -7.945691115533e-03 + 8.928000000000e-10 -1.527560420249e-01 + 9.028000000000e-10 -2.356465048672e-01 + 9.128000000000e-10 -2.668543449819e-01 + 9.228000000000e-10 -3.046422495200e-01 + 9.328000000000e-10 -3.526772110923e-01 + 9.428000000000e-10 -3.880628732866e-01 + 9.528000000000e-10 -3.925266759429e-01 + 9.628000000000e-10 -3.260456785141e-01 + 9.728000000000e-10 -1.729665660062e-01 + 9.828000000000e-10 7.967487161613e-03 + 9.928000000000e-10 1.527347010769e-01 + 1.000000000000e-09 2.198236907112e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/conditions.yaml new file mode 100644 index 00000000..98cbbbe9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 22 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_22 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/CML_core_tb.sch new file mode 100644 index 00000000..cfabd885 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/CML_core_tb_23.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/CML_core_tb_23.data new file mode 100644 index 00000000..7b2e7ab2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/CML_core_tb_23.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.957054612407e-01 + 1.728000000000e-10 -1.475216919691e-01 + 1.828000000000e-10 3.196996632833e-02 + 1.928000000000e-10 1.773696584526e-01 + 2.028000000000e-10 2.602670445343e-01 + 2.128000000000e-10 2.919684489720e-01 + 2.228000000000e-10 3.273690981683e-01 + 2.328000000000e-10 3.736661732429e-01 + 2.428000000000e-10 4.086769482098e-01 + 2.528000000000e-10 4.113258498473e-01 + 2.628000000000e-10 3.414272197123e-01 + 2.728000000000e-10 1.833836328070e-01 + 2.828000000000e-10 -4.501363849837e-03 + 2.928000000000e-10 -1.562318489881e-01 + 3.028000000000e-10 -2.435570784568e-01 + 3.128000000000e-10 -2.775386220390e-01 + 3.228000000000e-10 -3.142878056355e-01 + 3.328000000000e-10 -3.618442790176e-01 + 3.428000000000e-10 -3.986028140213e-01 + 3.528000000000e-10 -4.040381865127e-01 + 3.628000000000e-10 -3.369104214062e-01 + 3.728000000000e-10 -1.811830752063e-01 + 3.828000000000e-10 5.355128083595e-03 + 3.928000000000e-10 1.563630270676e-01 + 4.028000000000e-10 2.436522664355e-01 + 4.128000000000e-10 2.777202130414e-01 + 4.228000000000e-10 3.146716935396e-01 + 4.328000000000e-10 3.621309165835e-01 + 4.428000000000e-10 3.988648293319e-01 + 4.528000000000e-10 4.040567761896e-01 + 4.628000000000e-10 3.368362274946e-01 + 4.728000000000e-10 1.809052635954e-01 + 4.828000000000e-10 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7.328000000000e-10 -3.622826637804e-01 + 7.428000000000e-10 -3.989411843085e-01 + 7.528000000000e-10 -4.041807678845e-01 + 7.628000000000e-10 -3.368790616195e-01 + 7.728000000000e-10 -1.809947630224e-01 + 7.828000000000e-10 5.591512634984e-03 + 7.928000000000e-10 1.566120178189e-01 + 8.028000000000e-10 2.438458933358e-01 + 8.128000000000e-10 2.778849719194e-01 + 8.228000000000e-10 3.147945034671e-01 + 8.328000000000e-10 3.622568751046e-01 + 8.428000000000e-10 3.989662140554e-01 + 8.528000000000e-10 4.041558823701e-01 + 8.628000000000e-10 3.369030769235e-01 + 8.728000000000e-10 1.809706945647e-01 + 8.828000000000e-10 -5.568483515763e-03 + 8.928000000000e-10 -1.566340912711e-01 + 9.028000000000e-10 -2.438236181184e-01 + 9.128000000000e-10 -2.779064153414e-01 + 9.228000000000e-10 -3.147718720666e-01 + 9.328000000000e-10 -3.622798572716e-01 + 9.428000000000e-10 -3.989444036153e-01 + 9.528000000000e-10 -4.041778978449e-01 + 9.628000000000e-10 -3.368819513246e-01 + 9.728000000000e-10 -1.809921012276e-01 + 9.828000000000e-10 5.588724287086e-03 + 9.928000000000e-10 1.566143682128e-01 + 1.000000000000e-09 2.267750497136e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/conditions.yaml new file mode 100644 index 00000000..cfb5c2d9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 23 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_23 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/CML_core_tb.sch new file mode 100644 index 00000000..f684fcc8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/CML_core_tb_24.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/CML_core_tb_24.data new file mode 100644 index 00000000..a01deb89 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/CML_core_tb_24.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.908985659112e-01 + 1.728000000000e-10 -9.049079150817e-02 + 1.828000000000e-10 3.945873683219e-02 + 1.928000000000e-10 1.521437177417e-01 + 2.028000000000e-10 2.220068772324e-01 + 2.128000000000e-10 2.535092334052e-01 + 2.228000000000e-10 2.861973397174e-01 + 2.328000000000e-10 3.239843013312e-01 + 2.428000000000e-10 3.520113017607e-01 + 2.528000000000e-10 3.540468115658e-01 + 2.628000000000e-10 2.949447709683e-01 + 2.728000000000e-10 1.587983397866e-01 + 2.828000000000e-10 -6.865354773069e-03 + 2.928000000000e-10 -1.448078480843e-01 + 3.028000000000e-10 -2.275605338030e-01 + 3.128000000000e-10 -2.625604064747e-01 + 3.228000000000e-10 -2.958552078644e-01 + 3.328000000000e-10 -3.351711406638e-01 + 3.428000000000e-10 -3.644984224381e-01 + 3.528000000000e-10 -3.669950471097e-01 + 3.628000000000e-10 -3.072796408874e-01 + 3.728000000000e-10 -1.699866077827e-01 + 3.828000000000e-10 -2.842045316933e-03 + 3.928000000000e-10 1.365086891956e-01 + 4.028000000000e-10 2.207869920157e-01 + 4.128000000000e-10 2.567713461579e-01 + 4.228000000000e-10 2.907030026757e-01 + 4.328000000000e-10 3.302687598301e-01 + 4.428000000000e-10 3.600803190405e-01 + 4.528000000000e-10 3.632331450943e-01 + 4.628000000000e-10 3.045482678871e-01 + 4.728000000000e-10 1.682698274629e-01 + 4.828000000000e-10 2.058504292284e-03 + 4.928000000000e-10 -1.367871396964e-01 + 5.028000000000e-10 -2.207717990252e-01 + 5.128000000000e-10 -2.567684885934e-01 + 5.228000000000e-10 -2.906651825463e-01 + 5.328000000000e-10 -3.302494358660e-01 + 5.428000000000e-10 -3.599712284157e-01 + 5.528000000000e-10 -3.631239508150e-01 + 5.628000000000e-10 -3.043584109358e-01 + 5.728000000000e-10 -1.680958385636e-01 + 5.828000000000e-10 -1.834034512727e-03 + 5.928000000000e-10 1.369613450439e-01 + 6.028000000000e-10 2.209618957221e-01 + 6.128000000000e-10 2.568952536478e-01 + 6.228000000000e-10 2.908171185353e-01 + 6.328000000000e-10 3.303549214919e-01 + 6.428000000000e-10 3.601082390759e-01 + 6.528000000000e-10 3.632059905221e-01 + 6.628000000000e-10 3.044557238628e-01 + 6.728000000000e-10 1.681292777859e-01 + 6.828000000000e-10 1.882442241730e-03 + 6.928000000000e-10 -1.369637862409e-01 + 7.028000000000e-10 -2.209363992802e-01 + 7.128000000000e-10 -2.569065829626e-01 + 7.228000000000e-10 -2.907936706940e-01 + 7.328000000000e-10 -3.303682701482e-01 + 7.428000000000e-10 -3.600879594395e-01 + 7.528000000000e-10 -3.632220959958e-01 + 7.628000000000e-10 -3.044401007882e-01 + 7.728000000000e-10 -1.681486407544e-01 + 7.828000000000e-10 -1.870004957548e-03 + 7.928000000000e-10 1.369437070838e-01 + 8.028000000000e-10 2.209481957039e-01 + 8.128000000000e-10 2.568879030180e-01 + 8.228000000000e-10 2.908064848389e-01 + 8.328000000000e-10 3.303493303219e-01 + 8.428000000000e-10 3.601006147126e-01 + 8.528000000000e-10 3.632041339109e-01 + 8.628000000000e-10 3.044528281549e-01 + 8.728000000000e-10 1.681322760827e-01 + 8.828000000000e-10 1.883536763259e-03 + 8.928000000000e-10 -1.369582535540e-01 + 9.028000000000e-10 -2.209346296842e-01 + 9.128000000000e-10 -2.569016830366e-01 + 9.228000000000e-10 -2.907925936742e-01 + 9.328000000000e-10 -3.303636164667e-01 + 9.428000000000e-10 -3.600871302257e-01 + 9.528000000000e-10 -3.632178492939e-01 + 9.628000000000e-10 -3.044398392752e-01 + 9.728000000000e-10 -1.681454261603e-01 + 9.828000000000e-10 -1.870628705438e-03 + 9.928000000000e-10 1.369459433541e-01 + 1.000000000000e-09 2.037746084522e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/conditions.yaml new file mode 100644 index 00000000..25f37c6c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 24 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_24 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/CML_core_tb.sch new file mode 100644 index 00000000..67e9e639 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/CML_core_tb_25.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/CML_core_tb_25.data new file mode 100644 index 00000000..182746dc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/CML_core_tb_25.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.878715792581e-01 + 1.728000000000e-10 -8.812036120597e-02 + 1.828000000000e-10 4.046526586524e-02 + 1.928000000000e-10 1.515705626527e-01 + 2.028000000000e-10 2.200566198342e-01 + 2.128000000000e-10 2.503583455541e-01 + 2.228000000000e-10 2.832914205797e-01 + 2.328000000000e-10 3.216696186231e-01 + 2.428000000000e-10 3.500303926946e-01 + 2.528000000000e-10 3.524815741411e-01 + 2.628000000000e-10 2.936462106779e-01 + 2.728000000000e-10 1.576219496242e-01 + 2.828000000000e-10 -7.121462127754e-03 + 2.928000000000e-10 -1.436071598858e-01 + 3.028000000000e-10 -2.249496922999e-01 + 3.128000000000e-10 -2.586592240194e-01 + 3.228000000000e-10 -2.922419569702e-01 + 3.328000000000e-10 -3.321983211521e-01 + 3.428000000000e-10 -3.618684381611e-01 + 3.528000000000e-10 -3.648249016007e-01 + 3.628000000000e-10 -3.055379959953e-01 + 3.728000000000e-10 -1.686105488568e-01 + 3.828000000000e-10 -2.582643774162e-03 + 3.928000000000e-10 1.352182085241e-01 + 4.028000000000e-10 2.180702244722e-01 + 4.128000000000e-10 2.527783389641e-01 + 4.228000000000e-10 2.869845016096e-01 + 4.328000000000e-10 3.271697550530e-01 + 4.428000000000e-10 3.573213651505e-01 + 4.528000000000e-10 3.609341509143e-01 + 4.628000000000e-10 3.026708512688e-01 + 4.728000000000e-10 1.667591862946e-01 + 4.828000000000e-10 1.676053368052e-03 + 4.928000000000e-10 -1.356064331336e-01 + 5.028000000000e-10 -2.181494577446e-01 + 5.128000000000e-10 -2.528581012316e-01 + 5.228000000000e-10 -2.870203472690e-01 + 5.328000000000e-10 -3.272198972187e-01 + 5.428000000000e-10 -3.572767955086e-01 + 5.528000000000e-10 -3.608816832152e-01 + 5.628000000000e-10 -3.025243774497e-01 + 5.728000000000e-10 -1.666129730216e-01 + 5.828000000000e-10 -1.465204057357e-03 + 5.928000000000e-10 1.357749931272e-01 + 6.028000000000e-10 2.183376260095e-01 + 6.128000000000e-10 2.529831758691e-01 + 6.228000000000e-10 2.871716452249e-01 + 6.328000000000e-10 3.273254918206e-01 + 6.428000000000e-10 3.574148326524e-01 + 6.528000000000e-10 3.609652866209e-01 + 6.628000000000e-10 3.026246199120e-01 + 6.728000000000e-10 1.666502220733e-01 + 6.828000000000e-10 1.518129196282e-03 + 6.928000000000e-10 -1.357732099566e-01 + 7.028000000000e-10 -2.183080403425e-01 + 7.128000000000e-10 -2.529912058397e-01 + 7.228000000000e-10 -2.871450109118e-01 + 7.328000000000e-10 -3.273360198503e-01 + 7.428000000000e-10 -3.573916245859e-01 + 7.528000000000e-10 -3.609790664977e-01 + 7.628000000000e-10 -3.026068066478e-01 + 7.728000000000e-10 -1.666683959674e-01 + 7.828000000000e-10 -1.504711775466e-03 + 7.928000000000e-10 1.357534602326e-01 + 8.028000000000e-10 2.183202914392e-01 + 8.128000000000e-10 2.529726082081e-01 + 8.228000000000e-10 2.871582302084e-01 + 8.328000000000e-10 3.273171284192e-01 + 8.428000000000e-10 3.574045685766e-01 + 8.528000000000e-10 3.609610284998e-01 + 8.628000000000e-10 3.026196909841e-01 + 8.728000000000e-10 1.666518528053e-01 + 8.828000000000e-10 1.518315117290e-03 + 8.928000000000e-10 -1.357682747942e-01 + 9.028000000000e-10 -2.183066580359e-01 + 9.128000000000e-10 -2.529866332266e-01 + 9.228000000000e-10 -2.871442829871e-01 + 9.328000000000e-10 -3.273316607928e-01 + 9.428000000000e-10 -3.573910212469e-01 + 9.528000000000e-10 -3.609749965926e-01 + 9.628000000000e-10 -3.026065830591e-01 + 9.728000000000e-10 -1.666652414066e-01 + 9.828000000000e-10 -1.505286118034e-03 + 9.928000000000e-10 1.357557668798e-01 + 1.000000000000e-09 2.016242513907e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/conditions.yaml new file mode 100644 index 00000000..44d04af8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 25 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_25 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/CML_core_tb.sch new file mode 100644 index 00000000..bfdd1260 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/CML_core_tb_26.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/CML_core_tb_26.data new file mode 100644 index 00000000..c21b093d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/CML_core_tb_26.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.135873679018e-01 + 1.728000000000e-10 -1.054229355639e-01 + 1.828000000000e-10 3.485798650969e-02 + 1.928000000000e-10 1.569675139767e-01 + 2.028000000000e-10 2.330635404696e-01 + 2.128000000000e-10 2.680443549179e-01 + 2.228000000000e-10 3.014044829899e-01 + 2.328000000000e-10 3.394080314353e-01 + 2.428000000000e-10 3.679529618424e-01 + 2.528000000000e-10 3.700593040123e-01 + 2.628000000000e-10 3.097824620429e-01 + 2.728000000000e-10 1.706514675999e-01 + 2.828000000000e-10 3.558070014658e-04 + 2.928000000000e-10 -1.428409974599e-01 + 3.028000000000e-10 -2.298289579719e-01 + 3.128000000000e-10 -2.678794741753e-01 + 3.228000000000e-10 -3.017454056957e-01 + 3.328000000000e-10 -3.410620518407e-01 + 3.428000000000e-10 -3.712405389398e-01 + 3.528000000000e-10 -3.749327973471e-01 + 3.628000000000e-10 -3.157484466493e-01 + 3.728000000000e-10 -1.773087198166e-01 + 3.828000000000e-10 -7.070252178339e-03 + 3.928000000000e-10 1.364462941621e-01 + 4.028000000000e-10 2.243241068758e-01 + 4.128000000000e-10 2.631279769125e-01 + 4.228000000000e-10 2.976097246349e-01 + 4.328000000000e-10 3.371159716785e-01 + 4.428000000000e-10 3.676405775058e-01 + 4.528000000000e-10 3.717787254056e-01 + 4.628000000000e-10 3.133854979421e-01 + 4.728000000000e-10 1.756870158595e-01 + 4.828000000000e-10 6.171257018760e-03 + 4.928000000000e-10 -1.369680995621e-01 + 5.028000000000e-10 -2.245781248931e-01 + 5.128000000000e-10 -2.633829468620e-01 + 5.228000000000e-10 -2.978042748481e-01 + 5.328000000000e-10 -3.373348877854e-01 + 5.428000000000e-10 -3.677584906255e-01 + 5.528000000000e-10 -3.718812762918e-01 + 5.628000000000e-10 -3.133649557524e-01 + 5.728000000000e-10 -1.756479312047e-01 + 5.828000000000e-10 -6.040608056278e-03 + 5.928000000000e-10 1.370690415770e-01 + 6.028000000000e-10 2.247181767783e-01 + 6.128000000000e-10 2.634617265965e-01 + 6.228000000000e-10 2.979157296699e-01 + 6.328000000000e-10 3.373958940353e-01 + 6.428000000000e-10 3.678612954525e-01 + 6.528000000000e-10 3.719309221475e-01 + 6.628000000000e-10 3.134447453066e-01 + 6.728000000000e-10 1.756687688086e-01 + 6.828000000000e-10 6.090200135509e-03 + 6.928000000000e-10 -1.370702307281e-01 + 7.028000000000e-10 -2.246847420648e-01 + 7.128000000000e-10 -2.634701196121e-01 + 7.228000000000e-10 -2.978849158722e-01 + 7.328000000000e-10 -3.374068878437e-01 + 7.428000000000e-10 -3.678336110941e-01 + 7.528000000000e-10 -3.719446503824e-01 + 7.628000000000e-10 -3.134227431793e-01 + 7.728000000000e-10 -1.756868885858e-01 + 7.828000000000e-10 -6.072676723321e-03 + 7.928000000000e-10 1.370503070743e-01 + 8.028000000000e-10 2.247004966695e-01 + 8.128000000000e-10 2.634509722982e-01 + 8.228000000000e-10 2.979013793804e-01 + 8.328000000000e-10 3.373870921905e-01 + 8.428000000000e-10 3.678495602861e-01 + 8.528000000000e-10 3.719256264749e-01 + 8.628000000000e-10 3.134381864470e-01 + 8.728000000000e-10 1.756688935561e-01 + 8.828000000000e-10 6.088345643719e-03 + 8.928000000000e-10 -1.370666831053e-01 + 9.028000000000e-10 -2.246851372638e-01 + 9.128000000000e-10 -2.634666121684e-01 + 9.228000000000e-10 -2.978856025968e-01 + 9.328000000000e-10 -3.374033621769e-01 + 9.428000000000e-10 -3.678342837151e-01 + 9.528000000000e-10 -3.719412125322e-01 + 9.628000000000e-10 -3.134235677100e-01 + 9.728000000000e-10 -1.756838495744e-01 + 9.828000000000e-10 -6.073781243164e-03 + 9.928000000000e-10 1.370527135588e-01 + 1.000000000000e-09 2.065229990524e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/conditions.yaml new file mode 100644 index 00000000..1374b11f --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 26 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/run_26 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..1422d52e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,28 @@ +run,corner,temperature,vdd,time,vo_diff,frequency,amplitude,voltage_swing +run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.111e-01, -1.870e-01, -3.563e-02, …]",4.722e+09,0.382,0.763 +run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.099e-01, -1.895e-01, -4.060e-02, …]",4.722e+09,0.377,0.754 +run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.876e-01, -3.217e-02, …]",4.722e+09,0.390,0.780 +run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.915e-01, -1.780e-01, -3.803e-02, …]",4.722e+09,0.357,0.715 +run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.909e-01, -1.806e-01, -4.276e-02, …]",4.722e+09,0.353,0.706 +run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.959e-01, -1.792e-01, -3.599e-02, …]",4.722e+09,0.366,0.732 +run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.689e-01, -1.692e-01, -4.423e-02, …]",4.722e+09,0.319,0.639 +run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.694e-01, -1.722e-01, -4.907e-02, …]",4.722e+09,0.315,0.629 +run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.723e-01, -1.701e-01, -4.252e-02, …]",4.722e+09,0.330,0.659 +run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.623e-01, -1.963e-01, -5.713e-03, …]",4.722e+09,0.421,0.843 +run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.622e-01, -1.984e-01, -1.024e-02, …]",4.722e+09,0.418,0.836 +run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.669e-01, -1.979e-01, -3.070e-03, …]",4.722e+09,0.429,0.857 +run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",4.722e+09,0.401,0.803 +run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.407e-01, -1.880e-01, -9.263e-03, …]",4.722e+09,0.398,0.796 +run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.446e-01, -1.889e-01, -5.355e-03, …]",4.722e+09,0.409,0.817 +run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.832e-01, -1.548e-01, 2.955e-03, …]",4.722e+09,0.371,0.743 +run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.908e-01, -1.609e-01, -2.321e-03, …]",4.722e+09,0.368,0.736 +run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.858e-01, -1.573e-01, 2.540e-03, …]",4.722e+09,0.379,0.758 +run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.214e-01, -1.558e-01, 3.477e-02, …]",4.722e+09,0.418,0.836 +run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.529e-01, 3.475e-02, …]",4.722e+09,0.415,0.830 +run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.365e-01, -1.657e-01, 3.100e-02, …]",4.722e+09,0.426,0.853 +run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.748e-01, -1.328e-01, 3.931e-02, …]",4.722e+09,0.400,0.799 +run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.701e-01, -1.295e-01, 4.028e-02, …]",4.722e+09,0.397,0.793 +run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.957e-01, -1.475e-01, 3.197e-02, …]",4.722e+09,0.408,0.816 +run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.909e-01, -9.049e-02, 3.946e-02, …]",4.722e+09,0.365,0.730 +run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.879e-01, -8.812e-02, 4.047e-02, …]",4.722e+09,0.363,0.726 +run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.136e-01, -1.054e-01, 3.486e-02, …]",4.722e+09,0.373,0.747 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..34c2c715 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/parameters/Frequency/simulation_summary.md @@ -0,0 +1,31 @@ +# Simulation Summary for Freq + +| run | corner | temperature | vdd | time | vo_diff | frequency | amplitude | voltage_swing | +| :-- | -----: | ----------: | --: | ---: | ------: | --------: | --------: | ------------: | +| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.111e-01, -1.870e-01, -3.563e-02, …] | 4.722e+09 | 0.382 | 0.763 | +| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.099e-01, -1.895e-01, -4.060e-02, …] | 4.722e+09 | 0.377 | 0.754 | +| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.876e-01, -3.217e-02, …] | 4.722e+09 | 0.390 | 0.780 | +| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.915e-01, -1.780e-01, -3.803e-02, …] | 4.722e+09 | 0.357 | 0.715 | +| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.909e-01, -1.806e-01, -4.276e-02, …] | 4.722e+09 | 0.353 | 0.706 | +| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.959e-01, -1.792e-01, -3.599e-02, …] | 4.722e+09 | 0.366 | 0.732 | +| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.689e-01, -1.692e-01, -4.423e-02, …] | 4.722e+09 | 0.319 | 0.639 | +| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.694e-01, -1.722e-01, -4.907e-02, …] | 4.722e+09 | 0.315 | 0.629 | +| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.723e-01, -1.701e-01, -4.252e-02, …] | 4.722e+09 | 0.330 | 0.659 | +| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.623e-01, -1.963e-01, -5.713e-03, …] | 4.722e+09 | 0.421 | 0.843 | +| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.622e-01, -1.984e-01, -1.024e-02, …] | 4.722e+09 | 0.418 | 0.836 | +| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.669e-01, -1.979e-01, -3.070e-03, …] | 4.722e+09 | 0.429 | 0.857 | +| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 4.722e+09 | 0.401 | 0.803 | +| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.407e-01, -1.880e-01, -9.263e-03, …] | 4.722e+09 | 0.398 | 0.796 | +| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.446e-01, -1.889e-01, -5.355e-03, …] | 4.722e+09 | 0.409 | 0.817 | +| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.832e-01, -1.548e-01, 2.955e-03, …] | 4.722e+09 | 0.371 | 0.743 | +| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.908e-01, -1.609e-01, -2.321e-03, …] | 4.722e+09 | 0.368 | 0.736 | +| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.858e-01, -1.573e-01, 2.540e-03, …] | 4.722e+09 | 0.379 | 0.758 | +| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.214e-01, -1.558e-01, 3.477e-02, …] | 4.722e+09 | 0.418 | 0.836 | +| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.529e-01, 3.475e-02, …] | 4.722e+09 | 0.415 | 0.830 | +| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.365e-01, -1.657e-01, 3.100e-02, …] | 4.722e+09 | 0.426 | 0.853 | +| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.748e-01, -1.328e-01, 3.931e-02, …] | 4.722e+09 | 0.400 | 0.799 | +| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.701e-01, -1.295e-01, 4.028e-02, …] | 4.722e+09 | 0.397 | 0.793 | +| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.957e-01, -1.475e-01, 3.197e-02, …] | 4.722e+09 | 0.408 | 0.816 | +| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.909e-01, -9.049e-02, 3.946e-02, …] | 4.722e+09 | 0.365 | 0.730 | +| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.879e-01, -8.812e-02, 4.047e-02, …] | 4.722e+09 | 0.363 | 0.726 | +| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.136e-01, -1.054e-01, 3.486e-02, …] | 4.722e+09 | 0.373 | 0.747 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/summary.md new file mode 100644 index 00000000..9d0663f3 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-55-08/summary.md @@ -0,0 +1,11 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.3 GHz | 4.722 GHz | 5.0 GHz | 4.722 GHz | 5.2 GHz | 4.722 GHz | Pass ✅ | +| Freq | ngspice | amplitude | 0.2 GHz | 0.000 GHz | 0.4 GHz | 0.000 GHz | 0.6 GHz | 0.000 GHz | Fail ❌ | +| Freq | ngspice | voltage_swing | 0.4 GHz | 0.000 GHz | 0.8 GHz | 0.000 GHz | 1.2 GHz | 0.000 GHz | Fail ❌ | + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/CML_core_tb.sch new file mode 100644 index 00000000..d286e55c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/CML_core_tb_0.data new file mode 100644 index 00000000..4cb5b399 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.110742996065e-01 + 1.728000000000e-10 -1.869505717284e-01 + 1.828000000000e-10 -3.563037101706e-02 + 1.928000000000e-10 1.056708524540e-01 + 2.028000000000e-10 2.100393804445e-01 + 2.128000000000e-10 2.784249297688e-01 + 2.228000000000e-10 3.224310579067e-01 + 2.328000000000e-10 3.548600651170e-01 + 2.428000000000e-10 3.792482005271e-01 + 2.528000000000e-10 3.740820324036e-01 + 2.628000000000e-10 3.079440308227e-01 + 2.728000000000e-10 1.813826171807e-01 + 2.828000000000e-10 2.923027813912e-02 + 2.928000000000e-10 -1.118282325615e-01 + 3.028000000000e-10 -2.157337068367e-01 + 3.128000000000e-10 -2.829033176767e-01 + 3.228000000000e-10 -3.260714502323e-01 + 3.328000000000e-10 -3.577361248183e-01 + 3.428000000000e-10 -3.819104006606e-01 + 3.528000000000e-10 -3.764730474160e-01 + 3.628000000000e-10 -3.102968359246e-01 + 3.728000000000e-10 -1.832608913655e-01 + 3.828000000000e-10 -3.084931437320e-02 + 3.928000000000e-10 1.106163095990e-01 + 4.028000000000e-10 2.145714971977e-01 + 4.128000000000e-10 2.819937231053e-01 + 4.228000000000e-10 3.251740998910e-01 + 4.328000000000e-10 3.570946969464e-01 + 4.428000000000e-10 3.813004444382e-01 + 4.528000000000e-10 3.761230596147e-01 + 4.628000000000e-10 3.099646053412e-01 + 4.728000000000e-10 1.831473345022e-01 + 4.828000000000e-10 3.069401022130e-02 + 4.928000000000e-10 -1.106258411343e-01 + 5.028000000000e-10 -2.146793601179e-01 + 5.128000000000e-10 -2.820035552799e-01 + 5.228000000000e-10 -3.252909243829e-01 + 5.328000000000e-10 -3.570986338553e-01 + 5.428000000000e-10 -3.813904658256e-01 + 5.528000000000e-10 -3.760889514061e-01 + 5.628000000000e-10 -3.100114096943e-01 + 5.728000000000e-10 -1.830827247194e-01 + 5.828000000000e-10 -3.072480545922e-02 + 5.928000000000e-10 1.106906463094e-01 + 6.028000000000e-10 2.146493837568e-01 + 6.128000000000e-10 2.820610673881e-01 + 6.228000000000e-10 3.252525482967e-01 + 6.328000000000e-10 3.571504708749e-01 + 6.428000000000e-10 3.813516648295e-01 + 6.528000000000e-10 3.761390656738e-01 + 6.628000000000e-10 3.099742259389e-01 + 6.728000000000e-10 1.831331110808e-01 + 6.828000000000e-10 3.068765829312e-02 + 6.928000000000e-10 -1.106445812930e-01 + 7.028000000000e-10 -2.146859050297e-01 + 7.128000000000e-10 -2.820172231683e-01 + 7.228000000000e-10 -3.252905125649e-01 + 7.328000000000e-10 -3.571078709926e-01 + 7.428000000000e-10 -3.813893177320e-01 + 7.528000000000e-10 -3.760986555866e-01 + 7.628000000000e-10 -3.100117776476e-01 + 7.728000000000e-10 -1.830935153198e-01 + 7.828000000000e-10 -3.072484475908e-02 + 7.928000000000e-10 1.106810594907e-01 + 8.028000000000e-10 2.146507312123e-01 + 8.128000000000e-10 2.820530370402e-01 + 8.228000000000e-10 3.252547871433e-01 + 8.328000000000e-10 3.571432636036e-01 + 8.428000000000e-10 3.813547544577e-01 + 8.528000000000e-10 3.761324372121e-01 + 8.628000000000e-10 3.099775475493e-01 + 8.728000000000e-10 1.831274535707e-01 + 8.828000000000e-10 3.069175078476e-02 + 8.928000000000e-10 -1.106491559136e-01 + 9.028000000000e-10 -2.146821655528e-01 + 9.128000000000e-10 -2.820218639330e-01 + 9.228000000000e-10 -3.252864642203e-01 + 9.328000000000e-10 -3.571122611941e-01 + 9.428000000000e-10 -3.813854215351e-01 + 9.528000000000e-10 -3.761024723822e-01 + 9.628000000000e-10 -3.100075395903e-01 + 9.728000000000e-10 -1.830975404653e-01 + 9.828000000000e-10 -3.072097080048e-02 + 9.928000000000e-10 1.106770531472e-01 + 1.000000000000e-09 1.895325033433e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/conditions.yaml new file mode 100644 index 00000000..e969b02e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_00 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/CML_core_tb.sch new file mode 100644 index 00000000..436e0b26 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/CML_core_tb_1.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/CML_core_tb_1.data new file mode 100644 index 00000000..2b8492c0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/CML_core_tb_1.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.098686002716e-01 + 1.728000000000e-10 -1.894560696460e-01 + 1.828000000000e-10 -4.059695742871e-02 + 1.928000000000e-10 9.940964501315e-02 + 2.028000000000e-10 2.033133834097e-01 + 2.128000000000e-10 2.719620830710e-01 + 2.228000000000e-10 3.163098950569e-01 + 2.328000000000e-10 3.491513279687e-01 + 2.428000000000e-10 3.741332087119e-01 + 2.528000000000e-10 3.700254590965e-01 + 2.628000000000e-10 3.062168938694e-01 + 2.728000000000e-10 1.827341653261e-01 + 2.828000000000e-10 3.280764574542e-02 + 2.928000000000e-10 -1.069769977212e-01 + 3.028000000000e-10 -2.102924295592e-01 + 3.128000000000e-10 -2.774748738503e-01 + 3.228000000000e-10 -3.207751929169e-01 + 3.328000000000e-10 -3.527202709264e-01 + 3.428000000000e-10 -3.774342269369e-01 + 3.528000000000e-10 -3.730540733905e-01 + 3.628000000000e-10 -3.091949741363e-01 + 3.728000000000e-10 -1.851642002832e-01 + 3.828000000000e-10 -3.487935842603e-02 + 3.928000000000e-10 1.053970083053e-01 + 4.028000000000e-10 2.088131472734e-01 + 4.128000000000e-10 2.762908135843e-01 + 4.228000000000e-10 3.196385089100e-01 + 4.328000000000e-10 3.518763575372e-01 + 4.428000000000e-10 3.766558038448e-01 + 4.528000000000e-10 3.725714207051e-01 + 4.628000000000e-10 3.087619830708e-01 + 4.728000000000e-10 1.849833837695e-01 + 4.828000000000e-10 3.467977975354e-02 + 4.928000000000e-10 -1.054340839288e-01 + 5.028000000000e-10 -2.089448612506e-01 + 5.128000000000e-10 -2.763231704068e-01 + 5.228000000000e-10 -3.197791718821e-01 + 5.328000000000e-10 -3.518998659973e-01 + 5.428000000000e-10 -3.767613178326e-01 + 5.528000000000e-10 -3.725445308461e-01 + 5.628000000000e-10 -3.088109693961e-01 + 5.728000000000e-10 -1.849155432321e-01 + 5.828000000000e-10 -3.470667341543e-02 + 5.928000000000e-10 1.055048847061e-01 + 6.028000000000e-10 2.089187592091e-01 + 6.128000000000e-10 2.763849186823e-01 + 6.228000000000e-10 3.197425041182e-01 + 6.328000000000e-10 3.519544114659e-01 + 6.428000000000e-10 3.767237647599e-01 + 6.528000000000e-10 3.725977061828e-01 + 6.628000000000e-10 3.087755728399e-01 + 6.728000000000e-10 1.849692271918e-01 + 6.828000000000e-10 3.467099374312e-02 + 6.928000000000e-10 -1.054562384013e-01 + 7.028000000000e-10 -2.089544093361e-01 + 7.128000000000e-10 -2.763388509076e-01 + 7.228000000000e-10 -3.197800091948e-01 + 7.328000000000e-10 -3.519101110125e-01 + 7.428000000000e-10 -3.767612419697e-01 + 7.528000000000e-10 -3.725558598664e-01 + 7.628000000000e-10 -3.088133010441e-01 + 7.728000000000e-10 -1.849285593480e-01 + 7.828000000000e-10 -3.470862903587e-02 + 7.928000000000e-10 1.054936381918e-01 + 8.028000000000e-10 2.089186129636e-01 + 8.128000000000e-10 2.763755879874e-01 + 8.228000000000e-10 3.197437164625e-01 + 8.328000000000e-10 3.519463479929e-01 + 8.428000000000e-10 3.767260853907e-01 + 8.528000000000e-10 3.725904126785e-01 + 8.628000000000e-10 3.087783440951e-01 + 8.728000000000e-10 1.849632167070e-01 + 8.828000000000e-10 3.467482549783e-02 + 8.928000000000e-10 -1.054610682584e-01 + 9.028000000000e-10 -2.089507846182e-01 + 9.128000000000e-10 -2.763436586770e-01 + 9.228000000000e-10 -3.197760754687e-01 + 9.328000000000e-10 -3.519146615050e-01 + 9.428000000000e-10 -3.767573997120e-01 + 9.528000000000e-10 -3.725597535055e-01 + 9.628000000000e-10 -3.088090609970e-01 + 9.728000000000e-10 -1.849326628321e-01 + 9.828000000000e-10 -3.470475490247e-02 + 9.928000000000e-10 1.054896146910e-01 + 1.000000000000e-09 1.838520001242e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/conditions.yaml new file mode 100644 index 00000000..b62c65a7 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 1 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_01 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/CML_core_tb.sch new file mode 100644 index 00000000..2b654df9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/CML_core_tb_2.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/CML_core_tb_2.data new file mode 100644 index 00000000..b332ca2c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/CML_core_tb_2.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162797108708e-01 + 1.728000000000e-10 -1.875883768906e-01 + 1.828000000000e-10 -3.217177564589e-02 + 1.928000000000e-10 1.118453904517e-01 + 2.028000000000e-10 2.178869753922e-01 + 2.128000000000e-10 2.869187499571e-01 + 2.228000000000e-10 3.311831063176e-01 + 2.328000000000e-10 3.637965093552e-01 + 2.428000000000e-10 3.884475585753e-01 + 2.528000000000e-10 3.831703446637e-01 + 2.628000000000e-10 3.149426000366e-01 + 2.728000000000e-10 1.840825734866e-01 + 2.828000000000e-10 2.786370536806e-02 + 2.928000000000e-10 -1.159899232258e-01 + 3.028000000000e-10 -2.217323928122e-01 + 3.128000000000e-10 -2.897841810826e-01 + 3.228000000000e-10 -3.334256487170e-01 + 3.328000000000e-10 -3.654508602495e-01 + 3.428000000000e-10 -3.900407544937e-01 + 3.528000000000e-10 -3.846189534315e-01 + 3.628000000000e-10 -3.164922452622e-01 + 3.728000000000e-10 -1.853182634851e-01 + 3.828000000000e-10 -2.898615964086e-02 + 3.928000000000e-10 1.151710782521e-01 + 4.028000000000e-10 2.209054309263e-01 + 4.128000000000e-10 2.891817322742e-01 + 4.228000000000e-10 3.328077516782e-01 + 4.328000000000e-10 3.650515838921e-01 + 4.428000000000e-10 3.896233583948e-01 + 4.528000000000e-10 3.844074302627e-01 + 4.628000000000e-10 3.162448842688e-01 + 4.728000000000e-10 1.852475068120e-01 + 4.828000000000e-10 2.884623360652e-02 + 4.928000000000e-10 -1.151788252337e-01 + 5.028000000000e-10 -2.210147130581e-01 + 5.128000000000e-10 -2.891872658193e-01 + 5.228000000000e-10 -3.329167168088e-01 + 5.328000000000e-10 -3.650471930963e-01 + 5.428000000000e-10 -3.897100874545e-01 + 5.528000000000e-10 -3.843762306477e-01 + 5.628000000000e-10 -3.163013912188e-01 + 5.728000000000e-10 -1.851950213487e-01 + 5.828000000000e-10 -2.889036873678e-02 + 5.928000000000e-10 1.152312899162e-01 + 6.028000000000e-10 2.209735588305e-01 + 6.128000000000e-10 2.892357416511e-01 + 6.228000000000e-10 3.328707955285e-01 + 6.328000000000e-10 3.650931065031e-01 + 6.428000000000e-10 3.896657987149e-01 + 6.528000000000e-10 3.844215105032e-01 + 6.628000000000e-10 3.162596917265e-01 + 6.728000000000e-10 1.852417351036e-01 + 6.828000000000e-10 2.884992827621e-02 + 6.928000000000e-10 -1.151876679011e-01 + 7.028000000000e-10 -2.210123101756e-01 + 7.128000000000e-10 -2.891938845816e-01 + 7.228000000000e-10 -3.329106389600e-01 + 7.328000000000e-10 -3.650518039465e-01 + 7.428000000000e-10 -3.897047407363e-01 + 7.528000000000e-10 -3.843819858648e-01 + 7.628000000000e-10 -3.162978744015e-01 + 7.728000000000e-10 -1.852023753321e-01 + 7.828000000000e-10 -2.888743165850e-02 + 7.928000000000e-10 1.152240030808e-01 + 8.028000000000e-10 2.209771419031e-01 + 8.128000000000e-10 2.892295361788e-01 + 8.228000000000e-10 3.328747680971e-01 + 8.328000000000e-10 3.650871456099e-01 + 8.428000000000e-10 3.896701175780e-01 + 8.528000000000e-10 3.844156912621e-01 + 8.628000000000e-10 3.162637401476e-01 + 8.728000000000e-10 1.852363586492e-01 + 8.828000000000e-10 2.885434112124e-02 + 8.928000000000e-10 -1.151920978903e-01 + 9.028000000000e-10 -2.210084087345e-01 + 9.128000000000e-10 -2.891984388712e-01 + 9.228000000000e-10 -3.329064027155e-01 + 9.328000000000e-10 -3.650560988894e-01 + 9.428000000000e-10 -3.897007143418e-01 + 9.528000000000e-10 -3.843858173814e-01 + 9.628000000000e-10 -3.162935974835e-01 + 9.728000000000e-10 -1.852064424274e-01 + 9.828000000000e-10 -2.888350905479e-02 + 9.928000000000e-10 1.152199079204e-01 + 1.000000000000e-09 1.954791142410e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/conditions.yaml new file mode 100644 index 00000000..b95c5153 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 2 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_02 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/CML_core_tb.sch new file mode 100644 index 00000000..0bd6852e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/CML_core_tb_3.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/CML_core_tb_3.data new file mode 100644 index 00000000..6dccbfd6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/CML_core_tb_3.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.914571027454e-01 + 1.728000000000e-10 -1.780117263272e-01 + 1.828000000000e-10 -3.802564096594e-02 + 1.928000000000e-10 9.479025580261e-02 + 2.028000000000e-10 1.961220444980e-01 + 2.128000000000e-10 2.643669322964e-01 + 2.228000000000e-10 3.071498875260e-01 + 2.328000000000e-10 3.351667250191e-01 + 2.428000000000e-10 3.529478733093e-01 + 2.528000000000e-10 3.439767079911e-01 + 2.628000000000e-10 2.827109934029e-01 + 2.728000000000e-10 1.683025534555e-01 + 2.828000000000e-10 2.843266655337e-02 + 2.928000000000e-10 -1.036223502576e-01 + 3.028000000000e-10 -2.042863713809e-01 + 3.128000000000e-10 -2.713818104821e-01 + 3.228000000000e-10 -3.132717880322e-01 + 3.328000000000e-10 -3.402903477971e-01 + 3.428000000000e-10 -3.574262556597e-01 + 3.528000000000e-10 -3.476240566503e-01 + 3.628000000000e-10 -2.857203755187e-01 + 3.728000000000e-10 -1.703849236420e-01 + 3.828000000000e-10 -2.994825869373e-02 + 3.928000000000e-10 1.026817167876e-01 + 4.028000000000e-10 2.034750084544e-01 + 4.128000000000e-10 2.707812081585e-01 + 4.228000000000e-10 3.126503625184e-01 + 4.328000000000e-10 3.399043734480e-01 + 4.428000000000e-10 3.571021595385e-01 + 4.528000000000e-10 3.475896983741e-01 + 4.628000000000e-10 2.857411927694e-01 + 4.728000000000e-10 1.706053611761e-01 + 4.828000000000e-10 3.010795594348e-02 + 4.928000000000e-10 -1.024135388755e-01 + 5.028000000000e-10 -2.033190471438e-01 + 5.128000000000e-10 -2.705615444577e-01 + 5.228000000000e-10 -3.125558523975e-01 + 5.328000000000e-10 -3.397330193449e-01 + 5.428000000000e-10 -3.570354300338e-01 + 5.528000000000e-10 -3.474353611027e-01 + 5.628000000000e-10 -2.856876769732e-01 + 5.728000000000e-10 -1.704760895977e-01 + 5.828000000000e-10 -3.008641427314e-02 + 5.928000000000e-10 1.025087996136e-01 + 6.028000000000e-10 2.033209986443e-01 + 6.128000000000e-10 2.706412375819e-01 + 6.228000000000e-10 3.125457575810e-01 + 6.328000000000e-10 3.398008382665e-01 + 6.428000000000e-10 3.570145583479e-01 + 6.528000000000e-10 3.474888598072e-01 + 6.628000000000e-10 2.856551852535e-01 + 6.728000000000e-10 1.705188293935e-01 + 6.828000000000e-10 3.004736925580e-02 + 6.928000000000e-10 -1.024728514478e-01 + 7.028000000000e-10 -2.033602328622e-01 + 7.128000000000e-10 -2.706061106716e-01 + 7.228000000000e-10 -3.125843283316e-01 + 7.328000000000e-10 -3.397655433228e-01 + 7.428000000000e-10 -3.570523646632e-01 + 7.528000000000e-10 -3.474554820929e-01 + 7.628000000000e-10 -2.856929985560e-01 + 7.728000000000e-10 -1.704859799650e-01 + 7.828000000000e-10 -3.008383757896e-02 + 7.928000000000e-10 1.025039608177e-01 + 8.028000000000e-10 2.033261442763e-01 + 8.128000000000e-10 2.706371082838e-01 + 8.228000000000e-10 3.125504649737e-01 + 8.328000000000e-10 3.397966066528e-01 + 8.428000000000e-10 3.570198965640e-01 + 8.528000000000e-10 3.474857187206e-01 + 8.628000000000e-10 2.856614378232e-01 + 8.728000000000e-10 1.705164607562e-01 + 8.828000000000e-10 3.005354621749e-02 + 8.928000000000e-10 -1.024749769036e-01 + 9.028000000000e-10 -2.033548454455e-01 + 9.128000000000e-10 -2.706087008930e-01 + 9.228000000000e-10 -3.125792630790e-01 + 9.328000000000e-10 -3.397683901773e-01 + 9.428000000000e-10 -3.570478314069e-01 + 9.528000000000e-10 -3.474583427153e-01 + 9.628000000000e-10 -2.856887110961e-01 + 9.728000000000e-10 -1.704892548593e-01 + 9.828000000000e-10 -3.008001356704e-02 + 9.928000000000e-10 1.025005080892e-01 + 1.000000000000e-09 1.786649040194e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/conditions.yaml new file mode 100644 index 00000000..c908abbc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 3 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_03 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/CML_core_tb.sch new file mode 100644 index 00000000..454cb61a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/CML_core_tb_4.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/CML_core_tb_4.data new file mode 100644 index 00000000..3efc8a54 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/CML_core_tb_4.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908886906683e-01 + 1.728000000000e-10 -1.805890382926e-01 + 1.828000000000e-10 -4.276329247682e-02 + 1.928000000000e-10 8.882407595099e-02 + 2.028000000000e-10 1.894983505466e-01 + 2.128000000000e-10 2.576242567207e-01 + 2.228000000000e-10 3.005212718886e-01 + 2.328000000000e-10 3.289546768723e-01 + 2.428000000000e-10 3.474240530436e-01 + 2.528000000000e-10 3.394794629215e-01 + 2.628000000000e-10 2.802266193594e-01 + 2.728000000000e-10 1.685520573893e-01 + 2.828000000000e-10 3.081792474830e-02 + 2.928000000000e-10 -9.985913249602e-02 + 3.028000000000e-10 -1.996535082954e-01 + 3.128000000000e-10 -2.663519845580e-01 + 3.228000000000e-10 -3.081166100610e-01 + 3.328000000000e-10 -3.353557582557e-01 + 3.428000000000e-10 -3.530339682910e-01 + 3.528000000000e-10 -3.441234226063e-01 + 3.628000000000e-10 -2.840838930007e-01 + 3.728000000000e-10 -1.712890179908e-01 + 3.828000000000e-10 -3.280692441870e-02 + 3.928000000000e-10 9.858702888345e-02 + 4.028000000000e-10 1.985844458095e-01 + 4.128000000000e-10 2.655374220709e-01 + 4.228000000000e-10 3.073092043222e-01 + 4.328000000000e-10 3.348254361967e-01 + 4.428000000000e-10 3.526065806553e-01 + 4.528000000000e-10 3.440384505411e-01 + 4.628000000000e-10 2.840943593119e-01 + 4.728000000000e-10 1.715352376725e-01 + 4.828000000000e-10 3.300625747524e-02 + 4.928000000000e-10 -9.826793525126e-02 + 5.028000000000e-10 -1.983826392696e-01 + 5.128000000000e-10 -2.652748957302e-01 + 5.228000000000e-10 -3.071819372703e-01 + 5.328000000000e-10 -3.346211766496e-01 + 5.428000000000e-10 -3.525115401756e-01 + 5.528000000000e-10 -3.438520776438e-01 + 5.628000000000e-10 -2.840132934403e-01 + 5.728000000000e-10 -1.713783534881e-01 + 5.828000000000e-10 -3.296528839742e-02 + 5.928000000000e-10 9.838210726041e-02 + 6.028000000000e-10 1.983970962128e-01 + 6.128000000000e-10 2.653685996210e-01 + 6.228000000000e-10 3.071805271474e-01 + 6.328000000000e-10 3.346994451143e-01 + 6.428000000000e-10 3.524959527178e-01 + 6.528000000000e-10 3.439124816552e-01 + 6.628000000000e-10 2.839825148385e-01 + 6.728000000000e-10 1.714247364616e-01 + 6.828000000000e-10 3.292536702304e-02 + 6.928000000000e-10 -9.834444145178e-02 + 7.028000000000e-10 -1.984381153623e-01 + 7.128000000000e-10 -2.653318964793e-01 + 7.228000000000e-10 -3.072207693265e-01 + 7.328000000000e-10 -3.346627011511e-01 + 7.428000000000e-10 -3.525355719541e-01 + 7.528000000000e-10 -3.438780517049e-01 + 7.628000000000e-10 -2.840226095914e-01 + 7.728000000000e-10 -1.713910964736e-01 + 7.828000000000e-10 -3.296406429130e-02 + 7.928000000000e-10 9.837645950128e-02 + 8.028000000000e-10 1.984019833998e-01 + 8.128000000000e-10 2.653640104122e-01 + 8.228000000000e-10 3.071850636337e-01 + 8.328000000000e-10 3.346949515146e-01 + 8.428000000000e-10 3.525014052751e-01 + 8.528000000000e-10 3.439095067618e-01 + 8.628000000000e-10 2.839893402731e-01 + 8.728000000000e-10 1.714228569780e-01 + 8.828000000000e-10 3.293222880403e-02 + 8.928000000000e-10 -9.834616516704e-02 + 9.028000000000e-10 -1.984321208293e-01 + 9.128000000000e-10 -2.653341991167e-01 + 9.228000000000e-10 -3.072152380466e-01 + 9.328000000000e-10 -3.346653803170e-01 + 9.428000000000e-10 -3.525306496503e-01 + 9.528000000000e-10 -3.438807929682e-01 + 9.628000000000e-10 -2.840179937834e-01 + 9.728000000000e-10 -1.713943425416e-01 + 9.828000000000e-10 -3.296001530074e-02 + 9.928000000000e-10 9.837298926970e-02 + 1.000000000000e-09 1.738955459088e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/conditions.yaml new file mode 100644 index 00000000..96252d8e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 4 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_04 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/CML_core_tb.sch new file mode 100644 index 00000000..8c843a9b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/CML_core_tb_5.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/CML_core_tb_5.data new file mode 100644 index 00000000..0cc77d23 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/CML_core_tb_5.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.958574299710e-01 + 1.728000000000e-10 -1.791897212785e-01 + 1.828000000000e-10 -3.599075048614e-02 + 1.928000000000e-10 9.946703268478e-02 + 2.028000000000e-10 2.032502871016e-01 + 2.128000000000e-10 2.733994094958e-01 + 2.228000000000e-10 3.172845988123e-01 + 2.328000000000e-10 3.455609123691e-01 + 2.428000000000e-10 3.630923957132e-01 + 2.528000000000e-10 3.534419450967e-01 + 2.628000000000e-10 2.903663934708e-01 + 2.728000000000e-10 1.726743312860e-01 + 2.828000000000e-10 2.930291139472e-02 + 2.928000000000e-10 -1.057514312075e-01 + 3.028000000000e-10 -2.091913834589e-01 + 3.128000000000e-10 -2.784696434768e-01 + 3.228000000000e-10 -3.216873931074e-01 + 3.328000000000e-10 -3.491870426412e-01 + 3.428000000000e-10 -3.662894191498e-01 + 3.528000000000e-10 -3.560374131806e-01 + 3.628000000000e-10 -2.925719059469e-01 + 3.728000000000e-10 -1.742159787839e-01 + 3.828000000000e-10 -3.049391935212e-02 + 3.928000000000e-10 1.049756016137e-01 + 4.028000000000e-10 2.084672065617e-01 + 4.128000000000e-10 2.779301238417e-01 + 4.228000000000e-10 3.211180618030e-01 + 4.328000000000e-10 3.488255023686e-01 + 4.428000000000e-10 3.659572542624e-01 + 4.528000000000e-10 3.559493947967e-01 + 4.628000000000e-10 2.925058094407e-01 + 4.728000000000e-10 1.743267017008e-01 + 4.828000000000e-10 3.054314172764e-02 + 4.928000000000e-10 -1.048175245910e-01 + 5.028000000000e-10 -2.084096499031e-01 + 5.128000000000e-10 -2.777998408986e-01 + 5.228000000000e-10 -3.210985617265e-01 + 5.328000000000e-10 -3.487226120056e-01 + 5.428000000000e-10 -3.659481451181e-01 + 5.528000000000e-10 -3.558482598240e-01 + 5.628000000000e-10 -2.924942070749e-01 + 5.728000000000e-10 -1.742324941843e-01 + 5.828000000000e-10 -3.054486718364e-02 + 5.928000000000e-10 1.048934295445e-01 + 6.028000000000e-10 2.083991544976e-01 + 6.128000000000e-10 2.778660140822e-01 + 6.228000000000e-10 3.210794561497e-01 + 6.328000000000e-10 3.487805773205e-01 + 6.428000000000e-10 3.659226785140e-01 + 6.528000000000e-10 3.558970058340e-01 + 6.628000000000e-10 2.924624137185e-01 + 6.728000000000e-10 1.742748110039e-01 + 6.828000000000e-10 3.050920657876e-02 + 6.928000000000e-10 -1.048562048812e-01 + 7.028000000000e-10 -2.084343791218e-01 + 7.128000000000e-10 -2.778299623633e-01 + 7.228000000000e-10 -3.211147582115e-01 + 7.328000000000e-10 -3.487447461690e-01 + 7.428000000000e-10 -3.659575085549e-01 + 7.528000000000e-10 -3.558632428052e-01 + 7.628000000000e-10 -2.924972481137e-01 + 7.728000000000e-10 -1.742418088753e-01 + 7.828000000000e-10 -3.054328720193e-02 + 7.928000000000e-10 1.048870377838e-01 + 8.028000000000e-10 2.084024115537e-01 + 8.128000000000e-10 2.778603942564e-01 + 8.228000000000e-10 3.210827582845e-01 + 8.328000000000e-10 3.487751488045e-01 + 8.428000000000e-10 3.659266824704e-01 + 8.528000000000e-10 3.558925702991e-01 + 8.628000000000e-10 2.924671830422e-01 + 8.728000000000e-10 1.742711856894e-01 + 8.828000000000e-10 3.051417003050e-02 + 8.928000000000e-10 -1.048591994973e-01 + 9.028000000000e-10 -2.084299430076e-01 + 9.128000000000e-10 -2.778331783696e-01 + 9.228000000000e-10 -3.211104359655e-01 + 9.328000000000e-10 -3.487480244246e-01 + 9.428000000000e-10 -3.659535267111e-01 + 9.528000000000e-10 -3.558663548813e-01 + 9.628000000000e-10 -2.924933270906e-01 + 9.728000000000e-10 -1.742451324195e-01 + 9.828000000000e-10 -3.053963678018e-02 + 9.928000000000e-10 1.048836196344e-01 + 1.000000000000e-09 1.830293824662e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/conditions.yaml new file mode 100644 index 00000000..99793cf5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 5 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_05 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/CML_core_tb.sch new file mode 100644 index 00000000..3b8f1fb1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/CML_core_tb_6.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/CML_core_tb_6.data new file mode 100644 index 00000000..38ffd8bf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/CML_core_tb_6.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.689355033953e-01 + 1.728000000000e-10 -1.691728954892e-01 + 1.828000000000e-10 -4.423302134033e-02 + 1.928000000000e-10 7.663444207075e-02 + 2.028000000000e-10 1.714764750752e-01 + 2.128000000000e-10 2.368219567798e-01 + 2.228000000000e-10 2.772768132445e-01 + 2.328000000000e-10 3.013675537348e-01 + 2.428000000000e-10 3.140706479520e-01 + 2.528000000000e-10 3.038549886105e-01 + 2.628000000000e-10 2.508404086347e-01 + 2.728000000000e-10 1.528360605683e-01 + 2.828000000000e-10 3.040034809293e-02 + 2.928000000000e-10 -8.785381094258e-02 + 3.028000000000e-10 -1.808734961109e-01 + 3.128000000000e-10 -2.445795528199e-01 + 3.228000000000e-10 -2.838354337528e-01 + 3.328000000000e-10 -3.065800962400e-01 + 3.428000000000e-10 -3.181767360109e-01 + 3.528000000000e-10 -3.065752663659e-01 + 3.628000000000e-10 -2.523878800401e-01 + 3.728000000000e-10 -1.531173668737e-01 + 3.828000000000e-10 -2.992055538556e-02 + 3.928000000000e-10 8.900435641641e-02 + 4.028000000000e-10 1.821756238512e-01 + 4.128000000000e-10 2.460123650690e-01 + 4.228000000000e-10 2.851182310100e-01 + 4.328000000000e-10 3.079291995556e-01 + 4.428000000000e-10 3.194129911462e-01 + 4.528000000000e-10 3.078915366323e-01 + 4.628000000000e-10 2.535144344421e-01 + 4.728000000000e-10 1.541542026196e-01 + 4.828000000000e-10 3.063651583090e-02 + 4.928000000000e-10 -8.839161491074e-02 + 5.028000000000e-10 -1.817999659778e-01 + 5.128000000000e-10 -2.456456661989e-01 + 5.228000000000e-10 -2.849195350591e-01 + 5.328000000000e-10 -3.077091828990e-01 + 5.428000000000e-10 -3.193505374448e-01 + 5.528000000000e-10 -3.078081521678e-01 + 5.628000000000e-10 -2.535787813503e-01 + 5.728000000000e-10 -1.541764927596e-01 + 5.828000000000e-10 -3.077048554081e-02 + 5.928000000000e-10 8.832790620553e-02 + 6.028000000000e-10 1.816551916875e-01 + 6.128000000000e-10 2.455879975104e-01 + 6.228000000000e-10 2.847911932982e-01 + 6.328000000000e-10 3.076677363016e-01 + 6.428000000000e-10 3.192371229053e-01 + 6.528000000000e-10 3.077778412262e-01 + 6.628000000000e-10 2.534819327505e-01 + 6.728000000000e-10 1.541683138663e-01 + 6.828000000000e-10 3.070155435378e-02 + 6.928000000000e-10 -8.831320560130e-02 + 7.028000000000e-10 -1.817038543937e-01 + 7.128000000000e-10 -2.455619958387e-01 + 7.228000000000e-10 -2.848320347671e-01 + 7.328000000000e-10 -3.076358698550e-01 + 7.428000000000e-10 -3.192710667609e-01 + 7.528000000000e-10 -3.077409972388e-01 + 7.628000000000e-10 -2.535098012890e-01 + 7.728000000000e-10 -1.541282589474e-01 + 7.828000000000e-10 -3.072672689244e-02 + 7.928000000000e-10 8.835148526653e-02 + 8.028000000000e-10 1.816795669555e-01 + 8.128000000000e-10 2.455984246601e-01 + 8.228000000000e-10 2.848062931006e-01 + 8.328000000000e-10 3.076705916890e-01 + 8.428000000000e-10 3.192450073559e-01 + 8.528000000000e-10 3.077736319697e-01 + 8.628000000000e-10 2.534831121829e-01 + 8.728000000000e-10 1.541590953584e-01 + 8.828000000000e-10 3.069946612700e-02 + 8.928000000000e-10 -8.832341199891e-02 + 9.028000000000e-10 -1.817063952021e-01 + 9.128000000000e-10 -2.455714256322e-01 + 9.228000000000e-10 -2.848333922463e-01 + 9.328000000000e-10 -3.076440936715e-01 + 9.428000000000e-10 -3.192716274515e-01 + 9.528000000000e-10 -3.077481608676e-01 + 9.628000000000e-10 -2.535093614867e-01 + 9.728000000000e-10 -1.541340765567e-01 + 9.828000000000e-10 -3.072486745089e-02 + 9.928000000000e-10 8.834711873249e-02 + 1.000000000000e-09 1.586239577417e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/conditions.yaml new file mode 100644 index 00000000..670ec0c1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 6 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_06 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/CML_core_tb.sch new file mode 100644 index 00000000..437739ac --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/CML_core_tb_7.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/CML_core_tb_7.data new file mode 100644 index 00000000..1cfe87b5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/CML_core_tb_7.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.694477874818e-01 + 1.728000000000e-10 -1.721829739194e-01 + 1.828000000000e-10 -4.906833766415e-02 + 1.928000000000e-10 7.069743134728e-02 + 2.028000000000e-10 1.648418946330e-01 + 2.128000000000e-10 2.298765389610e-01 + 2.228000000000e-10 2.702802052070e-01 + 2.328000000000e-10 2.947129455777e-01 + 2.428000000000e-10 3.081296602318e-01 + 2.528000000000e-10 2.990063012040e-01 + 2.628000000000e-10 2.478884705263e-01 + 2.728000000000e-10 1.524230846398e-01 + 2.828000000000e-10 3.216725009037e-02 + 2.928000000000e-10 -8.452884553171e-02 + 3.028000000000e-10 -1.764495371150e-01 + 3.128000000000e-10 -2.394951663999e-01 + 3.228000000000e-10 -2.784178156025e-01 + 3.328000000000e-10 -3.012580547427e-01 + 3.428000000000e-10 -3.133510931360e-01 + 3.528000000000e-10 -3.026055002423e-01 + 3.628000000000e-10 -2.500554574282e-01 + 3.728000000000e-10 -1.530444893437e-01 + 3.828000000000e-10 -3.179895766292e-02 + 3.928000000000e-10 8.573594509971e-02 + 4.028000000000e-10 1.778922744476e-01 + 4.128000000000e-10 2.411102030583e-01 + 4.228000000000e-10 2.798967112063e-01 + 4.328000000000e-10 3.028156837380e-01 + 4.428000000000e-10 3.148075876296e-01 + 4.528000000000e-10 3.041758344829e-01 + 4.628000000000e-10 2.514478797306e-01 + 4.728000000000e-10 1.543354303295e-01 + 4.828000000000e-10 3.272908827542e-02 + 4.928000000000e-10 -8.494488064942e-02 + 5.028000000000e-10 -1.773750790235e-01 + 5.128000000000e-10 -2.406241070550e-01 + 5.228000000000e-10 -2.796032327906e-01 + 5.328000000000e-10 -3.025154625175e-01 + 5.428000000000e-10 -3.146850050735e-01 + 5.528000000000e-10 -3.040456856306e-01 + 5.628000000000e-10 -2.514865398019e-01 + 5.728000000000e-10 -1.543455010081e-01 + 5.828000000000e-10 -3.286780649422e-02 + 5.928000000000e-10 8.487071769529e-02 + 6.028000000000e-10 1.772120847555e-01 + 6.128000000000e-10 2.405506532865e-01 + 6.228000000000e-10 2.794557736074e-01 + 6.328000000000e-10 3.024581955274e-01 + 6.428000000000e-10 3.145521515255e-01 + 6.528000000000e-10 3.039990633934e-01 + 6.628000000000e-10 2.513709142203e-01 + 6.728000000000e-10 1.543241408079e-01 + 6.828000000000e-10 3.278555364704e-02 + 6.928000000000e-10 -8.486327141666e-02 + 7.028000000000e-10 -1.772689800248e-01 + 7.128000000000e-10 -2.405282060865e-01 + 7.228000000000e-10 -2.795021370136e-01 + 7.328000000000e-10 -3.024278022377e-01 + 7.428000000000e-10 -3.145896170200e-01 + 7.528000000000e-10 -3.039617953787e-01 + 7.628000000000e-10 -2.514004690324e-01 + 7.728000000000e-10 -1.542820043229e-01 + 7.828000000000e-10 -3.281110337775e-02 + 7.928000000000e-10 8.490436306023e-02 + 8.028000000000e-10 1.772446330839e-01 + 8.128000000000e-10 2.405674335146e-01 + 8.228000000000e-10 2.794761963085e-01 + 8.328000000000e-10 3.024650976088e-01 + 8.428000000000e-10 3.145632644585e-01 + 8.528000000000e-10 3.039968961590e-01 + 8.628000000000e-10 2.513733111446e-01 + 8.728000000000e-10 1.543150179356e-01 + 8.828000000000e-10 3.278304586331e-02 + 8.928000000000e-10 -8.487456857602e-02 + 9.028000000000e-10 -1.772725618584e-01 + 9.128000000000e-10 -2.405389250041e-01 + 9.228000000000e-10 -2.795045102279e-01 + 9.328000000000e-10 -3.024372521320e-01 + 9.428000000000e-10 -3.145911572553e-01 + 9.528000000000e-10 -3.039701598993e-01 + 9.628000000000e-10 -2.514009218164e-01 + 9.728000000000e-10 -1.542887967264e-01 + 9.828000000000e-10 -3.280979517783e-02 + 9.928000000000e-10 8.489941508642e-02 + 1.000000000000e-09 1.544118489485e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/conditions.yaml new file mode 100644 index 00000000..adbbf12b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 7 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_07 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/CML_core_tb.sch new file mode 100644 index 00000000..da7eb663 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/CML_core_tb_8.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/CML_core_tb_8.data new file mode 100644 index 00000000..b4ed17dd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/CML_core_tb_8.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.722799425151e-01 + 1.728000000000e-10 -1.701277707773e-01 + 1.828000000000e-10 -4.252496989706e-02 + 1.928000000000e-10 8.092536896213e-02 + 2.028000000000e-10 1.785199933375e-01 + 2.128000000000e-10 2.463984181452e-01 + 2.228000000000e-10 2.885755113271e-01 + 2.328000000000e-10 3.131967480955e-01 + 2.428000000000e-10 3.255285716483e-01 + 2.528000000000e-10 3.143820454109e-01 + 2.628000000000e-10 2.595824958850e-01 + 2.728000000000e-10 1.585585813323e-01 + 2.828000000000e-10 3.254606172598e-02 + 2.928000000000e-10 -8.921916265210e-02 + 3.028000000000e-10 -1.857143058967e-01 + 3.128000000000e-10 -2.524588707093e-01 + 3.228000000000e-10 -2.937876617757e-01 + 3.328000000000e-10 -3.173655773168e-01 + 3.428000000000e-10 -3.288566343508e-01 + 3.528000000000e-10 -3.166123605828e-01 + 3.628000000000e-10 -2.609360611345e-01 + 3.728000000000e-10 -1.589355414621e-01 + 3.828000000000e-10 -3.237621747627e-02 + 3.928000000000e-10 8.990939637816e-02 + 4.028000000000e-10 1.864994737191e-01 + 4.128000000000e-10 2.533636311879e-01 + 4.228000000000e-10 2.945633129641e-01 + 4.328000000000e-10 3.182197832362e-01 + 4.428000000000e-10 3.296245618008e-01 + 4.528000000000e-10 3.174841059207e-01 + 4.628000000000e-10 2.616780558587e-01 + 4.728000000000e-10 1.596622360522e-01 + 4.828000000000e-10 3.287681921596e-02 + 4.928000000000e-10 -8.943999963453e-02 + 5.028000000000e-10 -1.862066308093e-01 + 5.128000000000e-10 -2.530527908612e-01 + 5.228000000000e-10 -2.943931136832e-01 + 5.328000000000e-10 -3.180152021024e-01 + 5.428000000000e-10 -3.295545667130e-01 + 5.528000000000e-10 -3.173812952412e-01 + 5.628000000000e-10 -2.617027726155e-01 + 5.728000000000e-10 -1.596411992093e-01 + 5.828000000000e-10 -3.295895028258e-02 + 5.928000000000e-10 8.942267434718e-02 + 6.028000000000e-10 1.861105403656e-01 + 6.128000000000e-10 2.530344325895e-01 + 6.228000000000e-10 2.943051008579e-01 + 6.328000000000e-10 3.180051485103e-01 + 6.428000000000e-10 3.294737915539e-01 + 6.528000000000e-10 3.173744791022e-01 + 6.628000000000e-10 2.616291881364e-01 + 6.728000000000e-10 1.596450333001e-01 + 6.828000000000e-10 3.290088244348e-02 + 6.928000000000e-10 -8.940659470005e-02 + 7.028000000000e-10 -1.861562133447e-01 + 7.128000000000e-10 -2.530116656482e-01 + 7.228000000000e-10 -2.943454309811e-01 + 7.328000000000e-10 -3.179780561670e-01 + 7.428000000000e-10 -3.295087969733e-01 + 7.528000000000e-10 -3.173438661274e-01 + 7.628000000000e-10 -2.616591955397e-01 + 7.728000000000e-10 -1.596115565426e-01 + 7.828000000000e-10 -3.292790237402e-02 + 7.928000000000e-10 8.943927261705e-02 + 8.028000000000e-10 1.861310420114e-01 + 8.128000000000e-10 2.530433655174e-01 + 8.228000000000e-10 2.943195630770e-01 + 8.328000000000e-10 3.180088285378e-01 + 8.428000000000e-10 3.294832118435e-01 + 8.528000000000e-10 3.173732295072e-01 + 8.628000000000e-10 2.616337486722e-01 + 8.728000000000e-10 1.596399004289e-01 + 8.828000000000e-10 3.290244884503e-02 + 8.928000000000e-10 -8.941301350766e-02 + 9.028000000000e-10 -1.861557185261e-01 + 9.128000000000e-10 -2.530180139920e-01 + 9.228000000000e-10 -2.943444772306e-01 + 9.328000000000e-10 -3.179838696148e-01 + 9.428000000000e-10 -3.295076633013e-01 + 9.528000000000e-10 -3.173492560727e-01 + 9.628000000000e-10 -2.616577755083e-01 + 9.728000000000e-10 -1.596163947717e-01 + 9.828000000000e-10 -3.292583900074e-02 + 9.928000000000e-10 8.943518431692e-02 + 1.000000000000e-09 1.621529465729e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/conditions.yaml new file mode 100644 index 00000000..26daba71 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 8 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_08 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/CML_core_tb.sch new file mode 100644 index 00000000..1a87694e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/CML_core_tb_9.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/CML_core_tb_9.data new file mode 100644 index 00000000..6b24d1d6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/CML_core_tb_9.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.622644182692e-01 + 1.728000000000e-10 -1.962653738736e-01 + 1.828000000000e-10 -5.712895575235e-03 + 1.928000000000e-10 1.510345047594e-01 + 2.028000000000e-10 2.432775412534e-01 + 2.128000000000e-10 2.772000132926e-01 + 2.228000000000e-10 3.161630086256e-01 + 2.328000000000e-10 3.654121904616e-01 + 2.428000000000e-10 4.070200809677e-01 + 2.528000000000e-10 4.211809118313e-01 + 2.628000000000e-10 3.552666659990e-01 + 2.728000000000e-10 1.954111420719e-01 + 2.828000000000e-10 7.499275151763e-03 + 2.928000000000e-10 -1.488912332472e-01 + 3.028000000000e-10 -2.420325529570e-01 + 3.128000000000e-10 -2.768171400503e-01 + 3.228000000000e-10 -3.164103191401e-01 + 3.328000000000e-10 -3.656815561297e-01 + 3.428000000000e-10 -4.072561733660e-01 + 3.528000000000e-10 -4.210637971044e-01 + 3.628000000000e-10 -3.548415521036e-01 + 3.728000000000e-10 -1.946286859654e-01 + 3.828000000000e-10 -6.746438981043e-03 + 3.928000000000e-10 1.496127957227e-01 + 4.028000000000e-10 2.425057762271e-01 + 4.128000000000e-10 2.772590268750e-01 + 4.228000000000e-10 3.167075169816e-01 + 4.328000000000e-10 3.660182242119e-01 + 4.428000000000e-10 4.074726111052e-01 + 4.528000000000e-10 4.212975956202e-01 + 4.628000000000e-10 3.549573822535e-01 + 4.728000000000e-10 1.947835560361e-01 + 4.828000000000e-10 6.801482567115e-03 + 4.928000000000e-10 -1.495086456760e-01 + 5.028000000000e-10 -2.424863730465e-01 + 5.128000000000e-10 -2.771744431737e-01 + 5.228000000000e-10 -3.166940000076e-01 + 5.328000000000e-10 -3.659398771497e-01 + 5.428000000000e-10 -4.074689465730e-01 + 5.528000000000e-10 -4.212394549000e-01 + 5.628000000000e-10 -3.549741510035e-01 + 5.728000000000e-10 -1.947436351784e-01 + 5.828000000000e-10 -6.830080160870e-03 + 5.928000000000e-10 1.495407150967e-01 + 6.028000000000e-10 2.424570295697e-01 + 6.128000000000e-10 2.772066160972e-01 + 6.228000000000e-10 3.166654934082e-01 + 6.328000000000e-10 3.659723864247e-01 + 6.428000000000e-10 4.074416211051e-01 + 6.528000000000e-10 4.212697301261e-01 + 6.628000000000e-10 3.549467093259e-01 + 6.728000000000e-10 1.947718238583e-01 + 6.828000000000e-10 6.800951177238e-03 + 6.928000000000e-10 -1.495148390529e-01 + 7.028000000000e-10 -2.424852043575e-01 + 7.128000000000e-10 -2.771809105751e-01 + 7.228000000000e-10 -3.166930947909e-01 + 7.328000000000e-10 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9.828000000000e-10 -6.823236278537e-03 + 9.928000000000e-10 1.495363177485e-01 + 1.000000000000e-09 2.250264100511e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/conditions.yaml new file mode 100644 index 00000000..a359e7f5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 9 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_09 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/CML_core_tb.sch new file mode 100644 index 00000000..53f7e781 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/CML_core_tb_10.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/CML_core_tb_10.data new file mode 100644 index 00000000..f64d27bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/CML_core_tb_10.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.621881537650e-01 + 1.728000000000e-10 -1.984429143572e-01 + 1.828000000000e-10 -1.024381876325e-02 + 1.928000000000e-10 1.456486678579e-01 + 2.028000000000e-10 2.379497773075e-01 + 2.128000000000e-10 2.714724605336e-01 + 2.228000000000e-10 3.108042897090e-01 + 2.328000000000e-10 3.600441003378e-01 + 2.428000000000e-10 4.020596908788e-01 + 2.528000000000e-10 4.176332246346e-01 + 2.628000000000e-10 3.534480183483e-01 + 2.728000000000e-10 1.957884716864e-01 + 2.828000000000e-10 1.048070619246e-02 + 2.928000000000e-10 -1.446967472000e-01 + 3.028000000000e-10 -2.375576326508e-01 + 3.128000000000e-10 -2.717915022579e-01 + 3.228000000000e-10 -3.116603869888e-01 + 3.328000000000e-10 -3.608573425706e-01 + 3.428000000000e-10 -4.027490548925e-01 + 3.528000000000e-10 -4.178578104758e-01 + 3.628000000000e-10 -3.532507313188e-01 + 3.728000000000e-10 -1.951536666098e-01 + 3.828000000000e-10 -9.813336101525e-03 + 3.928000000000e-10 1.453604720604e-01 + 4.028000000000e-10 2.379857130154e-01 + 4.128000000000e-10 2.721818635676e-01 + 4.228000000000e-10 3.119088225778e-01 + 4.328000000000e-10 3.611475798924e-01 + 4.428000000000e-10 4.029304727738e-01 + 4.528000000000e-10 4.180700216423e-01 + 4.628000000000e-10 3.533627988360e-01 + 4.728000000000e-10 1.953149158213e-01 + 4.828000000000e-10 9.881134950277e-03 + 4.928000000000e-10 -1.452466419838e-01 + 5.028000000000e-10 -2.379576224969e-01 + 5.128000000000e-10 -2.720935242692e-01 + 5.228000000000e-10 -3.118909714313e-01 + 5.328000000000e-10 -3.610674239906e-01 + 5.428000000000e-10 -4.029229661263e-01 + 5.528000000000e-10 -4.180098057029e-01 + 5.628000000000e-10 -3.533753449283e-01 + 5.728000000000e-10 -1.952727841385e-01 + 5.828000000000e-10 -9.906008920915e-03 + 5.928000000000e-10 1.452800172029e-01 + 6.028000000000e-10 2.379306740359e-01 + 6.128000000000e-10 2.721261300904e-01 + 6.228000000000e-10 3.118646486801e-01 + 6.328000000000e-10 3.611003417151e-01 + 6.428000000000e-10 4.028972890619e-01 + 6.528000000000e-10 4.180401129989e-01 + 6.628000000000e-10 3.533488930459e-01 + 6.728000000000e-10 1.953007885397e-01 + 6.828000000000e-10 9.878072761317e-03 + 6.928000000000e-10 -1.452545395230e-01 + 7.028000000000e-10 -2.379578117562e-01 + 7.128000000000e-10 -2.721008877684e-01 + 7.228000000000e-10 -3.118914026492e-01 + 7.328000000000e-10 -3.610744602697e-01 + 7.428000000000e-10 -4.029226014194e-01 + 7.528000000000e-10 -4.180151483436e-01 + 7.628000000000e-10 -3.533732531474e-01 + 7.728000000000e-10 -1.952759500525e-01 + 7.828000000000e-10 -9.902411226855e-03 + 7.928000000000e-10 1.452776462046e-01 + 8.028000000000e-10 2.379341379884e-01 + 8.128000000000e-10 2.721234101956e-01 + 8.228000000000e-10 3.118677116052e-01 + 8.328000000000e-10 3.610975209728e-01 + 8.428000000000e-10 4.029000595077e-01 + 8.528000000000e-10 4.180375331400e-01 + 8.628000000000e-10 3.533517750284e-01 + 8.728000000000e-10 1.952981248182e-01 + 8.828000000000e-10 9.880873061622e-03 + 8.928000000000e-10 -1.452571579233e-01 + 9.028000000000e-10 -2.379551078725e-01 + 9.128000000000e-10 -2.721034614056e-01 + 9.228000000000e-10 -3.118886463518e-01 + 9.328000000000e-10 -3.610770519544e-01 + 9.428000000000e-10 -4.029199107687e-01 + 9.528000000000e-10 -4.180177452829e-01 + 9.628000000000e-10 -3.533708821878e-01 + 9.728000000000e-10 -1.952784134813e-01 + 9.828000000000e-10 -9.899898542678e-03 + 9.928000000000e-10 1.452754037376e-01 + 1.000000000000e-09 2.207322871295e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/conditions.yaml new file mode 100644 index 00000000..04b6ac79 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 10 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_10 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/CML_core_tb.sch new file mode 100644 index 00000000..582610e2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/CML_core_tb_11.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/CML_core_tb_11.data new file mode 100644 index 00000000..1453012b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/CML_core_tb_11.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.668500025046e-01 + 1.728000000000e-10 -1.978704758130e-01 + 1.828000000000e-10 -3.069550951996e-03 + 1.928000000000e-10 1.561389387989e-01 + 2.028000000000e-10 2.488697408913e-01 + 2.128000000000e-10 2.833379270136e-01 + 2.228000000000e-10 3.221467647695e-01 + 2.328000000000e-10 3.723176028273e-01 + 2.428000000000e-10 4.147931582649e-01 + 2.528000000000e-10 4.286646301121e-01 + 2.628000000000e-10 3.614677855799e-01 + 2.728000000000e-10 1.982726052647e-01 + 2.828000000000e-10 5.580533140739e-03 + 2.928000000000e-10 -1.536551403474e-01 + 3.028000000000e-10 -2.474729097395e-01 + 3.128000000000e-10 -2.827981749211e-01 + 3.228000000000e-10 -3.222400643179e-01 + 3.328000000000e-10 -3.724510578191e-01 + 3.428000000000e-10 -4.149487937489e-01 + 3.528000000000e-10 -4.285094572794e-01 + 3.628000000000e-10 -3.610716711123e-01 + 3.728000000000e-10 -1.975613483211e-01 + 3.828000000000e-10 -4.936396792217e-03 + 3.928000000000e-10 1.542720670721e-01 + 4.028000000000e-10 2.478554934965e-01 + 4.128000000000e-10 2.831768205427e-01 + 4.228000000000e-10 3.224764565266e-01 + 4.328000000000e-10 3.727376628527e-01 + 4.428000000000e-10 4.151128450004e-01 + 4.528000000000e-10 4.287030398326e-01 + 4.628000000000e-10 3.611465460996e-01 + 4.728000000000e-10 1.976871290976e-01 + 4.828000000000e-10 4.962067120498e-03 + 4.928000000000e-10 -1.541857483448e-01 + 5.028000000000e-10 -2.478549856990e-01 + 5.128000000000e-10 -2.831031432303e-01 + 5.228000000000e-10 -3.224786212940e-01 + 5.328000000000e-10 -3.726675199031e-01 + 5.428000000000e-10 -4.151222726988e-01 + 5.528000000000e-10 -4.286496175832e-01 + 5.628000000000e-10 -3.611719348809e-01 + 5.728000000000e-10 -1.976471175954e-01 + 5.828000000000e-10 -4.995016715658e-03 + 5.928000000000e-10 1.542195273485e-01 + 6.028000000000e-10 2.478226151197e-01 + 6.128000000000e-10 2.831371441394e-01 + 6.228000000000e-10 3.224465270882e-01 + 6.328000000000e-10 3.727020829784e-01 + 6.428000000000e-10 4.150919188021e-01 + 6.528000000000e-10 4.286821395136e-01 + 6.628000000000e-10 3.611419365066e-01 + 6.728000000000e-10 1.976777927703e-01 + 6.828000000000e-10 4.963507878799e-03 + 6.928000000000e-10 -1.541913949207e-01 + 7.028000000000e-10 -2.478529800499e-01 + 7.128000000000e-10 -2.831092109235e-01 + 7.228000000000e-10 -3.224762894768e-01 + 7.328000000000e-10 -3.726728668334e-01 + 7.428000000000e-10 -4.151201370880e-01 + 7.528000000000e-10 -4.286543531433e-01 + 7.628000000000e-10 -3.611692599178e-01 + 7.728000000000e-10 -1.976499135935e-01 + 7.828000000000e-10 -4.990471824028e-03 + 7.928000000000e-10 1.542171227717e-01 + 8.028000000000e-10 2.478269854332e-01 + 8.128000000000e-10 2.831343470853e-01 + 8.228000000000e-10 3.224500362551e-01 + 8.328000000000e-10 3.726987138014e-01 + 8.428000000000e-10 4.150953468135e-01 + 8.528000000000e-10 4.286792233560e-01 + 8.628000000000e-10 3.611455588852e-01 + 8.728000000000e-10 1.976743961081e-01 + 8.828000000000e-10 4.966432661841e-03 + 8.928000000000e-10 -1.541946484524e-01 + 9.028000000000e-10 -2.478502288236e-01 + 9.128000000000e-10 -2.831123474050e-01 + 9.228000000000e-10 -3.224731331421e-01 + 9.328000000000e-10 -3.726757720747e-01 + 9.428000000000e-10 -4.151172388981e-01 + 9.528000000000e-10 -4.286573581279e-01 + 9.628000000000e-10 -3.611667698498e-01 + 9.728000000000e-10 -1.976525646923e-01 + 9.828000000000e-10 -4.987471597641e-03 + 9.928000000000e-10 1.542147143463e-01 + 1.000000000000e-09 2.301006397866e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/conditions.yaml new file mode 100644 index 00000000..e5fb07dc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 11 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_11 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/CML_core_tb.sch new file mode 100644 index 00000000..82545e8d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/CML_core_tb_12.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/CML_core_tb_12.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/CML_core_tb_12.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/conditions.yaml new file mode 100644 index 00000000..a16247e5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 12 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_12 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/CML_core_tb.sch new file mode 100644 index 00000000..25de1bfb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/CML_core_tb_13.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/CML_core_tb_13.data new file mode 100644 index 00000000..36de6040 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/CML_core_tb_13.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.406999838743e-01 + 1.728000000000e-10 -1.879936990253e-01 + 1.828000000000e-10 -9.262901303246e-03 + 1.928000000000e-10 1.413611635485e-01 + 2.028000000000e-10 2.336775345801e-01 + 2.128000000000e-10 2.717294842894e-01 + 2.228000000000e-10 3.082620487639e-01 + 2.328000000000e-10 3.509422339502e-01 + 2.428000000000e-10 3.871053596645e-01 + 2.528000000000e-10 3.988940820744e-01 + 2.628000000000e-10 3.384312270542e-01 + 2.728000000000e-10 1.913281233779e-01 + 2.828000000000e-10 1.537343295661e-02 + 2.928000000000e-10 -1.347916275204e-01 + 3.028000000000e-10 -2.283419665374e-01 + 3.128000000000e-10 -2.677291408127e-01 + 3.228000000000e-10 -3.052231075401e-01 + 3.328000000000e-10 -3.481601477547e-01 + 3.428000000000e-10 -3.845854123080e-01 + 3.528000000000e-10 -3.965379624605e-01 + 3.628000000000e-10 -3.363314255870e-01 + 3.728000000000e-10 -1.893723794407e-01 + 3.828000000000e-10 -1.375643865463e-02 + 3.928000000000e-10 1.361849816757e-01 + 4.028000000000e-10 2.294005939140e-01 + 4.128000000000e-10 2.686949729273e-01 + 4.228000000000e-10 3.060328157788e-01 + 4.328000000000e-10 3.489590274886e-01 + 4.428000000000e-10 3.852266672724e-01 + 4.528000000000e-10 3.970921187630e-01 + 4.628000000000e-10 3.366736237881e-01 + 4.728000000000e-10 1.896320772426e-01 + 4.828000000000e-10 1.386475371506e-02 + 4.928000000000e-10 -1.360753156283e-01 + 5.028000000000e-10 -2.293675908871e-01 + 5.128000000000e-10 -2.686062530832e-01 + 5.228000000000e-10 -3.059945800423e-01 + 5.328000000000e-10 -3.488729675224e-01 + 5.428000000000e-10 -3.852026785029e-01 + 5.528000000000e-10 -3.970350594993e-01 + 5.628000000000e-10 -3.366834486256e-01 + 5.728000000000e-10 -1.896077423819e-01 + 5.828000000000e-10 -1.389840122586e-02 + 5.928000000000e-10 1.360876217327e-01 + 6.028000000000e-10 2.293336021557e-01 + 6.128000000000e-10 2.686225622920e-01 + 6.228000000000e-10 3.059648098566e-01 + 6.328000000000e-10 3.488907093130e-01 + 6.428000000000e-10 3.851753633828e-01 + 6.528000000000e-10 3.970526526302e-01 + 6.628000000000e-10 3.366583891048e-01 + 6.728000000000e-10 1.896251667832e-01 + 6.828000000000e-10 1.387242911077e-02 + 6.928000000000e-10 -1.360702314024e-01 + 7.028000000000e-10 -2.293580006158e-01 + 7.128000000000e-10 -2.686047945045e-01 + 7.228000000000e-10 -3.059879182353e-01 + 7.328000000000e-10 -3.488722408399e-01 + 7.428000000000e-10 -3.851969589401e-01 + 7.528000000000e-10 -3.970345404264e-01 + 7.628000000000e-10 -3.366782708831e-01 + 7.728000000000e-10 -1.896058621860e-01 + 7.828000000000e-10 -1.389192450355e-02 + 7.928000000000e-10 1.360888260036e-01 + 8.028000000000e-10 2.293391038565e-01 + 8.128000000000e-10 2.686227634282e-01 + 8.228000000000e-10 3.059688096850e-01 + 8.328000000000e-10 3.488900661997e-01 + 8.428000000000e-10 3.851789257250e-01 + 8.528000000000e-10 3.970519764807e-01 + 8.628000000000e-10 3.366616134215e-01 + 8.728000000000e-10 1.896231972496e-01 + 8.828000000000e-10 1.387461571983e-02 + 8.928000000000e-10 -1.360724758723e-01 + 9.028000000000e-10 -2.293560182270e-01 + 9.128000000000e-10 -2.686070528237e-01 + 9.228000000000e-10 -3.059854790954e-01 + 9.328000000000e-10 -3.488740842624e-01 + 9.428000000000e-10 -3.851947329758e-01 + 9.528000000000e-10 -3.970365843841e-01 + 9.628000000000e-10 -3.366766115599e-01 + 9.728000000000e-10 -1.896075309897e-01 + 9.828000000000e-10 -1.388973786858e-02 + 9.928000000000e-10 1.360872156510e-01 + 1.000000000000e-09 2.108297225004e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/conditions.yaml new file mode 100644 index 00000000..a1f0e95c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 13 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_13 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/CML_core_tb.sch new file mode 100644 index 00000000..579ef1c1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/CML_core_tb_14.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/CML_core_tb_14.data new file mode 100644 index 00000000..73c31d13 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/CML_core_tb_14.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.445927026449e-01 + 1.728000000000e-10 -1.889320969581e-01 + 1.828000000000e-10 -5.355234564888e-03 + 1.928000000000e-10 1.489911128277e-01 + 2.028000000000e-10 2.434822449071e-01 + 2.128000000000e-10 2.838702060450e-01 + 2.228000000000e-10 3.202156401988e-01 + 2.328000000000e-10 3.629401474789e-01 + 2.428000000000e-10 3.990998051164e-01 + 2.528000000000e-10 4.099063275401e-01 + 2.628000000000e-10 3.477923521709e-01 + 2.728000000000e-10 1.968519788675e-01 + 2.828000000000e-10 1.493750763318e-02 + 2.928000000000e-10 -1.398437743336e-01 + 3.028000000000e-10 -2.362338093992e-01 + 3.128000000000e-10 -2.782887085314e-01 + 3.228000000000e-10 -3.158910292643e-01 + 3.328000000000e-10 -3.590893499920e-01 + 3.428000000000e-10 -3.957248346768e-01 + 3.528000000000e-10 -4.069627998073e-01 + 3.628000000000e-10 -3.454070734708e-01 + 3.728000000000e-10 -1.948243362004e-01 + 3.828000000000e-10 -1.337926088934e-02 + 3.928000000000e-10 1.411472162204e-01 + 4.028000000000e-10 2.372231231196e-01 + 4.128000000000e-10 2.792284454069e-01 + 4.228000000000e-10 3.166817589057e-01 + 4.328000000000e-10 3.598702175634e-01 + 4.428000000000e-10 3.963375250752e-01 + 4.528000000000e-10 4.074753309124e-01 + 4.628000000000e-10 3.456854225481e-01 + 4.728000000000e-10 1.950177434222e-01 + 4.828000000000e-10 1.342430394201e-02 + 4.928000000000e-10 -1.410850608466e-01 + 5.028000000000e-10 -2.372286880899e-01 + 5.128000000000e-10 -2.791659662153e-01 + 5.228000000000e-10 -3.166689293508e-01 + 5.328000000000e-10 -3.598026374101e-01 + 5.428000000000e-10 -3.963331138013e-01 + 5.528000000000e-10 -4.074316676804e-01 + 5.628000000000e-10 -3.457088001737e-01 + 5.728000000000e-10 -1.950000158899e-01 + 5.828000000000e-10 -1.346504722293e-02 + 5.928000000000e-10 1.410957635246e-01 + 6.028000000000e-10 2.371909425038e-01 + 6.128000000000e-10 2.791817404178e-01 + 6.228000000000e-10 3.166356138828e-01 + 6.328000000000e-10 3.598203377806e-01 + 6.428000000000e-10 3.963033609435e-01 + 6.528000000000e-10 4.074499160221e-01 + 6.628000000000e-10 3.456826167292e-01 + 6.728000000000e-10 1.950190841630e-01 + 6.828000000000e-10 1.343803454206e-02 + 6.928000000000e-10 -1.410764950259e-01 + 7.028000000000e-10 -2.372163265848e-01 + 7.128000000000e-10 -2.791624229651e-01 + 7.228000000000e-10 -3.166599225368e-01 + 7.328000000000e-10 -3.598002455584e-01 + 7.428000000000e-10 -3.963259615583e-01 + 7.528000000000e-10 -4.074304662079e-01 + 7.628000000000e-10 -3.457033629648e-01 + 7.728000000000e-10 -1.949983704767e-01 + 7.828000000000e-10 -1.345872104163e-02 + 7.928000000000e-10 1.410962716693e-01 + 8.028000000000e-10 2.371963808526e-01 + 8.128000000000e-10 2.791814500218e-01 + 8.228000000000e-10 3.166396456569e-01 + 8.328000000000e-10 3.598191409746e-01 + 8.428000000000e-10 3.963069790813e-01 + 8.528000000000e-10 4.074488078929e-01 + 8.628000000000e-10 3.456858987705e-01 + 8.728000000000e-10 1.950166421641e-01 + 8.828000000000e-10 1.344025602045e-02 + 8.928000000000e-10 -1.410790665154e-01 + 9.028000000000e-10 -2.372142995262e-01 + 9.128000000000e-10 -2.791649325552e-01 + 9.228000000000e-10 -3.166573514474e-01 + 9.328000000000e-10 -3.598022359716e-01 + 9.428000000000e-10 -3.963236588924e-01 + 9.528000000000e-10 -4.074326778223e-01 + 9.628000000000e-10 -3.457016440453e-01 + 9.728000000000e-10 -1.950001702792e-01 + 9.828000000000e-10 -1.345633761364e-02 + 9.928000000000e-10 1.410945129066e-01 + 1.000000000000e-09 2.176807579100e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/conditions.yaml new file mode 100644 index 00000000..da3f3f71 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 14 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_14 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/CML_core_tb.sch new file mode 100644 index 00000000..c82cd7b5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/CML_core_tb_15.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/CML_core_tb_15.data new file mode 100644 index 00000000..6f87c434 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/CML_core_tb_15.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.831577979118e-01 + 1.728000000000e-10 -1.548331321524e-01 + 1.828000000000e-10 2.954507991941e-03 + 1.928000000000e-10 1.412083661187e-01 + 2.028000000000e-10 2.303947789211e-01 + 2.128000000000e-10 2.725788032239e-01 + 2.228000000000e-10 3.064646814943e-01 + 2.328000000000e-10 3.412898568956e-01 + 2.428000000000e-10 3.692979025942e-01 + 2.528000000000e-10 3.751979264520e-01 + 2.628000000000e-10 3.186495551608e-01 + 2.728000000000e-10 1.849115684226e-01 + 2.828000000000e-10 2.146912258403e-02 + 2.928000000000e-10 -1.215319416200e-01 + 3.028000000000e-10 -2.147336364713e-01 + 3.128000000000e-10 -2.593628319189e-01 + 3.228000000000e-10 -2.947919001104e-01 + 3.328000000000e-10 -3.306034656465e-01 + 3.428000000000e-10 -3.598903423599e-01 + 3.528000000000e-10 -3.674806029527e-01 + 3.628000000000e-10 -3.131864519443e-01 + 3.728000000000e-10 -1.816607205648e-01 + 3.828000000000e-10 -2.002885045896e-02 + 3.928000000000e-10 1.219326732879e-01 + 4.028000000000e-10 2.146583452252e-01 + 4.128000000000e-10 2.593288859790e-01 + 4.228000000000e-10 2.947836961551e-01 + 4.328000000000e-10 3.305873089453e-01 + 4.428000000000e-10 3.597520160348e-01 + 4.528000000000e-10 3.672634041173e-01 + 4.628000000000e-10 3.128292575731e-01 + 4.728000000000e-10 1.812525079401e-01 + 4.828000000000e-10 1.956255085056e-02 + 4.928000000000e-10 -1.223539241893e-01 + 5.028000000000e-10 -2.150587893921e-01 + 5.128000000000e-10 -2.596440912838e-01 + 5.228000000000e-10 -2.950896959018e-01 + 5.328000000000e-10 -3.308452440946e-01 + 5.428000000000e-10 -3.600168265621e-01 + 5.528000000000e-10 -3.674687038170e-01 + 5.628000000000e-10 -3.130140501398e-01 + 5.728000000000e-10 -1.813584327872e-01 + 5.828000000000e-10 -1.965159115909e-02 + 5.928000000000e-10 1.223212864923e-01 + 6.028000000000e-10 2.150157103205e-01 + 6.128000000000e-10 2.596318060931e-01 + 6.228000000000e-10 2.950524078153e-01 + 6.328000000000e-10 3.308363963911e-01 + 6.428000000000e-10 3.599874022300e-01 + 6.528000000000e-10 3.674690181116e-01 + 6.628000000000e-10 3.129980588961e-01 + 6.728000000000e-10 1.813712653368e-01 + 6.828000000000e-10 1.964491680526e-02 + 6.928000000000e-10 -1.223023112353e-01 + 7.028000000000e-10 -2.150202483004e-01 + 7.128000000000e-10 -2.596144309164e-01 + 7.228000000000e-10 -2.950582886643e-01 + 7.328000000000e-10 -3.308199600200e-01 + 7.428000000000e-10 -3.599931640339e-01 + 7.528000000000e-10 -3.674538095645e-01 + 7.628000000000e-10 -3.130042913922e-01 + 7.728000000000e-10 -1.813570925598e-01 + 7.828000000000e-10 -1.965290666609e-02 + 7.928000000000e-10 1.223145971689e-01 + 8.028000000000e-10 2.150114430495e-01 + 8.128000000000e-10 2.596256780136e-01 + 8.228000000000e-10 2.950490452158e-01 + 8.328000000000e-10 3.308307530718e-01 + 8.428000000000e-10 3.599842799802e-01 + 8.528000000000e-10 3.674639698479e-01 + 8.628000000000e-10 3.129957925611e-01 + 8.728000000000e-10 1.813666711568e-01 + 8.828000000000e-10 1.964348030724e-02 + 8.928000000000e-10 -1.223056361887e-01 + 9.028000000000e-10 -2.150207890100e-01 + 9.128000000000e-10 -2.596171721225e-01 + 9.228000000000e-10 -2.950581404305e-01 + 9.328000000000e-10 -3.308221104591e-01 + 9.428000000000e-10 -3.599929167296e-01 + 9.528000000000e-10 -3.674557320782e-01 + 9.628000000000e-10 -3.130039671541e-01 + 9.728000000000e-10 -1.813582011282e-01 + 9.828000000000e-10 -1.965175786777e-02 + 9.928000000000e-10 1.223137237372e-01 + 1.000000000000e-09 1.953703252853e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/conditions.yaml new file mode 100644 index 00000000..9f850701 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 15 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_15 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/CML_core_tb.sch new file mode 100644 index 00000000..1db2b016 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/CML_core_tb_16.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/CML_core_tb_16.data new file mode 100644 index 00000000..c0c44c66 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/CML_core_tb_16.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908214410229e-01 + 1.728000000000e-10 -1.609006026552e-01 + 1.828000000000e-10 -2.321243117629e-03 + 1.928000000000e-10 1.363185315112e-01 + 2.028000000000e-10 2.253864999197e-01 + 2.128000000000e-10 2.667546328680e-01 + 2.228000000000e-10 3.007016001191e-01 + 2.328000000000e-10 3.359037685855e-01 + 2.428000000000e-10 3.646369081917e-01 + 2.528000000000e-10 3.717564842409e-01 + 2.628000000000e-10 3.164681086559e-01 + 2.728000000000e-10 1.842122200319e-01 + 2.828000000000e-10 2.261788955655e-02 + 2.928000000000e-10 -1.190364341005e-01 + 3.028000000000e-10 -2.112326750882e-01 + 3.128000000000e-10 -2.547832728498e-01 + 3.228000000000e-10 -2.901354995194e-01 + 3.328000000000e-10 -3.261256516764e-01 + 3.428000000000e-10 -3.558916364396e-01 + 3.528000000000e-10 -3.643768878587e-01 + 3.628000000000e-10 -3.109660871267e-01 + 3.728000000000e-10 -1.806005122430e-01 + 3.828000000000e-10 -2.063463882859e-02 + 3.928000000000e-10 1.200417121301e-01 + 4.028000000000e-10 2.117115066678e-01 + 4.128000000000e-10 2.552245954862e-01 + 4.228000000000e-10 2.905358174314e-01 + 4.328000000000e-10 3.264964127076e-01 + 4.428000000000e-10 3.561164409890e-01 + 4.528000000000e-10 3.644937527082e-01 + 4.628000000000e-10 3.108863598347e-01 + 4.728000000000e-10 1.804066968471e-01 + 4.828000000000e-10 2.031749353463e-02 + 4.928000000000e-10 -1.203543467152e-01 + 5.028000000000e-10 -2.120338656010e-01 + 5.128000000000e-10 -2.554694201182e-01 + 5.228000000000e-10 -2.907816217466e-01 + 5.328000000000e-10 -3.266973931907e-01 + 5.428000000000e-10 -3.563354715244e-01 + 5.528000000000e-10 -3.646612654323e-01 + 5.628000000000e-10 -3.110514282819e-01 + 5.728000000000e-10 -1.805042989376e-01 + 5.828000000000e-10 -2.041198102925e-02 + 5.928000000000e-10 1.203139122453e-01 + 6.028000000000e-10 2.119789678115e-01 + 6.128000000000e-10 2.554499136191e-01 + 6.228000000000e-10 2.907352766216e-01 + 6.328000000000e-10 3.266827936599e-01 + 6.428000000000e-10 3.562972261563e-01 + 6.528000000000e-10 3.646559193667e-01 + 6.628000000000e-10 3.110272539685e-01 + 6.728000000000e-10 1.805126920434e-01 + 6.828000000000e-10 2.039901072518e-02 + 6.928000000000e-10 -1.202975671206e-01 + 7.028000000000e-10 -2.119881389434e-01 + 7.128000000000e-10 -2.554339974826e-01 + 7.228000000000e-10 -2.907449786827e-01 + 7.328000000000e-10 -3.266672756474e-01 + 7.428000000000e-10 -3.563063206496e-01 + 7.528000000000e-10 -3.646410588059e-01 + 7.628000000000e-10 -3.110359790738e-01 + 7.728000000000e-10 -1.804978632753e-01 + 7.828000000000e-10 -2.040852410596e-02 + 7.928000000000e-10 1.203110667878e-01 + 8.028000000000e-10 2.119781439274e-01 + 8.128000000000e-10 2.554465105638e-01 + 8.228000000000e-10 2.907345088651e-01 + 8.328000000000e-10 3.266793442083e-01 + 8.428000000000e-10 3.562962712815e-01 + 8.528000000000e-10 3.646525269207e-01 + 8.628000000000e-10 3.110264147595e-01 + 8.728000000000e-10 1.805087495738e-01 + 8.828000000000e-10 2.039807927138e-02 + 8.928000000000e-10 -1.203008828088e-01 + 9.028000000000e-10 -2.119885143169e-01 + 9.128000000000e-10 -2.554368509477e-01 + 9.228000000000e-10 -2.907446372900e-01 + 9.328000000000e-10 -3.266695427412e-01 + 9.428000000000e-10 -3.563059183968e-01 + 9.528000000000e-10 -3.646431522847e-01 + 9.628000000000e-10 -3.110356032735e-01 + 9.728000000000e-10 -1.804991631480e-01 + 9.828000000000e-10 -2.040735001275e-02 + 9.928000000000e-10 1.203099974113e-01 + 1.000000000000e-09 1.927324868168e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/conditions.yaml new file mode 100644 index 00000000..2bb1db93 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 16 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_16 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/CML_core_tb.sch new file mode 100644 index 00000000..412ffd3b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/CML_core_tb_17.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/CML_core_tb_17.data new file mode 100644 index 00000000..1e62d263 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/CML_core_tb_17.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.857852225245e-01 + 1.728000000000e-10 -1.572533595452e-01 + 1.828000000000e-10 2.540381659783e-03 + 1.928000000000e-10 1.434374080790e-01 + 2.028000000000e-10 2.351272809546e-01 + 2.128000000000e-10 2.797956268783e-01 + 2.228000000000e-10 3.144243918962e-01 + 2.328000000000e-10 3.493618787392e-01 + 2.428000000000e-10 3.773715695689e-01 + 2.528000000000e-10 3.831823569325e-01 + 2.628000000000e-10 3.264482498061e-01 + 2.728000000000e-10 1.910530045686e-01 + 2.828000000000e-10 2.436059711742e-02 + 2.928000000000e-10 -1.220220612332e-01 + 3.028000000000e-10 -2.180809390746e-01 + 3.128000000000e-10 -2.653775774444e-01 + 3.228000000000e-10 -3.017848824321e-01 + 3.328000000000e-10 -3.379021858146e-01 + 3.428000000000e-10 -3.673696540777e-01 + 3.528000000000e-10 -3.751149757425e-01 + 3.628000000000e-10 -3.209083740174e-01 + 3.728000000000e-10 -1.878979131572e-01 + 3.828000000000e-10 -2.307531260616e-02 + 3.928000000000e-10 1.222703025101e-01 + 4.028000000000e-10 2.179003509445e-01 + 4.128000000000e-10 2.652908784701e-01 + 4.228000000000e-10 3.017672646237e-01 + 4.328000000000e-10 3.378931599738e-01 + 4.428000000000e-10 3.672390198172e-01 + 4.528000000000e-10 3.748903812400e-01 + 4.628000000000e-10 3.205316331029e-01 + 4.728000000000e-10 1.874647700937e-01 + 4.828000000000e-10 2.258819957166e-02 + 4.928000000000e-10 -1.227112688171e-01 + 5.028000000000e-10 -2.183172764214e-01 + 5.128000000000e-10 -2.656203742551e-01 + 5.228000000000e-10 -3.020800906145e-01 + 5.328000000000e-10 -3.381553362553e-01 + 5.428000000000e-10 -3.675051891202e-01 + 5.528000000000e-10 -3.750972240389e-01 + 5.628000000000e-10 -3.207148935088e-01 + 5.728000000000e-10 -1.875700292984e-01 + 5.828000000000e-10 -2.267596999196e-02 + 5.928000000000e-10 1.226776663562e-01 + 6.028000000000e-10 2.182733434309e-01 + 6.128000000000e-10 2.656053081095e-01 + 6.228000000000e-10 3.020411985396e-01 + 6.328000000000e-10 3.381435634392e-01 + 6.428000000000e-10 3.674743818406e-01 + 6.528000000000e-10 3.750952532513e-01 + 6.628000000000e-10 3.206986438750e-01 + 6.728000000000e-10 1.875816736609e-01 + 6.828000000000e-10 2.266940437016e-02 + 6.928000000000e-10 -1.226596158426e-01 + 7.028000000000e-10 -2.182776851932e-01 + 7.128000000000e-10 -2.655888997029e-01 + 7.228000000000e-10 -3.020470638059e-01 + 7.328000000000e-10 -3.381282771084e-01 + 7.428000000000e-10 -3.674800981492e-01 + 7.528000000000e-10 -3.750811166601e-01 + 7.628000000000e-10 -3.207046174850e-01 + 7.728000000000e-10 -1.875682790354e-01 + 7.828000000000e-10 -2.267703281628e-02 + 7.928000000000e-10 1.226713327530e-01 + 8.028000000000e-10 2.182693863135e-01 + 8.128000000000e-10 2.655996099454e-01 + 8.228000000000e-10 3.020383466326e-01 + 8.328000000000e-10 3.381385294735e-01 + 8.428000000000e-10 3.674717742910e-01 + 8.528000000000e-10 3.750907045119e-01 + 8.628000000000e-10 3.206966644115e-01 + 8.728000000000e-10 1.875773616331e-01 + 8.828000000000e-10 2.266807684955e-02 + 8.928000000000e-10 -1.226628120211e-01 + 9.028000000000e-10 -2.182782381400e-01 + 9.128000000000e-10 -2.655915506047e-01 + 9.228000000000e-10 -3.020469590318e-01 + 9.328000000000e-10 -3.381303351991e-01 + 9.428000000000e-10 -3.674798958779e-01 + 9.528000000000e-10 -3.750829516380e-01 + 9.628000000000e-10 -3.207043265993e-01 + 9.728000000000e-10 -1.875693454762e-01 + 9.828000000000e-10 -2.267594148777e-02 + 9.928000000000e-10 1.226704651969e-01 + 1.000000000000e-09 1.977257563344e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/conditions.yaml new file mode 100644 index 00000000..caab2f97 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 17 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_17 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/CML_core_tb.sch new file mode 100644 index 00000000..db7b143c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/CML_core_tb_18.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/CML_core_tb_18.data new file mode 100644 index 00000000..16422ca1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/CML_core_tb_18.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.213526702696e-01 + 1.728000000000e-10 -1.557909441213e-01 + 1.828000000000e-10 3.476956205809e-02 + 1.928000000000e-10 1.811250151598e-01 + 2.028000000000e-10 2.596166993269e-01 + 2.128000000000e-10 2.853727091731e-01 + 2.228000000000e-10 3.254453264627e-01 + 2.328000000000e-10 3.792799604087e-01 + 2.428000000000e-10 4.176388066249e-01 + 2.528000000000e-10 4.205544301124e-01 + 2.628000000000e-10 3.463528198985e-01 + 2.728000000000e-10 1.792096076204e-01 + 2.828000000000e-10 -1.442396833933e-02 + 2.928000000000e-10 -1.649237711275e-01 + 3.028000000000e-10 -2.471596975948e-01 + 3.128000000000e-10 -2.748735614517e-01 + 3.228000000000e-10 -3.160128767795e-01 + 3.328000000000e-10 -3.707930594343e-01 + 3.428000000000e-10 -4.104823651943e-01 + 3.528000000000e-10 -4.153692056047e-01 + 3.628000000000e-10 -3.427931169871e-01 + 3.728000000000e-10 -1.769552164151e-01 + 3.828000000000e-10 1.590673093360e-02 + 3.928000000000e-10 1.658834812043e-01 + 4.028000000000e-10 2.479775600913e-01 + 4.128000000000e-10 2.756409688001e-01 + 4.228000000000e-10 3.168596600790e-01 + 4.328000000000e-10 3.715133147191e-01 + 4.428000000000e-10 4.111218222953e-01 + 4.528000000000e-10 4.157229971644e-01 + 4.628000000000e-10 3.430019798682e-01 + 4.728000000000e-10 1.769456026445e-01 + 4.828000000000e-10 -1.592886494610e-02 + 4.928000000000e-10 -1.659782283296e-01 + 5.028000000000e-10 -2.479947853664e-01 + 5.128000000000e-10 -2.756931315881e-01 + 5.228000000000e-10 -3.168416717549e-01 + 5.328000000000e-10 -3.715547211919e-01 + 5.428000000000e-10 -4.111034138799e-01 + 5.528000000000e-10 -4.157691346087e-01 + 5.628000000000e-10 -3.429925568898e-01 + 5.728000000000e-10 -1.770024985869e-01 + 5.828000000000e-10 1.592938202906e-02 + 5.928000000000e-10 1.659292038608e-01 + 6.028000000000e-10 2.480043512000e-01 + 6.128000000000e-10 2.756533285421e-01 + 6.228000000000e-10 3.168576585763e-01 + 6.328000000000e-10 3.715156583068e-01 + 6.428000000000e-10 4.111207690964e-01 + 6.528000000000e-10 4.157343976531e-01 + 6.628000000000e-10 3.430135347581e-01 + 6.728000000000e-10 1.769734665185e-01 + 6.828000000000e-10 -1.590652763180e-02 + 6.928000000000e-10 -1.659537152419e-01 + 7.028000000000e-10 -2.479812550746e-01 + 7.128000000000e-10 -2.756768834918e-01 + 7.228000000000e-10 -3.168350969677e-01 + 7.328000000000e-10 -3.715419152243e-01 + 7.428000000000e-10 -4.110983779981e-01 + 7.528000000000e-10 -4.157587194411e-01 + 7.628000000000e-10 -3.429901444601e-01 + 7.728000000000e-10 -1.769973775521e-01 + 7.828000000000e-10 1.592723735432e-02 + 7.928000000000e-10 1.659318535084e-01 + 8.028000000000e-10 2.480017799848e-01 + 8.128000000000e-10 2.756559811492e-01 + 8.228000000000e-10 3.168566227283e-01 + 8.328000000000e-10 3.715195500188e-01 + 8.428000000000e-10 4.111190536097e-01 + 8.528000000000e-10 4.157370668569e-01 + 8.628000000000e-10 3.430103710665e-01 + 8.728000000000e-10 1.769771675859e-01 + 8.828000000000e-10 -1.590770493918e-02 + 8.928000000000e-10 -1.659501582149e-01 + 9.028000000000e-10 -2.479827571068e-01 + 9.128000000000e-10 -2.756738772283e-01 + 9.228000000000e-10 -3.168377001445e-01 + 9.328000000000e-10 -3.715391180409e-01 + 9.428000000000e-10 -4.111007797151e-01 + 9.528000000000e-10 -4.157556639381e-01 + 9.628000000000e-10 -3.429919881202e-01 + 9.728000000000e-10 -1.769955652012e-01 + 9.828000000000e-10 1.592430721908e-02 + 9.928000000000e-10 1.659331850974e-01 + 1.000000000000e-09 2.332140069758e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/conditions.yaml new file mode 100644 index 00000000..02012398 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 18 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_18 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/CML_core_tb.sch new file mode 100644 index 00000000..186750d7 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/CML_core_tb_19.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/CML_core_tb_19.data new file mode 100644 index 00000000..6e384890 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/CML_core_tb_19.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162777317791e-01 + 1.728000000000e-10 -1.528661974147e-01 + 1.828000000000e-10 3.474832458294e-02 + 1.928000000000e-10 1.787124308466e-01 + 2.028000000000e-10 2.559986610902e-01 + 2.128000000000e-10 2.810767408313e-01 + 2.228000000000e-10 3.219404824571e-01 + 2.328000000000e-10 3.760375868322e-01 + 2.428000000000e-10 4.141294975409e-01 + 2.528000000000e-10 4.175370858756e-01 + 2.628000000000e-10 3.443891646085e-01 + 2.728000000000e-10 1.786024667409e-01 + 2.828000000000e-10 -1.272368439666e-02 + 2.928000000000e-10 -1.612661145276e-01 + 3.028000000000e-10 -2.425558656005e-01 + 3.128000000000e-10 -2.696709375544e-01 + 3.228000000000e-10 -3.115976016931e-01 + 3.328000000000e-10 -3.666762080522e-01 + 3.428000000000e-10 -4.062269757432e-01 + 3.528000000000e-10 -4.117682170104e-01 + 3.628000000000e-10 -3.403932990270e-01 + 3.728000000000e-10 -1.760595961534e-01 + 3.828000000000e-10 1.438676142530e-02 + 3.928000000000e-10 1.623380571180e-01 + 4.028000000000e-10 2.434588647096e-01 + 4.128000000000e-10 2.705169080514e-01 + 4.228000000000e-10 3.125303134845e-01 + 4.328000000000e-10 3.674735521527e-01 + 4.428000000000e-10 4.069324770669e-01 + 4.528000000000e-10 4.121668816011e-01 + 4.628000000000e-10 3.406314536055e-01 + 4.728000000000e-10 1.760592839129e-01 + 4.828000000000e-10 -1.440702618479e-02 + 4.928000000000e-10 -1.624387020945e-01 + 5.028000000000e-10 -2.434775787799e-01 + 5.128000000000e-10 -2.705727170369e-01 + 5.228000000000e-10 -3.125119373252e-01 + 5.328000000000e-10 -3.675184828947e-01 + 5.428000000000e-10 -4.069140356329e-01 + 5.528000000000e-10 -4.122173977207e-01 + 5.628000000000e-10 -3.406230488723e-01 + 5.728000000000e-10 -1.761225643375e-01 + 5.828000000000e-10 1.440482600394e-02 + 5.928000000000e-10 1.623840500109e-01 + 6.028000000000e-10 2.434858819416e-01 + 6.128000000000e-10 2.705285901327e-01 + 6.228000000000e-10 3.125279242462e-01 + 6.328000000000e-10 3.674758375852e-01 + 6.428000000000e-10 4.069313048189e-01 + 6.528000000000e-10 4.121794941223e-01 + 6.628000000000e-10 3.406442721772e-01 + 6.728000000000e-10 1.760913923029e-01 + 6.828000000000e-10 -1.438048626859e-02 + 6.928000000000e-10 -1.624102913298e-01 + 7.028000000000e-10 -2.434611919520e-01 + 7.128000000000e-10 -2.705537859875e-01 + 7.228000000000e-10 -3.125040211699e-01 + 7.328000000000e-10 -3.675038904367e-01 + 7.428000000000e-10 -4.069074652851e-01 + 7.528000000000e-10 -4.122054838885e-01 + 7.628000000000e-10 -3.406192567768e-01 + 7.728000000000e-10 -1.761170868219e-01 + 7.828000000000e-10 1.440247036537e-02 + 7.928000000000e-10 1.623867436405e-01 + 8.028000000000e-10 2.434830143217e-01 + 8.128000000000e-10 2.705312548291e-01 + 8.228000000000e-10 3.125271394700e-01 + 8.328000000000e-10 3.674800931307e-01 + 8.428000000000e-10 4.069295144266e-01 + 8.528000000000e-10 4.121823557439e-01 + 8.628000000000e-10 3.406407407456e-01 + 8.728000000000e-10 1.760956573916e-01 + 8.828000000000e-10 -1.438135361500e-02 + 8.928000000000e-10 -1.624062315135e-01 + 9.028000000000e-10 -2.434625084707e-01 + 9.128000000000e-10 -2.705503455528e-01 + 9.228000000000e-10 -3.125068466958e-01 + 9.328000000000e-10 -3.675009271833e-01 + 9.428000000000e-10 -4.069098943042e-01 + 9.528000000000e-10 -4.122022218921e-01 + 9.628000000000e-10 -3.406210058100e-01 + 9.728000000000e-10 -1.761154015725e-01 + 9.828000000000e-10 1.439913133121e-02 + 9.928000000000e-10 1.623879640093e-01 + 1.000000000000e-09 2.290402036537e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/conditions.yaml new file mode 100644 index 00000000..7bd19f05 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 19 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_19 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/CML_core_tb.sch new file mode 100644 index 00000000..0ec0aa03 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/CML_core_tb_20.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/CML_core_tb_20.data new file mode 100644 index 00000000..3dfcf241 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/CML_core_tb_20.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.365386572536e-01 + 1.728000000000e-10 -1.657072094068e-01 + 1.828000000000e-10 3.099865584261e-02 + 1.928000000000e-10 1.820426436768e-01 + 2.028000000000e-10 2.627018214462e-01 + 2.128000000000e-10 2.893736945719e-01 + 2.228000000000e-10 3.287984169352e-01 + 2.328000000000e-10 3.833334317825e-01 + 2.428000000000e-10 4.238785365972e-01 + 2.528000000000e-10 4.280322768716e-01 + 2.628000000000e-10 3.532409470363e-01 + 2.728000000000e-10 1.834641899168e-01 + 2.828000000000e-10 -1.474496205711e-02 + 2.928000000000e-10 -1.691349612478e-01 + 3.028000000000e-10 -2.530204867896e-01 + 3.128000000000e-10 -2.814070764654e-01 + 3.228000000000e-10 -3.218416847899e-01 + 3.328000000000e-10 -3.771799136100e-01 + 3.428000000000e-10 -4.187055626636e-01 + 3.528000000000e-10 -4.243036771430e-01 + 3.628000000000e-10 -3.506062035467e-01 + 3.728000000000e-10 -1.816763297909e-01 + 3.828000000000e-10 1.601938741723e-02 + 3.928000000000e-10 1.700087907901e-01 + 4.028000000000e-10 2.537596951165e-01 + 4.128000000000e-10 2.820887501770e-01 + 4.228000000000e-10 3.225625541805e-01 + 4.328000000000e-10 3.777928583784e-01 + 4.428000000000e-10 4.192485534625e-01 + 4.528000000000e-10 4.246080285894e-01 + 4.628000000000e-10 3.507916132015e-01 + 4.728000000000e-10 1.816929452641e-01 + 4.828000000000e-10 -1.601075067965e-02 + 4.928000000000e-10 -1.700562644838e-01 + 5.028000000000e-10 -2.537513990380e-01 + 5.128000000000e-10 -2.821086741965e-01 + 5.228000000000e-10 -3.225309737549e-01 + 5.328000000000e-10 -3.778081660132e-01 + 5.428000000000e-10 -4.192196231589e-01 + 5.528000000000e-10 -4.246325132019e-01 + 5.628000000000e-10 -3.507765562578e-01 + 5.728000000000e-10 -1.817315603141e-01 + 5.828000000000e-10 1.601468821266e-02 + 5.928000000000e-10 1.700220210141e-01 + 6.028000000000e-10 2.537612841477e-01 + 6.128000000000e-10 2.820810469197e-01 + 6.228000000000e-10 3.225454957468e-01 + 6.328000000000e-10 3.777800822765e-01 + 6.428000000000e-10 4.192350742948e-01 + 6.528000000000e-10 4.246071005326e-01 + 6.628000000000e-10 3.507940665347e-01 + 6.728000000000e-10 1.817094337521e-01 + 6.828000000000e-10 -1.599736953115e-02 + 6.928000000000e-10 -1.700405869499e-01 + 7.028000000000e-10 -2.537437685408e-01 + 7.128000000000e-10 -2.820988428465e-01 + 7.228000000000e-10 -3.225283133162e-01 + 7.328000000000e-10 -3.778004844844e-01 + 7.428000000000e-10 -4.192180216890e-01 + 7.528000000000e-10 -4.246257635725e-01 + 7.628000000000e-10 -3.507760422929e-01 + 7.728000000000e-10 -1.817278922025e-01 + 7.828000000000e-10 1.601285231965e-02 + 7.928000000000e-10 1.700238629540e-01 + 8.028000000000e-10 2.537592487741e-01 + 8.128000000000e-10 2.820829438407e-01 + 8.228000000000e-10 3.225445511573e-01 + 8.328000000000e-10 3.777829985044e-01 + 8.428000000000e-10 4.192337708379e-01 + 8.528000000000e-10 4.246090234999e-01 + 8.628000000000e-10 3.507916632731e-01 + 8.728000000000e-10 1.817122417436e-01 + 8.828000000000e-10 -1.599824136343e-02 + 8.928000000000e-10 -1.700377849177e-01 + 9.028000000000e-10 -2.537449127629e-01 + 9.128000000000e-10 -2.820965585668e-01 + 9.228000000000e-10 -3.225302446360e-01 + 9.328000000000e-10 -3.777982010874e-01 + 9.428000000000e-10 -4.192199753705e-01 + 9.528000000000e-10 -4.246232587341e-01 + 9.628000000000e-10 -3.507775800865e-01 + 9.728000000000e-10 -1.817263367247e-01 + 9.828000000000e-10 1.601066647660e-02 + 9.928000000000e-10 1.700248857455e-01 + 1.000000000000e-09 2.385375784000e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/conditions.yaml new file mode 100644 index 00000000..d93cfdf6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 20 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_20 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/CML_core_tb.sch new file mode 100644 index 00000000..18b81367 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/CML_core_tb_21.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/CML_core_tb_21.data new file mode 100644 index 00000000..86f9b023 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/CML_core_tb_21.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.747912795524e-01 + 1.728000000000e-10 -1.327955908449e-01 + 1.828000000000e-10 3.931332790349e-02 + 1.928000000000e-10 1.782957289495e-01 + 2.028000000000e-10 2.573194188668e-01 + 2.128000000000e-10 2.870254911902e-01 + 2.228000000000e-10 3.228650321442e-01 + 2.328000000000e-10 3.690575149088e-01 + 2.428000000000e-10 4.023791308175e-01 + 2.528000000000e-10 4.034409994944e-01 + 2.628000000000e-10 3.332295993533e-01 + 2.728000000000e-10 1.767123870243e-01 + 2.828000000000e-10 -7.574880255958e-03 + 2.928000000000e-10 -1.550892096227e-01 + 3.028000000000e-10 -2.394679486139e-01 + 3.128000000000e-10 -2.715465054757e-01 + 3.228000000000e-10 -3.085580168164e-01 + 3.328000000000e-10 -3.560821219044e-01 + 3.428000000000e-10 -3.914831036325e-01 + 3.528000000000e-10 -3.956717314322e-01 + 3.628000000000e-10 -3.285929470428e-01 + 3.728000000000e-10 -1.747908753666e-01 + 3.828000000000e-10 7.882784627431e-03 + 3.928000000000e-10 1.545893087045e-01 + 4.028000000000e-10 2.389887597051e-01 + 4.128000000000e-10 2.712307710628e-01 + 4.228000000000e-10 3.085047043395e-01 + 4.328000000000e-10 3.559448484744e-01 + 4.428000000000e-10 3.913507819782e-01 + 4.528000000000e-10 3.953547803018e-01 + 4.628000000000e-10 3.282585464854e-01 + 4.728000000000e-10 1.743078825018e-01 + 4.828000000000e-10 -8.291328068348e-03 + 4.928000000000e-10 -1.550293895867e-01 + 5.028000000000e-10 -2.392804293874e-01 + 5.128000000000e-10 -2.715405217782e-01 + 5.228000000000e-10 -3.087067361985e-01 + 5.328000000000e-10 -3.562070457914e-01 + 5.428000000000e-10 -3.915132320474e-01 + 5.528000000000e-10 -3.955548280332e-01 + 5.628000000000e-10 -3.283427048941e-01 + 5.728000000000e-10 -1.744282326244e-01 + 5.828000000000e-10 8.270645751064e-03 + 5.928000000000e-10 1.549582711486e-01 + 6.028000000000e-10 2.392860039329e-01 + 6.128000000000e-10 2.714820836214e-01 + 6.228000000000e-10 3.087161022039e-01 + 6.328000000000e-10 3.561494137047e-01 + 6.428000000000e-10 3.915273490759e-01 + 6.528000000000e-10 3.955079501007e-01 + 6.628000000000e-10 3.283677191723e-01 + 6.728000000000e-10 1.743944727908e-01 + 6.828000000000e-10 -8.238033211244e-03 + 6.928000000000e-10 -1.549849820320e-01 + 7.028000000000e-10 -2.392533741503e-01 + 7.128000000000e-10 -2.715088112944e-01 + 7.228000000000e-10 -3.086845279612e-01 + 7.328000000000e-10 -3.561786907982e-01 + 7.428000000000e-10 -3.914967682891e-01 + 7.528000000000e-10 -3.955360247734e-01 + 7.628000000000e-10 -3.283379458960e-01 + 7.728000000000e-10 -1.744219452106e-01 + 7.828000000000e-10 8.266285029230e-03 + 7.928000000000e-10 1.549592969714e-01 + 8.028000000000e-10 2.392805186707e-01 + 8.128000000000e-10 2.714837558368e-01 + 8.228000000000e-10 3.087120651005e-01 + 8.328000000000e-10 3.561520690508e-01 + 8.428000000000e-10 3.915233230940e-01 + 8.528000000000e-10 3.955100606400e-01 + 8.628000000000e-10 3.283632493206e-01 + 8.728000000000e-10 1.743968536756e-01 + 8.828000000000e-10 -8.241845610385e-03 + 8.928000000000e-10 -1.549825747228e-01 + 9.028000000000e-10 -2.392568734068e-01 + 9.128000000000e-10 -2.715063119250e-01 + 9.228000000000e-10 -3.086881712182e-01 + 9.328000000000e-10 -3.561760305782e-01 + 9.428000000000e-10 -3.915002731039e-01 + 9.528000000000e-10 -3.955331724158e-01 + 9.628000000000e-10 -3.283409163093e-01 + 9.728000000000e-10 -1.744193777973e-01 + 9.828000000000e-10 8.263272108901e-03 + 9.928000000000e-10 1.549616575981e-01 + 1.000000000000e-09 2.229820050464e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/conditions.yaml new file mode 100644 index 00000000..2779604e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 21 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_21 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/CML_core_tb.sch new file mode 100644 index 00000000..2006b916 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/CML_core_tb_22.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/CML_core_tb_22.data new file mode 100644 index 00000000..ef0e6c8e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/CML_core_tb_22.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.701426652476e-01 + 1.728000000000e-10 -1.295079168872e-01 + 1.828000000000e-10 4.028305902420e-02 + 1.928000000000e-10 1.769160181627e-01 + 2.028000000000e-10 2.543038782058e-01 + 2.128000000000e-10 2.828787064062e-01 + 2.228000000000e-10 3.193333275112e-01 + 2.328000000000e-10 3.660596632426e-01 + 2.428000000000e-10 3.993599084345e-01 + 2.528000000000e-10 4.007883413226e-01 + 2.628000000000e-10 3.312419521143e-01 + 2.728000000000e-10 1.754810620333e-01 + 2.828000000000e-10 -7.142746942805e-03 + 2.928000000000e-10 -1.527779354444e-01 + 3.028000000000e-10 -2.358001938178e-01 + 3.128000000000e-10 -2.668485168237e-01 + 3.228000000000e-10 -3.044746718514e-01 + 3.328000000000e-10 -3.525545062341e-01 + 3.428000000000e-10 -3.880254364838e-01 + 3.528000000000e-10 -3.926522183008e-01 + 3.628000000000e-10 -3.262954780243e-01 + 3.728000000000e-10 -1.733443838482e-01 + 3.828000000000e-10 7.573790689709e-03 + 3.928000000000e-10 1.523487073311e-01 + 4.028000000000e-10 2.353677758316e-01 + 4.128000000000e-10 2.665695097895e-01 + 4.228000000000e-10 3.044490522149e-01 + 4.328000000000e-10 3.524353166192e-01 + 4.428000000000e-10 3.879041587545e-01 + 4.528000000000e-10 3.923389296672e-01 + 4.628000000000e-10 3.259554596391e-01 + 4.728000000000e-10 1.728458619818e-01 + 4.828000000000e-10 -8.002573892585e-03 + 4.928000000000e-10 -1.528088090159e-01 + 5.028000000000e-10 -2.356747724378e-01 + 5.128000000000e-10 -2.668925685814e-01 + 5.228000000000e-10 -3.046638401901e-01 + 5.328000000000e-10 -3.527112223433e-01 + 5.428000000000e-10 -3.880786380631e-01 + 5.528000000000e-10 -3.925506229445e-01 + 5.628000000000e-10 -3.260495799326e-01 + 5.728000000000e-10 -1.729761662154e-01 + 5.828000000000e-10 7.974498187451e-03 + 5.928000000000e-10 1.527311696558e-01 + 6.028000000000e-10 2.356760074325e-01 + 6.128000000000e-10 2.668297167568e-01 + 6.228000000000e-10 3.046702367069e-01 + 6.328000000000e-10 3.526500635637e-01 + 6.428000000000e-10 3.880902250634e-01 + 6.528000000000e-10 3.925010528185e-01 + 6.628000000000e-10 3.260730653917e-01 + 6.728000000000e-10 1.729410953112e-01 + 6.828000000000e-10 -7.941970684065e-03 + 6.928000000000e-10 -1.527585341072e-01 + 7.028000000000e-10 -2.356430884825e-01 + 7.128000000000e-10 -2.668569558480e-01 + 7.228000000000e-10 -3.046384985761e-01 + 7.328000000000e-10 -3.526798341051e-01 + 7.428000000000e-10 -3.880593641809e-01 + 7.528000000000e-10 -3.925295324367e-01 + 7.628000000000e-10 -3.260427874257e-01 + 7.728000000000e-10 -1.729689796013e-01 + 7.828000000000e-10 7.970639231343e-03 + 7.928000000000e-10 1.527324506408e-01 + 8.028000000000e-10 2.356706370408e-01 + 8.128000000000e-10 2.668314718812e-01 + 8.228000000000e-10 3.046665550415e-01 + 8.328000000000e-10 3.526529348742e-01 + 8.428000000000e-10 3.880863283995e-01 + 8.528000000000e-10 3.925032166540e-01 + 8.628000000000e-10 3.260684590033e-01 + 8.728000000000e-10 1.729436324779e-01 + 8.828000000000e-10 -7.945691115533e-03 + 8.928000000000e-10 -1.527560420249e-01 + 9.028000000000e-10 -2.356465048672e-01 + 9.128000000000e-10 -2.668543449819e-01 + 9.228000000000e-10 -3.046422495200e-01 + 9.328000000000e-10 -3.526772110923e-01 + 9.428000000000e-10 -3.880628732866e-01 + 9.528000000000e-10 -3.925266759429e-01 + 9.628000000000e-10 -3.260456785141e-01 + 9.728000000000e-10 -1.729665660062e-01 + 9.828000000000e-10 7.967487161613e-03 + 9.928000000000e-10 1.527347010769e-01 + 1.000000000000e-09 2.198236907112e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/conditions.yaml new file mode 100644 index 00000000..0119210d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 22 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_22 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/CML_core_tb.sch new file mode 100644 index 00000000..67aff21a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/CML_core_tb_23.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/CML_core_tb_23.data new file mode 100644 index 00000000..7b2e7ab2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/CML_core_tb_23.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.957054612407e-01 + 1.728000000000e-10 -1.475216919691e-01 + 1.828000000000e-10 3.196996632833e-02 + 1.928000000000e-10 1.773696584526e-01 + 2.028000000000e-10 2.602670445343e-01 + 2.128000000000e-10 2.919684489720e-01 + 2.228000000000e-10 3.273690981683e-01 + 2.328000000000e-10 3.736661732429e-01 + 2.428000000000e-10 4.086769482098e-01 + 2.528000000000e-10 4.113258498473e-01 + 2.628000000000e-10 3.414272197123e-01 + 2.728000000000e-10 1.833836328070e-01 + 2.828000000000e-10 -4.501363849837e-03 + 2.928000000000e-10 -1.562318489881e-01 + 3.028000000000e-10 -2.435570784568e-01 + 3.128000000000e-10 -2.775386220390e-01 + 3.228000000000e-10 -3.142878056355e-01 + 3.328000000000e-10 -3.618442790176e-01 + 3.428000000000e-10 -3.986028140213e-01 + 3.528000000000e-10 -4.040381865127e-01 + 3.628000000000e-10 -3.369104214062e-01 + 3.728000000000e-10 -1.811830752063e-01 + 3.828000000000e-10 5.355128083595e-03 + 3.928000000000e-10 1.563630270676e-01 + 4.028000000000e-10 2.436522664355e-01 + 4.128000000000e-10 2.777202130414e-01 + 4.228000000000e-10 3.146716935396e-01 + 4.328000000000e-10 3.621309165835e-01 + 4.428000000000e-10 3.988648293319e-01 + 4.528000000000e-10 4.040567761896e-01 + 4.628000000000e-10 3.368362274946e-01 + 4.728000000000e-10 1.809052635954e-01 + 4.828000000000e-10 -5.606347307292e-03 + 4.928000000000e-10 -1.566747533637e-01 + 5.028000000000e-10 -2.438438929936e-01 + 5.128000000000e-10 -2.779365198916e-01 + 5.228000000000e-10 -3.147868656031e-01 + 5.328000000000e-10 -3.623069078218e-01 + 5.428000000000e-10 -3.989546307961e-01 + 5.528000000000e-10 -4.041975741324e-01 + 5.628000000000e-10 -3.368831845243e-01 + 5.728000000000e-10 -1.810020824460e-01 + 5.828000000000e-10 5.593858826262e-03 + 5.928000000000e-10 1.566090374935e-01 + 6.028000000000e-10 2.438493522755e-01 + 6.128000000000e-10 2.778818285943e-01 + 6.228000000000e-10 3.147972496077e-01 + 6.328000000000e-10 3.622530927659e-01 + 6.428000000000e-10 3.989689895438e-01 + 6.528000000000e-10 4.041528360847e-01 + 6.628000000000e-10 3.369065350765e-01 + 6.728000000000e-10 1.809679655825e-01 + 6.828000000000e-10 -5.565139497590e-03 + 6.928000000000e-10 -1.566366178225e-01 + 7.028000000000e-10 -2.438204188033e-01 + 7.128000000000e-10 -2.779089356335e-01 + 7.228000000000e-10 -3.147686522157e-01 + 7.328000000000e-10 -3.622826637804e-01 + 7.428000000000e-10 -3.989411843085e-01 + 7.528000000000e-10 -4.041807678845e-01 + 7.628000000000e-10 -3.368790616195e-01 + 7.728000000000e-10 -1.809947630224e-01 + 7.828000000000e-10 5.591512634984e-03 + 7.928000000000e-10 1.566120178189e-01 + 8.028000000000e-10 2.438458933358e-01 + 8.128000000000e-10 2.778849719194e-01 + 8.228000000000e-10 3.147945034671e-01 + 8.328000000000e-10 3.622568751046e-01 + 8.428000000000e-10 3.989662140554e-01 + 8.528000000000e-10 4.041558823701e-01 + 8.628000000000e-10 3.369030769235e-01 + 8.728000000000e-10 1.809706945647e-01 + 8.828000000000e-10 -5.568483515763e-03 + 8.928000000000e-10 -1.566340912711e-01 + 9.028000000000e-10 -2.438236181184e-01 + 9.128000000000e-10 -2.779064153414e-01 + 9.228000000000e-10 -3.147718720666e-01 + 9.328000000000e-10 -3.622798572716e-01 + 9.428000000000e-10 -3.989444036153e-01 + 9.528000000000e-10 -4.041778978449e-01 + 9.628000000000e-10 -3.368819513246e-01 + 9.728000000000e-10 -1.809921012276e-01 + 9.828000000000e-10 5.588724287086e-03 + 9.928000000000e-10 1.566143682128e-01 + 1.000000000000e-09 2.267750497136e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/conditions.yaml new file mode 100644 index 00000000..b643cd45 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 23 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_23 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/CML_core_tb.sch new file mode 100644 index 00000000..d0cf47f8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/CML_core_tb_24.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/CML_core_tb_24.data new file mode 100644 index 00000000..a01deb89 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/CML_core_tb_24.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.908985659112e-01 + 1.728000000000e-10 -9.049079150817e-02 + 1.828000000000e-10 3.945873683219e-02 + 1.928000000000e-10 1.521437177417e-01 + 2.028000000000e-10 2.220068772324e-01 + 2.128000000000e-10 2.535092334052e-01 + 2.228000000000e-10 2.861973397174e-01 + 2.328000000000e-10 3.239843013312e-01 + 2.428000000000e-10 3.520113017607e-01 + 2.528000000000e-10 3.540468115658e-01 + 2.628000000000e-10 2.949447709683e-01 + 2.728000000000e-10 1.587983397866e-01 + 2.828000000000e-10 -6.865354773069e-03 + 2.928000000000e-10 -1.448078480843e-01 + 3.028000000000e-10 -2.275605338030e-01 + 3.128000000000e-10 -2.625604064747e-01 + 3.228000000000e-10 -2.958552078644e-01 + 3.328000000000e-10 -3.351711406638e-01 + 3.428000000000e-10 -3.644984224381e-01 + 3.528000000000e-10 -3.669950471097e-01 + 3.628000000000e-10 -3.072796408874e-01 + 3.728000000000e-10 -1.699866077827e-01 + 3.828000000000e-10 -2.842045316933e-03 + 3.928000000000e-10 1.365086891956e-01 + 4.028000000000e-10 2.207869920157e-01 + 4.128000000000e-10 2.567713461579e-01 + 4.228000000000e-10 2.907030026757e-01 + 4.328000000000e-10 3.302687598301e-01 + 4.428000000000e-10 3.600803190405e-01 + 4.528000000000e-10 3.632331450943e-01 + 4.628000000000e-10 3.045482678871e-01 + 4.728000000000e-10 1.682698274629e-01 + 4.828000000000e-10 2.058504292284e-03 + 4.928000000000e-10 -1.367871396964e-01 + 5.028000000000e-10 -2.207717990252e-01 + 5.128000000000e-10 -2.567684885934e-01 + 5.228000000000e-10 -2.906651825463e-01 + 5.328000000000e-10 -3.302494358660e-01 + 5.428000000000e-10 -3.599712284157e-01 + 5.528000000000e-10 -3.631239508150e-01 + 5.628000000000e-10 -3.043584109358e-01 + 5.728000000000e-10 -1.680958385636e-01 + 5.828000000000e-10 -1.834034512727e-03 + 5.928000000000e-10 1.369613450439e-01 + 6.028000000000e-10 2.209618957221e-01 + 6.128000000000e-10 2.568952536478e-01 + 6.228000000000e-10 2.908171185353e-01 + 6.328000000000e-10 3.303549214919e-01 + 6.428000000000e-10 3.601082390759e-01 + 6.528000000000e-10 3.632059905221e-01 + 6.628000000000e-10 3.044557238628e-01 + 6.728000000000e-10 1.681292777859e-01 + 6.828000000000e-10 1.882442241730e-03 + 6.928000000000e-10 -1.369637862409e-01 + 7.028000000000e-10 -2.209363992802e-01 + 7.128000000000e-10 -2.569065829626e-01 + 7.228000000000e-10 -2.907936706940e-01 + 7.328000000000e-10 -3.303682701482e-01 + 7.428000000000e-10 -3.600879594395e-01 + 7.528000000000e-10 -3.632220959958e-01 + 7.628000000000e-10 -3.044401007882e-01 + 7.728000000000e-10 -1.681486407544e-01 + 7.828000000000e-10 -1.870004957548e-03 + 7.928000000000e-10 1.369437070838e-01 + 8.028000000000e-10 2.209481957039e-01 + 8.128000000000e-10 2.568879030180e-01 + 8.228000000000e-10 2.908064848389e-01 + 8.328000000000e-10 3.303493303219e-01 + 8.428000000000e-10 3.601006147126e-01 + 8.528000000000e-10 3.632041339109e-01 + 8.628000000000e-10 3.044528281549e-01 + 8.728000000000e-10 1.681322760827e-01 + 8.828000000000e-10 1.883536763259e-03 + 8.928000000000e-10 -1.369582535540e-01 + 9.028000000000e-10 -2.209346296842e-01 + 9.128000000000e-10 -2.569016830366e-01 + 9.228000000000e-10 -2.907925936742e-01 + 9.328000000000e-10 -3.303636164667e-01 + 9.428000000000e-10 -3.600871302257e-01 + 9.528000000000e-10 -3.632178492939e-01 + 9.628000000000e-10 -3.044398392752e-01 + 9.728000000000e-10 -1.681454261603e-01 + 9.828000000000e-10 -1.870628705438e-03 + 9.928000000000e-10 1.369459433541e-01 + 1.000000000000e-09 2.037746084522e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/conditions.yaml new file mode 100644 index 00000000..732b12b0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 24 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_24 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/CML_core_tb.sch new file mode 100644 index 00000000..bbf3946c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/CML_core_tb_25.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/CML_core_tb_25.data new file mode 100644 index 00000000..182746dc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/CML_core_tb_25.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.878715792581e-01 + 1.728000000000e-10 -8.812036120597e-02 + 1.828000000000e-10 4.046526586524e-02 + 1.928000000000e-10 1.515705626527e-01 + 2.028000000000e-10 2.200566198342e-01 + 2.128000000000e-10 2.503583455541e-01 + 2.228000000000e-10 2.832914205797e-01 + 2.328000000000e-10 3.216696186231e-01 + 2.428000000000e-10 3.500303926946e-01 + 2.528000000000e-10 3.524815741411e-01 + 2.628000000000e-10 2.936462106779e-01 + 2.728000000000e-10 1.576219496242e-01 + 2.828000000000e-10 -7.121462127754e-03 + 2.928000000000e-10 -1.436071598858e-01 + 3.028000000000e-10 -2.249496922999e-01 + 3.128000000000e-10 -2.586592240194e-01 + 3.228000000000e-10 -2.922419569702e-01 + 3.328000000000e-10 -3.321983211521e-01 + 3.428000000000e-10 -3.618684381611e-01 + 3.528000000000e-10 -3.648249016007e-01 + 3.628000000000e-10 -3.055379959953e-01 + 3.728000000000e-10 -1.686105488568e-01 + 3.828000000000e-10 -2.582643774162e-03 + 3.928000000000e-10 1.352182085241e-01 + 4.028000000000e-10 2.180702244722e-01 + 4.128000000000e-10 2.527783389641e-01 + 4.228000000000e-10 2.869845016096e-01 + 4.328000000000e-10 3.271697550530e-01 + 4.428000000000e-10 3.573213651505e-01 + 4.528000000000e-10 3.609341509143e-01 + 4.628000000000e-10 3.026708512688e-01 + 4.728000000000e-10 1.667591862946e-01 + 4.828000000000e-10 1.676053368052e-03 + 4.928000000000e-10 -1.356064331336e-01 + 5.028000000000e-10 -2.181494577446e-01 + 5.128000000000e-10 -2.528581012316e-01 + 5.228000000000e-10 -2.870203472690e-01 + 5.328000000000e-10 -3.272198972187e-01 + 5.428000000000e-10 -3.572767955086e-01 + 5.528000000000e-10 -3.608816832152e-01 + 5.628000000000e-10 -3.025243774497e-01 + 5.728000000000e-10 -1.666129730216e-01 + 5.828000000000e-10 -1.465204057357e-03 + 5.928000000000e-10 1.357749931272e-01 + 6.028000000000e-10 2.183376260095e-01 + 6.128000000000e-10 2.529831758691e-01 + 6.228000000000e-10 2.871716452249e-01 + 6.328000000000e-10 3.273254918206e-01 + 6.428000000000e-10 3.574148326524e-01 + 6.528000000000e-10 3.609652866209e-01 + 6.628000000000e-10 3.026246199120e-01 + 6.728000000000e-10 1.666502220733e-01 + 6.828000000000e-10 1.518129196282e-03 + 6.928000000000e-10 -1.357732099566e-01 + 7.028000000000e-10 -2.183080403425e-01 + 7.128000000000e-10 -2.529912058397e-01 + 7.228000000000e-10 -2.871450109118e-01 + 7.328000000000e-10 -3.273360198503e-01 + 7.428000000000e-10 -3.573916245859e-01 + 7.528000000000e-10 -3.609790664977e-01 + 7.628000000000e-10 -3.026068066478e-01 + 7.728000000000e-10 -1.666683959674e-01 + 7.828000000000e-10 -1.504711775466e-03 + 7.928000000000e-10 1.357534602326e-01 + 8.028000000000e-10 2.183202914392e-01 + 8.128000000000e-10 2.529726082081e-01 + 8.228000000000e-10 2.871582302084e-01 + 8.328000000000e-10 3.273171284192e-01 + 8.428000000000e-10 3.574045685766e-01 + 8.528000000000e-10 3.609610284998e-01 + 8.628000000000e-10 3.026196909841e-01 + 8.728000000000e-10 1.666518528053e-01 + 8.828000000000e-10 1.518315117290e-03 + 8.928000000000e-10 -1.357682747942e-01 + 9.028000000000e-10 -2.183066580359e-01 + 9.128000000000e-10 -2.529866332266e-01 + 9.228000000000e-10 -2.871442829871e-01 + 9.328000000000e-10 -3.273316607928e-01 + 9.428000000000e-10 -3.573910212469e-01 + 9.528000000000e-10 -3.609749965926e-01 + 9.628000000000e-10 -3.026065830591e-01 + 9.728000000000e-10 -1.666652414066e-01 + 9.828000000000e-10 -1.505286118034e-03 + 9.928000000000e-10 1.357557668798e-01 + 1.000000000000e-09 2.016242513907e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/conditions.yaml new file mode 100644 index 00000000..9845abaf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 25 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_25 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/CML_core_tb.sch new file mode 100644 index 00000000..b7b8186b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/CML_core_tb_26.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/CML_core_tb_26.data new file mode 100644 index 00000000..c21b093d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/CML_core_tb_26.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.135873679018e-01 + 1.728000000000e-10 -1.054229355639e-01 + 1.828000000000e-10 3.485798650969e-02 + 1.928000000000e-10 1.569675139767e-01 + 2.028000000000e-10 2.330635404696e-01 + 2.128000000000e-10 2.680443549179e-01 + 2.228000000000e-10 3.014044829899e-01 + 2.328000000000e-10 3.394080314353e-01 + 2.428000000000e-10 3.679529618424e-01 + 2.528000000000e-10 3.700593040123e-01 + 2.628000000000e-10 3.097824620429e-01 + 2.728000000000e-10 1.706514675999e-01 + 2.828000000000e-10 3.558070014658e-04 + 2.928000000000e-10 -1.428409974599e-01 + 3.028000000000e-10 -2.298289579719e-01 + 3.128000000000e-10 -2.678794741753e-01 + 3.228000000000e-10 -3.017454056957e-01 + 3.328000000000e-10 -3.410620518407e-01 + 3.428000000000e-10 -3.712405389398e-01 + 3.528000000000e-10 -3.749327973471e-01 + 3.628000000000e-10 -3.157484466493e-01 + 3.728000000000e-10 -1.773087198166e-01 + 3.828000000000e-10 -7.070252178339e-03 + 3.928000000000e-10 1.364462941621e-01 + 4.028000000000e-10 2.243241068758e-01 + 4.128000000000e-10 2.631279769125e-01 + 4.228000000000e-10 2.976097246349e-01 + 4.328000000000e-10 3.371159716785e-01 + 4.428000000000e-10 3.676405775058e-01 + 4.528000000000e-10 3.717787254056e-01 + 4.628000000000e-10 3.133854979421e-01 + 4.728000000000e-10 1.756870158595e-01 + 4.828000000000e-10 6.171257018760e-03 + 4.928000000000e-10 -1.369680995621e-01 + 5.028000000000e-10 -2.245781248931e-01 + 5.128000000000e-10 -2.633829468620e-01 + 5.228000000000e-10 -2.978042748481e-01 + 5.328000000000e-10 -3.373348877854e-01 + 5.428000000000e-10 -3.677584906255e-01 + 5.528000000000e-10 -3.718812762918e-01 + 5.628000000000e-10 -3.133649557524e-01 + 5.728000000000e-10 -1.756479312047e-01 + 5.828000000000e-10 -6.040608056278e-03 + 5.928000000000e-10 1.370690415770e-01 + 6.028000000000e-10 2.247181767783e-01 + 6.128000000000e-10 2.634617265965e-01 + 6.228000000000e-10 2.979157296699e-01 + 6.328000000000e-10 3.373958940353e-01 + 6.428000000000e-10 3.678612954525e-01 + 6.528000000000e-10 3.719309221475e-01 + 6.628000000000e-10 3.134447453066e-01 + 6.728000000000e-10 1.756687688086e-01 + 6.828000000000e-10 6.090200135509e-03 + 6.928000000000e-10 -1.370702307281e-01 + 7.028000000000e-10 -2.246847420648e-01 + 7.128000000000e-10 -2.634701196121e-01 + 7.228000000000e-10 -2.978849158722e-01 + 7.328000000000e-10 -3.374068878437e-01 + 7.428000000000e-10 -3.678336110941e-01 + 7.528000000000e-10 -3.719446503824e-01 + 7.628000000000e-10 -3.134227431793e-01 + 7.728000000000e-10 -1.756868885858e-01 + 7.828000000000e-10 -6.072676723321e-03 + 7.928000000000e-10 1.370503070743e-01 + 8.028000000000e-10 2.247004966695e-01 + 8.128000000000e-10 2.634509722982e-01 + 8.228000000000e-10 2.979013793804e-01 + 8.328000000000e-10 3.373870921905e-01 + 8.428000000000e-10 3.678495602861e-01 + 8.528000000000e-10 3.719256264749e-01 + 8.628000000000e-10 3.134381864470e-01 + 8.728000000000e-10 1.756688935561e-01 + 8.828000000000e-10 6.088345643719e-03 + 8.928000000000e-10 -1.370666831053e-01 + 9.028000000000e-10 -2.246851372638e-01 + 9.128000000000e-10 -2.634666121684e-01 + 9.228000000000e-10 -2.978856025968e-01 + 9.328000000000e-10 -3.374033621769e-01 + 9.428000000000e-10 -3.678342837151e-01 + 9.528000000000e-10 -3.719412125322e-01 + 9.628000000000e-10 -3.134235677100e-01 + 9.728000000000e-10 -1.756838495744e-01 + 9.828000000000e-10 -6.073781243164e-03 + 9.928000000000e-10 1.370527135588e-01 + 1.000000000000e-09 2.065229990524e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/conditions.yaml new file mode 100644 index 00000000..dc7ab87e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 26 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/run_26 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/simulation_summary.csv new file mode 100644 index 00000000..6598603d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/simulation_summary.csv @@ -0,0 +1,28 @@ +run,corner,temperature,vdd,time,vo_diff,amplitude +run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.111e-01, -1.870e-01, -3.563e-02, …]",0.382 +run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.099e-01, -1.895e-01, -4.060e-02, …]",0.377 +run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.876e-01, -3.217e-02, …]",0.390 +run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.915e-01, -1.780e-01, -3.803e-02, …]",0.357 +run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.909e-01, -1.806e-01, -4.276e-02, …]",0.353 +run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.959e-01, -1.792e-01, -3.599e-02, …]",0.366 +run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.689e-01, -1.692e-01, -4.423e-02, …]",0.319 +run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.694e-01, -1.722e-01, -4.907e-02, …]",0.315 +run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.723e-01, -1.701e-01, -4.252e-02, …]",0.330 +run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.623e-01, -1.963e-01, -5.713e-03, …]",0.421 +run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.622e-01, -1.984e-01, -1.024e-02, …]",0.418 +run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.669e-01, -1.979e-01, -3.070e-03, …]",0.429 +run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",0.401 +run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.407e-01, -1.880e-01, -9.263e-03, …]",0.398 +run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.446e-01, -1.889e-01, -5.355e-03, …]",0.409 +run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.832e-01, -1.548e-01, 2.955e-03, …]",0.371 +run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.908e-01, -1.609e-01, -2.321e-03, …]",0.368 +run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.858e-01, -1.573e-01, 2.540e-03, …]",0.379 +run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.214e-01, -1.558e-01, 3.477e-02, …]",0.418 +run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.529e-01, 3.475e-02, …]",0.415 +run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.365e-01, -1.657e-01, 3.100e-02, …]",0.426 +run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.748e-01, -1.328e-01, 3.931e-02, …]",0.400 +run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.701e-01, -1.295e-01, 4.028e-02, …]",0.397 +run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.957e-01, -1.475e-01, 3.197e-02, …]",0.408 +run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.909e-01, -9.049e-02, 3.946e-02, …]",0.365 +run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.879e-01, -8.812e-02, 4.047e-02, …]",0.363 +run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.136e-01, -1.054e-01, 3.486e-02, …]",0.373 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/simulation_summary.md new file mode 100644 index 00000000..f9fdc781 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Amplitude/simulation_summary.md @@ -0,0 +1,31 @@ +# Simulation Summary for Amplitude + +| run | corner | temperature | vdd | time | vo_diff | amplitude | +| :-- | -----: | ----------: | --: | ---: | ------: | --------: | +| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.111e-01, -1.870e-01, -3.563e-02, …] | 0.382 | +| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.099e-01, -1.895e-01, -4.060e-02, …] | 0.377 | +| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.876e-01, -3.217e-02, …] | 0.390 | +| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.915e-01, -1.780e-01, -3.803e-02, …] | 0.357 | +| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.909e-01, -1.806e-01, -4.276e-02, …] | 0.353 | +| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.959e-01, -1.792e-01, -3.599e-02, …] | 0.366 | +| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.689e-01, -1.692e-01, -4.423e-02, …] | 0.319 | +| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.694e-01, -1.722e-01, -4.907e-02, …] | 0.315 | +| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.723e-01, -1.701e-01, -4.252e-02, …] | 0.330 | +| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.623e-01, -1.963e-01, -5.713e-03, …] | 0.421 | +| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.622e-01, -1.984e-01, -1.024e-02, …] | 0.418 | +| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.669e-01, -1.979e-01, -3.070e-03, …] | 0.429 | +| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 0.401 | +| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.407e-01, -1.880e-01, -9.263e-03, …] | 0.398 | +| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.446e-01, -1.889e-01, -5.355e-03, …] | 0.409 | +| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.832e-01, -1.548e-01, 2.955e-03, …] | 0.371 | +| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.908e-01, -1.609e-01, -2.321e-03, …] | 0.368 | +| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.858e-01, -1.573e-01, 2.540e-03, …] | 0.379 | +| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.214e-01, -1.558e-01, 3.477e-02, …] | 0.418 | +| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.529e-01, 3.475e-02, …] | 0.415 | +| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.365e-01, -1.657e-01, 3.100e-02, …] | 0.426 | +| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.748e-01, -1.328e-01, 3.931e-02, …] | 0.400 | +| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.701e-01, -1.295e-01, 4.028e-02, …] | 0.397 | +| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.957e-01, -1.475e-01, 3.197e-02, …] | 0.408 | +| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.909e-01, -9.049e-02, 3.946e-02, …] | 0.365 | +| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.879e-01, -8.812e-02, 4.047e-02, …] | 0.363 | +| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.136e-01, -1.054e-01, 3.486e-02, …] | 0.373 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/frequency.png new file mode 100644 index 00000000..e4b0a21a Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/CML_core_tb.sch new file mode 100644 index 00000000..f7566d3a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/CML_core_tb_0.data new file mode 100644 index 00000000..4cb5b399 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.110742996065e-01 + 1.728000000000e-10 -1.869505717284e-01 + 1.828000000000e-10 -3.563037101706e-02 + 1.928000000000e-10 1.056708524540e-01 + 2.028000000000e-10 2.100393804445e-01 + 2.128000000000e-10 2.784249297688e-01 + 2.228000000000e-10 3.224310579067e-01 + 2.328000000000e-10 3.548600651170e-01 + 2.428000000000e-10 3.792482005271e-01 + 2.528000000000e-10 3.740820324036e-01 + 2.628000000000e-10 3.079440308227e-01 + 2.728000000000e-10 1.813826171807e-01 + 2.828000000000e-10 2.923027813912e-02 + 2.928000000000e-10 -1.118282325615e-01 + 3.028000000000e-10 -2.157337068367e-01 + 3.128000000000e-10 -2.829033176767e-01 + 3.228000000000e-10 -3.260714502323e-01 + 3.328000000000e-10 -3.577361248183e-01 + 3.428000000000e-10 -3.819104006606e-01 + 3.528000000000e-10 -3.764730474160e-01 + 3.628000000000e-10 -3.102968359246e-01 + 3.728000000000e-10 -1.832608913655e-01 + 3.828000000000e-10 -3.084931437320e-02 + 3.928000000000e-10 1.106163095990e-01 + 4.028000000000e-10 2.145714971977e-01 + 4.128000000000e-10 2.819937231053e-01 + 4.228000000000e-10 3.251740998910e-01 + 4.328000000000e-10 3.570946969464e-01 + 4.428000000000e-10 3.813004444382e-01 + 4.528000000000e-10 3.761230596147e-01 + 4.628000000000e-10 3.099646053412e-01 + 4.728000000000e-10 1.831473345022e-01 + 4.828000000000e-10 3.069401022130e-02 + 4.928000000000e-10 -1.106258411343e-01 + 5.028000000000e-10 -2.146793601179e-01 + 5.128000000000e-10 -2.820035552799e-01 + 5.228000000000e-10 -3.252909243829e-01 + 5.328000000000e-10 -3.570986338553e-01 + 5.428000000000e-10 -3.813904658256e-01 + 5.528000000000e-10 -3.760889514061e-01 + 5.628000000000e-10 -3.100114096943e-01 + 5.728000000000e-10 -1.830827247194e-01 + 5.828000000000e-10 -3.072480545922e-02 + 5.928000000000e-10 1.106906463094e-01 + 6.028000000000e-10 2.146493837568e-01 + 6.128000000000e-10 2.820610673881e-01 + 6.228000000000e-10 3.252525482967e-01 + 6.328000000000e-10 3.571504708749e-01 + 6.428000000000e-10 3.813516648295e-01 + 6.528000000000e-10 3.761390656738e-01 + 6.628000000000e-10 3.099742259389e-01 + 6.728000000000e-10 1.831331110808e-01 + 6.828000000000e-10 3.068765829312e-02 + 6.928000000000e-10 -1.106445812930e-01 + 7.028000000000e-10 -2.146859050297e-01 + 7.128000000000e-10 -2.820172231683e-01 + 7.228000000000e-10 -3.252905125649e-01 + 7.328000000000e-10 -3.571078709926e-01 + 7.428000000000e-10 -3.813893177320e-01 + 7.528000000000e-10 -3.760986555866e-01 + 7.628000000000e-10 -3.100117776476e-01 + 7.728000000000e-10 -1.830935153198e-01 + 7.828000000000e-10 -3.072484475908e-02 + 7.928000000000e-10 1.106810594907e-01 + 8.028000000000e-10 2.146507312123e-01 + 8.128000000000e-10 2.820530370402e-01 + 8.228000000000e-10 3.252547871433e-01 + 8.328000000000e-10 3.571432636036e-01 + 8.428000000000e-10 3.813547544577e-01 + 8.528000000000e-10 3.761324372121e-01 + 8.628000000000e-10 3.099775475493e-01 + 8.728000000000e-10 1.831274535707e-01 + 8.828000000000e-10 3.069175078476e-02 + 8.928000000000e-10 -1.106491559136e-01 + 9.028000000000e-10 -2.146821655528e-01 + 9.128000000000e-10 -2.820218639330e-01 + 9.228000000000e-10 -3.252864642203e-01 + 9.328000000000e-10 -3.571122611941e-01 + 9.428000000000e-10 -3.813854215351e-01 + 9.528000000000e-10 -3.761024723822e-01 + 9.628000000000e-10 -3.100075395903e-01 + 9.728000000000e-10 -1.830975404653e-01 + 9.828000000000e-10 -3.072097080048e-02 + 9.928000000000e-10 1.106770531472e-01 + 1.000000000000e-09 1.895325033433e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/conditions.yaml new file mode 100644 index 00000000..62a942f3 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_00 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/CML_core_tb.sch new file mode 100644 index 00000000..ce2556fe --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/CML_core_tb_1.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/CML_core_tb_1.data new file mode 100644 index 00000000..2b8492c0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/CML_core_tb_1.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.098686002716e-01 + 1.728000000000e-10 -1.894560696460e-01 + 1.828000000000e-10 -4.059695742871e-02 + 1.928000000000e-10 9.940964501315e-02 + 2.028000000000e-10 2.033133834097e-01 + 2.128000000000e-10 2.719620830710e-01 + 2.228000000000e-10 3.163098950569e-01 + 2.328000000000e-10 3.491513279687e-01 + 2.428000000000e-10 3.741332087119e-01 + 2.528000000000e-10 3.700254590965e-01 + 2.628000000000e-10 3.062168938694e-01 + 2.728000000000e-10 1.827341653261e-01 + 2.828000000000e-10 3.280764574542e-02 + 2.928000000000e-10 -1.069769977212e-01 + 3.028000000000e-10 -2.102924295592e-01 + 3.128000000000e-10 -2.774748738503e-01 + 3.228000000000e-10 -3.207751929169e-01 + 3.328000000000e-10 -3.527202709264e-01 + 3.428000000000e-10 -3.774342269369e-01 + 3.528000000000e-10 -3.730540733905e-01 + 3.628000000000e-10 -3.091949741363e-01 + 3.728000000000e-10 -1.851642002832e-01 + 3.828000000000e-10 -3.487935842603e-02 + 3.928000000000e-10 1.053970083053e-01 + 4.028000000000e-10 2.088131472734e-01 + 4.128000000000e-10 2.762908135843e-01 + 4.228000000000e-10 3.196385089100e-01 + 4.328000000000e-10 3.518763575372e-01 + 4.428000000000e-10 3.766558038448e-01 + 4.528000000000e-10 3.725714207051e-01 + 4.628000000000e-10 3.087619830708e-01 + 4.728000000000e-10 1.849833837695e-01 + 4.828000000000e-10 3.467977975354e-02 + 4.928000000000e-10 -1.054340839288e-01 + 5.028000000000e-10 -2.089448612506e-01 + 5.128000000000e-10 -2.763231704068e-01 + 5.228000000000e-10 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7.728000000000e-10 -1.849285593480e-01 + 7.828000000000e-10 -3.470862903587e-02 + 7.928000000000e-10 1.054936381918e-01 + 8.028000000000e-10 2.089186129636e-01 + 8.128000000000e-10 2.763755879874e-01 + 8.228000000000e-10 3.197437164625e-01 + 8.328000000000e-10 3.519463479929e-01 + 8.428000000000e-10 3.767260853907e-01 + 8.528000000000e-10 3.725904126785e-01 + 8.628000000000e-10 3.087783440951e-01 + 8.728000000000e-10 1.849632167070e-01 + 8.828000000000e-10 3.467482549783e-02 + 8.928000000000e-10 -1.054610682584e-01 + 9.028000000000e-10 -2.089507846182e-01 + 9.128000000000e-10 -2.763436586770e-01 + 9.228000000000e-10 -3.197760754687e-01 + 9.328000000000e-10 -3.519146615050e-01 + 9.428000000000e-10 -3.767573997120e-01 + 9.528000000000e-10 -3.725597535055e-01 + 9.628000000000e-10 -3.088090609970e-01 + 9.728000000000e-10 -1.849326628321e-01 + 9.828000000000e-10 -3.470475490247e-02 + 9.928000000000e-10 1.054896146910e-01 + 1.000000000000e-09 1.838520001242e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/conditions.yaml new file mode 100644 index 00000000..075641ac --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 1 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_01 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/CML_core_tb.sch new file mode 100644 index 00000000..bda4d5a9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/CML_core_tb_2.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/CML_core_tb_2.data new file mode 100644 index 00000000..b332ca2c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/CML_core_tb_2.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162797108708e-01 + 1.728000000000e-10 -1.875883768906e-01 + 1.828000000000e-10 -3.217177564589e-02 + 1.928000000000e-10 1.118453904517e-01 + 2.028000000000e-10 2.178869753922e-01 + 2.128000000000e-10 2.869187499571e-01 + 2.228000000000e-10 3.311831063176e-01 + 2.328000000000e-10 3.637965093552e-01 + 2.428000000000e-10 3.884475585753e-01 + 2.528000000000e-10 3.831703446637e-01 + 2.628000000000e-10 3.149426000366e-01 + 2.728000000000e-10 1.840825734866e-01 + 2.828000000000e-10 2.786370536806e-02 + 2.928000000000e-10 -1.159899232258e-01 + 3.028000000000e-10 -2.217323928122e-01 + 3.128000000000e-10 -2.897841810826e-01 + 3.228000000000e-10 -3.334256487170e-01 + 3.328000000000e-10 -3.654508602495e-01 + 3.428000000000e-10 -3.900407544937e-01 + 3.528000000000e-10 -3.846189534315e-01 + 3.628000000000e-10 -3.164922452622e-01 + 3.728000000000e-10 -1.853182634851e-01 + 3.828000000000e-10 -2.898615964086e-02 + 3.928000000000e-10 1.151710782521e-01 + 4.028000000000e-10 2.209054309263e-01 + 4.128000000000e-10 2.891817322742e-01 + 4.228000000000e-10 3.328077516782e-01 + 4.328000000000e-10 3.650515838921e-01 + 4.428000000000e-10 3.896233583948e-01 + 4.528000000000e-10 3.844074302627e-01 + 4.628000000000e-10 3.162448842688e-01 + 4.728000000000e-10 1.852475068120e-01 + 4.828000000000e-10 2.884623360652e-02 + 4.928000000000e-10 -1.151788252337e-01 + 5.028000000000e-10 -2.210147130581e-01 + 5.128000000000e-10 -2.891872658193e-01 + 5.228000000000e-10 -3.329167168088e-01 + 5.328000000000e-10 -3.650471930963e-01 + 5.428000000000e-10 -3.897100874545e-01 + 5.528000000000e-10 -3.843762306477e-01 + 5.628000000000e-10 -3.163013912188e-01 + 5.728000000000e-10 -1.851950213487e-01 + 5.828000000000e-10 -2.889036873678e-02 + 5.928000000000e-10 1.152312899162e-01 + 6.028000000000e-10 2.209735588305e-01 + 6.128000000000e-10 2.892357416511e-01 + 6.228000000000e-10 3.328707955285e-01 + 6.328000000000e-10 3.650931065031e-01 + 6.428000000000e-10 3.896657987149e-01 + 6.528000000000e-10 3.844215105032e-01 + 6.628000000000e-10 3.162596917265e-01 + 6.728000000000e-10 1.852417351036e-01 + 6.828000000000e-10 2.884992827621e-02 + 6.928000000000e-10 -1.151876679011e-01 + 7.028000000000e-10 -2.210123101756e-01 + 7.128000000000e-10 -2.891938845816e-01 + 7.228000000000e-10 -3.329106389600e-01 + 7.328000000000e-10 -3.650518039465e-01 + 7.428000000000e-10 -3.897047407363e-01 + 7.528000000000e-10 -3.843819858648e-01 + 7.628000000000e-10 -3.162978744015e-01 + 7.728000000000e-10 -1.852023753321e-01 + 7.828000000000e-10 -2.888743165850e-02 + 7.928000000000e-10 1.152240030808e-01 + 8.028000000000e-10 2.209771419031e-01 + 8.128000000000e-10 2.892295361788e-01 + 8.228000000000e-10 3.328747680971e-01 + 8.328000000000e-10 3.650871456099e-01 + 8.428000000000e-10 3.896701175780e-01 + 8.528000000000e-10 3.844156912621e-01 + 8.628000000000e-10 3.162637401476e-01 + 8.728000000000e-10 1.852363586492e-01 + 8.828000000000e-10 2.885434112124e-02 + 8.928000000000e-10 -1.151920978903e-01 + 9.028000000000e-10 -2.210084087345e-01 + 9.128000000000e-10 -2.891984388712e-01 + 9.228000000000e-10 -3.329064027155e-01 + 9.328000000000e-10 -3.650560988894e-01 + 9.428000000000e-10 -3.897007143418e-01 + 9.528000000000e-10 -3.843858173814e-01 + 9.628000000000e-10 -3.162935974835e-01 + 9.728000000000e-10 -1.852064424274e-01 + 9.828000000000e-10 -2.888350905479e-02 + 9.928000000000e-10 1.152199079204e-01 + 1.000000000000e-09 1.954791142410e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/conditions.yaml new file mode 100644 index 00000000..03a4d140 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 2 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_02 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/CML_core_tb.sch new file mode 100644 index 00000000..41b0e418 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/CML_core_tb_3.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/CML_core_tb_3.data new file mode 100644 index 00000000..6dccbfd6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/CML_core_tb_3.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.914571027454e-01 + 1.728000000000e-10 -1.780117263272e-01 + 1.828000000000e-10 -3.802564096594e-02 + 1.928000000000e-10 9.479025580261e-02 + 2.028000000000e-10 1.961220444980e-01 + 2.128000000000e-10 2.643669322964e-01 + 2.228000000000e-10 3.071498875260e-01 + 2.328000000000e-10 3.351667250191e-01 + 2.428000000000e-10 3.529478733093e-01 + 2.528000000000e-10 3.439767079911e-01 + 2.628000000000e-10 2.827109934029e-01 + 2.728000000000e-10 1.683025534555e-01 + 2.828000000000e-10 2.843266655337e-02 + 2.928000000000e-10 -1.036223502576e-01 + 3.028000000000e-10 -2.042863713809e-01 + 3.128000000000e-10 -2.713818104821e-01 + 3.228000000000e-10 -3.132717880322e-01 + 3.328000000000e-10 -3.402903477971e-01 + 3.428000000000e-10 -3.574262556597e-01 + 3.528000000000e-10 -3.476240566503e-01 + 3.628000000000e-10 -2.857203755187e-01 + 3.728000000000e-10 -1.703849236420e-01 + 3.828000000000e-10 -2.994825869373e-02 + 3.928000000000e-10 1.026817167876e-01 + 4.028000000000e-10 2.034750084544e-01 + 4.128000000000e-10 2.707812081585e-01 + 4.228000000000e-10 3.126503625184e-01 + 4.328000000000e-10 3.399043734480e-01 + 4.428000000000e-10 3.571021595385e-01 + 4.528000000000e-10 3.475896983741e-01 + 4.628000000000e-10 2.857411927694e-01 + 4.728000000000e-10 1.706053611761e-01 + 4.828000000000e-10 3.010795594348e-02 + 4.928000000000e-10 -1.024135388755e-01 + 5.028000000000e-10 -2.033190471438e-01 + 5.128000000000e-10 -2.705615444577e-01 + 5.228000000000e-10 -3.125558523975e-01 + 5.328000000000e-10 -3.397330193449e-01 + 5.428000000000e-10 -3.570354300338e-01 + 5.528000000000e-10 -3.474353611027e-01 + 5.628000000000e-10 -2.856876769732e-01 + 5.728000000000e-10 -1.704760895977e-01 + 5.828000000000e-10 -3.008641427314e-02 + 5.928000000000e-10 1.025087996136e-01 + 6.028000000000e-10 2.033209986443e-01 + 6.128000000000e-10 2.706412375819e-01 + 6.228000000000e-10 3.125457575810e-01 + 6.328000000000e-10 3.398008382665e-01 + 6.428000000000e-10 3.570145583479e-01 + 6.528000000000e-10 3.474888598072e-01 + 6.628000000000e-10 2.856551852535e-01 + 6.728000000000e-10 1.705188293935e-01 + 6.828000000000e-10 3.004736925580e-02 + 6.928000000000e-10 -1.024728514478e-01 + 7.028000000000e-10 -2.033602328622e-01 + 7.128000000000e-10 -2.706061106716e-01 + 7.228000000000e-10 -3.125843283316e-01 + 7.328000000000e-10 -3.397655433228e-01 + 7.428000000000e-10 -3.570523646632e-01 + 7.528000000000e-10 -3.474554820929e-01 + 7.628000000000e-10 -2.856929985560e-01 + 7.728000000000e-10 -1.704859799650e-01 + 7.828000000000e-10 -3.008383757896e-02 + 7.928000000000e-10 1.025039608177e-01 + 8.028000000000e-10 2.033261442763e-01 + 8.128000000000e-10 2.706371082838e-01 + 8.228000000000e-10 3.125504649737e-01 + 8.328000000000e-10 3.397966066528e-01 + 8.428000000000e-10 3.570198965640e-01 + 8.528000000000e-10 3.474857187206e-01 + 8.628000000000e-10 2.856614378232e-01 + 8.728000000000e-10 1.705164607562e-01 + 8.828000000000e-10 3.005354621749e-02 + 8.928000000000e-10 -1.024749769036e-01 + 9.028000000000e-10 -2.033548454455e-01 + 9.128000000000e-10 -2.706087008930e-01 + 9.228000000000e-10 -3.125792630790e-01 + 9.328000000000e-10 -3.397683901773e-01 + 9.428000000000e-10 -3.570478314069e-01 + 9.528000000000e-10 -3.474583427153e-01 + 9.628000000000e-10 -2.856887110961e-01 + 9.728000000000e-10 -1.704892548593e-01 + 9.828000000000e-10 -3.008001356704e-02 + 9.928000000000e-10 1.025005080892e-01 + 1.000000000000e-09 1.786649040194e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/conditions.yaml new file mode 100644 index 00000000..e3645c5e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 3 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_03 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/CML_core_tb.sch new file mode 100644 index 00000000..9a826220 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/CML_core_tb_4.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/CML_core_tb_4.data new file mode 100644 index 00000000..3efc8a54 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/CML_core_tb_4.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908886906683e-01 + 1.728000000000e-10 -1.805890382926e-01 + 1.828000000000e-10 -4.276329247682e-02 + 1.928000000000e-10 8.882407595099e-02 + 2.028000000000e-10 1.894983505466e-01 + 2.128000000000e-10 2.576242567207e-01 + 2.228000000000e-10 3.005212718886e-01 + 2.328000000000e-10 3.289546768723e-01 + 2.428000000000e-10 3.474240530436e-01 + 2.528000000000e-10 3.394794629215e-01 + 2.628000000000e-10 2.802266193594e-01 + 2.728000000000e-10 1.685520573893e-01 + 2.828000000000e-10 3.081792474830e-02 + 2.928000000000e-10 -9.985913249602e-02 + 3.028000000000e-10 -1.996535082954e-01 + 3.128000000000e-10 -2.663519845580e-01 + 3.228000000000e-10 -3.081166100610e-01 + 3.328000000000e-10 -3.353557582557e-01 + 3.428000000000e-10 -3.530339682910e-01 + 3.528000000000e-10 -3.441234226063e-01 + 3.628000000000e-10 -2.840838930007e-01 + 3.728000000000e-10 -1.712890179908e-01 + 3.828000000000e-10 -3.280692441870e-02 + 3.928000000000e-10 9.858702888345e-02 + 4.028000000000e-10 1.985844458095e-01 + 4.128000000000e-10 2.655374220709e-01 + 4.228000000000e-10 3.073092043222e-01 + 4.328000000000e-10 3.348254361967e-01 + 4.428000000000e-10 3.526065806553e-01 + 4.528000000000e-10 3.440384505411e-01 + 4.628000000000e-10 2.840943593119e-01 + 4.728000000000e-10 1.715352376725e-01 + 4.828000000000e-10 3.300625747524e-02 + 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9.828000000000e-10 -3.296001530074e-02 + 9.928000000000e-10 9.837298926970e-02 + 1.000000000000e-09 1.738955459088e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/conditions.yaml new file mode 100644 index 00000000..3dbeec10 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 4 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_04 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/CML_core_tb.sch new file mode 100644 index 00000000..1e05865b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/CML_core_tb_5.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/CML_core_tb_5.data new file mode 100644 index 00000000..0cc77d23 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/CML_core_tb_5.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.958574299710e-01 + 1.728000000000e-10 -1.791897212785e-01 + 1.828000000000e-10 -3.599075048614e-02 + 1.928000000000e-10 9.946703268478e-02 + 2.028000000000e-10 2.032502871016e-01 + 2.128000000000e-10 2.733994094958e-01 + 2.228000000000e-10 3.172845988123e-01 + 2.328000000000e-10 3.455609123691e-01 + 2.428000000000e-10 3.630923957132e-01 + 2.528000000000e-10 3.534419450967e-01 + 2.628000000000e-10 2.903663934708e-01 + 2.728000000000e-10 1.726743312860e-01 + 2.828000000000e-10 2.930291139472e-02 + 2.928000000000e-10 -1.057514312075e-01 + 3.028000000000e-10 -2.091913834589e-01 + 3.128000000000e-10 -2.784696434768e-01 + 3.228000000000e-10 -3.216873931074e-01 + 3.328000000000e-10 -3.491870426412e-01 + 3.428000000000e-10 -3.662894191498e-01 + 3.528000000000e-10 -3.560374131806e-01 + 3.628000000000e-10 -2.925719059469e-01 + 3.728000000000e-10 -1.742159787839e-01 + 3.828000000000e-10 -3.049391935212e-02 + 3.928000000000e-10 1.049756016137e-01 + 4.028000000000e-10 2.084672065617e-01 + 4.128000000000e-10 2.779301238417e-01 + 4.228000000000e-10 3.211180618030e-01 + 4.328000000000e-10 3.488255023686e-01 + 4.428000000000e-10 3.659572542624e-01 + 4.528000000000e-10 3.559493947967e-01 + 4.628000000000e-10 2.925058094407e-01 + 4.728000000000e-10 1.743267017008e-01 + 4.828000000000e-10 3.054314172764e-02 + 4.928000000000e-10 -1.048175245910e-01 + 5.028000000000e-10 -2.084096499031e-01 + 5.128000000000e-10 -2.777998408986e-01 + 5.228000000000e-10 -3.210985617265e-01 + 5.328000000000e-10 -3.487226120056e-01 + 5.428000000000e-10 -3.659481451181e-01 + 5.528000000000e-10 -3.558482598240e-01 + 5.628000000000e-10 -2.924942070749e-01 + 5.728000000000e-10 -1.742324941843e-01 + 5.828000000000e-10 -3.054486718364e-02 + 5.928000000000e-10 1.048934295445e-01 + 6.028000000000e-10 2.083991544976e-01 + 6.128000000000e-10 2.778660140822e-01 + 6.228000000000e-10 3.210794561497e-01 + 6.328000000000e-10 3.487805773205e-01 + 6.428000000000e-10 3.659226785140e-01 + 6.528000000000e-10 3.558970058340e-01 + 6.628000000000e-10 2.924624137185e-01 + 6.728000000000e-10 1.742748110039e-01 + 6.828000000000e-10 3.050920657876e-02 + 6.928000000000e-10 -1.048562048812e-01 + 7.028000000000e-10 -2.084343791218e-01 + 7.128000000000e-10 -2.778299623633e-01 + 7.228000000000e-10 -3.211147582115e-01 + 7.328000000000e-10 -3.487447461690e-01 + 7.428000000000e-10 -3.659575085549e-01 + 7.528000000000e-10 -3.558632428052e-01 + 7.628000000000e-10 -2.924972481137e-01 + 7.728000000000e-10 -1.742418088753e-01 + 7.828000000000e-10 -3.054328720193e-02 + 7.928000000000e-10 1.048870377838e-01 + 8.028000000000e-10 2.084024115537e-01 + 8.128000000000e-10 2.778603942564e-01 + 8.228000000000e-10 3.210827582845e-01 + 8.328000000000e-10 3.487751488045e-01 + 8.428000000000e-10 3.659266824704e-01 + 8.528000000000e-10 3.558925702991e-01 + 8.628000000000e-10 2.924671830422e-01 + 8.728000000000e-10 1.742711856894e-01 + 8.828000000000e-10 3.051417003050e-02 + 8.928000000000e-10 -1.048591994973e-01 + 9.028000000000e-10 -2.084299430076e-01 + 9.128000000000e-10 -2.778331783696e-01 + 9.228000000000e-10 -3.211104359655e-01 + 9.328000000000e-10 -3.487480244246e-01 + 9.428000000000e-10 -3.659535267111e-01 + 9.528000000000e-10 -3.558663548813e-01 + 9.628000000000e-10 -2.924933270906e-01 + 9.728000000000e-10 -1.742451324195e-01 + 9.828000000000e-10 -3.053963678018e-02 + 9.928000000000e-10 1.048836196344e-01 + 1.000000000000e-09 1.830293824662e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/conditions.yaml new file mode 100644 index 00000000..0d1d4faa --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 5 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_05 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/CML_core_tb.sch new file mode 100644 index 00000000..55e67d0d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/CML_core_tb_6.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/CML_core_tb_6.data new file mode 100644 index 00000000..38ffd8bf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/CML_core_tb_6.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.689355033953e-01 + 1.728000000000e-10 -1.691728954892e-01 + 1.828000000000e-10 -4.423302134033e-02 + 1.928000000000e-10 7.663444207075e-02 + 2.028000000000e-10 1.714764750752e-01 + 2.128000000000e-10 2.368219567798e-01 + 2.228000000000e-10 2.772768132445e-01 + 2.328000000000e-10 3.013675537348e-01 + 2.428000000000e-10 3.140706479520e-01 + 2.528000000000e-10 3.038549886105e-01 + 2.628000000000e-10 2.508404086347e-01 + 2.728000000000e-10 1.528360605683e-01 + 2.828000000000e-10 3.040034809293e-02 + 2.928000000000e-10 -8.785381094258e-02 + 3.028000000000e-10 -1.808734961109e-01 + 3.128000000000e-10 -2.445795528199e-01 + 3.228000000000e-10 -2.838354337528e-01 + 3.328000000000e-10 -3.065800962400e-01 + 3.428000000000e-10 -3.181767360109e-01 + 3.528000000000e-10 -3.065752663659e-01 + 3.628000000000e-10 -2.523878800401e-01 + 3.728000000000e-10 -1.531173668737e-01 + 3.828000000000e-10 -2.992055538556e-02 + 3.928000000000e-10 8.900435641641e-02 + 4.028000000000e-10 1.821756238512e-01 + 4.128000000000e-10 2.460123650690e-01 + 4.228000000000e-10 2.851182310100e-01 + 4.328000000000e-10 3.079291995556e-01 + 4.428000000000e-10 3.194129911462e-01 + 4.528000000000e-10 3.078915366323e-01 + 4.628000000000e-10 2.535144344421e-01 + 4.728000000000e-10 1.541542026196e-01 + 4.828000000000e-10 3.063651583090e-02 + 4.928000000000e-10 -8.839161491074e-02 + 5.028000000000e-10 -1.817999659778e-01 + 5.128000000000e-10 -2.456456661989e-01 + 5.228000000000e-10 -2.849195350591e-01 + 5.328000000000e-10 -3.077091828990e-01 + 5.428000000000e-10 -3.193505374448e-01 + 5.528000000000e-10 -3.078081521678e-01 + 5.628000000000e-10 -2.535787813503e-01 + 5.728000000000e-10 -1.541764927596e-01 + 5.828000000000e-10 -3.077048554081e-02 + 5.928000000000e-10 8.832790620553e-02 + 6.028000000000e-10 1.816551916875e-01 + 6.128000000000e-10 2.455879975104e-01 + 6.228000000000e-10 2.847911932982e-01 + 6.328000000000e-10 3.076677363016e-01 + 6.428000000000e-10 3.192371229053e-01 + 6.528000000000e-10 3.077778412262e-01 + 6.628000000000e-10 2.534819327505e-01 + 6.728000000000e-10 1.541683138663e-01 + 6.828000000000e-10 3.070155435378e-02 + 6.928000000000e-10 -8.831320560130e-02 + 7.028000000000e-10 -1.817038543937e-01 + 7.128000000000e-10 -2.455619958387e-01 + 7.228000000000e-10 -2.848320347671e-01 + 7.328000000000e-10 -3.076358698550e-01 + 7.428000000000e-10 -3.192710667609e-01 + 7.528000000000e-10 -3.077409972388e-01 + 7.628000000000e-10 -2.535098012890e-01 + 7.728000000000e-10 -1.541282589474e-01 + 7.828000000000e-10 -3.072672689244e-02 + 7.928000000000e-10 8.835148526653e-02 + 8.028000000000e-10 1.816795669555e-01 + 8.128000000000e-10 2.455984246601e-01 + 8.228000000000e-10 2.848062931006e-01 + 8.328000000000e-10 3.076705916890e-01 + 8.428000000000e-10 3.192450073559e-01 + 8.528000000000e-10 3.077736319697e-01 + 8.628000000000e-10 2.534831121829e-01 + 8.728000000000e-10 1.541590953584e-01 + 8.828000000000e-10 3.069946612700e-02 + 8.928000000000e-10 -8.832341199891e-02 + 9.028000000000e-10 -1.817063952021e-01 + 9.128000000000e-10 -2.455714256322e-01 + 9.228000000000e-10 -2.848333922463e-01 + 9.328000000000e-10 -3.076440936715e-01 + 9.428000000000e-10 -3.192716274515e-01 + 9.528000000000e-10 -3.077481608676e-01 + 9.628000000000e-10 -2.535093614867e-01 + 9.728000000000e-10 -1.541340765567e-01 + 9.828000000000e-10 -3.072486745089e-02 + 9.928000000000e-10 8.834711873249e-02 + 1.000000000000e-09 1.586239577417e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/conditions.yaml new file mode 100644 index 00000000..817f52bc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 6 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_06 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/CML_core_tb.sch new file mode 100644 index 00000000..201a3f16 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/CML_core_tb_7.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/CML_core_tb_7.data new file mode 100644 index 00000000..1cfe87b5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/CML_core_tb_7.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.694477874818e-01 + 1.728000000000e-10 -1.721829739194e-01 + 1.828000000000e-10 -4.906833766415e-02 + 1.928000000000e-10 7.069743134728e-02 + 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6.928000000000e-10 -8.486327141666e-02 + 7.028000000000e-10 -1.772689800248e-01 + 7.128000000000e-10 -2.405282060865e-01 + 7.228000000000e-10 -2.795021370136e-01 + 7.328000000000e-10 -3.024278022377e-01 + 7.428000000000e-10 -3.145896170200e-01 + 7.528000000000e-10 -3.039617953787e-01 + 7.628000000000e-10 -2.514004690324e-01 + 7.728000000000e-10 -1.542820043229e-01 + 7.828000000000e-10 -3.281110337775e-02 + 7.928000000000e-10 8.490436306023e-02 + 8.028000000000e-10 1.772446330839e-01 + 8.128000000000e-10 2.405674335146e-01 + 8.228000000000e-10 2.794761963085e-01 + 8.328000000000e-10 3.024650976088e-01 + 8.428000000000e-10 3.145632644585e-01 + 8.528000000000e-10 3.039968961590e-01 + 8.628000000000e-10 2.513733111446e-01 + 8.728000000000e-10 1.543150179356e-01 + 8.828000000000e-10 3.278304586331e-02 + 8.928000000000e-10 -8.487456857602e-02 + 9.028000000000e-10 -1.772725618584e-01 + 9.128000000000e-10 -2.405389250041e-01 + 9.228000000000e-10 -2.795045102279e-01 + 9.328000000000e-10 -3.024372521320e-01 + 9.428000000000e-10 -3.145911572553e-01 + 9.528000000000e-10 -3.039701598993e-01 + 9.628000000000e-10 -2.514009218164e-01 + 9.728000000000e-10 -1.542887967264e-01 + 9.828000000000e-10 -3.280979517783e-02 + 9.928000000000e-10 8.489941508642e-02 + 1.000000000000e-09 1.544118489485e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/conditions.yaml new file mode 100644 index 00000000..08e8ff34 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 7 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_07 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/CML_core_tb.sch new file mode 100644 index 00000000..e3d0951d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/CML_core_tb_8.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/CML_core_tb_8.data new file mode 100644 index 00000000..b4ed17dd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/CML_core_tb_8.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.722799425151e-01 + 1.728000000000e-10 -1.701277707773e-01 + 1.828000000000e-10 -4.252496989706e-02 + 1.928000000000e-10 8.092536896213e-02 + 2.028000000000e-10 1.785199933375e-01 + 2.128000000000e-10 2.463984181452e-01 + 2.228000000000e-10 2.885755113271e-01 + 2.328000000000e-10 3.131967480955e-01 + 2.428000000000e-10 3.255285716483e-01 + 2.528000000000e-10 3.143820454109e-01 + 2.628000000000e-10 2.595824958850e-01 + 2.728000000000e-10 1.585585813323e-01 + 2.828000000000e-10 3.254606172598e-02 + 2.928000000000e-10 -8.921916265210e-02 + 3.028000000000e-10 -1.857143058967e-01 + 3.128000000000e-10 -2.524588707093e-01 + 3.228000000000e-10 -2.937876617757e-01 + 3.328000000000e-10 -3.173655773168e-01 + 3.428000000000e-10 -3.288566343508e-01 + 3.528000000000e-10 -3.166123605828e-01 + 3.628000000000e-10 -2.609360611345e-01 + 3.728000000000e-10 -1.589355414621e-01 + 3.828000000000e-10 -3.237621747627e-02 + 3.928000000000e-10 8.990939637816e-02 + 4.028000000000e-10 1.864994737191e-01 + 4.128000000000e-10 2.533636311879e-01 + 4.228000000000e-10 2.945633129641e-01 + 4.328000000000e-10 3.182197832362e-01 + 4.428000000000e-10 3.296245618008e-01 + 4.528000000000e-10 3.174841059207e-01 + 4.628000000000e-10 2.616780558587e-01 + 4.728000000000e-10 1.596622360522e-01 + 4.828000000000e-10 3.287681921596e-02 + 4.928000000000e-10 -8.943999963453e-02 + 5.028000000000e-10 -1.862066308093e-01 + 5.128000000000e-10 -2.530527908612e-01 + 5.228000000000e-10 -2.943931136832e-01 + 5.328000000000e-10 -3.180152021024e-01 + 5.428000000000e-10 -3.295545667130e-01 + 5.528000000000e-10 -3.173812952412e-01 + 5.628000000000e-10 -2.617027726155e-01 + 5.728000000000e-10 -1.596411992093e-01 + 5.828000000000e-10 -3.295895028258e-02 + 5.928000000000e-10 8.942267434718e-02 + 6.028000000000e-10 1.861105403656e-01 + 6.128000000000e-10 2.530344325895e-01 + 6.228000000000e-10 2.943051008579e-01 + 6.328000000000e-10 3.180051485103e-01 + 6.428000000000e-10 3.294737915539e-01 + 6.528000000000e-10 3.173744791022e-01 + 6.628000000000e-10 2.616291881364e-01 + 6.728000000000e-10 1.596450333001e-01 + 6.828000000000e-10 3.290088244348e-02 + 6.928000000000e-10 -8.940659470005e-02 + 7.028000000000e-10 -1.861562133447e-01 + 7.128000000000e-10 -2.530116656482e-01 + 7.228000000000e-10 -2.943454309811e-01 + 7.328000000000e-10 -3.179780561670e-01 + 7.428000000000e-10 -3.295087969733e-01 + 7.528000000000e-10 -3.173438661274e-01 + 7.628000000000e-10 -2.616591955397e-01 + 7.728000000000e-10 -1.596115565426e-01 + 7.828000000000e-10 -3.292790237402e-02 + 7.928000000000e-10 8.943927261705e-02 + 8.028000000000e-10 1.861310420114e-01 + 8.128000000000e-10 2.530433655174e-01 + 8.228000000000e-10 2.943195630770e-01 + 8.328000000000e-10 3.180088285378e-01 + 8.428000000000e-10 3.294832118435e-01 + 8.528000000000e-10 3.173732295072e-01 + 8.628000000000e-10 2.616337486722e-01 + 8.728000000000e-10 1.596399004289e-01 + 8.828000000000e-10 3.290244884503e-02 + 8.928000000000e-10 -8.941301350766e-02 + 9.028000000000e-10 -1.861557185261e-01 + 9.128000000000e-10 -2.530180139920e-01 + 9.228000000000e-10 -2.943444772306e-01 + 9.328000000000e-10 -3.179838696148e-01 + 9.428000000000e-10 -3.295076633013e-01 + 9.528000000000e-10 -3.173492560727e-01 + 9.628000000000e-10 -2.616577755083e-01 + 9.728000000000e-10 -1.596163947717e-01 + 9.828000000000e-10 -3.292583900074e-02 + 9.928000000000e-10 8.943518431692e-02 + 1.000000000000e-09 1.621529465729e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/conditions.yaml new file mode 100644 index 00000000..25e239b1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 8 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_08 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/CML_core_tb.sch new file mode 100644 index 00000000..e903fb36 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/CML_core_tb_9.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/CML_core_tb_9.data new file mode 100644 index 00000000..6b24d1d6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/CML_core_tb_9.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.622644182692e-01 + 1.728000000000e-10 -1.962653738736e-01 + 1.828000000000e-10 -5.712895575235e-03 + 1.928000000000e-10 1.510345047594e-01 + 2.028000000000e-10 2.432775412534e-01 + 2.128000000000e-10 2.772000132926e-01 + 2.228000000000e-10 3.161630086256e-01 + 2.328000000000e-10 3.654121904616e-01 + 2.428000000000e-10 4.070200809677e-01 + 2.528000000000e-10 4.211809118313e-01 + 2.628000000000e-10 3.552666659990e-01 + 2.728000000000e-10 1.954111420719e-01 + 2.828000000000e-10 7.499275151763e-03 + 2.928000000000e-10 -1.488912332472e-01 + 3.028000000000e-10 -2.420325529570e-01 + 3.128000000000e-10 -2.768171400503e-01 + 3.228000000000e-10 -3.164103191401e-01 + 3.328000000000e-10 -3.656815561297e-01 + 3.428000000000e-10 -4.072561733660e-01 + 3.528000000000e-10 -4.210637971044e-01 + 3.628000000000e-10 -3.548415521036e-01 + 3.728000000000e-10 -1.946286859654e-01 + 3.828000000000e-10 -6.746438981043e-03 + 3.928000000000e-10 1.496127957227e-01 + 4.028000000000e-10 2.425057762271e-01 + 4.128000000000e-10 2.772590268750e-01 + 4.228000000000e-10 3.167075169816e-01 + 4.328000000000e-10 3.660182242119e-01 + 4.428000000000e-10 4.074726111052e-01 + 4.528000000000e-10 4.212975956202e-01 + 4.628000000000e-10 3.549573822535e-01 + 4.728000000000e-10 1.947835560361e-01 + 4.828000000000e-10 6.801482567115e-03 + 4.928000000000e-10 -1.495086456760e-01 + 5.028000000000e-10 -2.424863730465e-01 + 5.128000000000e-10 -2.771744431737e-01 + 5.228000000000e-10 -3.166940000076e-01 + 5.328000000000e-10 -3.659398771497e-01 + 5.428000000000e-10 -4.074689465730e-01 + 5.528000000000e-10 -4.212394549000e-01 + 5.628000000000e-10 -3.549741510035e-01 + 5.728000000000e-10 -1.947436351784e-01 + 5.828000000000e-10 -6.830080160870e-03 + 5.928000000000e-10 1.495407150967e-01 + 6.028000000000e-10 2.424570295697e-01 + 6.128000000000e-10 2.772066160972e-01 + 6.228000000000e-10 3.166654934082e-01 + 6.328000000000e-10 3.659723864247e-01 + 6.428000000000e-10 4.074416211051e-01 + 6.528000000000e-10 4.212697301261e-01 + 6.628000000000e-10 3.549467093259e-01 + 6.728000000000e-10 1.947718238583e-01 + 6.828000000000e-10 6.800951177238e-03 + 6.928000000000e-10 -1.495148390529e-01 + 7.028000000000e-10 -2.424852043575e-01 + 7.128000000000e-10 -2.771809105751e-01 + 7.228000000000e-10 -3.166930947909e-01 + 7.328000000000e-10 -3.659459016360e-01 + 7.428000000000e-10 -4.074677461547e-01 + 7.528000000000e-10 -4.212442717757e-01 + 7.628000000000e-10 -3.549717520551e-01 + 7.728000000000e-10 -1.947463263521e-01 + 7.828000000000e-10 -6.825916545420e-03 + 7.928000000000e-10 1.495385751436e-01 + 8.028000000000e-10 2.424609931904e-01 + 8.128000000000e-10 2.772040406871e-01 + 8.228000000000e-10 3.166687905139e-01 + 8.328000000000e-10 3.659694951712e-01 + 8.428000000000e-10 4.074447010218e-01 + 8.528000000000e-10 4.212671408417e-01 + 8.628000000000e-10 3.549498827484e-01 + 8.728000000000e-10 1.947689363825e-01 + 8.828000000000e-10 6.803756635994e-03 + 8.928000000000e-10 -1.495176738691e-01 + 9.028000000000e-10 -2.424825342063e-01 + 9.128000000000e-10 -2.771836734306e-01 + 9.228000000000e-10 -3.166902103892e-01 + 9.328000000000e-10 -3.659485359213e-01 + 9.428000000000e-10 -4.074650210911e-01 + 9.528000000000e-10 -4.212469657833e-01 + 9.628000000000e-10 -3.549694058275e-01 + 9.728000000000e-10 -1.947487958951e-01 + 9.828000000000e-10 -6.823236278537e-03 + 9.928000000000e-10 1.495363177485e-01 + 1.000000000000e-09 2.250264100511e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/conditions.yaml new file mode 100644 index 00000000..3bbed872 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 9 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_09 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/CML_core_tb.sch new file mode 100644 index 00000000..a7c357a8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/CML_core_tb_10.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/CML_core_tb_10.data new file mode 100644 index 00000000..f64d27bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/CML_core_tb_10.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.621881537650e-01 + 1.728000000000e-10 -1.984429143572e-01 + 1.828000000000e-10 -1.024381876325e-02 + 1.928000000000e-10 1.456486678579e-01 + 2.028000000000e-10 2.379497773075e-01 + 2.128000000000e-10 2.714724605336e-01 + 2.228000000000e-10 3.108042897090e-01 + 2.328000000000e-10 3.600441003378e-01 + 2.428000000000e-10 4.020596908788e-01 + 2.528000000000e-10 4.176332246346e-01 + 2.628000000000e-10 3.534480183483e-01 + 2.728000000000e-10 1.957884716864e-01 + 2.828000000000e-10 1.048070619246e-02 + 2.928000000000e-10 -1.446967472000e-01 + 3.028000000000e-10 -2.375576326508e-01 + 3.128000000000e-10 -2.717915022579e-01 + 3.228000000000e-10 -3.116603869888e-01 + 3.328000000000e-10 -3.608573425706e-01 + 3.428000000000e-10 -4.027490548925e-01 + 3.528000000000e-10 -4.178578104758e-01 + 3.628000000000e-10 -3.532507313188e-01 + 3.728000000000e-10 -1.951536666098e-01 + 3.828000000000e-10 -9.813336101525e-03 + 3.928000000000e-10 1.453604720604e-01 + 4.028000000000e-10 2.379857130154e-01 + 4.128000000000e-10 2.721818635676e-01 + 4.228000000000e-10 3.119088225778e-01 + 4.328000000000e-10 3.611475798924e-01 + 4.428000000000e-10 4.029304727738e-01 + 4.528000000000e-10 4.180700216423e-01 + 4.628000000000e-10 3.533627988360e-01 + 4.728000000000e-10 1.953149158213e-01 + 4.828000000000e-10 9.881134950277e-03 + 4.928000000000e-10 -1.452466419838e-01 + 5.028000000000e-10 -2.379576224969e-01 + 5.128000000000e-10 -2.720935242692e-01 + 5.228000000000e-10 -3.118909714313e-01 + 5.328000000000e-10 -3.610674239906e-01 + 5.428000000000e-10 -4.029229661263e-01 + 5.528000000000e-10 -4.180098057029e-01 + 5.628000000000e-10 -3.533753449283e-01 + 5.728000000000e-10 -1.952727841385e-01 + 5.828000000000e-10 -9.906008920915e-03 + 5.928000000000e-10 1.452800172029e-01 + 6.028000000000e-10 2.379306740359e-01 + 6.128000000000e-10 2.721261300904e-01 + 6.228000000000e-10 3.118646486801e-01 + 6.328000000000e-10 3.611003417151e-01 + 6.428000000000e-10 4.028972890619e-01 + 6.528000000000e-10 4.180401129989e-01 + 6.628000000000e-10 3.533488930459e-01 + 6.728000000000e-10 1.953007885397e-01 + 6.828000000000e-10 9.878072761317e-03 + 6.928000000000e-10 -1.452545395230e-01 + 7.028000000000e-10 -2.379578117562e-01 + 7.128000000000e-10 -2.721008877684e-01 + 7.228000000000e-10 -3.118914026492e-01 + 7.328000000000e-10 -3.610744602697e-01 + 7.428000000000e-10 -4.029226014194e-01 + 7.528000000000e-10 -4.180151483436e-01 + 7.628000000000e-10 -3.533732531474e-01 + 7.728000000000e-10 -1.952759500525e-01 + 7.828000000000e-10 -9.902411226855e-03 + 7.928000000000e-10 1.452776462046e-01 + 8.028000000000e-10 2.379341379884e-01 + 8.128000000000e-10 2.721234101956e-01 + 8.228000000000e-10 3.118677116052e-01 + 8.328000000000e-10 3.610975209728e-01 + 8.428000000000e-10 4.029000595077e-01 + 8.528000000000e-10 4.180375331400e-01 + 8.628000000000e-10 3.533517750284e-01 + 8.728000000000e-10 1.952981248182e-01 + 8.828000000000e-10 9.880873061622e-03 + 8.928000000000e-10 -1.452571579233e-01 + 9.028000000000e-10 -2.379551078725e-01 + 9.128000000000e-10 -2.721034614056e-01 + 9.228000000000e-10 -3.118886463518e-01 + 9.328000000000e-10 -3.610770519544e-01 + 9.428000000000e-10 -4.029199107687e-01 + 9.528000000000e-10 -4.180177452829e-01 + 9.628000000000e-10 -3.533708821878e-01 + 9.728000000000e-10 -1.952784134813e-01 + 9.828000000000e-10 -9.899898542678e-03 + 9.928000000000e-10 1.452754037376e-01 + 1.000000000000e-09 2.207322871295e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/conditions.yaml new file mode 100644 index 00000000..41e7da55 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 10 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_10 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/CML_core_tb.sch new file mode 100644 index 00000000..36ade9a1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/CML_core_tb_11.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/CML_core_tb_11.data new file mode 100644 index 00000000..1453012b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/CML_core_tb_11.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.668500025046e-01 + 1.728000000000e-10 -1.978704758130e-01 + 1.828000000000e-10 -3.069550951996e-03 + 1.928000000000e-10 1.561389387989e-01 + 2.028000000000e-10 2.488697408913e-01 + 2.128000000000e-10 2.833379270136e-01 + 2.228000000000e-10 3.221467647695e-01 + 2.328000000000e-10 3.723176028273e-01 + 2.428000000000e-10 4.147931582649e-01 + 2.528000000000e-10 4.286646301121e-01 + 2.628000000000e-10 3.614677855799e-01 + 2.728000000000e-10 1.982726052647e-01 + 2.828000000000e-10 5.580533140739e-03 + 2.928000000000e-10 -1.536551403474e-01 + 3.028000000000e-10 -2.474729097395e-01 + 3.128000000000e-10 -2.827981749211e-01 + 3.228000000000e-10 -3.222400643179e-01 + 3.328000000000e-10 -3.724510578191e-01 + 3.428000000000e-10 -4.149487937489e-01 + 3.528000000000e-10 -4.285094572794e-01 + 3.628000000000e-10 -3.610716711123e-01 + 3.728000000000e-10 -1.975613483211e-01 + 3.828000000000e-10 -4.936396792217e-03 + 3.928000000000e-10 1.542720670721e-01 + 4.028000000000e-10 2.478554934965e-01 + 4.128000000000e-10 2.831768205427e-01 + 4.228000000000e-10 3.224764565266e-01 + 4.328000000000e-10 3.727376628527e-01 + 4.428000000000e-10 4.151128450004e-01 + 4.528000000000e-10 4.287030398326e-01 + 4.628000000000e-10 3.611465460996e-01 + 4.728000000000e-10 1.976871290976e-01 + 4.828000000000e-10 4.962067120498e-03 + 4.928000000000e-10 -1.541857483448e-01 + 5.028000000000e-10 -2.478549856990e-01 + 5.128000000000e-10 -2.831031432303e-01 + 5.228000000000e-10 -3.224786212940e-01 + 5.328000000000e-10 -3.726675199031e-01 + 5.428000000000e-10 -4.151222726988e-01 + 5.528000000000e-10 -4.286496175832e-01 + 5.628000000000e-10 -3.611719348809e-01 + 5.728000000000e-10 -1.976471175954e-01 + 5.828000000000e-10 -4.995016715658e-03 + 5.928000000000e-10 1.542195273485e-01 + 6.028000000000e-10 2.478226151197e-01 + 6.128000000000e-10 2.831371441394e-01 + 6.228000000000e-10 3.224465270882e-01 + 6.328000000000e-10 3.727020829784e-01 + 6.428000000000e-10 4.150919188021e-01 + 6.528000000000e-10 4.286821395136e-01 + 6.628000000000e-10 3.611419365066e-01 + 6.728000000000e-10 1.976777927703e-01 + 6.828000000000e-10 4.963507878799e-03 + 6.928000000000e-10 -1.541913949207e-01 + 7.028000000000e-10 -2.478529800499e-01 + 7.128000000000e-10 -2.831092109235e-01 + 7.228000000000e-10 -3.224762894768e-01 + 7.328000000000e-10 -3.726728668334e-01 + 7.428000000000e-10 -4.151201370880e-01 + 7.528000000000e-10 -4.286543531433e-01 + 7.628000000000e-10 -3.611692599178e-01 + 7.728000000000e-10 -1.976499135935e-01 + 7.828000000000e-10 -4.990471824028e-03 + 7.928000000000e-10 1.542171227717e-01 + 8.028000000000e-10 2.478269854332e-01 + 8.128000000000e-10 2.831343470853e-01 + 8.228000000000e-10 3.224500362551e-01 + 8.328000000000e-10 3.726987138014e-01 + 8.428000000000e-10 4.150953468135e-01 + 8.528000000000e-10 4.286792233560e-01 + 8.628000000000e-10 3.611455588852e-01 + 8.728000000000e-10 1.976743961081e-01 + 8.828000000000e-10 4.966432661841e-03 + 8.928000000000e-10 -1.541946484524e-01 + 9.028000000000e-10 -2.478502288236e-01 + 9.128000000000e-10 -2.831123474050e-01 + 9.228000000000e-10 -3.224731331421e-01 + 9.328000000000e-10 -3.726757720747e-01 + 9.428000000000e-10 -4.151172388981e-01 + 9.528000000000e-10 -4.286573581279e-01 + 9.628000000000e-10 -3.611667698498e-01 + 9.728000000000e-10 -1.976525646923e-01 + 9.828000000000e-10 -4.987471597641e-03 + 9.928000000000e-10 1.542147143463e-01 + 1.000000000000e-09 2.301006397866e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/conditions.yaml new file mode 100644 index 00000000..88ded064 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 11 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_11 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/CML_core_tb.sch new file mode 100644 index 00000000..db33ed1d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/CML_core_tb_12.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/CML_core_tb_12.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/CML_core_tb_12.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/conditions.yaml new file mode 100644 index 00000000..11003009 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 12 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_12 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/CML_core_tb.sch new file mode 100644 index 00000000..44208482 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/CML_core_tb_13.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/CML_core_tb_13.data new file mode 100644 index 00000000..36de6040 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/CML_core_tb_13.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.406999838743e-01 + 1.728000000000e-10 -1.879936990253e-01 + 1.828000000000e-10 -9.262901303246e-03 + 1.928000000000e-10 1.413611635485e-01 + 2.028000000000e-10 2.336775345801e-01 + 2.128000000000e-10 2.717294842894e-01 + 2.228000000000e-10 3.082620487639e-01 + 2.328000000000e-10 3.509422339502e-01 + 2.428000000000e-10 3.871053596645e-01 + 2.528000000000e-10 3.988940820744e-01 + 2.628000000000e-10 3.384312270542e-01 + 2.728000000000e-10 1.913281233779e-01 + 2.828000000000e-10 1.537343295661e-02 + 2.928000000000e-10 -1.347916275204e-01 + 3.028000000000e-10 -2.283419665374e-01 + 3.128000000000e-10 -2.677291408127e-01 + 3.228000000000e-10 -3.052231075401e-01 + 3.328000000000e-10 -3.481601477547e-01 + 3.428000000000e-10 -3.845854123080e-01 + 3.528000000000e-10 -3.965379624605e-01 + 3.628000000000e-10 -3.363314255870e-01 + 3.728000000000e-10 -1.893723794407e-01 + 3.828000000000e-10 -1.375643865463e-02 + 3.928000000000e-10 1.361849816757e-01 + 4.028000000000e-10 2.294005939140e-01 + 4.128000000000e-10 2.686949729273e-01 + 4.228000000000e-10 3.060328157788e-01 + 4.328000000000e-10 3.489590274886e-01 + 4.428000000000e-10 3.852266672724e-01 + 4.528000000000e-10 3.970921187630e-01 + 4.628000000000e-10 3.366736237881e-01 + 4.728000000000e-10 1.896320772426e-01 + 4.828000000000e-10 1.386475371506e-02 + 4.928000000000e-10 -1.360753156283e-01 + 5.028000000000e-10 -2.293675908871e-01 + 5.128000000000e-10 -2.686062530832e-01 + 5.228000000000e-10 -3.059945800423e-01 + 5.328000000000e-10 -3.488729675224e-01 + 5.428000000000e-10 -3.852026785029e-01 + 5.528000000000e-10 -3.970350594993e-01 + 5.628000000000e-10 -3.366834486256e-01 + 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2.686227634282e-01 + 8.228000000000e-10 3.059688096850e-01 + 8.328000000000e-10 3.488900661997e-01 + 8.428000000000e-10 3.851789257250e-01 + 8.528000000000e-10 3.970519764807e-01 + 8.628000000000e-10 3.366616134215e-01 + 8.728000000000e-10 1.896231972496e-01 + 8.828000000000e-10 1.387461571983e-02 + 8.928000000000e-10 -1.360724758723e-01 + 9.028000000000e-10 -2.293560182270e-01 + 9.128000000000e-10 -2.686070528237e-01 + 9.228000000000e-10 -3.059854790954e-01 + 9.328000000000e-10 -3.488740842624e-01 + 9.428000000000e-10 -3.851947329758e-01 + 9.528000000000e-10 -3.970365843841e-01 + 9.628000000000e-10 -3.366766115599e-01 + 9.728000000000e-10 -1.896075309897e-01 + 9.828000000000e-10 -1.388973786858e-02 + 9.928000000000e-10 1.360872156510e-01 + 1.000000000000e-09 2.108297225004e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/conditions.yaml new file mode 100644 index 00000000..164a4242 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 13 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_13 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/CML_core_tb.sch new file mode 100644 index 00000000..56f9a390 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/CML_core_tb_14.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/CML_core_tb_14.data new file mode 100644 index 00000000..73c31d13 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/CML_core_tb_14.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.445927026449e-01 + 1.728000000000e-10 -1.889320969581e-01 + 1.828000000000e-10 -5.355234564888e-03 + 1.928000000000e-10 1.489911128277e-01 + 2.028000000000e-10 2.434822449071e-01 + 2.128000000000e-10 2.838702060450e-01 + 2.228000000000e-10 3.202156401988e-01 + 2.328000000000e-10 3.629401474789e-01 + 2.428000000000e-10 3.990998051164e-01 + 2.528000000000e-10 4.099063275401e-01 + 2.628000000000e-10 3.477923521709e-01 + 2.728000000000e-10 1.968519788675e-01 + 2.828000000000e-10 1.493750763318e-02 + 2.928000000000e-10 -1.398437743336e-01 + 3.028000000000e-10 -2.362338093992e-01 + 3.128000000000e-10 -2.782887085314e-01 + 3.228000000000e-10 -3.158910292643e-01 + 3.328000000000e-10 -3.590893499920e-01 + 3.428000000000e-10 -3.957248346768e-01 + 3.528000000000e-10 -4.069627998073e-01 + 3.628000000000e-10 -3.454070734708e-01 + 3.728000000000e-10 -1.948243362004e-01 + 3.828000000000e-10 -1.337926088934e-02 + 3.928000000000e-10 1.411472162204e-01 + 4.028000000000e-10 2.372231231196e-01 + 4.128000000000e-10 2.792284454069e-01 + 4.228000000000e-10 3.166817589057e-01 + 4.328000000000e-10 3.598702175634e-01 + 4.428000000000e-10 3.963375250752e-01 + 4.528000000000e-10 4.074753309124e-01 + 4.628000000000e-10 3.456854225481e-01 + 4.728000000000e-10 1.950177434222e-01 + 4.828000000000e-10 1.342430394201e-02 + 4.928000000000e-10 -1.410850608466e-01 + 5.028000000000e-10 -2.372286880899e-01 + 5.128000000000e-10 -2.791659662153e-01 + 5.228000000000e-10 -3.166689293508e-01 + 5.328000000000e-10 -3.598026374101e-01 + 5.428000000000e-10 -3.963331138013e-01 + 5.528000000000e-10 -4.074316676804e-01 + 5.628000000000e-10 -3.457088001737e-01 + 5.728000000000e-10 -1.950000158899e-01 + 5.828000000000e-10 -1.346504722293e-02 + 5.928000000000e-10 1.410957635246e-01 + 6.028000000000e-10 2.371909425038e-01 + 6.128000000000e-10 2.791817404178e-01 + 6.228000000000e-10 3.166356138828e-01 + 6.328000000000e-10 3.598203377806e-01 + 6.428000000000e-10 3.963033609435e-01 + 6.528000000000e-10 4.074499160221e-01 + 6.628000000000e-10 3.456826167292e-01 + 6.728000000000e-10 1.950190841630e-01 + 6.828000000000e-10 1.343803454206e-02 + 6.928000000000e-10 -1.410764950259e-01 + 7.028000000000e-10 -2.372163265848e-01 + 7.128000000000e-10 -2.791624229651e-01 + 7.228000000000e-10 -3.166599225368e-01 + 7.328000000000e-10 -3.598002455584e-01 + 7.428000000000e-10 -3.963259615583e-01 + 7.528000000000e-10 -4.074304662079e-01 + 7.628000000000e-10 -3.457033629648e-01 + 7.728000000000e-10 -1.949983704767e-01 + 7.828000000000e-10 -1.345872104163e-02 + 7.928000000000e-10 1.410962716693e-01 + 8.028000000000e-10 2.371963808526e-01 + 8.128000000000e-10 2.791814500218e-01 + 8.228000000000e-10 3.166396456569e-01 + 8.328000000000e-10 3.598191409746e-01 + 8.428000000000e-10 3.963069790813e-01 + 8.528000000000e-10 4.074488078929e-01 + 8.628000000000e-10 3.456858987705e-01 + 8.728000000000e-10 1.950166421641e-01 + 8.828000000000e-10 1.344025602045e-02 + 8.928000000000e-10 -1.410790665154e-01 + 9.028000000000e-10 -2.372142995262e-01 + 9.128000000000e-10 -2.791649325552e-01 + 9.228000000000e-10 -3.166573514474e-01 + 9.328000000000e-10 -3.598022359716e-01 + 9.428000000000e-10 -3.963236588924e-01 + 9.528000000000e-10 -4.074326778223e-01 + 9.628000000000e-10 -3.457016440453e-01 + 9.728000000000e-10 -1.950001702792e-01 + 9.828000000000e-10 -1.345633761364e-02 + 9.928000000000e-10 1.410945129066e-01 + 1.000000000000e-09 2.176807579100e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/conditions.yaml new file mode 100644 index 00000000..d3c752b5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 14 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_14 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/CML_core_tb.sch new file mode 100644 index 00000000..4bc025b8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/CML_core_tb_15.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/CML_core_tb_15.data new file mode 100644 index 00000000..6f87c434 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/CML_core_tb_15.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.831577979118e-01 + 1.728000000000e-10 -1.548331321524e-01 + 1.828000000000e-10 2.954507991941e-03 + 1.928000000000e-10 1.412083661187e-01 + 2.028000000000e-10 2.303947789211e-01 + 2.128000000000e-10 2.725788032239e-01 + 2.228000000000e-10 3.064646814943e-01 + 2.328000000000e-10 3.412898568956e-01 + 2.428000000000e-10 3.692979025942e-01 + 2.528000000000e-10 3.751979264520e-01 + 2.628000000000e-10 3.186495551608e-01 + 2.728000000000e-10 1.849115684226e-01 + 2.828000000000e-10 2.146912258403e-02 + 2.928000000000e-10 -1.215319416200e-01 + 3.028000000000e-10 -2.147336364713e-01 + 3.128000000000e-10 -2.593628319189e-01 + 3.228000000000e-10 -2.947919001104e-01 + 3.328000000000e-10 -3.306034656465e-01 + 3.428000000000e-10 -3.598903423599e-01 + 3.528000000000e-10 -3.674806029527e-01 + 3.628000000000e-10 -3.131864519443e-01 + 3.728000000000e-10 -1.816607205648e-01 + 3.828000000000e-10 -2.002885045896e-02 + 3.928000000000e-10 1.219326732879e-01 + 4.028000000000e-10 2.146583452252e-01 + 4.128000000000e-10 2.593288859790e-01 + 4.228000000000e-10 2.947836961551e-01 + 4.328000000000e-10 3.305873089453e-01 + 4.428000000000e-10 3.597520160348e-01 + 4.528000000000e-10 3.672634041173e-01 + 4.628000000000e-10 3.128292575731e-01 + 4.728000000000e-10 1.812525079401e-01 + 4.828000000000e-10 1.956255085056e-02 + 4.928000000000e-10 -1.223539241893e-01 + 5.028000000000e-10 -2.150587893921e-01 + 5.128000000000e-10 -2.596440912838e-01 + 5.228000000000e-10 -2.950896959018e-01 + 5.328000000000e-10 -3.308452440946e-01 + 5.428000000000e-10 -3.600168265621e-01 + 5.528000000000e-10 -3.674687038170e-01 + 5.628000000000e-10 -3.130140501398e-01 + 5.728000000000e-10 -1.813584327872e-01 + 5.828000000000e-10 -1.965159115909e-02 + 5.928000000000e-10 1.223212864923e-01 + 6.028000000000e-10 2.150157103205e-01 + 6.128000000000e-10 2.596318060931e-01 + 6.228000000000e-10 2.950524078153e-01 + 6.328000000000e-10 3.308363963911e-01 + 6.428000000000e-10 3.599874022300e-01 + 6.528000000000e-10 3.674690181116e-01 + 6.628000000000e-10 3.129980588961e-01 + 6.728000000000e-10 1.813712653368e-01 + 6.828000000000e-10 1.964491680526e-02 + 6.928000000000e-10 -1.223023112353e-01 + 7.028000000000e-10 -2.150202483004e-01 + 7.128000000000e-10 -2.596144309164e-01 + 7.228000000000e-10 -2.950582886643e-01 + 7.328000000000e-10 -3.308199600200e-01 + 7.428000000000e-10 -3.599931640339e-01 + 7.528000000000e-10 -3.674538095645e-01 + 7.628000000000e-10 -3.130042913922e-01 + 7.728000000000e-10 -1.813570925598e-01 + 7.828000000000e-10 -1.965290666609e-02 + 7.928000000000e-10 1.223145971689e-01 + 8.028000000000e-10 2.150114430495e-01 + 8.128000000000e-10 2.596256780136e-01 + 8.228000000000e-10 2.950490452158e-01 + 8.328000000000e-10 3.308307530718e-01 + 8.428000000000e-10 3.599842799802e-01 + 8.528000000000e-10 3.674639698479e-01 + 8.628000000000e-10 3.129957925611e-01 + 8.728000000000e-10 1.813666711568e-01 + 8.828000000000e-10 1.964348030724e-02 + 8.928000000000e-10 -1.223056361887e-01 + 9.028000000000e-10 -2.150207890100e-01 + 9.128000000000e-10 -2.596171721225e-01 + 9.228000000000e-10 -2.950581404305e-01 + 9.328000000000e-10 -3.308221104591e-01 + 9.428000000000e-10 -3.599929167296e-01 + 9.528000000000e-10 -3.674557320782e-01 + 9.628000000000e-10 -3.130039671541e-01 + 9.728000000000e-10 -1.813582011282e-01 + 9.828000000000e-10 -1.965175786777e-02 + 9.928000000000e-10 1.223137237372e-01 + 1.000000000000e-09 1.953703252853e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/conditions.yaml new file mode 100644 index 00000000..4c7ed31b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 15 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_15 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/CML_core_tb.sch new file mode 100644 index 00000000..a6fe83e5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/CML_core_tb_16.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/CML_core_tb_16.data new file mode 100644 index 00000000..c0c44c66 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/CML_core_tb_16.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908214410229e-01 + 1.728000000000e-10 -1.609006026552e-01 + 1.828000000000e-10 -2.321243117629e-03 + 1.928000000000e-10 1.363185315112e-01 + 2.028000000000e-10 2.253864999197e-01 + 2.128000000000e-10 2.667546328680e-01 + 2.228000000000e-10 3.007016001191e-01 + 2.328000000000e-10 3.359037685855e-01 + 2.428000000000e-10 3.646369081917e-01 + 2.528000000000e-10 3.717564842409e-01 + 2.628000000000e-10 3.164681086559e-01 + 2.728000000000e-10 1.842122200319e-01 + 2.828000000000e-10 2.261788955655e-02 + 2.928000000000e-10 -1.190364341005e-01 + 3.028000000000e-10 -2.112326750882e-01 + 3.128000000000e-10 -2.547832728498e-01 + 3.228000000000e-10 -2.901354995194e-01 + 3.328000000000e-10 -3.261256516764e-01 + 3.428000000000e-10 -3.558916364396e-01 + 3.528000000000e-10 -3.643768878587e-01 + 3.628000000000e-10 -3.109660871267e-01 + 3.728000000000e-10 -1.806005122430e-01 + 3.828000000000e-10 -2.063463882859e-02 + 3.928000000000e-10 1.200417121301e-01 + 4.028000000000e-10 2.117115066678e-01 + 4.128000000000e-10 2.552245954862e-01 + 4.228000000000e-10 2.905358174314e-01 + 4.328000000000e-10 3.264964127076e-01 + 4.428000000000e-10 3.561164409890e-01 + 4.528000000000e-10 3.644937527082e-01 + 4.628000000000e-10 3.108863598347e-01 + 4.728000000000e-10 1.804066968471e-01 + 4.828000000000e-10 2.031749353463e-02 + 4.928000000000e-10 -1.203543467152e-01 + 5.028000000000e-10 -2.120338656010e-01 + 5.128000000000e-10 -2.554694201182e-01 + 5.228000000000e-10 -2.907816217466e-01 + 5.328000000000e-10 -3.266973931907e-01 + 5.428000000000e-10 -3.563354715244e-01 + 5.528000000000e-10 -3.646612654323e-01 + 5.628000000000e-10 -3.110514282819e-01 + 5.728000000000e-10 -1.805042989376e-01 + 5.828000000000e-10 -2.041198102925e-02 + 5.928000000000e-10 1.203139122453e-01 + 6.028000000000e-10 2.119789678115e-01 + 6.128000000000e-10 2.554499136191e-01 + 6.228000000000e-10 2.907352766216e-01 + 6.328000000000e-10 3.266827936599e-01 + 6.428000000000e-10 3.562972261563e-01 + 6.528000000000e-10 3.646559193667e-01 + 6.628000000000e-10 3.110272539685e-01 + 6.728000000000e-10 1.805126920434e-01 + 6.828000000000e-10 2.039901072518e-02 + 6.928000000000e-10 -1.202975671206e-01 + 7.028000000000e-10 -2.119881389434e-01 + 7.128000000000e-10 -2.554339974826e-01 + 7.228000000000e-10 -2.907449786827e-01 + 7.328000000000e-10 -3.266672756474e-01 + 7.428000000000e-10 -3.563063206496e-01 + 7.528000000000e-10 -3.646410588059e-01 + 7.628000000000e-10 -3.110359790738e-01 + 7.728000000000e-10 -1.804978632753e-01 + 7.828000000000e-10 -2.040852410596e-02 + 7.928000000000e-10 1.203110667878e-01 + 8.028000000000e-10 2.119781439274e-01 + 8.128000000000e-10 2.554465105638e-01 + 8.228000000000e-10 2.907345088651e-01 + 8.328000000000e-10 3.266793442083e-01 + 8.428000000000e-10 3.562962712815e-01 + 8.528000000000e-10 3.646525269207e-01 + 8.628000000000e-10 3.110264147595e-01 + 8.728000000000e-10 1.805087495738e-01 + 8.828000000000e-10 2.039807927138e-02 + 8.928000000000e-10 -1.203008828088e-01 + 9.028000000000e-10 -2.119885143169e-01 + 9.128000000000e-10 -2.554368509477e-01 + 9.228000000000e-10 -2.907446372900e-01 + 9.328000000000e-10 -3.266695427412e-01 + 9.428000000000e-10 -3.563059183968e-01 + 9.528000000000e-10 -3.646431522847e-01 + 9.628000000000e-10 -3.110356032735e-01 + 9.728000000000e-10 -1.804991631480e-01 + 9.828000000000e-10 -2.040735001275e-02 + 9.928000000000e-10 1.203099974113e-01 + 1.000000000000e-09 1.927324868168e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/conditions.yaml new file mode 100644 index 00000000..91a94e2b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 16 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_16 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/CML_core_tb.sch new file mode 100644 index 00000000..a433649c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/CML_core_tb_17.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/CML_core_tb_17.data new file mode 100644 index 00000000..1e62d263 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/CML_core_tb_17.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.857852225245e-01 + 1.728000000000e-10 -1.572533595452e-01 + 1.828000000000e-10 2.540381659783e-03 + 1.928000000000e-10 1.434374080790e-01 + 2.028000000000e-10 2.351272809546e-01 + 2.128000000000e-10 2.797956268783e-01 + 2.228000000000e-10 3.144243918962e-01 + 2.328000000000e-10 3.493618787392e-01 + 2.428000000000e-10 3.773715695689e-01 + 2.528000000000e-10 3.831823569325e-01 + 2.628000000000e-10 3.264482498061e-01 + 2.728000000000e-10 1.910530045686e-01 + 2.828000000000e-10 2.436059711742e-02 + 2.928000000000e-10 -1.220220612332e-01 + 3.028000000000e-10 -2.180809390746e-01 + 3.128000000000e-10 -2.653775774444e-01 + 3.228000000000e-10 -3.017848824321e-01 + 3.328000000000e-10 -3.379021858146e-01 + 3.428000000000e-10 -3.673696540777e-01 + 3.528000000000e-10 -3.751149757425e-01 + 3.628000000000e-10 -3.209083740174e-01 + 3.728000000000e-10 -1.878979131572e-01 + 3.828000000000e-10 -2.307531260616e-02 + 3.928000000000e-10 1.222703025101e-01 + 4.028000000000e-10 2.179003509445e-01 + 4.128000000000e-10 2.652908784701e-01 + 4.228000000000e-10 3.017672646237e-01 + 4.328000000000e-10 3.378931599738e-01 + 4.428000000000e-10 3.672390198172e-01 + 4.528000000000e-10 3.748903812400e-01 + 4.628000000000e-10 3.205316331029e-01 + 4.728000000000e-10 1.874647700937e-01 + 4.828000000000e-10 2.258819957166e-02 + 4.928000000000e-10 -1.227112688171e-01 + 5.028000000000e-10 -2.183172764214e-01 + 5.128000000000e-10 -2.656203742551e-01 + 5.228000000000e-10 -3.020800906145e-01 + 5.328000000000e-10 -3.381553362553e-01 + 5.428000000000e-10 -3.675051891202e-01 + 5.528000000000e-10 -3.750972240389e-01 + 5.628000000000e-10 -3.207148935088e-01 + 5.728000000000e-10 -1.875700292984e-01 + 5.828000000000e-10 -2.267596999196e-02 + 5.928000000000e-10 1.226776663562e-01 + 6.028000000000e-10 2.182733434309e-01 + 6.128000000000e-10 2.656053081095e-01 + 6.228000000000e-10 3.020411985396e-01 + 6.328000000000e-10 3.381435634392e-01 + 6.428000000000e-10 3.674743818406e-01 + 6.528000000000e-10 3.750952532513e-01 + 6.628000000000e-10 3.206986438750e-01 + 6.728000000000e-10 1.875816736609e-01 + 6.828000000000e-10 2.266940437016e-02 + 6.928000000000e-10 -1.226596158426e-01 + 7.028000000000e-10 -2.182776851932e-01 + 7.128000000000e-10 -2.655888997029e-01 + 7.228000000000e-10 -3.020470638059e-01 + 7.328000000000e-10 -3.381282771084e-01 + 7.428000000000e-10 -3.674800981492e-01 + 7.528000000000e-10 -3.750811166601e-01 + 7.628000000000e-10 -3.207046174850e-01 + 7.728000000000e-10 -1.875682790354e-01 + 7.828000000000e-10 -2.267703281628e-02 + 7.928000000000e-10 1.226713327530e-01 + 8.028000000000e-10 2.182693863135e-01 + 8.128000000000e-10 2.655996099454e-01 + 8.228000000000e-10 3.020383466326e-01 + 8.328000000000e-10 3.381385294735e-01 + 8.428000000000e-10 3.674717742910e-01 + 8.528000000000e-10 3.750907045119e-01 + 8.628000000000e-10 3.206966644115e-01 + 8.728000000000e-10 1.875773616331e-01 + 8.828000000000e-10 2.266807684955e-02 + 8.928000000000e-10 -1.226628120211e-01 + 9.028000000000e-10 -2.182782381400e-01 + 9.128000000000e-10 -2.655915506047e-01 + 9.228000000000e-10 -3.020469590318e-01 + 9.328000000000e-10 -3.381303351991e-01 + 9.428000000000e-10 -3.674798958779e-01 + 9.528000000000e-10 -3.750829516380e-01 + 9.628000000000e-10 -3.207043265993e-01 + 9.728000000000e-10 -1.875693454762e-01 + 9.828000000000e-10 -2.267594148777e-02 + 9.928000000000e-10 1.226704651969e-01 + 1.000000000000e-09 1.977257563344e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/conditions.yaml new file mode 100644 index 00000000..f814a5c3 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 17 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_17 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/CML_core_tb.sch new file mode 100644 index 00000000..f656c9a1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/CML_core_tb_18.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/CML_core_tb_18.data new file mode 100644 index 00000000..16422ca1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/CML_core_tb_18.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.213526702696e-01 + 1.728000000000e-10 -1.557909441213e-01 + 1.828000000000e-10 3.476956205809e-02 + 1.928000000000e-10 1.811250151598e-01 + 2.028000000000e-10 2.596166993269e-01 + 2.128000000000e-10 2.853727091731e-01 + 2.228000000000e-10 3.254453264627e-01 + 2.328000000000e-10 3.792799604087e-01 + 2.428000000000e-10 4.176388066249e-01 + 2.528000000000e-10 4.205544301124e-01 + 2.628000000000e-10 3.463528198985e-01 + 2.728000000000e-10 1.792096076204e-01 + 2.828000000000e-10 -1.442396833933e-02 + 2.928000000000e-10 -1.649237711275e-01 + 3.028000000000e-10 -2.471596975948e-01 + 3.128000000000e-10 -2.748735614517e-01 + 3.228000000000e-10 -3.160128767795e-01 + 3.328000000000e-10 -3.707930594343e-01 + 3.428000000000e-10 -4.104823651943e-01 + 3.528000000000e-10 -4.153692056047e-01 + 3.628000000000e-10 -3.427931169871e-01 + 3.728000000000e-10 -1.769552164151e-01 + 3.828000000000e-10 1.590673093360e-02 + 3.928000000000e-10 1.658834812043e-01 + 4.028000000000e-10 2.479775600913e-01 + 4.128000000000e-10 2.756409688001e-01 + 4.228000000000e-10 3.168596600790e-01 + 4.328000000000e-10 3.715133147191e-01 + 4.428000000000e-10 4.111218222953e-01 + 4.528000000000e-10 4.157229971644e-01 + 4.628000000000e-10 3.430019798682e-01 + 4.728000000000e-10 1.769456026445e-01 + 4.828000000000e-10 -1.592886494610e-02 + 4.928000000000e-10 -1.659782283296e-01 + 5.028000000000e-10 -2.479947853664e-01 + 5.128000000000e-10 -2.756931315881e-01 + 5.228000000000e-10 -3.168416717549e-01 + 5.328000000000e-10 -3.715547211919e-01 + 5.428000000000e-10 -4.111034138799e-01 + 5.528000000000e-10 -4.157691346087e-01 + 5.628000000000e-10 -3.429925568898e-01 + 5.728000000000e-10 -1.770024985869e-01 + 5.828000000000e-10 1.592938202906e-02 + 5.928000000000e-10 1.659292038608e-01 + 6.028000000000e-10 2.480043512000e-01 + 6.128000000000e-10 2.756533285421e-01 + 6.228000000000e-10 3.168576585763e-01 + 6.328000000000e-10 3.715156583068e-01 + 6.428000000000e-10 4.111207690964e-01 + 6.528000000000e-10 4.157343976531e-01 + 6.628000000000e-10 3.430135347581e-01 + 6.728000000000e-10 1.769734665185e-01 + 6.828000000000e-10 -1.590652763180e-02 + 6.928000000000e-10 -1.659537152419e-01 + 7.028000000000e-10 -2.479812550746e-01 + 7.128000000000e-10 -2.756768834918e-01 + 7.228000000000e-10 -3.168350969677e-01 + 7.328000000000e-10 -3.715419152243e-01 + 7.428000000000e-10 -4.110983779981e-01 + 7.528000000000e-10 -4.157587194411e-01 + 7.628000000000e-10 -3.429901444601e-01 + 7.728000000000e-10 -1.769973775521e-01 + 7.828000000000e-10 1.592723735432e-02 + 7.928000000000e-10 1.659318535084e-01 + 8.028000000000e-10 2.480017799848e-01 + 8.128000000000e-10 2.756559811492e-01 + 8.228000000000e-10 3.168566227283e-01 + 8.328000000000e-10 3.715195500188e-01 + 8.428000000000e-10 4.111190536097e-01 + 8.528000000000e-10 4.157370668569e-01 + 8.628000000000e-10 3.430103710665e-01 + 8.728000000000e-10 1.769771675859e-01 + 8.828000000000e-10 -1.590770493918e-02 + 8.928000000000e-10 -1.659501582149e-01 + 9.028000000000e-10 -2.479827571068e-01 + 9.128000000000e-10 -2.756738772283e-01 + 9.228000000000e-10 -3.168377001445e-01 + 9.328000000000e-10 -3.715391180409e-01 + 9.428000000000e-10 -4.111007797151e-01 + 9.528000000000e-10 -4.157556639381e-01 + 9.628000000000e-10 -3.429919881202e-01 + 9.728000000000e-10 -1.769955652012e-01 + 9.828000000000e-10 1.592430721908e-02 + 9.928000000000e-10 1.659331850974e-01 + 1.000000000000e-09 2.332140069758e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/conditions.yaml new file mode 100644 index 00000000..bdb15e03 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 18 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_18 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/CML_core_tb.sch new file mode 100644 index 00000000..cc0a304c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/CML_core_tb_19.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/CML_core_tb_19.data new file mode 100644 index 00000000..6e384890 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/CML_core_tb_19.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162777317791e-01 + 1.728000000000e-10 -1.528661974147e-01 + 1.828000000000e-10 3.474832458294e-02 + 1.928000000000e-10 1.787124308466e-01 + 2.028000000000e-10 2.559986610902e-01 + 2.128000000000e-10 2.810767408313e-01 + 2.228000000000e-10 3.219404824571e-01 + 2.328000000000e-10 3.760375868322e-01 + 2.428000000000e-10 4.141294975409e-01 + 2.528000000000e-10 4.175370858756e-01 + 2.628000000000e-10 3.443891646085e-01 + 2.728000000000e-10 1.786024667409e-01 + 2.828000000000e-10 -1.272368439666e-02 + 2.928000000000e-10 -1.612661145276e-01 + 3.028000000000e-10 -2.425558656005e-01 + 3.128000000000e-10 -2.696709375544e-01 + 3.228000000000e-10 -3.115976016931e-01 + 3.328000000000e-10 -3.666762080522e-01 + 3.428000000000e-10 -4.062269757432e-01 + 3.528000000000e-10 -4.117682170104e-01 + 3.628000000000e-10 -3.403932990270e-01 + 3.728000000000e-10 -1.760595961534e-01 + 3.828000000000e-10 1.438676142530e-02 + 3.928000000000e-10 1.623380571180e-01 + 4.028000000000e-10 2.434588647096e-01 + 4.128000000000e-10 2.705169080514e-01 + 4.228000000000e-10 3.125303134845e-01 + 4.328000000000e-10 3.674735521527e-01 + 4.428000000000e-10 4.069324770669e-01 + 4.528000000000e-10 4.121668816011e-01 + 4.628000000000e-10 3.406314536055e-01 + 4.728000000000e-10 1.760592839129e-01 + 4.828000000000e-10 -1.440702618479e-02 + 4.928000000000e-10 -1.624387020945e-01 + 5.028000000000e-10 -2.434775787799e-01 + 5.128000000000e-10 -2.705727170369e-01 + 5.228000000000e-10 -3.125119373252e-01 + 5.328000000000e-10 -3.675184828947e-01 + 5.428000000000e-10 -4.069140356329e-01 + 5.528000000000e-10 -4.122173977207e-01 + 5.628000000000e-10 -3.406230488723e-01 + 5.728000000000e-10 -1.761225643375e-01 + 5.828000000000e-10 1.440482600394e-02 + 5.928000000000e-10 1.623840500109e-01 + 6.028000000000e-10 2.434858819416e-01 + 6.128000000000e-10 2.705285901327e-01 + 6.228000000000e-10 3.125279242462e-01 + 6.328000000000e-10 3.674758375852e-01 + 6.428000000000e-10 4.069313048189e-01 + 6.528000000000e-10 4.121794941223e-01 + 6.628000000000e-10 3.406442721772e-01 + 6.728000000000e-10 1.760913923029e-01 + 6.828000000000e-10 -1.438048626859e-02 + 6.928000000000e-10 -1.624102913298e-01 + 7.028000000000e-10 -2.434611919520e-01 + 7.128000000000e-10 -2.705537859875e-01 + 7.228000000000e-10 -3.125040211699e-01 + 7.328000000000e-10 -3.675038904367e-01 + 7.428000000000e-10 -4.069074652851e-01 + 7.528000000000e-10 -4.122054838885e-01 + 7.628000000000e-10 -3.406192567768e-01 + 7.728000000000e-10 -1.761170868219e-01 + 7.828000000000e-10 1.440247036537e-02 + 7.928000000000e-10 1.623867436405e-01 + 8.028000000000e-10 2.434830143217e-01 + 8.128000000000e-10 2.705312548291e-01 + 8.228000000000e-10 3.125271394700e-01 + 8.328000000000e-10 3.674800931307e-01 + 8.428000000000e-10 4.069295144266e-01 + 8.528000000000e-10 4.121823557439e-01 + 8.628000000000e-10 3.406407407456e-01 + 8.728000000000e-10 1.760956573916e-01 + 8.828000000000e-10 -1.438135361500e-02 + 8.928000000000e-10 -1.624062315135e-01 + 9.028000000000e-10 -2.434625084707e-01 + 9.128000000000e-10 -2.705503455528e-01 + 9.228000000000e-10 -3.125068466958e-01 + 9.328000000000e-10 -3.675009271833e-01 + 9.428000000000e-10 -4.069098943042e-01 + 9.528000000000e-10 -4.122022218921e-01 + 9.628000000000e-10 -3.406210058100e-01 + 9.728000000000e-10 -1.761154015725e-01 + 9.828000000000e-10 1.439913133121e-02 + 9.928000000000e-10 1.623879640093e-01 + 1.000000000000e-09 2.290402036537e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/conditions.yaml new file mode 100644 index 00000000..3ff7992b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 19 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_19 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/CML_core_tb.sch new file mode 100644 index 00000000..3b08c6f4 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/CML_core_tb_20.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/CML_core_tb_20.data new file mode 100644 index 00000000..3dfcf241 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/CML_core_tb_20.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.365386572536e-01 + 1.728000000000e-10 -1.657072094068e-01 + 1.828000000000e-10 3.099865584261e-02 + 1.928000000000e-10 1.820426436768e-01 + 2.028000000000e-10 2.627018214462e-01 + 2.128000000000e-10 2.893736945719e-01 + 2.228000000000e-10 3.287984169352e-01 + 2.328000000000e-10 3.833334317825e-01 + 2.428000000000e-10 4.238785365972e-01 + 2.528000000000e-10 4.280322768716e-01 + 2.628000000000e-10 3.532409470363e-01 + 2.728000000000e-10 1.834641899168e-01 + 2.828000000000e-10 -1.474496205711e-02 + 2.928000000000e-10 -1.691349612478e-01 + 3.028000000000e-10 -2.530204867896e-01 + 3.128000000000e-10 -2.814070764654e-01 + 3.228000000000e-10 -3.218416847899e-01 + 3.328000000000e-10 -3.771799136100e-01 + 3.428000000000e-10 -4.187055626636e-01 + 3.528000000000e-10 -4.243036771430e-01 + 3.628000000000e-10 -3.506062035467e-01 + 3.728000000000e-10 -1.816763297909e-01 + 3.828000000000e-10 1.601938741723e-02 + 3.928000000000e-10 1.700087907901e-01 + 4.028000000000e-10 2.537596951165e-01 + 4.128000000000e-10 2.820887501770e-01 + 4.228000000000e-10 3.225625541805e-01 + 4.328000000000e-10 3.777928583784e-01 + 4.428000000000e-10 4.192485534625e-01 + 4.528000000000e-10 4.246080285894e-01 + 4.628000000000e-10 3.507916132015e-01 + 4.728000000000e-10 1.816929452641e-01 + 4.828000000000e-10 -1.601075067965e-02 + 4.928000000000e-10 -1.700562644838e-01 + 5.028000000000e-10 -2.537513990380e-01 + 5.128000000000e-10 -2.821086741965e-01 + 5.228000000000e-10 -3.225309737549e-01 + 5.328000000000e-10 -3.778081660132e-01 + 5.428000000000e-10 -4.192196231589e-01 + 5.528000000000e-10 -4.246325132019e-01 + 5.628000000000e-10 -3.507765562578e-01 + 5.728000000000e-10 -1.817315603141e-01 + 5.828000000000e-10 1.601468821266e-02 + 5.928000000000e-10 1.700220210141e-01 + 6.028000000000e-10 2.537612841477e-01 + 6.128000000000e-10 2.820810469197e-01 + 6.228000000000e-10 3.225454957468e-01 + 6.328000000000e-10 3.777800822765e-01 + 6.428000000000e-10 4.192350742948e-01 + 6.528000000000e-10 4.246071005326e-01 + 6.628000000000e-10 3.507940665347e-01 + 6.728000000000e-10 1.817094337521e-01 + 6.828000000000e-10 -1.599736953115e-02 + 6.928000000000e-10 -1.700405869499e-01 + 7.028000000000e-10 -2.537437685408e-01 + 7.128000000000e-10 -2.820988428465e-01 + 7.228000000000e-10 -3.225283133162e-01 + 7.328000000000e-10 -3.778004844844e-01 + 7.428000000000e-10 -4.192180216890e-01 + 7.528000000000e-10 -4.246257635725e-01 + 7.628000000000e-10 -3.507760422929e-01 + 7.728000000000e-10 -1.817278922025e-01 + 7.828000000000e-10 1.601285231965e-02 + 7.928000000000e-10 1.700238629540e-01 + 8.028000000000e-10 2.537592487741e-01 + 8.128000000000e-10 2.820829438407e-01 + 8.228000000000e-10 3.225445511573e-01 + 8.328000000000e-10 3.777829985044e-01 + 8.428000000000e-10 4.192337708379e-01 + 8.528000000000e-10 4.246090234999e-01 + 8.628000000000e-10 3.507916632731e-01 + 8.728000000000e-10 1.817122417436e-01 + 8.828000000000e-10 -1.599824136343e-02 + 8.928000000000e-10 -1.700377849177e-01 + 9.028000000000e-10 -2.537449127629e-01 + 9.128000000000e-10 -2.820965585668e-01 + 9.228000000000e-10 -3.225302446360e-01 + 9.328000000000e-10 -3.777982010874e-01 + 9.428000000000e-10 -4.192199753705e-01 + 9.528000000000e-10 -4.246232587341e-01 + 9.628000000000e-10 -3.507775800865e-01 + 9.728000000000e-10 -1.817263367247e-01 + 9.828000000000e-10 1.601066647660e-02 + 9.928000000000e-10 1.700248857455e-01 + 1.000000000000e-09 2.385375784000e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/conditions.yaml new file mode 100644 index 00000000..50bd287d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 20 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_20 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/CML_core_tb.sch new file mode 100644 index 00000000..51ef8f31 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/CML_core_tb_21.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/CML_core_tb_21.data new file mode 100644 index 00000000..86f9b023 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/CML_core_tb_21.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.747912795524e-01 + 1.728000000000e-10 -1.327955908449e-01 + 1.828000000000e-10 3.931332790349e-02 + 1.928000000000e-10 1.782957289495e-01 + 2.028000000000e-10 2.573194188668e-01 + 2.128000000000e-10 2.870254911902e-01 + 2.228000000000e-10 3.228650321442e-01 + 2.328000000000e-10 3.690575149088e-01 + 2.428000000000e-10 4.023791308175e-01 + 2.528000000000e-10 4.034409994944e-01 + 2.628000000000e-10 3.332295993533e-01 + 2.728000000000e-10 1.767123870243e-01 + 2.828000000000e-10 -7.574880255958e-03 + 2.928000000000e-10 -1.550892096227e-01 + 3.028000000000e-10 -2.394679486139e-01 + 3.128000000000e-10 -2.715465054757e-01 + 3.228000000000e-10 -3.085580168164e-01 + 3.328000000000e-10 -3.560821219044e-01 + 3.428000000000e-10 -3.914831036325e-01 + 3.528000000000e-10 -3.956717314322e-01 + 3.628000000000e-10 -3.285929470428e-01 + 3.728000000000e-10 -1.747908753666e-01 + 3.828000000000e-10 7.882784627431e-03 + 3.928000000000e-10 1.545893087045e-01 + 4.028000000000e-10 2.389887597051e-01 + 4.128000000000e-10 2.712307710628e-01 + 4.228000000000e-10 3.085047043395e-01 + 4.328000000000e-10 3.559448484744e-01 + 4.428000000000e-10 3.913507819782e-01 + 4.528000000000e-10 3.953547803018e-01 + 4.628000000000e-10 3.282585464854e-01 + 4.728000000000e-10 1.743078825018e-01 + 4.828000000000e-10 -8.291328068348e-03 + 4.928000000000e-10 -1.550293895867e-01 + 5.028000000000e-10 -2.392804293874e-01 + 5.128000000000e-10 -2.715405217782e-01 + 5.228000000000e-10 -3.087067361985e-01 + 5.328000000000e-10 -3.562070457914e-01 + 5.428000000000e-10 -3.915132320474e-01 + 5.528000000000e-10 -3.955548280332e-01 + 5.628000000000e-10 -3.283427048941e-01 + 5.728000000000e-10 -1.744282326244e-01 + 5.828000000000e-10 8.270645751064e-03 + 5.928000000000e-10 1.549582711486e-01 + 6.028000000000e-10 2.392860039329e-01 + 6.128000000000e-10 2.714820836214e-01 + 6.228000000000e-10 3.087161022039e-01 + 6.328000000000e-10 3.561494137047e-01 + 6.428000000000e-10 3.915273490759e-01 + 6.528000000000e-10 3.955079501007e-01 + 6.628000000000e-10 3.283677191723e-01 + 6.728000000000e-10 1.743944727908e-01 + 6.828000000000e-10 -8.238033211244e-03 + 6.928000000000e-10 -1.549849820320e-01 + 7.028000000000e-10 -2.392533741503e-01 + 7.128000000000e-10 -2.715088112944e-01 + 7.228000000000e-10 -3.086845279612e-01 + 7.328000000000e-10 -3.561786907982e-01 + 7.428000000000e-10 -3.914967682891e-01 + 7.528000000000e-10 -3.955360247734e-01 + 7.628000000000e-10 -3.283379458960e-01 + 7.728000000000e-10 -1.744219452106e-01 + 7.828000000000e-10 8.266285029230e-03 + 7.928000000000e-10 1.549592969714e-01 + 8.028000000000e-10 2.392805186707e-01 + 8.128000000000e-10 2.714837558368e-01 + 8.228000000000e-10 3.087120651005e-01 + 8.328000000000e-10 3.561520690508e-01 + 8.428000000000e-10 3.915233230940e-01 + 8.528000000000e-10 3.955100606400e-01 + 8.628000000000e-10 3.283632493206e-01 + 8.728000000000e-10 1.743968536756e-01 + 8.828000000000e-10 -8.241845610385e-03 + 8.928000000000e-10 -1.549825747228e-01 + 9.028000000000e-10 -2.392568734068e-01 + 9.128000000000e-10 -2.715063119250e-01 + 9.228000000000e-10 -3.086881712182e-01 + 9.328000000000e-10 -3.561760305782e-01 + 9.428000000000e-10 -3.915002731039e-01 + 9.528000000000e-10 -3.955331724158e-01 + 9.628000000000e-10 -3.283409163093e-01 + 9.728000000000e-10 -1.744193777973e-01 + 9.828000000000e-10 8.263272108901e-03 + 9.928000000000e-10 1.549616575981e-01 + 1.000000000000e-09 2.229820050464e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/conditions.yaml new file mode 100644 index 00000000..3d4d9340 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 21 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_21 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/CML_core_tb.sch new file mode 100644 index 00000000..3836095d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/CML_core_tb_22.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/CML_core_tb_22.data new file mode 100644 index 00000000..ef0e6c8e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/CML_core_tb_22.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.701426652476e-01 + 1.728000000000e-10 -1.295079168872e-01 + 1.828000000000e-10 4.028305902420e-02 + 1.928000000000e-10 1.769160181627e-01 + 2.028000000000e-10 2.543038782058e-01 + 2.128000000000e-10 2.828787064062e-01 + 2.228000000000e-10 3.193333275112e-01 + 2.328000000000e-10 3.660596632426e-01 + 2.428000000000e-10 3.993599084345e-01 + 2.528000000000e-10 4.007883413226e-01 + 2.628000000000e-10 3.312419521143e-01 + 2.728000000000e-10 1.754810620333e-01 + 2.828000000000e-10 -7.142746942805e-03 + 2.928000000000e-10 -1.527779354444e-01 + 3.028000000000e-10 -2.358001938178e-01 + 3.128000000000e-10 -2.668485168237e-01 + 3.228000000000e-10 -3.044746718514e-01 + 3.328000000000e-10 -3.525545062341e-01 + 3.428000000000e-10 -3.880254364838e-01 + 3.528000000000e-10 -3.926522183008e-01 + 3.628000000000e-10 -3.262954780243e-01 + 3.728000000000e-10 -1.733443838482e-01 + 3.828000000000e-10 7.573790689709e-03 + 3.928000000000e-10 1.523487073311e-01 + 4.028000000000e-10 2.353677758316e-01 + 4.128000000000e-10 2.665695097895e-01 + 4.228000000000e-10 3.044490522149e-01 + 4.328000000000e-10 3.524353166192e-01 + 4.428000000000e-10 3.879041587545e-01 + 4.528000000000e-10 3.923389296672e-01 + 4.628000000000e-10 3.259554596391e-01 + 4.728000000000e-10 1.728458619818e-01 + 4.828000000000e-10 -8.002573892585e-03 + 4.928000000000e-10 -1.528088090159e-01 + 5.028000000000e-10 -2.356747724378e-01 + 5.128000000000e-10 -2.668925685814e-01 + 5.228000000000e-10 -3.046638401901e-01 + 5.328000000000e-10 -3.527112223433e-01 + 5.428000000000e-10 -3.880786380631e-01 + 5.528000000000e-10 -3.925506229445e-01 + 5.628000000000e-10 -3.260495799326e-01 + 5.728000000000e-10 -1.729761662154e-01 + 5.828000000000e-10 7.974498187451e-03 + 5.928000000000e-10 1.527311696558e-01 + 6.028000000000e-10 2.356760074325e-01 + 6.128000000000e-10 2.668297167568e-01 + 6.228000000000e-10 3.046702367069e-01 + 6.328000000000e-10 3.526500635637e-01 + 6.428000000000e-10 3.880902250634e-01 + 6.528000000000e-10 3.925010528185e-01 + 6.628000000000e-10 3.260730653917e-01 + 6.728000000000e-10 1.729410953112e-01 + 6.828000000000e-10 -7.941970684065e-03 + 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-3.526772110923e-01 + 9.428000000000e-10 -3.880628732866e-01 + 9.528000000000e-10 -3.925266759429e-01 + 9.628000000000e-10 -3.260456785141e-01 + 9.728000000000e-10 -1.729665660062e-01 + 9.828000000000e-10 7.967487161613e-03 + 9.928000000000e-10 1.527347010769e-01 + 1.000000000000e-09 2.198236907112e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/conditions.yaml new file mode 100644 index 00000000..f61c2d5f --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 22 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_22 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/CML_core_tb.sch new file mode 100644 index 00000000..bf76a047 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/CML_core_tb_23.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/CML_core_tb_23.data new file mode 100644 index 00000000..7b2e7ab2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/CML_core_tb_23.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.957054612407e-01 + 1.728000000000e-10 -1.475216919691e-01 + 1.828000000000e-10 3.196996632833e-02 + 1.928000000000e-10 1.773696584526e-01 + 2.028000000000e-10 2.602670445343e-01 + 2.128000000000e-10 2.919684489720e-01 + 2.228000000000e-10 3.273690981683e-01 + 2.328000000000e-10 3.736661732429e-01 + 2.428000000000e-10 4.086769482098e-01 + 2.528000000000e-10 4.113258498473e-01 + 2.628000000000e-10 3.414272197123e-01 + 2.728000000000e-10 1.833836328070e-01 + 2.828000000000e-10 -4.501363849837e-03 + 2.928000000000e-10 -1.562318489881e-01 + 3.028000000000e-10 -2.435570784568e-01 + 3.128000000000e-10 -2.775386220390e-01 + 3.228000000000e-10 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2.778849719194e-01 + 8.228000000000e-10 3.147945034671e-01 + 8.328000000000e-10 3.622568751046e-01 + 8.428000000000e-10 3.989662140554e-01 + 8.528000000000e-10 4.041558823701e-01 + 8.628000000000e-10 3.369030769235e-01 + 8.728000000000e-10 1.809706945647e-01 + 8.828000000000e-10 -5.568483515763e-03 + 8.928000000000e-10 -1.566340912711e-01 + 9.028000000000e-10 -2.438236181184e-01 + 9.128000000000e-10 -2.779064153414e-01 + 9.228000000000e-10 -3.147718720666e-01 + 9.328000000000e-10 -3.622798572716e-01 + 9.428000000000e-10 -3.989444036153e-01 + 9.528000000000e-10 -4.041778978449e-01 + 9.628000000000e-10 -3.368819513246e-01 + 9.728000000000e-10 -1.809921012276e-01 + 9.828000000000e-10 5.588724287086e-03 + 9.928000000000e-10 1.566143682128e-01 + 1.000000000000e-09 2.267750497136e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/conditions.yaml new file mode 100644 index 00000000..58ee4146 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 23 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_23 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/CML_core_tb.sch new file mode 100644 index 00000000..30e2fa1b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/CML_core_tb_24.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/CML_core_tb_24.data new file mode 100644 index 00000000..a01deb89 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/CML_core_tb_24.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.908985659112e-01 + 1.728000000000e-10 -9.049079150817e-02 + 1.828000000000e-10 3.945873683219e-02 + 1.928000000000e-10 1.521437177417e-01 + 2.028000000000e-10 2.220068772324e-01 + 2.128000000000e-10 2.535092334052e-01 + 2.228000000000e-10 2.861973397174e-01 + 2.328000000000e-10 3.239843013312e-01 + 2.428000000000e-10 3.520113017607e-01 + 2.528000000000e-10 3.540468115658e-01 + 2.628000000000e-10 2.949447709683e-01 + 2.728000000000e-10 1.587983397866e-01 + 2.828000000000e-10 -6.865354773069e-03 + 2.928000000000e-10 -1.448078480843e-01 + 3.028000000000e-10 -2.275605338030e-01 + 3.128000000000e-10 -2.625604064747e-01 + 3.228000000000e-10 -2.958552078644e-01 + 3.328000000000e-10 -3.351711406638e-01 + 3.428000000000e-10 -3.644984224381e-01 + 3.528000000000e-10 -3.669950471097e-01 + 3.628000000000e-10 -3.072796408874e-01 + 3.728000000000e-10 -1.699866077827e-01 + 3.828000000000e-10 -2.842045316933e-03 + 3.928000000000e-10 1.365086891956e-01 + 4.028000000000e-10 2.207869920157e-01 + 4.128000000000e-10 2.567713461579e-01 + 4.228000000000e-10 2.907030026757e-01 + 4.328000000000e-10 3.302687598301e-01 + 4.428000000000e-10 3.600803190405e-01 + 4.528000000000e-10 3.632331450943e-01 + 4.628000000000e-10 3.045482678871e-01 + 4.728000000000e-10 1.682698274629e-01 + 4.828000000000e-10 2.058504292284e-03 + 4.928000000000e-10 -1.367871396964e-01 + 5.028000000000e-10 -2.207717990252e-01 + 5.128000000000e-10 -2.567684885934e-01 + 5.228000000000e-10 -2.906651825463e-01 + 5.328000000000e-10 -3.302494358660e-01 + 5.428000000000e-10 -3.599712284157e-01 + 5.528000000000e-10 -3.631239508150e-01 + 5.628000000000e-10 -3.043584109358e-01 + 5.728000000000e-10 -1.680958385636e-01 + 5.828000000000e-10 -1.834034512727e-03 + 5.928000000000e-10 1.369613450439e-01 + 6.028000000000e-10 2.209618957221e-01 + 6.128000000000e-10 2.568952536478e-01 + 6.228000000000e-10 2.908171185353e-01 + 6.328000000000e-10 3.303549214919e-01 + 6.428000000000e-10 3.601082390759e-01 + 6.528000000000e-10 3.632059905221e-01 + 6.628000000000e-10 3.044557238628e-01 + 6.728000000000e-10 1.681292777859e-01 + 6.828000000000e-10 1.882442241730e-03 + 6.928000000000e-10 -1.369637862409e-01 + 7.028000000000e-10 -2.209363992802e-01 + 7.128000000000e-10 -2.569065829626e-01 + 7.228000000000e-10 -2.907936706940e-01 + 7.328000000000e-10 -3.303682701482e-01 + 7.428000000000e-10 -3.600879594395e-01 + 7.528000000000e-10 -3.632220959958e-01 + 7.628000000000e-10 -3.044401007882e-01 + 7.728000000000e-10 -1.681486407544e-01 + 7.828000000000e-10 -1.870004957548e-03 + 7.928000000000e-10 1.369437070838e-01 + 8.028000000000e-10 2.209481957039e-01 + 8.128000000000e-10 2.568879030180e-01 + 8.228000000000e-10 2.908064848389e-01 + 8.328000000000e-10 3.303493303219e-01 + 8.428000000000e-10 3.601006147126e-01 + 8.528000000000e-10 3.632041339109e-01 + 8.628000000000e-10 3.044528281549e-01 + 8.728000000000e-10 1.681322760827e-01 + 8.828000000000e-10 1.883536763259e-03 + 8.928000000000e-10 -1.369582535540e-01 + 9.028000000000e-10 -2.209346296842e-01 + 9.128000000000e-10 -2.569016830366e-01 + 9.228000000000e-10 -2.907925936742e-01 + 9.328000000000e-10 -3.303636164667e-01 + 9.428000000000e-10 -3.600871302257e-01 + 9.528000000000e-10 -3.632178492939e-01 + 9.628000000000e-10 -3.044398392752e-01 + 9.728000000000e-10 -1.681454261603e-01 + 9.828000000000e-10 -1.870628705438e-03 + 9.928000000000e-10 1.369459433541e-01 + 1.000000000000e-09 2.037746084522e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/conditions.yaml new file mode 100644 index 00000000..7f7d0098 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 24 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_24 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/CML_core_tb.sch new file mode 100644 index 00000000..5f457e9d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/CML_core_tb_25.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/CML_core_tb_25.data new file mode 100644 index 00000000..182746dc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/CML_core_tb_25.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.878715792581e-01 + 1.728000000000e-10 -8.812036120597e-02 + 1.828000000000e-10 4.046526586524e-02 + 1.928000000000e-10 1.515705626527e-01 + 2.028000000000e-10 2.200566198342e-01 + 2.128000000000e-10 2.503583455541e-01 + 2.228000000000e-10 2.832914205797e-01 + 2.328000000000e-10 3.216696186231e-01 + 2.428000000000e-10 3.500303926946e-01 + 2.528000000000e-10 3.524815741411e-01 + 2.628000000000e-10 2.936462106779e-01 + 2.728000000000e-10 1.576219496242e-01 + 2.828000000000e-10 -7.121462127754e-03 + 2.928000000000e-10 -1.436071598858e-01 + 3.028000000000e-10 -2.249496922999e-01 + 3.128000000000e-10 -2.586592240194e-01 + 3.228000000000e-10 -2.922419569702e-01 + 3.328000000000e-10 -3.321983211521e-01 + 3.428000000000e-10 -3.618684381611e-01 + 3.528000000000e-10 -3.648249016007e-01 + 3.628000000000e-10 -3.055379959953e-01 + 3.728000000000e-10 -1.686105488568e-01 + 3.828000000000e-10 -2.582643774162e-03 + 3.928000000000e-10 1.352182085241e-01 + 4.028000000000e-10 2.180702244722e-01 + 4.128000000000e-10 2.527783389641e-01 + 4.228000000000e-10 2.869845016096e-01 + 4.328000000000e-10 3.271697550530e-01 + 4.428000000000e-10 3.573213651505e-01 + 4.528000000000e-10 3.609341509143e-01 + 4.628000000000e-10 3.026708512688e-01 + 4.728000000000e-10 1.667591862946e-01 + 4.828000000000e-10 1.676053368052e-03 + 4.928000000000e-10 -1.356064331336e-01 + 5.028000000000e-10 -2.181494577446e-01 + 5.128000000000e-10 -2.528581012316e-01 + 5.228000000000e-10 -2.870203472690e-01 + 5.328000000000e-10 -3.272198972187e-01 + 5.428000000000e-10 -3.572767955086e-01 + 5.528000000000e-10 -3.608816832152e-01 + 5.628000000000e-10 -3.025243774497e-01 + 5.728000000000e-10 -1.666129730216e-01 + 5.828000000000e-10 -1.465204057357e-03 + 5.928000000000e-10 1.357749931272e-01 + 6.028000000000e-10 2.183376260095e-01 + 6.128000000000e-10 2.529831758691e-01 + 6.228000000000e-10 2.871716452249e-01 + 6.328000000000e-10 3.273254918206e-01 + 6.428000000000e-10 3.574148326524e-01 + 6.528000000000e-10 3.609652866209e-01 + 6.628000000000e-10 3.026246199120e-01 + 6.728000000000e-10 1.666502220733e-01 + 6.828000000000e-10 1.518129196282e-03 + 6.928000000000e-10 -1.357732099566e-01 + 7.028000000000e-10 -2.183080403425e-01 + 7.128000000000e-10 -2.529912058397e-01 + 7.228000000000e-10 -2.871450109118e-01 + 7.328000000000e-10 -3.273360198503e-01 + 7.428000000000e-10 -3.573916245859e-01 + 7.528000000000e-10 -3.609790664977e-01 + 7.628000000000e-10 -3.026068066478e-01 + 7.728000000000e-10 -1.666683959674e-01 + 7.828000000000e-10 -1.504711775466e-03 + 7.928000000000e-10 1.357534602326e-01 + 8.028000000000e-10 2.183202914392e-01 + 8.128000000000e-10 2.529726082081e-01 + 8.228000000000e-10 2.871582302084e-01 + 8.328000000000e-10 3.273171284192e-01 + 8.428000000000e-10 3.574045685766e-01 + 8.528000000000e-10 3.609610284998e-01 + 8.628000000000e-10 3.026196909841e-01 + 8.728000000000e-10 1.666518528053e-01 + 8.828000000000e-10 1.518315117290e-03 + 8.928000000000e-10 -1.357682747942e-01 + 9.028000000000e-10 -2.183066580359e-01 + 9.128000000000e-10 -2.529866332266e-01 + 9.228000000000e-10 -2.871442829871e-01 + 9.328000000000e-10 -3.273316607928e-01 + 9.428000000000e-10 -3.573910212469e-01 + 9.528000000000e-10 -3.609749965926e-01 + 9.628000000000e-10 -3.026065830591e-01 + 9.728000000000e-10 -1.666652414066e-01 + 9.828000000000e-10 -1.505286118034e-03 + 9.928000000000e-10 1.357557668798e-01 + 1.000000000000e-09 2.016242513907e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/conditions.yaml new file mode 100644 index 00000000..32bc6355 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 25 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_25 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/CML_core_tb.sch new file mode 100644 index 00000000..b9f23b35 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/CML_core_tb_26.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/CML_core_tb_26.data new file mode 100644 index 00000000..c21b093d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/CML_core_tb_26.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.135873679018e-01 + 1.728000000000e-10 -1.054229355639e-01 + 1.828000000000e-10 3.485798650969e-02 + 1.928000000000e-10 1.569675139767e-01 + 2.028000000000e-10 2.330635404696e-01 + 2.128000000000e-10 2.680443549179e-01 + 2.228000000000e-10 3.014044829899e-01 + 2.328000000000e-10 3.394080314353e-01 + 2.428000000000e-10 3.679529618424e-01 + 2.528000000000e-10 3.700593040123e-01 + 2.628000000000e-10 3.097824620429e-01 + 2.728000000000e-10 1.706514675999e-01 + 2.828000000000e-10 3.558070014658e-04 + 2.928000000000e-10 -1.428409974599e-01 + 3.028000000000e-10 -2.298289579719e-01 + 3.128000000000e-10 -2.678794741753e-01 + 3.228000000000e-10 -3.017454056957e-01 + 3.328000000000e-10 -3.410620518407e-01 + 3.428000000000e-10 -3.712405389398e-01 + 3.528000000000e-10 -3.749327973471e-01 + 3.628000000000e-10 -3.157484466493e-01 + 3.728000000000e-10 -1.773087198166e-01 + 3.828000000000e-10 -7.070252178339e-03 + 3.928000000000e-10 1.364462941621e-01 + 4.028000000000e-10 2.243241068758e-01 + 4.128000000000e-10 2.631279769125e-01 + 4.228000000000e-10 2.976097246349e-01 + 4.328000000000e-10 3.371159716785e-01 + 4.428000000000e-10 3.676405775058e-01 + 4.528000000000e-10 3.717787254056e-01 + 4.628000000000e-10 3.133854979421e-01 + 4.728000000000e-10 1.756870158595e-01 + 4.828000000000e-10 6.171257018760e-03 + 4.928000000000e-10 -1.369680995621e-01 + 5.028000000000e-10 -2.245781248931e-01 + 5.128000000000e-10 -2.633829468620e-01 + 5.228000000000e-10 -2.978042748481e-01 + 5.328000000000e-10 -3.373348877854e-01 + 5.428000000000e-10 -3.677584906255e-01 + 5.528000000000e-10 -3.718812762918e-01 + 5.628000000000e-10 -3.133649557524e-01 + 5.728000000000e-10 -1.756479312047e-01 + 5.828000000000e-10 -6.040608056278e-03 + 5.928000000000e-10 1.370690415770e-01 + 6.028000000000e-10 2.247181767783e-01 + 6.128000000000e-10 2.634617265965e-01 + 6.228000000000e-10 2.979157296699e-01 + 6.328000000000e-10 3.373958940353e-01 + 6.428000000000e-10 3.678612954525e-01 + 6.528000000000e-10 3.719309221475e-01 + 6.628000000000e-10 3.134447453066e-01 + 6.728000000000e-10 1.756687688086e-01 + 6.828000000000e-10 6.090200135509e-03 + 6.928000000000e-10 -1.370702307281e-01 + 7.028000000000e-10 -2.246847420648e-01 + 7.128000000000e-10 -2.634701196121e-01 + 7.228000000000e-10 -2.978849158722e-01 + 7.328000000000e-10 -3.374068878437e-01 + 7.428000000000e-10 -3.678336110941e-01 + 7.528000000000e-10 -3.719446503824e-01 + 7.628000000000e-10 -3.134227431793e-01 + 7.728000000000e-10 -1.756868885858e-01 + 7.828000000000e-10 -6.072676723321e-03 + 7.928000000000e-10 1.370503070743e-01 + 8.028000000000e-10 2.247004966695e-01 + 8.128000000000e-10 2.634509722982e-01 + 8.228000000000e-10 2.979013793804e-01 + 8.328000000000e-10 3.373870921905e-01 + 8.428000000000e-10 3.678495602861e-01 + 8.528000000000e-10 3.719256264749e-01 + 8.628000000000e-10 3.134381864470e-01 + 8.728000000000e-10 1.756688935561e-01 + 8.828000000000e-10 6.088345643719e-03 + 8.928000000000e-10 -1.370666831053e-01 + 9.028000000000e-10 -2.246851372638e-01 + 9.128000000000e-10 -2.634666121684e-01 + 9.228000000000e-10 -2.978856025968e-01 + 9.328000000000e-10 -3.374033621769e-01 + 9.428000000000e-10 -3.678342837151e-01 + 9.528000000000e-10 -3.719412125322e-01 + 9.628000000000e-10 -3.134235677100e-01 + 9.728000000000e-10 -1.756838495744e-01 + 9.828000000000e-10 -6.073781243164e-03 + 9.928000000000e-10 1.370527135588e-01 + 1.000000000000e-09 2.065229990524e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/conditions.yaml new file mode 100644 index 00000000..7bd57a54 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 26 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/run_26 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..1c9074b8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,28 @@ +run,corner,temperature,vdd,time,vo_diff,frequency +run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.111e-01, -1.870e-01, -3.563e-02, …]",4.722e+09 +run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.099e-01, -1.895e-01, -4.060e-02, …]",4.722e+09 +run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.876e-01, -3.217e-02, …]",4.722e+09 +run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.915e-01, -1.780e-01, -3.803e-02, …]",4.722e+09 +run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.909e-01, -1.806e-01, -4.276e-02, …]",4.722e+09 +run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.959e-01, -1.792e-01, -3.599e-02, …]",4.722e+09 +run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.689e-01, -1.692e-01, -4.423e-02, …]",4.722e+09 +run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.694e-01, -1.722e-01, -4.907e-02, …]",4.722e+09 +run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.723e-01, -1.701e-01, -4.252e-02, …]",4.722e+09 +run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.623e-01, -1.963e-01, -5.713e-03, …]",4.722e+09 +run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.622e-01, -1.984e-01, -1.024e-02, …]",4.722e+09 +run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.669e-01, -1.979e-01, -3.070e-03, …]",4.722e+09 +run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",4.722e+09 +run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.407e-01, -1.880e-01, -9.263e-03, …]",4.722e+09 +run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.446e-01, -1.889e-01, -5.355e-03, …]",4.722e+09 +run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.832e-01, -1.548e-01, 2.955e-03, …]",4.722e+09 +run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.908e-01, -1.609e-01, -2.321e-03, …]",4.722e+09 +run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.858e-01, -1.573e-01, 2.540e-03, …]",4.722e+09 +run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.214e-01, -1.558e-01, 3.477e-02, …]",4.722e+09 +run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.529e-01, 3.475e-02, …]",4.722e+09 +run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.365e-01, -1.657e-01, 3.100e-02, …]",4.722e+09 +run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.748e-01, -1.328e-01, 3.931e-02, …]",4.722e+09 +run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.701e-01, -1.295e-01, 4.028e-02, …]",4.722e+09 +run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.957e-01, -1.475e-01, 3.197e-02, …]",4.722e+09 +run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.909e-01, -9.049e-02, 3.946e-02, …]",4.722e+09 +run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.879e-01, -8.812e-02, 4.047e-02, …]",4.722e+09 +run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.136e-01, -1.054e-01, 3.486e-02, …]",4.722e+09 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..31c8cc54 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/Frequency/simulation_summary.md @@ -0,0 +1,31 @@ +# Simulation Summary for Freq + +| run | corner | temperature | vdd | time | vo_diff | frequency | +| :-- | -----: | ----------: | --: | ---: | ------: | --------: | +| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.111e-01, -1.870e-01, -3.563e-02, …] | 4.722e+09 | +| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.099e-01, -1.895e-01, -4.060e-02, …] | 4.722e+09 | +| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.876e-01, -3.217e-02, …] | 4.722e+09 | +| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.915e-01, -1.780e-01, -3.803e-02, …] | 4.722e+09 | +| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.909e-01, -1.806e-01, -4.276e-02, …] | 4.722e+09 | +| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.959e-01, -1.792e-01, -3.599e-02, …] | 4.722e+09 | +| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.689e-01, -1.692e-01, -4.423e-02, …] | 4.722e+09 | +| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.694e-01, -1.722e-01, -4.907e-02, …] | 4.722e+09 | +| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.723e-01, -1.701e-01, -4.252e-02, …] | 4.722e+09 | +| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.623e-01, -1.963e-01, -5.713e-03, …] | 4.722e+09 | +| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.622e-01, -1.984e-01, -1.024e-02, …] | 4.722e+09 | +| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.669e-01, -1.979e-01, -3.070e-03, …] | 4.722e+09 | +| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 4.722e+09 | +| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.407e-01, -1.880e-01, -9.263e-03, …] | 4.722e+09 | +| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.446e-01, -1.889e-01, -5.355e-03, …] | 4.722e+09 | +| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.832e-01, -1.548e-01, 2.955e-03, …] | 4.722e+09 | +| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.908e-01, -1.609e-01, -2.321e-03, …] | 4.722e+09 | +| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.858e-01, -1.573e-01, 2.540e-03, …] | 4.722e+09 | +| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.214e-01, -1.558e-01, 3.477e-02, …] | 4.722e+09 | +| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.529e-01, 3.475e-02, …] | 4.722e+09 | +| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.365e-01, -1.657e-01, 3.100e-02, …] | 4.722e+09 | +| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.748e-01, -1.328e-01, 3.931e-02, …] | 4.722e+09 | +| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.701e-01, -1.295e-01, 4.028e-02, …] | 4.722e+09 | +| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.957e-01, -1.475e-01, 3.197e-02, …] | 4.722e+09 | +| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.909e-01, -9.049e-02, 3.946e-02, …] | 4.722e+09 | +| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.879e-01, -8.812e-02, 4.047e-02, …] | 4.722e+09 | +| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.136e-01, -1.054e-01, 3.486e-02, …] | 4.722e+09 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/CML_core_tb.sch new file mode 100644 index 00000000..e5ea876a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/CML_core_tb_0.data new file mode 100644 index 00000000..4cb5b399 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.110742996065e-01 + 1.728000000000e-10 -1.869505717284e-01 + 1.828000000000e-10 -3.563037101706e-02 + 1.928000000000e-10 1.056708524540e-01 + 2.028000000000e-10 2.100393804445e-01 + 2.128000000000e-10 2.784249297688e-01 + 2.228000000000e-10 3.224310579067e-01 + 2.328000000000e-10 3.548600651170e-01 + 2.428000000000e-10 3.792482005271e-01 + 2.528000000000e-10 3.740820324036e-01 + 2.628000000000e-10 3.079440308227e-01 + 2.728000000000e-10 1.813826171807e-01 + 2.828000000000e-10 2.923027813912e-02 + 2.928000000000e-10 -1.118282325615e-01 + 3.028000000000e-10 -2.157337068367e-01 + 3.128000000000e-10 -2.829033176767e-01 + 3.228000000000e-10 -3.260714502323e-01 + 3.328000000000e-10 -3.577361248183e-01 + 3.428000000000e-10 -3.819104006606e-01 + 3.528000000000e-10 -3.764730474160e-01 + 3.628000000000e-10 -3.102968359246e-01 + 3.728000000000e-10 -1.832608913655e-01 + 3.828000000000e-10 -3.084931437320e-02 + 3.928000000000e-10 1.106163095990e-01 + 4.028000000000e-10 2.145714971977e-01 + 4.128000000000e-10 2.819937231053e-01 + 4.228000000000e-10 3.251740998910e-01 + 4.328000000000e-10 3.570946969464e-01 + 4.428000000000e-10 3.813004444382e-01 + 4.528000000000e-10 3.761230596147e-01 + 4.628000000000e-10 3.099646053412e-01 + 4.728000000000e-10 1.831473345022e-01 + 4.828000000000e-10 3.069401022130e-02 + 4.928000000000e-10 -1.106258411343e-01 + 5.028000000000e-10 -2.146793601179e-01 + 5.128000000000e-10 -2.820035552799e-01 + 5.228000000000e-10 -3.252909243829e-01 + 5.328000000000e-10 -3.570986338553e-01 + 5.428000000000e-10 -3.813904658256e-01 + 5.528000000000e-10 -3.760889514061e-01 + 5.628000000000e-10 -3.100114096943e-01 + 5.728000000000e-10 -1.830827247194e-01 + 5.828000000000e-10 -3.072480545922e-02 + 5.928000000000e-10 1.106906463094e-01 + 6.028000000000e-10 2.146493837568e-01 + 6.128000000000e-10 2.820610673881e-01 + 6.228000000000e-10 3.252525482967e-01 + 6.328000000000e-10 3.571504708749e-01 + 6.428000000000e-10 3.813516648295e-01 + 6.528000000000e-10 3.761390656738e-01 + 6.628000000000e-10 3.099742259389e-01 + 6.728000000000e-10 1.831331110808e-01 + 6.828000000000e-10 3.068765829312e-02 + 6.928000000000e-10 -1.106445812930e-01 + 7.028000000000e-10 -2.146859050297e-01 + 7.128000000000e-10 -2.820172231683e-01 + 7.228000000000e-10 -3.252905125649e-01 + 7.328000000000e-10 -3.571078709926e-01 + 7.428000000000e-10 -3.813893177320e-01 + 7.528000000000e-10 -3.760986555866e-01 + 7.628000000000e-10 -3.100117776476e-01 + 7.728000000000e-10 -1.830935153198e-01 + 7.828000000000e-10 -3.072484475908e-02 + 7.928000000000e-10 1.106810594907e-01 + 8.028000000000e-10 2.146507312123e-01 + 8.128000000000e-10 2.820530370402e-01 + 8.228000000000e-10 3.252547871433e-01 + 8.328000000000e-10 3.571432636036e-01 + 8.428000000000e-10 3.813547544577e-01 + 8.528000000000e-10 3.761324372121e-01 + 8.628000000000e-10 3.099775475493e-01 + 8.728000000000e-10 1.831274535707e-01 + 8.828000000000e-10 3.069175078476e-02 + 8.928000000000e-10 -1.106491559136e-01 + 9.028000000000e-10 -2.146821655528e-01 + 9.128000000000e-10 -2.820218639330e-01 + 9.228000000000e-10 -3.252864642203e-01 + 9.328000000000e-10 -3.571122611941e-01 + 9.428000000000e-10 -3.813854215351e-01 + 9.528000000000e-10 -3.761024723822e-01 + 9.628000000000e-10 -3.100075395903e-01 + 9.728000000000e-10 -1.830975404653e-01 + 9.828000000000e-10 -3.072097080048e-02 + 9.928000000000e-10 1.106770531472e-01 + 1.000000000000e-09 1.895325033433e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/conditions.yaml new file mode 100644 index 00000000..d2b75cc9 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_00 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/CML_core_tb.sch new file mode 100644 index 00000000..31fd1993 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/CML_core_tb_1.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/CML_core_tb_1.data new file mode 100644 index 00000000..2b8492c0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/CML_core_tb_1.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.098686002716e-01 + 1.728000000000e-10 -1.894560696460e-01 + 1.828000000000e-10 -4.059695742871e-02 + 1.928000000000e-10 9.940964501315e-02 + 2.028000000000e-10 2.033133834097e-01 + 2.128000000000e-10 2.719620830710e-01 + 2.228000000000e-10 3.163098950569e-01 + 2.328000000000e-10 3.491513279687e-01 + 2.428000000000e-10 3.741332087119e-01 + 2.528000000000e-10 3.700254590965e-01 + 2.628000000000e-10 3.062168938694e-01 + 2.728000000000e-10 1.827341653261e-01 + 2.828000000000e-10 3.280764574542e-02 + 2.928000000000e-10 -1.069769977212e-01 + 3.028000000000e-10 -2.102924295592e-01 + 3.128000000000e-10 -2.774748738503e-01 + 3.228000000000e-10 -3.207751929169e-01 + 3.328000000000e-10 -3.527202709264e-01 + 3.428000000000e-10 -3.774342269369e-01 + 3.528000000000e-10 -3.730540733905e-01 + 3.628000000000e-10 -3.091949741363e-01 + 3.728000000000e-10 -1.851642002832e-01 + 3.828000000000e-10 -3.487935842603e-02 + 3.928000000000e-10 1.053970083053e-01 + 4.028000000000e-10 2.088131472734e-01 + 4.128000000000e-10 2.762908135843e-01 + 4.228000000000e-10 3.196385089100e-01 + 4.328000000000e-10 3.518763575372e-01 + 4.428000000000e-10 3.766558038448e-01 + 4.528000000000e-10 3.725714207051e-01 + 4.628000000000e-10 3.087619830708e-01 + 4.728000000000e-10 1.849833837695e-01 + 4.828000000000e-10 3.467977975354e-02 + 4.928000000000e-10 -1.054340839288e-01 + 5.028000000000e-10 -2.089448612506e-01 + 5.128000000000e-10 -2.763231704068e-01 + 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-3.088133010441e-01 + 7.728000000000e-10 -1.849285593480e-01 + 7.828000000000e-10 -3.470862903587e-02 + 7.928000000000e-10 1.054936381918e-01 + 8.028000000000e-10 2.089186129636e-01 + 8.128000000000e-10 2.763755879874e-01 + 8.228000000000e-10 3.197437164625e-01 + 8.328000000000e-10 3.519463479929e-01 + 8.428000000000e-10 3.767260853907e-01 + 8.528000000000e-10 3.725904126785e-01 + 8.628000000000e-10 3.087783440951e-01 + 8.728000000000e-10 1.849632167070e-01 + 8.828000000000e-10 3.467482549783e-02 + 8.928000000000e-10 -1.054610682584e-01 + 9.028000000000e-10 -2.089507846182e-01 + 9.128000000000e-10 -2.763436586770e-01 + 9.228000000000e-10 -3.197760754687e-01 + 9.328000000000e-10 -3.519146615050e-01 + 9.428000000000e-10 -3.767573997120e-01 + 9.528000000000e-10 -3.725597535055e-01 + 9.628000000000e-10 -3.088090609970e-01 + 9.728000000000e-10 -1.849326628321e-01 + 9.828000000000e-10 -3.470475490247e-02 + 9.928000000000e-10 1.054896146910e-01 + 1.000000000000e-09 1.838520001242e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/conditions.yaml new file mode 100644 index 00000000..d52ae0b6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 1 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_01 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/CML_core_tb.sch new file mode 100644 index 00000000..4d076e38 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/CML_core_tb_2.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/CML_core_tb_2.data new file mode 100644 index 00000000..b332ca2c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/CML_core_tb_2.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162797108708e-01 + 1.728000000000e-10 -1.875883768906e-01 + 1.828000000000e-10 -3.217177564589e-02 + 1.928000000000e-10 1.118453904517e-01 + 2.028000000000e-10 2.178869753922e-01 + 2.128000000000e-10 2.869187499571e-01 + 2.228000000000e-10 3.311831063176e-01 + 2.328000000000e-10 3.637965093552e-01 + 2.428000000000e-10 3.884475585753e-01 + 2.528000000000e-10 3.831703446637e-01 + 2.628000000000e-10 3.149426000366e-01 + 2.728000000000e-10 1.840825734866e-01 + 2.828000000000e-10 2.786370536806e-02 + 2.928000000000e-10 -1.159899232258e-01 + 3.028000000000e-10 -2.217323928122e-01 + 3.128000000000e-10 -2.897841810826e-01 + 3.228000000000e-10 -3.334256487170e-01 + 3.328000000000e-10 -3.654508602495e-01 + 3.428000000000e-10 -3.900407544937e-01 + 3.528000000000e-10 -3.846189534315e-01 + 3.628000000000e-10 -3.164922452622e-01 + 3.728000000000e-10 -1.853182634851e-01 + 3.828000000000e-10 -2.898615964086e-02 + 3.928000000000e-10 1.151710782521e-01 + 4.028000000000e-10 2.209054309263e-01 + 4.128000000000e-10 2.891817322742e-01 + 4.228000000000e-10 3.328077516782e-01 + 4.328000000000e-10 3.650515838921e-01 + 4.428000000000e-10 3.896233583948e-01 + 4.528000000000e-10 3.844074302627e-01 + 4.628000000000e-10 3.162448842688e-01 + 4.728000000000e-10 1.852475068120e-01 + 4.828000000000e-10 2.884623360652e-02 + 4.928000000000e-10 -1.151788252337e-01 + 5.028000000000e-10 -2.210147130581e-01 + 5.128000000000e-10 -2.891872658193e-01 + 5.228000000000e-10 -3.329167168088e-01 + 5.328000000000e-10 -3.650471930963e-01 + 5.428000000000e-10 -3.897100874545e-01 + 5.528000000000e-10 -3.843762306477e-01 + 5.628000000000e-10 -3.163013912188e-01 + 5.728000000000e-10 -1.851950213487e-01 + 5.828000000000e-10 -2.889036873678e-02 + 5.928000000000e-10 1.152312899162e-01 + 6.028000000000e-10 2.209735588305e-01 + 6.128000000000e-10 2.892357416511e-01 + 6.228000000000e-10 3.328707955285e-01 + 6.328000000000e-10 3.650931065031e-01 + 6.428000000000e-10 3.896657987149e-01 + 6.528000000000e-10 3.844215105032e-01 + 6.628000000000e-10 3.162596917265e-01 + 6.728000000000e-10 1.852417351036e-01 + 6.828000000000e-10 2.884992827621e-02 + 6.928000000000e-10 -1.151876679011e-01 + 7.028000000000e-10 -2.210123101756e-01 + 7.128000000000e-10 -2.891938845816e-01 + 7.228000000000e-10 -3.329106389600e-01 + 7.328000000000e-10 -3.650518039465e-01 + 7.428000000000e-10 -3.897047407363e-01 + 7.528000000000e-10 -3.843819858648e-01 + 7.628000000000e-10 -3.162978744015e-01 + 7.728000000000e-10 -1.852023753321e-01 + 7.828000000000e-10 -2.888743165850e-02 + 7.928000000000e-10 1.152240030808e-01 + 8.028000000000e-10 2.209771419031e-01 + 8.128000000000e-10 2.892295361788e-01 + 8.228000000000e-10 3.328747680971e-01 + 8.328000000000e-10 3.650871456099e-01 + 8.428000000000e-10 3.896701175780e-01 + 8.528000000000e-10 3.844156912621e-01 + 8.628000000000e-10 3.162637401476e-01 + 8.728000000000e-10 1.852363586492e-01 + 8.828000000000e-10 2.885434112124e-02 + 8.928000000000e-10 -1.151920978903e-01 + 9.028000000000e-10 -2.210084087345e-01 + 9.128000000000e-10 -2.891984388712e-01 + 9.228000000000e-10 -3.329064027155e-01 + 9.328000000000e-10 -3.650560988894e-01 + 9.428000000000e-10 -3.897007143418e-01 + 9.528000000000e-10 -3.843858173814e-01 + 9.628000000000e-10 -3.162935974835e-01 + 9.728000000000e-10 -1.852064424274e-01 + 9.828000000000e-10 -2.888350905479e-02 + 9.928000000000e-10 1.152199079204e-01 + 1.000000000000e-09 1.954791142410e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/conditions.yaml new file mode 100644 index 00000000..ede84efb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 2 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_02 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/CML_core_tb.sch new file mode 100644 index 00000000..00317020 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/CML_core_tb_3.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/CML_core_tb_3.data new file mode 100644 index 00000000..6dccbfd6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/CML_core_tb_3.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.914571027454e-01 + 1.728000000000e-10 -1.780117263272e-01 + 1.828000000000e-10 -3.802564096594e-02 + 1.928000000000e-10 9.479025580261e-02 + 2.028000000000e-10 1.961220444980e-01 + 2.128000000000e-10 2.643669322964e-01 + 2.228000000000e-10 3.071498875260e-01 + 2.328000000000e-10 3.351667250191e-01 + 2.428000000000e-10 3.529478733093e-01 + 2.528000000000e-10 3.439767079911e-01 + 2.628000000000e-10 2.827109934029e-01 + 2.728000000000e-10 1.683025534555e-01 + 2.828000000000e-10 2.843266655337e-02 + 2.928000000000e-10 -1.036223502576e-01 + 3.028000000000e-10 -2.042863713809e-01 + 3.128000000000e-10 -2.713818104821e-01 + 3.228000000000e-10 -3.132717880322e-01 + 3.328000000000e-10 -3.402903477971e-01 + 3.428000000000e-10 -3.574262556597e-01 + 3.528000000000e-10 -3.476240566503e-01 + 3.628000000000e-10 -2.857203755187e-01 + 3.728000000000e-10 -1.703849236420e-01 + 3.828000000000e-10 -2.994825869373e-02 + 3.928000000000e-10 1.026817167876e-01 + 4.028000000000e-10 2.034750084544e-01 + 4.128000000000e-10 2.707812081585e-01 + 4.228000000000e-10 3.126503625184e-01 + 4.328000000000e-10 3.399043734480e-01 + 4.428000000000e-10 3.571021595385e-01 + 4.528000000000e-10 3.475896983741e-01 + 4.628000000000e-10 2.857411927694e-01 + 4.728000000000e-10 1.706053611761e-01 + 4.828000000000e-10 3.010795594348e-02 + 4.928000000000e-10 -1.024135388755e-01 + 5.028000000000e-10 -2.033190471438e-01 + 5.128000000000e-10 -2.705615444577e-01 + 5.228000000000e-10 -3.125558523975e-01 + 5.328000000000e-10 -3.397330193449e-01 + 5.428000000000e-10 -3.570354300338e-01 + 5.528000000000e-10 -3.474353611027e-01 + 5.628000000000e-10 -2.856876769732e-01 + 5.728000000000e-10 -1.704760895977e-01 + 5.828000000000e-10 -3.008641427314e-02 + 5.928000000000e-10 1.025087996136e-01 + 6.028000000000e-10 2.033209986443e-01 + 6.128000000000e-10 2.706412375819e-01 + 6.228000000000e-10 3.125457575810e-01 + 6.328000000000e-10 3.398008382665e-01 + 6.428000000000e-10 3.570145583479e-01 + 6.528000000000e-10 3.474888598072e-01 + 6.628000000000e-10 2.856551852535e-01 + 6.728000000000e-10 1.705188293935e-01 + 6.828000000000e-10 3.004736925580e-02 + 6.928000000000e-10 -1.024728514478e-01 + 7.028000000000e-10 -2.033602328622e-01 + 7.128000000000e-10 -2.706061106716e-01 + 7.228000000000e-10 -3.125843283316e-01 + 7.328000000000e-10 -3.397655433228e-01 + 7.428000000000e-10 -3.570523646632e-01 + 7.528000000000e-10 -3.474554820929e-01 + 7.628000000000e-10 -2.856929985560e-01 + 7.728000000000e-10 -1.704859799650e-01 + 7.828000000000e-10 -3.008383757896e-02 + 7.928000000000e-10 1.025039608177e-01 + 8.028000000000e-10 2.033261442763e-01 + 8.128000000000e-10 2.706371082838e-01 + 8.228000000000e-10 3.125504649737e-01 + 8.328000000000e-10 3.397966066528e-01 + 8.428000000000e-10 3.570198965640e-01 + 8.528000000000e-10 3.474857187206e-01 + 8.628000000000e-10 2.856614378232e-01 + 8.728000000000e-10 1.705164607562e-01 + 8.828000000000e-10 3.005354621749e-02 + 8.928000000000e-10 -1.024749769036e-01 + 9.028000000000e-10 -2.033548454455e-01 + 9.128000000000e-10 -2.706087008930e-01 + 9.228000000000e-10 -3.125792630790e-01 + 9.328000000000e-10 -3.397683901773e-01 + 9.428000000000e-10 -3.570478314069e-01 + 9.528000000000e-10 -3.474583427153e-01 + 9.628000000000e-10 -2.856887110961e-01 + 9.728000000000e-10 -1.704892548593e-01 + 9.828000000000e-10 -3.008001356704e-02 + 9.928000000000e-10 1.025005080892e-01 + 1.000000000000e-09 1.786649040194e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/conditions.yaml new file mode 100644 index 00000000..b2ba9603 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 3 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_03 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/CML_core_tb.sch new file mode 100644 index 00000000..37684dfa --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/CML_core_tb_4.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/CML_core_tb_4.data new file mode 100644 index 00000000..3efc8a54 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/CML_core_tb_4.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908886906683e-01 + 1.728000000000e-10 -1.805890382926e-01 + 1.828000000000e-10 -4.276329247682e-02 + 1.928000000000e-10 8.882407595099e-02 + 2.028000000000e-10 1.894983505466e-01 + 2.128000000000e-10 2.576242567207e-01 + 2.228000000000e-10 3.005212718886e-01 + 2.328000000000e-10 3.289546768723e-01 + 2.428000000000e-10 3.474240530436e-01 + 2.528000000000e-10 3.394794629215e-01 + 2.628000000000e-10 2.802266193594e-01 + 2.728000000000e-10 1.685520573893e-01 + 2.828000000000e-10 3.081792474830e-02 + 2.928000000000e-10 -9.985913249602e-02 + 3.028000000000e-10 -1.996535082954e-01 + 3.128000000000e-10 -2.663519845580e-01 + 3.228000000000e-10 -3.081166100610e-01 + 3.328000000000e-10 -3.353557582557e-01 + 3.428000000000e-10 -3.530339682910e-01 + 3.528000000000e-10 -3.441234226063e-01 + 3.628000000000e-10 -2.840838930007e-01 + 3.728000000000e-10 -1.712890179908e-01 + 3.828000000000e-10 -3.280692441870e-02 + 3.928000000000e-10 9.858702888345e-02 + 4.028000000000e-10 1.985844458095e-01 + 4.128000000000e-10 2.655374220709e-01 + 4.228000000000e-10 3.073092043222e-01 + 4.328000000000e-10 3.348254361967e-01 + 4.428000000000e-10 3.526065806553e-01 + 4.528000000000e-10 3.440384505411e-01 + 4.628000000000e-10 2.840943593119e-01 + 4.728000000000e-10 1.715352376725e-01 + 4.828000000000e-10 3.300625747524e-02 + 4.928000000000e-10 -9.826793525126e-02 + 5.028000000000e-10 -1.983826392696e-01 + 5.128000000000e-10 -2.652748957302e-01 + 5.228000000000e-10 -3.071819372703e-01 + 5.328000000000e-10 -3.346211766496e-01 + 5.428000000000e-10 -3.525115401756e-01 + 5.528000000000e-10 -3.438520776438e-01 + 5.628000000000e-10 -2.840132934403e-01 + 5.728000000000e-10 -1.713783534881e-01 + 5.828000000000e-10 -3.296528839742e-02 + 5.928000000000e-10 9.838210726041e-02 + 6.028000000000e-10 1.983970962128e-01 + 6.128000000000e-10 2.653685996210e-01 + 6.228000000000e-10 3.071805271474e-01 + 6.328000000000e-10 3.346994451143e-01 + 6.428000000000e-10 3.524959527178e-01 + 6.528000000000e-10 3.439124816552e-01 + 6.628000000000e-10 2.839825148385e-01 + 6.728000000000e-10 1.714247364616e-01 + 6.828000000000e-10 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9.328000000000e-10 -3.346653803170e-01 + 9.428000000000e-10 -3.525306496503e-01 + 9.528000000000e-10 -3.438807929682e-01 + 9.628000000000e-10 -2.840179937834e-01 + 9.728000000000e-10 -1.713943425416e-01 + 9.828000000000e-10 -3.296001530074e-02 + 9.928000000000e-10 9.837298926970e-02 + 1.000000000000e-09 1.738955459088e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/conditions.yaml new file mode 100644 index 00000000..090213b1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 4 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_04 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/CML_core_tb.sch new file mode 100644 index 00000000..c281295d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/CML_core_tb_5.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/CML_core_tb_5.data new file mode 100644 index 00000000..0cc77d23 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/CML_core_tb_5.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.958574299710e-01 + 1.728000000000e-10 -1.791897212785e-01 + 1.828000000000e-10 -3.599075048614e-02 + 1.928000000000e-10 9.946703268478e-02 + 2.028000000000e-10 2.032502871016e-01 + 2.128000000000e-10 2.733994094958e-01 + 2.228000000000e-10 3.172845988123e-01 + 2.328000000000e-10 3.455609123691e-01 + 2.428000000000e-10 3.630923957132e-01 + 2.528000000000e-10 3.534419450967e-01 + 2.628000000000e-10 2.903663934708e-01 + 2.728000000000e-10 1.726743312860e-01 + 2.828000000000e-10 2.930291139472e-02 + 2.928000000000e-10 -1.057514312075e-01 + 3.028000000000e-10 -2.091913834589e-01 + 3.128000000000e-10 -2.784696434768e-01 + 3.228000000000e-10 -3.216873931074e-01 + 3.328000000000e-10 -3.491870426412e-01 + 3.428000000000e-10 -3.662894191498e-01 + 3.528000000000e-10 -3.560374131806e-01 + 3.628000000000e-10 -2.925719059469e-01 + 3.728000000000e-10 -1.742159787839e-01 + 3.828000000000e-10 -3.049391935212e-02 + 3.928000000000e-10 1.049756016137e-01 + 4.028000000000e-10 2.084672065617e-01 + 4.128000000000e-10 2.779301238417e-01 + 4.228000000000e-10 3.211180618030e-01 + 4.328000000000e-10 3.488255023686e-01 + 4.428000000000e-10 3.659572542624e-01 + 4.528000000000e-10 3.559493947967e-01 + 4.628000000000e-10 2.925058094407e-01 + 4.728000000000e-10 1.743267017008e-01 + 4.828000000000e-10 3.054314172764e-02 + 4.928000000000e-10 -1.048175245910e-01 + 5.028000000000e-10 -2.084096499031e-01 + 5.128000000000e-10 -2.777998408986e-01 + 5.228000000000e-10 -3.210985617265e-01 + 5.328000000000e-10 -3.487226120056e-01 + 5.428000000000e-10 -3.659481451181e-01 + 5.528000000000e-10 -3.558482598240e-01 + 5.628000000000e-10 -2.924942070749e-01 + 5.728000000000e-10 -1.742324941843e-01 + 5.828000000000e-10 -3.054486718364e-02 + 5.928000000000e-10 1.048934295445e-01 + 6.028000000000e-10 2.083991544976e-01 + 6.128000000000e-10 2.778660140822e-01 + 6.228000000000e-10 3.210794561497e-01 + 6.328000000000e-10 3.487805773205e-01 + 6.428000000000e-10 3.659226785140e-01 + 6.528000000000e-10 3.558970058340e-01 + 6.628000000000e-10 2.924624137185e-01 + 6.728000000000e-10 1.742748110039e-01 + 6.828000000000e-10 3.050920657876e-02 + 6.928000000000e-10 -1.048562048812e-01 + 7.028000000000e-10 -2.084343791218e-01 + 7.128000000000e-10 -2.778299623633e-01 + 7.228000000000e-10 -3.211147582115e-01 + 7.328000000000e-10 -3.487447461690e-01 + 7.428000000000e-10 -3.659575085549e-01 + 7.528000000000e-10 -3.558632428052e-01 + 7.628000000000e-10 -2.924972481137e-01 + 7.728000000000e-10 -1.742418088753e-01 + 7.828000000000e-10 -3.054328720193e-02 + 7.928000000000e-10 1.048870377838e-01 + 8.028000000000e-10 2.084024115537e-01 + 8.128000000000e-10 2.778603942564e-01 + 8.228000000000e-10 3.210827582845e-01 + 8.328000000000e-10 3.487751488045e-01 + 8.428000000000e-10 3.659266824704e-01 + 8.528000000000e-10 3.558925702991e-01 + 8.628000000000e-10 2.924671830422e-01 + 8.728000000000e-10 1.742711856894e-01 + 8.828000000000e-10 3.051417003050e-02 + 8.928000000000e-10 -1.048591994973e-01 + 9.028000000000e-10 -2.084299430076e-01 + 9.128000000000e-10 -2.778331783696e-01 + 9.228000000000e-10 -3.211104359655e-01 + 9.328000000000e-10 -3.487480244246e-01 + 9.428000000000e-10 -3.659535267111e-01 + 9.528000000000e-10 -3.558663548813e-01 + 9.628000000000e-10 -2.924933270906e-01 + 9.728000000000e-10 -1.742451324195e-01 + 9.828000000000e-10 -3.053963678018e-02 + 9.928000000000e-10 1.048836196344e-01 + 1.000000000000e-09 1.830293824662e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/conditions.yaml new file mode 100644 index 00000000..512289d6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 5 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_05 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/CML_core_tb.sch new file mode 100644 index 00000000..c2580788 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/CML_core_tb_6.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/CML_core_tb_6.data new file mode 100644 index 00000000..38ffd8bf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/CML_core_tb_6.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.689355033953e-01 + 1.728000000000e-10 -1.691728954892e-01 + 1.828000000000e-10 -4.423302134033e-02 + 1.928000000000e-10 7.663444207075e-02 + 2.028000000000e-10 1.714764750752e-01 + 2.128000000000e-10 2.368219567798e-01 + 2.228000000000e-10 2.772768132445e-01 + 2.328000000000e-10 3.013675537348e-01 + 2.428000000000e-10 3.140706479520e-01 + 2.528000000000e-10 3.038549886105e-01 + 2.628000000000e-10 2.508404086347e-01 + 2.728000000000e-10 1.528360605683e-01 + 2.828000000000e-10 3.040034809293e-02 + 2.928000000000e-10 -8.785381094258e-02 + 3.028000000000e-10 -1.808734961109e-01 + 3.128000000000e-10 -2.445795528199e-01 + 3.228000000000e-10 -2.838354337528e-01 + 3.328000000000e-10 -3.065800962400e-01 + 3.428000000000e-10 -3.181767360109e-01 + 3.528000000000e-10 -3.065752663659e-01 + 3.628000000000e-10 -2.523878800401e-01 + 3.728000000000e-10 -1.531173668737e-01 + 3.828000000000e-10 -2.992055538556e-02 + 3.928000000000e-10 8.900435641641e-02 + 4.028000000000e-10 1.821756238512e-01 + 4.128000000000e-10 2.460123650690e-01 + 4.228000000000e-10 2.851182310100e-01 + 4.328000000000e-10 3.079291995556e-01 + 4.428000000000e-10 3.194129911462e-01 + 4.528000000000e-10 3.078915366323e-01 + 4.628000000000e-10 2.535144344421e-01 + 4.728000000000e-10 1.541542026196e-01 + 4.828000000000e-10 3.063651583090e-02 + 4.928000000000e-10 -8.839161491074e-02 + 5.028000000000e-10 -1.817999659778e-01 + 5.128000000000e-10 -2.456456661989e-01 + 5.228000000000e-10 -2.849195350591e-01 + 5.328000000000e-10 -3.077091828990e-01 + 5.428000000000e-10 -3.193505374448e-01 + 5.528000000000e-10 -3.078081521678e-01 + 5.628000000000e-10 -2.535787813503e-01 + 5.728000000000e-10 -1.541764927596e-01 + 5.828000000000e-10 -3.077048554081e-02 + 5.928000000000e-10 8.832790620553e-02 + 6.028000000000e-10 1.816551916875e-01 + 6.128000000000e-10 2.455879975104e-01 + 6.228000000000e-10 2.847911932982e-01 + 6.328000000000e-10 3.076677363016e-01 + 6.428000000000e-10 3.192371229053e-01 + 6.528000000000e-10 3.077778412262e-01 + 6.628000000000e-10 2.534819327505e-01 + 6.728000000000e-10 1.541683138663e-01 + 6.828000000000e-10 3.070155435378e-02 + 6.928000000000e-10 -8.831320560130e-02 + 7.028000000000e-10 -1.817038543937e-01 + 7.128000000000e-10 -2.455619958387e-01 + 7.228000000000e-10 -2.848320347671e-01 + 7.328000000000e-10 -3.076358698550e-01 + 7.428000000000e-10 -3.192710667609e-01 + 7.528000000000e-10 -3.077409972388e-01 + 7.628000000000e-10 -2.535098012890e-01 + 7.728000000000e-10 -1.541282589474e-01 + 7.828000000000e-10 -3.072672689244e-02 + 7.928000000000e-10 8.835148526653e-02 + 8.028000000000e-10 1.816795669555e-01 + 8.128000000000e-10 2.455984246601e-01 + 8.228000000000e-10 2.848062931006e-01 + 8.328000000000e-10 3.076705916890e-01 + 8.428000000000e-10 3.192450073559e-01 + 8.528000000000e-10 3.077736319697e-01 + 8.628000000000e-10 2.534831121829e-01 + 8.728000000000e-10 1.541590953584e-01 + 8.828000000000e-10 3.069946612700e-02 + 8.928000000000e-10 -8.832341199891e-02 + 9.028000000000e-10 -1.817063952021e-01 + 9.128000000000e-10 -2.455714256322e-01 + 9.228000000000e-10 -2.848333922463e-01 + 9.328000000000e-10 -3.076440936715e-01 + 9.428000000000e-10 -3.192716274515e-01 + 9.528000000000e-10 -3.077481608676e-01 + 9.628000000000e-10 -2.535093614867e-01 + 9.728000000000e-10 -1.541340765567e-01 + 9.828000000000e-10 -3.072486745089e-02 + 9.928000000000e-10 8.834711873249e-02 + 1.000000000000e-09 1.586239577417e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/conditions.yaml new file mode 100644 index 00000000..61a1ff89 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 6 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_06 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/CML_core_tb.sch new file mode 100644 index 00000000..e7567dd4 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/CML_core_tb_7.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/CML_core_tb_7.data new file mode 100644 index 00000000..1cfe87b5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/CML_core_tb_7.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.694477874818e-01 + 1.728000000000e-10 -1.721829739194e-01 + 1.828000000000e-10 -4.906833766415e-02 + 1.928000000000e-10 7.069743134728e-02 + 2.028000000000e-10 1.648418946330e-01 + 2.128000000000e-10 2.298765389610e-01 + 2.228000000000e-10 2.702802052070e-01 + 2.328000000000e-10 2.947129455777e-01 + 2.428000000000e-10 3.081296602318e-01 + 2.528000000000e-10 2.990063012040e-01 + 2.628000000000e-10 2.478884705263e-01 + 2.728000000000e-10 1.524230846398e-01 + 2.828000000000e-10 3.216725009037e-02 + 2.928000000000e-10 -8.452884553171e-02 + 3.028000000000e-10 -1.764495371150e-01 + 3.128000000000e-10 -2.394951663999e-01 + 3.228000000000e-10 -2.784178156025e-01 + 3.328000000000e-10 -3.012580547427e-01 + 3.428000000000e-10 -3.133510931360e-01 + 3.528000000000e-10 -3.026055002423e-01 + 3.628000000000e-10 -2.500554574282e-01 + 3.728000000000e-10 -1.530444893437e-01 + 3.828000000000e-10 -3.179895766292e-02 + 3.928000000000e-10 8.573594509971e-02 + 4.028000000000e-10 1.778922744476e-01 + 4.128000000000e-10 2.411102030583e-01 + 4.228000000000e-10 2.798967112063e-01 + 4.328000000000e-10 3.028156837380e-01 + 4.428000000000e-10 3.148075876296e-01 + 4.528000000000e-10 3.041758344829e-01 + 4.628000000000e-10 2.514478797306e-01 + 4.728000000000e-10 1.543354303295e-01 + 4.828000000000e-10 3.272908827542e-02 + 4.928000000000e-10 -8.494488064942e-02 + 5.028000000000e-10 -1.773750790235e-01 + 5.128000000000e-10 -2.406241070550e-01 + 5.228000000000e-10 -2.796032327906e-01 + 5.328000000000e-10 -3.025154625175e-01 + 5.428000000000e-10 -3.146850050735e-01 + 5.528000000000e-10 -3.040456856306e-01 + 5.628000000000e-10 -2.514865398019e-01 + 5.728000000000e-10 -1.543455010081e-01 + 5.828000000000e-10 -3.286780649422e-02 + 5.928000000000e-10 8.487071769529e-02 + 6.028000000000e-10 1.772120847555e-01 + 6.128000000000e-10 2.405506532865e-01 + 6.228000000000e-10 2.794557736074e-01 + 6.328000000000e-10 3.024581955274e-01 + 6.428000000000e-10 3.145521515255e-01 + 6.528000000000e-10 3.039990633934e-01 + 6.628000000000e-10 2.513709142203e-01 + 6.728000000000e-10 1.543241408079e-01 + 6.828000000000e-10 3.278555364704e-02 + 6.928000000000e-10 -8.486327141666e-02 + 7.028000000000e-10 -1.772689800248e-01 + 7.128000000000e-10 -2.405282060865e-01 + 7.228000000000e-10 -2.795021370136e-01 + 7.328000000000e-10 -3.024278022377e-01 + 7.428000000000e-10 -3.145896170200e-01 + 7.528000000000e-10 -3.039617953787e-01 + 7.628000000000e-10 -2.514004690324e-01 + 7.728000000000e-10 -1.542820043229e-01 + 7.828000000000e-10 -3.281110337775e-02 + 7.928000000000e-10 8.490436306023e-02 + 8.028000000000e-10 1.772446330839e-01 + 8.128000000000e-10 2.405674335146e-01 + 8.228000000000e-10 2.794761963085e-01 + 8.328000000000e-10 3.024650976088e-01 + 8.428000000000e-10 3.145632644585e-01 + 8.528000000000e-10 3.039968961590e-01 + 8.628000000000e-10 2.513733111446e-01 + 8.728000000000e-10 1.543150179356e-01 + 8.828000000000e-10 3.278304586331e-02 + 8.928000000000e-10 -8.487456857602e-02 + 9.028000000000e-10 -1.772725618584e-01 + 9.128000000000e-10 -2.405389250041e-01 + 9.228000000000e-10 -2.795045102279e-01 + 9.328000000000e-10 -3.024372521320e-01 + 9.428000000000e-10 -3.145911572553e-01 + 9.528000000000e-10 -3.039701598993e-01 + 9.628000000000e-10 -2.514009218164e-01 + 9.728000000000e-10 -1.542887967264e-01 + 9.828000000000e-10 -3.280979517783e-02 + 9.928000000000e-10 8.489941508642e-02 + 1.000000000000e-09 1.544118489485e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/conditions.yaml new file mode 100644 index 00000000..7136a755 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 7 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_07 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/CML_core_tb.sch new file mode 100644 index 00000000..723fad9c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/CML_core_tb_8.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/CML_core_tb_8.data new file mode 100644 index 00000000..b4ed17dd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/CML_core_tb_8.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.722799425151e-01 + 1.728000000000e-10 -1.701277707773e-01 + 1.828000000000e-10 -4.252496989706e-02 + 1.928000000000e-10 8.092536896213e-02 + 2.028000000000e-10 1.785199933375e-01 + 2.128000000000e-10 2.463984181452e-01 + 2.228000000000e-10 2.885755113271e-01 + 2.328000000000e-10 3.131967480955e-01 + 2.428000000000e-10 3.255285716483e-01 + 2.528000000000e-10 3.143820454109e-01 + 2.628000000000e-10 2.595824958850e-01 + 2.728000000000e-10 1.585585813323e-01 + 2.828000000000e-10 3.254606172598e-02 + 2.928000000000e-10 -8.921916265210e-02 + 3.028000000000e-10 -1.857143058967e-01 + 3.128000000000e-10 -2.524588707093e-01 + 3.228000000000e-10 -2.937876617757e-01 + 3.328000000000e-10 -3.173655773168e-01 + 3.428000000000e-10 -3.288566343508e-01 + 3.528000000000e-10 -3.166123605828e-01 + 3.628000000000e-10 -2.609360611345e-01 + 3.728000000000e-10 -1.589355414621e-01 + 3.828000000000e-10 -3.237621747627e-02 + 3.928000000000e-10 8.990939637816e-02 + 4.028000000000e-10 1.864994737191e-01 + 4.128000000000e-10 2.533636311879e-01 + 4.228000000000e-10 2.945633129641e-01 + 4.328000000000e-10 3.182197832362e-01 + 4.428000000000e-10 3.296245618008e-01 + 4.528000000000e-10 3.174841059207e-01 + 4.628000000000e-10 2.616780558587e-01 + 4.728000000000e-10 1.596622360522e-01 + 4.828000000000e-10 3.287681921596e-02 + 4.928000000000e-10 -8.943999963453e-02 + 5.028000000000e-10 -1.862066308093e-01 + 5.128000000000e-10 -2.530527908612e-01 + 5.228000000000e-10 -2.943931136832e-01 + 5.328000000000e-10 -3.180152021024e-01 + 5.428000000000e-10 -3.295545667130e-01 + 5.528000000000e-10 -3.173812952412e-01 + 5.628000000000e-10 -2.617027726155e-01 + 5.728000000000e-10 -1.596411992093e-01 + 5.828000000000e-10 -3.295895028258e-02 + 5.928000000000e-10 8.942267434718e-02 + 6.028000000000e-10 1.861105403656e-01 + 6.128000000000e-10 2.530344325895e-01 + 6.228000000000e-10 2.943051008579e-01 + 6.328000000000e-10 3.180051485103e-01 + 6.428000000000e-10 3.294737915539e-01 + 6.528000000000e-10 3.173744791022e-01 + 6.628000000000e-10 2.616291881364e-01 + 6.728000000000e-10 1.596450333001e-01 + 6.828000000000e-10 3.290088244348e-02 + 6.928000000000e-10 -8.940659470005e-02 + 7.028000000000e-10 -1.861562133447e-01 + 7.128000000000e-10 -2.530116656482e-01 + 7.228000000000e-10 -2.943454309811e-01 + 7.328000000000e-10 -3.179780561670e-01 + 7.428000000000e-10 -3.295087969733e-01 + 7.528000000000e-10 -3.173438661274e-01 + 7.628000000000e-10 -2.616591955397e-01 + 7.728000000000e-10 -1.596115565426e-01 + 7.828000000000e-10 -3.292790237402e-02 + 7.928000000000e-10 8.943927261705e-02 + 8.028000000000e-10 1.861310420114e-01 + 8.128000000000e-10 2.530433655174e-01 + 8.228000000000e-10 2.943195630770e-01 + 8.328000000000e-10 3.180088285378e-01 + 8.428000000000e-10 3.294832118435e-01 + 8.528000000000e-10 3.173732295072e-01 + 8.628000000000e-10 2.616337486722e-01 + 8.728000000000e-10 1.596399004289e-01 + 8.828000000000e-10 3.290244884503e-02 + 8.928000000000e-10 -8.941301350766e-02 + 9.028000000000e-10 -1.861557185261e-01 + 9.128000000000e-10 -2.530180139920e-01 + 9.228000000000e-10 -2.943444772306e-01 + 9.328000000000e-10 -3.179838696148e-01 + 9.428000000000e-10 -3.295076633013e-01 + 9.528000000000e-10 -3.173492560727e-01 + 9.628000000000e-10 -2.616577755083e-01 + 9.728000000000e-10 -1.596163947717e-01 + 9.828000000000e-10 -3.292583900074e-02 + 9.928000000000e-10 8.943518431692e-02 + 1.000000000000e-09 1.621529465729e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/conditions.yaml new file mode 100644 index 00000000..e5d65a2e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 8 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_08 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/CML_core_tb.sch new file mode 100644 index 00000000..9cc3a624 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/CML_core_tb_9.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/CML_core_tb_9.data new file mode 100644 index 00000000..6b24d1d6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/CML_core_tb_9.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.622644182692e-01 + 1.728000000000e-10 -1.962653738736e-01 + 1.828000000000e-10 -5.712895575235e-03 + 1.928000000000e-10 1.510345047594e-01 + 2.028000000000e-10 2.432775412534e-01 + 2.128000000000e-10 2.772000132926e-01 + 2.228000000000e-10 3.161630086256e-01 + 2.328000000000e-10 3.654121904616e-01 + 2.428000000000e-10 4.070200809677e-01 + 2.528000000000e-10 4.211809118313e-01 + 2.628000000000e-10 3.552666659990e-01 + 2.728000000000e-10 1.954111420719e-01 + 2.828000000000e-10 7.499275151763e-03 + 2.928000000000e-10 -1.488912332472e-01 + 3.028000000000e-10 -2.420325529570e-01 + 3.128000000000e-10 -2.768171400503e-01 + 3.228000000000e-10 -3.164103191401e-01 + 3.328000000000e-10 -3.656815561297e-01 + 3.428000000000e-10 -4.072561733660e-01 + 3.528000000000e-10 -4.210637971044e-01 + 3.628000000000e-10 -3.548415521036e-01 + 3.728000000000e-10 -1.946286859654e-01 + 3.828000000000e-10 -6.746438981043e-03 + 3.928000000000e-10 1.496127957227e-01 + 4.028000000000e-10 2.425057762271e-01 + 4.128000000000e-10 2.772590268750e-01 + 4.228000000000e-10 3.167075169816e-01 + 4.328000000000e-10 3.660182242119e-01 + 4.428000000000e-10 4.074726111052e-01 + 4.528000000000e-10 4.212975956202e-01 + 4.628000000000e-10 3.549573822535e-01 + 4.728000000000e-10 1.947835560361e-01 + 4.828000000000e-10 6.801482567115e-03 + 4.928000000000e-10 -1.495086456760e-01 + 5.028000000000e-10 -2.424863730465e-01 + 5.128000000000e-10 -2.771744431737e-01 + 5.228000000000e-10 -3.166940000076e-01 + 5.328000000000e-10 -3.659398771497e-01 + 5.428000000000e-10 -4.074689465730e-01 + 5.528000000000e-10 -4.212394549000e-01 + 5.628000000000e-10 -3.549741510035e-01 + 5.728000000000e-10 -1.947436351784e-01 + 5.828000000000e-10 -6.830080160870e-03 + 5.928000000000e-10 1.495407150967e-01 + 6.028000000000e-10 2.424570295697e-01 + 6.128000000000e-10 2.772066160972e-01 + 6.228000000000e-10 3.166654934082e-01 + 6.328000000000e-10 3.659723864247e-01 + 6.428000000000e-10 4.074416211051e-01 + 6.528000000000e-10 4.212697301261e-01 + 6.628000000000e-10 3.549467093259e-01 + 6.728000000000e-10 1.947718238583e-01 + 6.828000000000e-10 6.800951177238e-03 + 6.928000000000e-10 -1.495148390529e-01 + 7.028000000000e-10 -2.424852043575e-01 + 7.128000000000e-10 -2.771809105751e-01 + 7.228000000000e-10 -3.166930947909e-01 + 7.328000000000e-10 -3.659459016360e-01 + 7.428000000000e-10 -4.074677461547e-01 + 7.528000000000e-10 -4.212442717757e-01 + 7.628000000000e-10 -3.549717520551e-01 + 7.728000000000e-10 -1.947463263521e-01 + 7.828000000000e-10 -6.825916545420e-03 + 7.928000000000e-10 1.495385751436e-01 + 8.028000000000e-10 2.424609931904e-01 + 8.128000000000e-10 2.772040406871e-01 + 8.228000000000e-10 3.166687905139e-01 + 8.328000000000e-10 3.659694951712e-01 + 8.428000000000e-10 4.074447010218e-01 + 8.528000000000e-10 4.212671408417e-01 + 8.628000000000e-10 3.549498827484e-01 + 8.728000000000e-10 1.947689363825e-01 + 8.828000000000e-10 6.803756635994e-03 + 8.928000000000e-10 -1.495176738691e-01 + 9.028000000000e-10 -2.424825342063e-01 + 9.128000000000e-10 -2.771836734306e-01 + 9.228000000000e-10 -3.166902103892e-01 + 9.328000000000e-10 -3.659485359213e-01 + 9.428000000000e-10 -4.074650210911e-01 + 9.528000000000e-10 -4.212469657833e-01 + 9.628000000000e-10 -3.549694058275e-01 + 9.728000000000e-10 -1.947487958951e-01 + 9.828000000000e-10 -6.823236278537e-03 + 9.928000000000e-10 1.495363177485e-01 + 1.000000000000e-09 2.250264100511e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/conditions.yaml new file mode 100644 index 00000000..65ec53fd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 9 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_09 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/CML_core_tb.sch new file mode 100644 index 00000000..25f9f97d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/CML_core_tb_10.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/CML_core_tb_10.data new file mode 100644 index 00000000..f64d27bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/CML_core_tb_10.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.621881537650e-01 + 1.728000000000e-10 -1.984429143572e-01 + 1.828000000000e-10 -1.024381876325e-02 + 1.928000000000e-10 1.456486678579e-01 + 2.028000000000e-10 2.379497773075e-01 + 2.128000000000e-10 2.714724605336e-01 + 2.228000000000e-10 3.108042897090e-01 + 2.328000000000e-10 3.600441003378e-01 + 2.428000000000e-10 4.020596908788e-01 + 2.528000000000e-10 4.176332246346e-01 + 2.628000000000e-10 3.534480183483e-01 + 2.728000000000e-10 1.957884716864e-01 + 2.828000000000e-10 1.048070619246e-02 + 2.928000000000e-10 -1.446967472000e-01 + 3.028000000000e-10 -2.375576326508e-01 + 3.128000000000e-10 -2.717915022579e-01 + 3.228000000000e-10 -3.116603869888e-01 + 3.328000000000e-10 -3.608573425706e-01 + 3.428000000000e-10 -4.027490548925e-01 + 3.528000000000e-10 -4.178578104758e-01 + 3.628000000000e-10 -3.532507313188e-01 + 3.728000000000e-10 -1.951536666098e-01 + 3.828000000000e-10 -9.813336101525e-03 + 3.928000000000e-10 1.453604720604e-01 + 4.028000000000e-10 2.379857130154e-01 + 4.128000000000e-10 2.721818635676e-01 + 4.228000000000e-10 3.119088225778e-01 + 4.328000000000e-10 3.611475798924e-01 + 4.428000000000e-10 4.029304727738e-01 + 4.528000000000e-10 4.180700216423e-01 + 4.628000000000e-10 3.533627988360e-01 + 4.728000000000e-10 1.953149158213e-01 + 4.828000000000e-10 9.881134950277e-03 + 4.928000000000e-10 -1.452466419838e-01 + 5.028000000000e-10 -2.379576224969e-01 + 5.128000000000e-10 -2.720935242692e-01 + 5.228000000000e-10 -3.118909714313e-01 + 5.328000000000e-10 -3.610674239906e-01 + 5.428000000000e-10 -4.029229661263e-01 + 5.528000000000e-10 -4.180098057029e-01 + 5.628000000000e-10 -3.533753449283e-01 + 5.728000000000e-10 -1.952727841385e-01 + 5.828000000000e-10 -9.906008920915e-03 + 5.928000000000e-10 1.452800172029e-01 + 6.028000000000e-10 2.379306740359e-01 + 6.128000000000e-10 2.721261300904e-01 + 6.228000000000e-10 3.118646486801e-01 + 6.328000000000e-10 3.611003417151e-01 + 6.428000000000e-10 4.028972890619e-01 + 6.528000000000e-10 4.180401129989e-01 + 6.628000000000e-10 3.533488930459e-01 + 6.728000000000e-10 1.953007885397e-01 + 6.828000000000e-10 9.878072761317e-03 + 6.928000000000e-10 -1.452545395230e-01 + 7.028000000000e-10 -2.379578117562e-01 + 7.128000000000e-10 -2.721008877684e-01 + 7.228000000000e-10 -3.118914026492e-01 + 7.328000000000e-10 -3.610744602697e-01 + 7.428000000000e-10 -4.029226014194e-01 + 7.528000000000e-10 -4.180151483436e-01 + 7.628000000000e-10 -3.533732531474e-01 + 7.728000000000e-10 -1.952759500525e-01 + 7.828000000000e-10 -9.902411226855e-03 + 7.928000000000e-10 1.452776462046e-01 + 8.028000000000e-10 2.379341379884e-01 + 8.128000000000e-10 2.721234101956e-01 + 8.228000000000e-10 3.118677116052e-01 + 8.328000000000e-10 3.610975209728e-01 + 8.428000000000e-10 4.029000595077e-01 + 8.528000000000e-10 4.180375331400e-01 + 8.628000000000e-10 3.533517750284e-01 + 8.728000000000e-10 1.952981248182e-01 + 8.828000000000e-10 9.880873061622e-03 + 8.928000000000e-10 -1.452571579233e-01 + 9.028000000000e-10 -2.379551078725e-01 + 9.128000000000e-10 -2.721034614056e-01 + 9.228000000000e-10 -3.118886463518e-01 + 9.328000000000e-10 -3.610770519544e-01 + 9.428000000000e-10 -4.029199107687e-01 + 9.528000000000e-10 -4.180177452829e-01 + 9.628000000000e-10 -3.533708821878e-01 + 9.728000000000e-10 -1.952784134813e-01 + 9.828000000000e-10 -9.899898542678e-03 + 9.928000000000e-10 1.452754037376e-01 + 1.000000000000e-09 2.207322871295e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/conditions.yaml new file mode 100644 index 00000000..a23dc1e6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 10 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_10 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/CML_core_tb.sch new file mode 100644 index 00000000..d4ca065e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/CML_core_tb_11.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/CML_core_tb_11.data new file mode 100644 index 00000000..1453012b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/CML_core_tb_11.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.668500025046e-01 + 1.728000000000e-10 -1.978704758130e-01 + 1.828000000000e-10 -3.069550951996e-03 + 1.928000000000e-10 1.561389387989e-01 + 2.028000000000e-10 2.488697408913e-01 + 2.128000000000e-10 2.833379270136e-01 + 2.228000000000e-10 3.221467647695e-01 + 2.328000000000e-10 3.723176028273e-01 + 2.428000000000e-10 4.147931582649e-01 + 2.528000000000e-10 4.286646301121e-01 + 2.628000000000e-10 3.614677855799e-01 + 2.728000000000e-10 1.982726052647e-01 + 2.828000000000e-10 5.580533140739e-03 + 2.928000000000e-10 -1.536551403474e-01 + 3.028000000000e-10 -2.474729097395e-01 + 3.128000000000e-10 -2.827981749211e-01 + 3.228000000000e-10 -3.222400643179e-01 + 3.328000000000e-10 -3.724510578191e-01 + 3.428000000000e-10 -4.149487937489e-01 + 3.528000000000e-10 -4.285094572794e-01 + 3.628000000000e-10 -3.610716711123e-01 + 3.728000000000e-10 -1.975613483211e-01 + 3.828000000000e-10 -4.936396792217e-03 + 3.928000000000e-10 1.542720670721e-01 + 4.028000000000e-10 2.478554934965e-01 + 4.128000000000e-10 2.831768205427e-01 + 4.228000000000e-10 3.224764565266e-01 + 4.328000000000e-10 3.727376628527e-01 + 4.428000000000e-10 4.151128450004e-01 + 4.528000000000e-10 4.287030398326e-01 + 4.628000000000e-10 3.611465460996e-01 + 4.728000000000e-10 1.976871290976e-01 + 4.828000000000e-10 4.962067120498e-03 + 4.928000000000e-10 -1.541857483448e-01 + 5.028000000000e-10 -2.478549856990e-01 + 5.128000000000e-10 -2.831031432303e-01 + 5.228000000000e-10 -3.224786212940e-01 + 5.328000000000e-10 -3.726675199031e-01 + 5.428000000000e-10 -4.151222726988e-01 + 5.528000000000e-10 -4.286496175832e-01 + 5.628000000000e-10 -3.611719348809e-01 + 5.728000000000e-10 -1.976471175954e-01 + 5.828000000000e-10 -4.995016715658e-03 + 5.928000000000e-10 1.542195273485e-01 + 6.028000000000e-10 2.478226151197e-01 + 6.128000000000e-10 2.831371441394e-01 + 6.228000000000e-10 3.224465270882e-01 + 6.328000000000e-10 3.727020829784e-01 + 6.428000000000e-10 4.150919188021e-01 + 6.528000000000e-10 4.286821395136e-01 + 6.628000000000e-10 3.611419365066e-01 + 6.728000000000e-10 1.976777927703e-01 + 6.828000000000e-10 4.963507878799e-03 + 6.928000000000e-10 -1.541913949207e-01 + 7.028000000000e-10 -2.478529800499e-01 + 7.128000000000e-10 -2.831092109235e-01 + 7.228000000000e-10 -3.224762894768e-01 + 7.328000000000e-10 -3.726728668334e-01 + 7.428000000000e-10 -4.151201370880e-01 + 7.528000000000e-10 -4.286543531433e-01 + 7.628000000000e-10 -3.611692599178e-01 + 7.728000000000e-10 -1.976499135935e-01 + 7.828000000000e-10 -4.990471824028e-03 + 7.928000000000e-10 1.542171227717e-01 + 8.028000000000e-10 2.478269854332e-01 + 8.128000000000e-10 2.831343470853e-01 + 8.228000000000e-10 3.224500362551e-01 + 8.328000000000e-10 3.726987138014e-01 + 8.428000000000e-10 4.150953468135e-01 + 8.528000000000e-10 4.286792233560e-01 + 8.628000000000e-10 3.611455588852e-01 + 8.728000000000e-10 1.976743961081e-01 + 8.828000000000e-10 4.966432661841e-03 + 8.928000000000e-10 -1.541946484524e-01 + 9.028000000000e-10 -2.478502288236e-01 + 9.128000000000e-10 -2.831123474050e-01 + 9.228000000000e-10 -3.224731331421e-01 + 9.328000000000e-10 -3.726757720747e-01 + 9.428000000000e-10 -4.151172388981e-01 + 9.528000000000e-10 -4.286573581279e-01 + 9.628000000000e-10 -3.611667698498e-01 + 9.728000000000e-10 -1.976525646923e-01 + 9.828000000000e-10 -4.987471597641e-03 + 9.928000000000e-10 1.542147143463e-01 + 1.000000000000e-09 2.301006397866e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/conditions.yaml new file mode 100644 index 00000000..84aaa3b7 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 11 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_11 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/CML_core_tb.sch new file mode 100644 index 00000000..c4849631 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/CML_core_tb_12.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/CML_core_tb_12.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/CML_core_tb_12.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 6.928000000000e-10 -1.390553921853e-01 + 7.028000000000e-10 -2.331263672195e-01 + 7.128000000000e-10 -2.732987102222e-01 + 7.228000000000e-10 -3.105421090081e-01 + 7.328000000000e-10 -3.532994962925e-01 + 7.428000000000e-10 -3.892451651423e-01 + 7.528000000000e-10 -4.000824543639e-01 + 7.628000000000e-10 -3.385783830881e-01 + 7.728000000000e-10 -1.899748483052e-01 + 7.828000000000e-10 -1.221334688082e-02 + 7.928000000000e-10 1.390733351530e-01 + 8.028000000000e-10 2.331082732353e-01 + 8.128000000000e-10 2.733160005972e-01 + 8.228000000000e-10 3.105237742784e-01 + 8.328000000000e-10 3.533165556732e-01 + 8.428000000000e-10 3.892279285214e-01 + 8.528000000000e-10 4.000991009611e-01 + 8.628000000000e-10 3.385625511294e-01 + 8.728000000000e-10 1.899914169425e-01 + 8.828000000000e-10 1.219669858142e-02 + 8.928000000000e-10 -1.390576717936e-01 + 9.028000000000e-10 -2.331245304799e-01 + 9.128000000000e-10 -2.733009677599e-01 + 9.228000000000e-10 -3.105397739050e-01 + 9.328000000000e-10 -3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/conditions.yaml new file mode 100644 index 00000000..f9219c6c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 12 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_12 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/CML_core_tb.sch new file mode 100644 index 00000000..3421eb12 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/CML_core_tb_13.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/CML_core_tb_13.data new file mode 100644 index 00000000..36de6040 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/CML_core_tb_13.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.406999838743e-01 + 1.728000000000e-10 -1.879936990253e-01 + 1.828000000000e-10 -9.262901303246e-03 + 1.928000000000e-10 1.413611635485e-01 + 2.028000000000e-10 2.336775345801e-01 + 2.128000000000e-10 2.717294842894e-01 + 2.228000000000e-10 3.082620487639e-01 + 2.328000000000e-10 3.509422339502e-01 + 2.428000000000e-10 3.871053596645e-01 + 2.528000000000e-10 3.988940820744e-01 + 2.628000000000e-10 3.384312270542e-01 + 2.728000000000e-10 1.913281233779e-01 + 2.828000000000e-10 1.537343295661e-02 + 2.928000000000e-10 -1.347916275204e-01 + 3.028000000000e-10 -2.283419665374e-01 + 3.128000000000e-10 -2.677291408127e-01 + 3.228000000000e-10 -3.052231075401e-01 + 3.328000000000e-10 -3.481601477547e-01 + 3.428000000000e-10 -3.845854123080e-01 + 3.528000000000e-10 -3.965379624605e-01 + 3.628000000000e-10 -3.363314255870e-01 + 3.728000000000e-10 -1.893723794407e-01 + 3.828000000000e-10 -1.375643865463e-02 + 3.928000000000e-10 1.361849816757e-01 + 4.028000000000e-10 2.294005939140e-01 + 4.128000000000e-10 2.686949729273e-01 + 4.228000000000e-10 3.060328157788e-01 + 4.328000000000e-10 3.489590274886e-01 + 4.428000000000e-10 3.852266672724e-01 + 4.528000000000e-10 3.970921187630e-01 + 4.628000000000e-10 3.366736237881e-01 + 4.728000000000e-10 1.896320772426e-01 + 4.828000000000e-10 1.386475371506e-02 + 4.928000000000e-10 -1.360753156283e-01 + 5.028000000000e-10 -2.293675908871e-01 + 5.128000000000e-10 -2.686062530832e-01 + 5.228000000000e-10 -3.059945800423e-01 + 5.328000000000e-10 -3.488729675224e-01 + 5.428000000000e-10 -3.852026785029e-01 + 5.528000000000e-10 -3.970350594993e-01 + 5.628000000000e-10 -3.366834486256e-01 + 5.728000000000e-10 -1.896077423819e-01 + 5.828000000000e-10 -1.389840122586e-02 + 5.928000000000e-10 1.360876217327e-01 + 6.028000000000e-10 2.293336021557e-01 + 6.128000000000e-10 2.686225622920e-01 + 6.228000000000e-10 3.059648098566e-01 + 6.328000000000e-10 3.488907093130e-01 + 6.428000000000e-10 3.851753633828e-01 + 6.528000000000e-10 3.970526526302e-01 + 6.628000000000e-10 3.366583891048e-01 + 6.728000000000e-10 1.896251667832e-01 + 6.828000000000e-10 1.387242911077e-02 + 6.928000000000e-10 -1.360702314024e-01 + 7.028000000000e-10 -2.293580006158e-01 + 7.128000000000e-10 -2.686047945045e-01 + 7.228000000000e-10 -3.059879182353e-01 + 7.328000000000e-10 -3.488722408399e-01 + 7.428000000000e-10 -3.851969589401e-01 + 7.528000000000e-10 -3.970345404264e-01 + 7.628000000000e-10 -3.366782708831e-01 + 7.728000000000e-10 -1.896058621860e-01 + 7.828000000000e-10 -1.389192450355e-02 + 7.928000000000e-10 1.360888260036e-01 + 8.028000000000e-10 2.293391038565e-01 + 8.128000000000e-10 2.686227634282e-01 + 8.228000000000e-10 3.059688096850e-01 + 8.328000000000e-10 3.488900661997e-01 + 8.428000000000e-10 3.851789257250e-01 + 8.528000000000e-10 3.970519764807e-01 + 8.628000000000e-10 3.366616134215e-01 + 8.728000000000e-10 1.896231972496e-01 + 8.828000000000e-10 1.387461571983e-02 + 8.928000000000e-10 -1.360724758723e-01 + 9.028000000000e-10 -2.293560182270e-01 + 9.128000000000e-10 -2.686070528237e-01 + 9.228000000000e-10 -3.059854790954e-01 + 9.328000000000e-10 -3.488740842624e-01 + 9.428000000000e-10 -3.851947329758e-01 + 9.528000000000e-10 -3.970365843841e-01 + 9.628000000000e-10 -3.366766115599e-01 + 9.728000000000e-10 -1.896075309897e-01 + 9.828000000000e-10 -1.388973786858e-02 + 9.928000000000e-10 1.360872156510e-01 + 1.000000000000e-09 2.108297225004e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/conditions.yaml new file mode 100644 index 00000000..191e2a61 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 13 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_13 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/CML_core_tb.sch new file mode 100644 index 00000000..e46477d4 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/CML_core_tb_14.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/CML_core_tb_14.data new file mode 100644 index 00000000..73c31d13 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/CML_core_tb_14.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.445927026449e-01 + 1.728000000000e-10 -1.889320969581e-01 + 1.828000000000e-10 -5.355234564888e-03 + 1.928000000000e-10 1.489911128277e-01 + 2.028000000000e-10 2.434822449071e-01 + 2.128000000000e-10 2.838702060450e-01 + 2.228000000000e-10 3.202156401988e-01 + 2.328000000000e-10 3.629401474789e-01 + 2.428000000000e-10 3.990998051164e-01 + 2.528000000000e-10 4.099063275401e-01 + 2.628000000000e-10 3.477923521709e-01 + 2.728000000000e-10 1.968519788675e-01 + 2.828000000000e-10 1.493750763318e-02 + 2.928000000000e-10 -1.398437743336e-01 + 3.028000000000e-10 -2.362338093992e-01 + 3.128000000000e-10 -2.782887085314e-01 + 3.228000000000e-10 -3.158910292643e-01 + 3.328000000000e-10 -3.590893499920e-01 + 3.428000000000e-10 -3.957248346768e-01 + 3.528000000000e-10 -4.069627998073e-01 + 3.628000000000e-10 -3.454070734708e-01 + 3.728000000000e-10 -1.948243362004e-01 + 3.828000000000e-10 -1.337926088934e-02 + 3.928000000000e-10 1.411472162204e-01 + 4.028000000000e-10 2.372231231196e-01 + 4.128000000000e-10 2.792284454069e-01 + 4.228000000000e-10 3.166817589057e-01 + 4.328000000000e-10 3.598702175634e-01 + 4.428000000000e-10 3.963375250752e-01 + 4.528000000000e-10 4.074753309124e-01 + 4.628000000000e-10 3.456854225481e-01 + 4.728000000000e-10 1.950177434222e-01 + 4.828000000000e-10 1.342430394201e-02 + 4.928000000000e-10 -1.410850608466e-01 + 5.028000000000e-10 -2.372286880899e-01 + 5.128000000000e-10 -2.791659662153e-01 + 5.228000000000e-10 -3.166689293508e-01 + 5.328000000000e-10 -3.598026374101e-01 + 5.428000000000e-10 -3.963331138013e-01 + 5.528000000000e-10 -4.074316676804e-01 + 5.628000000000e-10 -3.457088001737e-01 + 5.728000000000e-10 -1.950000158899e-01 + 5.828000000000e-10 -1.346504722293e-02 + 5.928000000000e-10 1.410957635246e-01 + 6.028000000000e-10 2.371909425038e-01 + 6.128000000000e-10 2.791817404178e-01 + 6.228000000000e-10 3.166356138828e-01 + 6.328000000000e-10 3.598203377806e-01 + 6.428000000000e-10 3.963033609435e-01 + 6.528000000000e-10 4.074499160221e-01 + 6.628000000000e-10 3.456826167292e-01 + 6.728000000000e-10 1.950190841630e-01 + 6.828000000000e-10 1.343803454206e-02 + 6.928000000000e-10 -1.410764950259e-01 + 7.028000000000e-10 -2.372163265848e-01 + 7.128000000000e-10 -2.791624229651e-01 + 7.228000000000e-10 -3.166599225368e-01 + 7.328000000000e-10 -3.598002455584e-01 + 7.428000000000e-10 -3.963259615583e-01 + 7.528000000000e-10 -4.074304662079e-01 + 7.628000000000e-10 -3.457033629648e-01 + 7.728000000000e-10 -1.949983704767e-01 + 7.828000000000e-10 -1.345872104163e-02 + 7.928000000000e-10 1.410962716693e-01 + 8.028000000000e-10 2.371963808526e-01 + 8.128000000000e-10 2.791814500218e-01 + 8.228000000000e-10 3.166396456569e-01 + 8.328000000000e-10 3.598191409746e-01 + 8.428000000000e-10 3.963069790813e-01 + 8.528000000000e-10 4.074488078929e-01 + 8.628000000000e-10 3.456858987705e-01 + 8.728000000000e-10 1.950166421641e-01 + 8.828000000000e-10 1.344025602045e-02 + 8.928000000000e-10 -1.410790665154e-01 + 9.028000000000e-10 -2.372142995262e-01 + 9.128000000000e-10 -2.791649325552e-01 + 9.228000000000e-10 -3.166573514474e-01 + 9.328000000000e-10 -3.598022359716e-01 + 9.428000000000e-10 -3.963236588924e-01 + 9.528000000000e-10 -4.074326778223e-01 + 9.628000000000e-10 -3.457016440453e-01 + 9.728000000000e-10 -1.950001702792e-01 + 9.828000000000e-10 -1.345633761364e-02 + 9.928000000000e-10 1.410945129066e-01 + 1.000000000000e-09 2.176807579100e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/conditions.yaml new file mode 100644 index 00000000..8d40025a --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 14 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_14 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/CML_core_tb.sch new file mode 100644 index 00000000..c0c12756 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/CML_core_tb_15.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/CML_core_tb_15.data new file mode 100644 index 00000000..6f87c434 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/CML_core_tb_15.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.831577979118e-01 + 1.728000000000e-10 -1.548331321524e-01 + 1.828000000000e-10 2.954507991941e-03 + 1.928000000000e-10 1.412083661187e-01 + 2.028000000000e-10 2.303947789211e-01 + 2.128000000000e-10 2.725788032239e-01 + 2.228000000000e-10 3.064646814943e-01 + 2.328000000000e-10 3.412898568956e-01 + 2.428000000000e-10 3.692979025942e-01 + 2.528000000000e-10 3.751979264520e-01 + 2.628000000000e-10 3.186495551608e-01 + 2.728000000000e-10 1.849115684226e-01 + 2.828000000000e-10 2.146912258403e-02 + 2.928000000000e-10 -1.215319416200e-01 + 3.028000000000e-10 -2.147336364713e-01 + 3.128000000000e-10 -2.593628319189e-01 + 3.228000000000e-10 -2.947919001104e-01 + 3.328000000000e-10 -3.306034656465e-01 + 3.428000000000e-10 -3.598903423599e-01 + 3.528000000000e-10 -3.674806029527e-01 + 3.628000000000e-10 -3.131864519443e-01 + 3.728000000000e-10 -1.816607205648e-01 + 3.828000000000e-10 -2.002885045896e-02 + 3.928000000000e-10 1.219326732879e-01 + 4.028000000000e-10 2.146583452252e-01 + 4.128000000000e-10 2.593288859790e-01 + 4.228000000000e-10 2.947836961551e-01 + 4.328000000000e-10 3.305873089453e-01 + 4.428000000000e-10 3.597520160348e-01 + 4.528000000000e-10 3.672634041173e-01 + 4.628000000000e-10 3.128292575731e-01 + 4.728000000000e-10 1.812525079401e-01 + 4.828000000000e-10 1.956255085056e-02 + 4.928000000000e-10 -1.223539241893e-01 + 5.028000000000e-10 -2.150587893921e-01 + 5.128000000000e-10 -2.596440912838e-01 + 5.228000000000e-10 -2.950896959018e-01 + 5.328000000000e-10 -3.308452440946e-01 + 5.428000000000e-10 -3.600168265621e-01 + 5.528000000000e-10 -3.674687038170e-01 + 5.628000000000e-10 -3.130140501398e-01 + 5.728000000000e-10 -1.813584327872e-01 + 5.828000000000e-10 -1.965159115909e-02 + 5.928000000000e-10 1.223212864923e-01 + 6.028000000000e-10 2.150157103205e-01 + 6.128000000000e-10 2.596318060931e-01 + 6.228000000000e-10 2.950524078153e-01 + 6.328000000000e-10 3.308363963911e-01 + 6.428000000000e-10 3.599874022300e-01 + 6.528000000000e-10 3.674690181116e-01 + 6.628000000000e-10 3.129980588961e-01 + 6.728000000000e-10 1.813712653368e-01 + 6.828000000000e-10 1.964491680526e-02 + 6.928000000000e-10 -1.223023112353e-01 + 7.028000000000e-10 -2.150202483004e-01 + 7.128000000000e-10 -2.596144309164e-01 + 7.228000000000e-10 -2.950582886643e-01 + 7.328000000000e-10 -3.308199600200e-01 + 7.428000000000e-10 -3.599931640339e-01 + 7.528000000000e-10 -3.674538095645e-01 + 7.628000000000e-10 -3.130042913922e-01 + 7.728000000000e-10 -1.813570925598e-01 + 7.828000000000e-10 -1.965290666609e-02 + 7.928000000000e-10 1.223145971689e-01 + 8.028000000000e-10 2.150114430495e-01 + 8.128000000000e-10 2.596256780136e-01 + 8.228000000000e-10 2.950490452158e-01 + 8.328000000000e-10 3.308307530718e-01 + 8.428000000000e-10 3.599842799802e-01 + 8.528000000000e-10 3.674639698479e-01 + 8.628000000000e-10 3.129957925611e-01 + 8.728000000000e-10 1.813666711568e-01 + 8.828000000000e-10 1.964348030724e-02 + 8.928000000000e-10 -1.223056361887e-01 + 9.028000000000e-10 -2.150207890100e-01 + 9.128000000000e-10 -2.596171721225e-01 + 9.228000000000e-10 -2.950581404305e-01 + 9.328000000000e-10 -3.308221104591e-01 + 9.428000000000e-10 -3.599929167296e-01 + 9.528000000000e-10 -3.674557320782e-01 + 9.628000000000e-10 -3.130039671541e-01 + 9.728000000000e-10 -1.813582011282e-01 + 9.828000000000e-10 -1.965175786777e-02 + 9.928000000000e-10 1.223137237372e-01 + 1.000000000000e-09 1.953703252853e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/conditions.yaml new file mode 100644 index 00000000..af051d44 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 15 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_15 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/CML_core_tb.sch new file mode 100644 index 00000000..1a545dad --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/CML_core_tb_16.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/CML_core_tb_16.data new file mode 100644 index 00000000..c0c44c66 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/CML_core_tb_16.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908214410229e-01 + 1.728000000000e-10 -1.609006026552e-01 + 1.828000000000e-10 -2.321243117629e-03 + 1.928000000000e-10 1.363185315112e-01 + 2.028000000000e-10 2.253864999197e-01 + 2.128000000000e-10 2.667546328680e-01 + 2.228000000000e-10 3.007016001191e-01 + 2.328000000000e-10 3.359037685855e-01 + 2.428000000000e-10 3.646369081917e-01 + 2.528000000000e-10 3.717564842409e-01 + 2.628000000000e-10 3.164681086559e-01 + 2.728000000000e-10 1.842122200319e-01 + 2.828000000000e-10 2.261788955655e-02 + 2.928000000000e-10 -1.190364341005e-01 + 3.028000000000e-10 -2.112326750882e-01 + 3.128000000000e-10 -2.547832728498e-01 + 3.228000000000e-10 -2.901354995194e-01 + 3.328000000000e-10 -3.261256516764e-01 + 3.428000000000e-10 -3.558916364396e-01 + 3.528000000000e-10 -3.643768878587e-01 + 3.628000000000e-10 -3.109660871267e-01 + 3.728000000000e-10 -1.806005122430e-01 + 3.828000000000e-10 -2.063463882859e-02 + 3.928000000000e-10 1.200417121301e-01 + 4.028000000000e-10 2.117115066678e-01 + 4.128000000000e-10 2.552245954862e-01 + 4.228000000000e-10 2.905358174314e-01 + 4.328000000000e-10 3.264964127076e-01 + 4.428000000000e-10 3.561164409890e-01 + 4.528000000000e-10 3.644937527082e-01 + 4.628000000000e-10 3.108863598347e-01 + 4.728000000000e-10 1.804066968471e-01 + 4.828000000000e-10 2.031749353463e-02 + 4.928000000000e-10 -1.203543467152e-01 + 5.028000000000e-10 -2.120338656010e-01 + 5.128000000000e-10 -2.554694201182e-01 + 5.228000000000e-10 -2.907816217466e-01 + 5.328000000000e-10 -3.266973931907e-01 + 5.428000000000e-10 -3.563354715244e-01 + 5.528000000000e-10 -3.646612654323e-01 + 5.628000000000e-10 -3.110514282819e-01 + 5.728000000000e-10 -1.805042989376e-01 + 5.828000000000e-10 -2.041198102925e-02 + 5.928000000000e-10 1.203139122453e-01 + 6.028000000000e-10 2.119789678115e-01 + 6.128000000000e-10 2.554499136191e-01 + 6.228000000000e-10 2.907352766216e-01 + 6.328000000000e-10 3.266827936599e-01 + 6.428000000000e-10 3.562972261563e-01 + 6.528000000000e-10 3.646559193667e-01 + 6.628000000000e-10 3.110272539685e-01 + 6.728000000000e-10 1.805126920434e-01 + 6.828000000000e-10 2.039901072518e-02 + 6.928000000000e-10 -1.202975671206e-01 + 7.028000000000e-10 -2.119881389434e-01 + 7.128000000000e-10 -2.554339974826e-01 + 7.228000000000e-10 -2.907449786827e-01 + 7.328000000000e-10 -3.266672756474e-01 + 7.428000000000e-10 -3.563063206496e-01 + 7.528000000000e-10 -3.646410588059e-01 + 7.628000000000e-10 -3.110359790738e-01 + 7.728000000000e-10 -1.804978632753e-01 + 7.828000000000e-10 -2.040852410596e-02 + 7.928000000000e-10 1.203110667878e-01 + 8.028000000000e-10 2.119781439274e-01 + 8.128000000000e-10 2.554465105638e-01 + 8.228000000000e-10 2.907345088651e-01 + 8.328000000000e-10 3.266793442083e-01 + 8.428000000000e-10 3.562962712815e-01 + 8.528000000000e-10 3.646525269207e-01 + 8.628000000000e-10 3.110264147595e-01 + 8.728000000000e-10 1.805087495738e-01 + 8.828000000000e-10 2.039807927138e-02 + 8.928000000000e-10 -1.203008828088e-01 + 9.028000000000e-10 -2.119885143169e-01 + 9.128000000000e-10 -2.554368509477e-01 + 9.228000000000e-10 -2.907446372900e-01 + 9.328000000000e-10 -3.266695427412e-01 + 9.428000000000e-10 -3.563059183968e-01 + 9.528000000000e-10 -3.646431522847e-01 + 9.628000000000e-10 -3.110356032735e-01 + 9.728000000000e-10 -1.804991631480e-01 + 9.828000000000e-10 -2.040735001275e-02 + 9.928000000000e-10 1.203099974113e-01 + 1.000000000000e-09 1.927324868168e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/conditions.yaml new file mode 100644 index 00000000..d825a315 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 16 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_16 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/CML_core_tb.sch new file mode 100644 index 00000000..64e75d03 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/CML_core_tb_17.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/CML_core_tb_17.data new file mode 100644 index 00000000..1e62d263 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/CML_core_tb_17.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.857852225245e-01 + 1.728000000000e-10 -1.572533595452e-01 + 1.828000000000e-10 2.540381659783e-03 + 1.928000000000e-10 1.434374080790e-01 + 2.028000000000e-10 2.351272809546e-01 + 2.128000000000e-10 2.797956268783e-01 + 2.228000000000e-10 3.144243918962e-01 + 2.328000000000e-10 3.493618787392e-01 + 2.428000000000e-10 3.773715695689e-01 + 2.528000000000e-10 3.831823569325e-01 + 2.628000000000e-10 3.264482498061e-01 + 2.728000000000e-10 1.910530045686e-01 + 2.828000000000e-10 2.436059711742e-02 + 2.928000000000e-10 -1.220220612332e-01 + 3.028000000000e-10 -2.180809390746e-01 + 3.128000000000e-10 -2.653775774444e-01 + 3.228000000000e-10 -3.017848824321e-01 + 3.328000000000e-10 -3.379021858146e-01 + 3.428000000000e-10 -3.673696540777e-01 + 3.528000000000e-10 -3.751149757425e-01 + 3.628000000000e-10 -3.209083740174e-01 + 3.728000000000e-10 -1.878979131572e-01 + 3.828000000000e-10 -2.307531260616e-02 + 3.928000000000e-10 1.222703025101e-01 + 4.028000000000e-10 2.179003509445e-01 + 4.128000000000e-10 2.652908784701e-01 + 4.228000000000e-10 3.017672646237e-01 + 4.328000000000e-10 3.378931599738e-01 + 4.428000000000e-10 3.672390198172e-01 + 4.528000000000e-10 3.748903812400e-01 + 4.628000000000e-10 3.205316331029e-01 + 4.728000000000e-10 1.874647700937e-01 + 4.828000000000e-10 2.258819957166e-02 + 4.928000000000e-10 -1.227112688171e-01 + 5.028000000000e-10 -2.183172764214e-01 + 5.128000000000e-10 -2.656203742551e-01 + 5.228000000000e-10 -3.020800906145e-01 + 5.328000000000e-10 -3.381553362553e-01 + 5.428000000000e-10 -3.675051891202e-01 + 5.528000000000e-10 -3.750972240389e-01 + 5.628000000000e-10 -3.207148935088e-01 + 5.728000000000e-10 -1.875700292984e-01 + 5.828000000000e-10 -2.267596999196e-02 + 5.928000000000e-10 1.226776663562e-01 + 6.028000000000e-10 2.182733434309e-01 + 6.128000000000e-10 2.656053081095e-01 + 6.228000000000e-10 3.020411985396e-01 + 6.328000000000e-10 3.381435634392e-01 + 6.428000000000e-10 3.674743818406e-01 + 6.528000000000e-10 3.750952532513e-01 + 6.628000000000e-10 3.206986438750e-01 + 6.728000000000e-10 1.875816736609e-01 + 6.828000000000e-10 2.266940437016e-02 + 6.928000000000e-10 -1.226596158426e-01 + 7.028000000000e-10 -2.182776851932e-01 + 7.128000000000e-10 -2.655888997029e-01 + 7.228000000000e-10 -3.020470638059e-01 + 7.328000000000e-10 -3.381282771084e-01 + 7.428000000000e-10 -3.674800981492e-01 + 7.528000000000e-10 -3.750811166601e-01 + 7.628000000000e-10 -3.207046174850e-01 + 7.728000000000e-10 -1.875682790354e-01 + 7.828000000000e-10 -2.267703281628e-02 + 7.928000000000e-10 1.226713327530e-01 + 8.028000000000e-10 2.182693863135e-01 + 8.128000000000e-10 2.655996099454e-01 + 8.228000000000e-10 3.020383466326e-01 + 8.328000000000e-10 3.381385294735e-01 + 8.428000000000e-10 3.674717742910e-01 + 8.528000000000e-10 3.750907045119e-01 + 8.628000000000e-10 3.206966644115e-01 + 8.728000000000e-10 1.875773616331e-01 + 8.828000000000e-10 2.266807684955e-02 + 8.928000000000e-10 -1.226628120211e-01 + 9.028000000000e-10 -2.182782381400e-01 + 9.128000000000e-10 -2.655915506047e-01 + 9.228000000000e-10 -3.020469590318e-01 + 9.328000000000e-10 -3.381303351991e-01 + 9.428000000000e-10 -3.674798958779e-01 + 9.528000000000e-10 -3.750829516380e-01 + 9.628000000000e-10 -3.207043265993e-01 + 9.728000000000e-10 -1.875693454762e-01 + 9.828000000000e-10 -2.267594148777e-02 + 9.928000000000e-10 1.226704651969e-01 + 1.000000000000e-09 1.977257563344e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/conditions.yaml new file mode 100644 index 00000000..3cb2e6fa --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 17 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_17 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/CML_core_tb.sch new file mode 100644 index 00000000..5197b24e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/CML_core_tb_18.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/CML_core_tb_18.data new file mode 100644 index 00000000..16422ca1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/CML_core_tb_18.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.213526702696e-01 + 1.728000000000e-10 -1.557909441213e-01 + 1.828000000000e-10 3.476956205809e-02 + 1.928000000000e-10 1.811250151598e-01 + 2.028000000000e-10 2.596166993269e-01 + 2.128000000000e-10 2.853727091731e-01 + 2.228000000000e-10 3.254453264627e-01 + 2.328000000000e-10 3.792799604087e-01 + 2.428000000000e-10 4.176388066249e-01 + 2.528000000000e-10 4.205544301124e-01 + 2.628000000000e-10 3.463528198985e-01 + 2.728000000000e-10 1.792096076204e-01 + 2.828000000000e-10 -1.442396833933e-02 + 2.928000000000e-10 -1.649237711275e-01 + 3.028000000000e-10 -2.471596975948e-01 + 3.128000000000e-10 -2.748735614517e-01 + 3.228000000000e-10 -3.160128767795e-01 + 3.328000000000e-10 -3.707930594343e-01 + 3.428000000000e-10 -4.104823651943e-01 + 3.528000000000e-10 -4.153692056047e-01 + 3.628000000000e-10 -3.427931169871e-01 + 3.728000000000e-10 -1.769552164151e-01 + 3.828000000000e-10 1.590673093360e-02 + 3.928000000000e-10 1.658834812043e-01 + 4.028000000000e-10 2.479775600913e-01 + 4.128000000000e-10 2.756409688001e-01 + 4.228000000000e-10 3.168596600790e-01 + 4.328000000000e-10 3.715133147191e-01 + 4.428000000000e-10 4.111218222953e-01 + 4.528000000000e-10 4.157229971644e-01 + 4.628000000000e-10 3.430019798682e-01 + 4.728000000000e-10 1.769456026445e-01 + 4.828000000000e-10 -1.592886494610e-02 + 4.928000000000e-10 -1.659782283296e-01 + 5.028000000000e-10 -2.479947853664e-01 + 5.128000000000e-10 -2.756931315881e-01 + 5.228000000000e-10 -3.168416717549e-01 + 5.328000000000e-10 -3.715547211919e-01 + 5.428000000000e-10 -4.111034138799e-01 + 5.528000000000e-10 -4.157691346087e-01 + 5.628000000000e-10 -3.429925568898e-01 + 5.728000000000e-10 -1.770024985869e-01 + 5.828000000000e-10 1.592938202906e-02 + 5.928000000000e-10 1.659292038608e-01 + 6.028000000000e-10 2.480043512000e-01 + 6.128000000000e-10 2.756533285421e-01 + 6.228000000000e-10 3.168576585763e-01 + 6.328000000000e-10 3.715156583068e-01 + 6.428000000000e-10 4.111207690964e-01 + 6.528000000000e-10 4.157343976531e-01 + 6.628000000000e-10 3.430135347581e-01 + 6.728000000000e-10 1.769734665185e-01 + 6.828000000000e-10 -1.590652763180e-02 + 6.928000000000e-10 -1.659537152419e-01 + 7.028000000000e-10 -2.479812550746e-01 + 7.128000000000e-10 -2.756768834918e-01 + 7.228000000000e-10 -3.168350969677e-01 + 7.328000000000e-10 -3.715419152243e-01 + 7.428000000000e-10 -4.110983779981e-01 + 7.528000000000e-10 -4.157587194411e-01 + 7.628000000000e-10 -3.429901444601e-01 + 7.728000000000e-10 -1.769973775521e-01 + 7.828000000000e-10 1.592723735432e-02 + 7.928000000000e-10 1.659318535084e-01 + 8.028000000000e-10 2.480017799848e-01 + 8.128000000000e-10 2.756559811492e-01 + 8.228000000000e-10 3.168566227283e-01 + 8.328000000000e-10 3.715195500188e-01 + 8.428000000000e-10 4.111190536097e-01 + 8.528000000000e-10 4.157370668569e-01 + 8.628000000000e-10 3.430103710665e-01 + 8.728000000000e-10 1.769771675859e-01 + 8.828000000000e-10 -1.590770493918e-02 + 8.928000000000e-10 -1.659501582149e-01 + 9.028000000000e-10 -2.479827571068e-01 + 9.128000000000e-10 -2.756738772283e-01 + 9.228000000000e-10 -3.168377001445e-01 + 9.328000000000e-10 -3.715391180409e-01 + 9.428000000000e-10 -4.111007797151e-01 + 9.528000000000e-10 -4.157556639381e-01 + 9.628000000000e-10 -3.429919881202e-01 + 9.728000000000e-10 -1.769955652012e-01 + 9.828000000000e-10 1.592430721908e-02 + 9.928000000000e-10 1.659331850974e-01 + 1.000000000000e-09 2.332140069758e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/conditions.yaml new file mode 100644 index 00000000..91af7080 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 18 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_18 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/CML_core_tb.sch new file mode 100644 index 00000000..a671bfb7 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/CML_core_tb_19.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/CML_core_tb_19.data new file mode 100644 index 00000000..6e384890 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/CML_core_tb_19.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162777317791e-01 + 1.728000000000e-10 -1.528661974147e-01 + 1.828000000000e-10 3.474832458294e-02 + 1.928000000000e-10 1.787124308466e-01 + 2.028000000000e-10 2.559986610902e-01 + 2.128000000000e-10 2.810767408313e-01 + 2.228000000000e-10 3.219404824571e-01 + 2.328000000000e-10 3.760375868322e-01 + 2.428000000000e-10 4.141294975409e-01 + 2.528000000000e-10 4.175370858756e-01 + 2.628000000000e-10 3.443891646085e-01 + 2.728000000000e-10 1.786024667409e-01 + 2.828000000000e-10 -1.272368439666e-02 + 2.928000000000e-10 -1.612661145276e-01 + 3.028000000000e-10 -2.425558656005e-01 + 3.128000000000e-10 -2.696709375544e-01 + 3.228000000000e-10 -3.115976016931e-01 + 3.328000000000e-10 -3.666762080522e-01 + 3.428000000000e-10 -4.062269757432e-01 + 3.528000000000e-10 -4.117682170104e-01 + 3.628000000000e-10 -3.403932990270e-01 + 3.728000000000e-10 -1.760595961534e-01 + 3.828000000000e-10 1.438676142530e-02 + 3.928000000000e-10 1.623380571180e-01 + 4.028000000000e-10 2.434588647096e-01 + 4.128000000000e-10 2.705169080514e-01 + 4.228000000000e-10 3.125303134845e-01 + 4.328000000000e-10 3.674735521527e-01 + 4.428000000000e-10 4.069324770669e-01 + 4.528000000000e-10 4.121668816011e-01 + 4.628000000000e-10 3.406314536055e-01 + 4.728000000000e-10 1.760592839129e-01 + 4.828000000000e-10 -1.440702618479e-02 + 4.928000000000e-10 -1.624387020945e-01 + 5.028000000000e-10 -2.434775787799e-01 + 5.128000000000e-10 -2.705727170369e-01 + 5.228000000000e-10 -3.125119373252e-01 + 5.328000000000e-10 -3.675184828947e-01 + 5.428000000000e-10 -4.069140356329e-01 + 5.528000000000e-10 -4.122173977207e-01 + 5.628000000000e-10 -3.406230488723e-01 + 5.728000000000e-10 -1.761225643375e-01 + 5.828000000000e-10 1.440482600394e-02 + 5.928000000000e-10 1.623840500109e-01 + 6.028000000000e-10 2.434858819416e-01 + 6.128000000000e-10 2.705285901327e-01 + 6.228000000000e-10 3.125279242462e-01 + 6.328000000000e-10 3.674758375852e-01 + 6.428000000000e-10 4.069313048189e-01 + 6.528000000000e-10 4.121794941223e-01 + 6.628000000000e-10 3.406442721772e-01 + 6.728000000000e-10 1.760913923029e-01 + 6.828000000000e-10 -1.438048626859e-02 + 6.928000000000e-10 -1.624102913298e-01 + 7.028000000000e-10 -2.434611919520e-01 + 7.128000000000e-10 -2.705537859875e-01 + 7.228000000000e-10 -3.125040211699e-01 + 7.328000000000e-10 -3.675038904367e-01 + 7.428000000000e-10 -4.069074652851e-01 + 7.528000000000e-10 -4.122054838885e-01 + 7.628000000000e-10 -3.406192567768e-01 + 7.728000000000e-10 -1.761170868219e-01 + 7.828000000000e-10 1.440247036537e-02 + 7.928000000000e-10 1.623867436405e-01 + 8.028000000000e-10 2.434830143217e-01 + 8.128000000000e-10 2.705312548291e-01 + 8.228000000000e-10 3.125271394700e-01 + 8.328000000000e-10 3.674800931307e-01 + 8.428000000000e-10 4.069295144266e-01 + 8.528000000000e-10 4.121823557439e-01 + 8.628000000000e-10 3.406407407456e-01 + 8.728000000000e-10 1.760956573916e-01 + 8.828000000000e-10 -1.438135361500e-02 + 8.928000000000e-10 -1.624062315135e-01 + 9.028000000000e-10 -2.434625084707e-01 + 9.128000000000e-10 -2.705503455528e-01 + 9.228000000000e-10 -3.125068466958e-01 + 9.328000000000e-10 -3.675009271833e-01 + 9.428000000000e-10 -4.069098943042e-01 + 9.528000000000e-10 -4.122022218921e-01 + 9.628000000000e-10 -3.406210058100e-01 + 9.728000000000e-10 -1.761154015725e-01 + 9.828000000000e-10 1.439913133121e-02 + 9.928000000000e-10 1.623879640093e-01 + 1.000000000000e-09 2.290402036537e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/conditions.yaml new file mode 100644 index 00000000..21cf7323 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 19 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_19 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/CML_core_tb.sch new file mode 100644 index 00000000..e0f62cb2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/CML_core_tb_20.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/CML_core_tb_20.data new file mode 100644 index 00000000..3dfcf241 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/CML_core_tb_20.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.365386572536e-01 + 1.728000000000e-10 -1.657072094068e-01 + 1.828000000000e-10 3.099865584261e-02 + 1.928000000000e-10 1.820426436768e-01 + 2.028000000000e-10 2.627018214462e-01 + 2.128000000000e-10 2.893736945719e-01 + 2.228000000000e-10 3.287984169352e-01 + 2.328000000000e-10 3.833334317825e-01 + 2.428000000000e-10 4.238785365972e-01 + 2.528000000000e-10 4.280322768716e-01 + 2.628000000000e-10 3.532409470363e-01 + 2.728000000000e-10 1.834641899168e-01 + 2.828000000000e-10 -1.474496205711e-02 + 2.928000000000e-10 -1.691349612478e-01 + 3.028000000000e-10 -2.530204867896e-01 + 3.128000000000e-10 -2.814070764654e-01 + 3.228000000000e-10 -3.218416847899e-01 + 3.328000000000e-10 -3.771799136100e-01 + 3.428000000000e-10 -4.187055626636e-01 + 3.528000000000e-10 -4.243036771430e-01 + 3.628000000000e-10 -3.506062035467e-01 + 3.728000000000e-10 -1.816763297909e-01 + 3.828000000000e-10 1.601938741723e-02 + 3.928000000000e-10 1.700087907901e-01 + 4.028000000000e-10 2.537596951165e-01 + 4.128000000000e-10 2.820887501770e-01 + 4.228000000000e-10 3.225625541805e-01 + 4.328000000000e-10 3.777928583784e-01 + 4.428000000000e-10 4.192485534625e-01 + 4.528000000000e-10 4.246080285894e-01 + 4.628000000000e-10 3.507916132015e-01 + 4.728000000000e-10 1.816929452641e-01 + 4.828000000000e-10 -1.601075067965e-02 + 4.928000000000e-10 -1.700562644838e-01 + 5.028000000000e-10 -2.537513990380e-01 + 5.128000000000e-10 -2.821086741965e-01 + 5.228000000000e-10 -3.225309737549e-01 + 5.328000000000e-10 -3.778081660132e-01 + 5.428000000000e-10 -4.192196231589e-01 + 5.528000000000e-10 -4.246325132019e-01 + 5.628000000000e-10 -3.507765562578e-01 + 5.728000000000e-10 -1.817315603141e-01 + 5.828000000000e-10 1.601468821266e-02 + 5.928000000000e-10 1.700220210141e-01 + 6.028000000000e-10 2.537612841477e-01 + 6.128000000000e-10 2.820810469197e-01 + 6.228000000000e-10 3.225454957468e-01 + 6.328000000000e-10 3.777800822765e-01 + 6.428000000000e-10 4.192350742948e-01 + 6.528000000000e-10 4.246071005326e-01 + 6.628000000000e-10 3.507940665347e-01 + 6.728000000000e-10 1.817094337521e-01 + 6.828000000000e-10 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9.328000000000e-10 -3.777982010874e-01 + 9.428000000000e-10 -4.192199753705e-01 + 9.528000000000e-10 -4.246232587341e-01 + 9.628000000000e-10 -3.507775800865e-01 + 9.728000000000e-10 -1.817263367247e-01 + 9.828000000000e-10 1.601066647660e-02 + 9.928000000000e-10 1.700248857455e-01 + 1.000000000000e-09 2.385375784000e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/conditions.yaml new file mode 100644 index 00000000..33a0c986 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 20 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_20 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/CML_core_tb.sch new file mode 100644 index 00000000..b1c82055 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/CML_core_tb_21.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/CML_core_tb_21.data new file mode 100644 index 00000000..86f9b023 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/CML_core_tb_21.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.747912795524e-01 + 1.728000000000e-10 -1.327955908449e-01 + 1.828000000000e-10 3.931332790349e-02 + 1.928000000000e-10 1.782957289495e-01 + 2.028000000000e-10 2.573194188668e-01 + 2.128000000000e-10 2.870254911902e-01 + 2.228000000000e-10 3.228650321442e-01 + 2.328000000000e-10 3.690575149088e-01 + 2.428000000000e-10 4.023791308175e-01 + 2.528000000000e-10 4.034409994944e-01 + 2.628000000000e-10 3.332295993533e-01 + 2.728000000000e-10 1.767123870243e-01 + 2.828000000000e-10 -7.574880255958e-03 + 2.928000000000e-10 -1.550892096227e-01 + 3.028000000000e-10 -2.394679486139e-01 + 3.128000000000e-10 -2.715465054757e-01 + 3.228000000000e-10 -3.085580168164e-01 + 3.328000000000e-10 -3.560821219044e-01 + 3.428000000000e-10 -3.914831036325e-01 + 3.528000000000e-10 -3.956717314322e-01 + 3.628000000000e-10 -3.285929470428e-01 + 3.728000000000e-10 -1.747908753666e-01 + 3.828000000000e-10 7.882784627431e-03 + 3.928000000000e-10 1.545893087045e-01 + 4.028000000000e-10 2.389887597051e-01 + 4.128000000000e-10 2.712307710628e-01 + 4.228000000000e-10 3.085047043395e-01 + 4.328000000000e-10 3.559448484744e-01 + 4.428000000000e-10 3.913507819782e-01 + 4.528000000000e-10 3.953547803018e-01 + 4.628000000000e-10 3.282585464854e-01 + 4.728000000000e-10 1.743078825018e-01 + 4.828000000000e-10 -8.291328068348e-03 + 4.928000000000e-10 -1.550293895867e-01 + 5.028000000000e-10 -2.392804293874e-01 + 5.128000000000e-10 -2.715405217782e-01 + 5.228000000000e-10 -3.087067361985e-01 + 5.328000000000e-10 -3.562070457914e-01 + 5.428000000000e-10 -3.915132320474e-01 + 5.528000000000e-10 -3.955548280332e-01 + 5.628000000000e-10 -3.283427048941e-01 + 5.728000000000e-10 -1.744282326244e-01 + 5.828000000000e-10 8.270645751064e-03 + 5.928000000000e-10 1.549582711486e-01 + 6.028000000000e-10 2.392860039329e-01 + 6.128000000000e-10 2.714820836214e-01 + 6.228000000000e-10 3.087161022039e-01 + 6.328000000000e-10 3.561494137047e-01 + 6.428000000000e-10 3.915273490759e-01 + 6.528000000000e-10 3.955079501007e-01 + 6.628000000000e-10 3.283677191723e-01 + 6.728000000000e-10 1.743944727908e-01 + 6.828000000000e-10 -8.238033211244e-03 + 6.928000000000e-10 -1.549849820320e-01 + 7.028000000000e-10 -2.392533741503e-01 + 7.128000000000e-10 -2.715088112944e-01 + 7.228000000000e-10 -3.086845279612e-01 + 7.328000000000e-10 -3.561786907982e-01 + 7.428000000000e-10 -3.914967682891e-01 + 7.528000000000e-10 -3.955360247734e-01 + 7.628000000000e-10 -3.283379458960e-01 + 7.728000000000e-10 -1.744219452106e-01 + 7.828000000000e-10 8.266285029230e-03 + 7.928000000000e-10 1.549592969714e-01 + 8.028000000000e-10 2.392805186707e-01 + 8.128000000000e-10 2.714837558368e-01 + 8.228000000000e-10 3.087120651005e-01 + 8.328000000000e-10 3.561520690508e-01 + 8.428000000000e-10 3.915233230940e-01 + 8.528000000000e-10 3.955100606400e-01 + 8.628000000000e-10 3.283632493206e-01 + 8.728000000000e-10 1.743968536756e-01 + 8.828000000000e-10 -8.241845610385e-03 + 8.928000000000e-10 -1.549825747228e-01 + 9.028000000000e-10 -2.392568734068e-01 + 9.128000000000e-10 -2.715063119250e-01 + 9.228000000000e-10 -3.086881712182e-01 + 9.328000000000e-10 -3.561760305782e-01 + 9.428000000000e-10 -3.915002731039e-01 + 9.528000000000e-10 -3.955331724158e-01 + 9.628000000000e-10 -3.283409163093e-01 + 9.728000000000e-10 -1.744193777973e-01 + 9.828000000000e-10 8.263272108901e-03 + 9.928000000000e-10 1.549616575981e-01 + 1.000000000000e-09 2.229820050464e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/conditions.yaml new file mode 100644 index 00000000..10533a26 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 21 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_21 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/CML_core_tb.sch new file mode 100644 index 00000000..247c0b46 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/CML_core_tb_22.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/CML_core_tb_22.data new file mode 100644 index 00000000..ef0e6c8e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/CML_core_tb_22.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.701426652476e-01 + 1.728000000000e-10 -1.295079168872e-01 + 1.828000000000e-10 4.028305902420e-02 + 1.928000000000e-10 1.769160181627e-01 + 2.028000000000e-10 2.543038782058e-01 + 2.128000000000e-10 2.828787064062e-01 + 2.228000000000e-10 3.193333275112e-01 + 2.328000000000e-10 3.660596632426e-01 + 2.428000000000e-10 3.993599084345e-01 + 2.528000000000e-10 4.007883413226e-01 + 2.628000000000e-10 3.312419521143e-01 + 2.728000000000e-10 1.754810620333e-01 + 2.828000000000e-10 -7.142746942805e-03 + 2.928000000000e-10 -1.527779354444e-01 + 3.028000000000e-10 -2.358001938178e-01 + 3.128000000000e-10 -2.668485168237e-01 + 3.228000000000e-10 -3.044746718514e-01 + 3.328000000000e-10 -3.525545062341e-01 + 3.428000000000e-10 -3.880254364838e-01 + 3.528000000000e-10 -3.926522183008e-01 + 3.628000000000e-10 -3.262954780243e-01 + 3.728000000000e-10 -1.733443838482e-01 + 3.828000000000e-10 7.573790689709e-03 + 3.928000000000e-10 1.523487073311e-01 + 4.028000000000e-10 2.353677758316e-01 + 4.128000000000e-10 2.665695097895e-01 + 4.228000000000e-10 3.044490522149e-01 + 4.328000000000e-10 3.524353166192e-01 + 4.428000000000e-10 3.879041587545e-01 + 4.528000000000e-10 3.923389296672e-01 + 4.628000000000e-10 3.259554596391e-01 + 4.728000000000e-10 1.728458619818e-01 + 4.828000000000e-10 -8.002573892585e-03 + 4.928000000000e-10 -1.528088090159e-01 + 5.028000000000e-10 -2.356747724378e-01 + 5.128000000000e-10 -2.668925685814e-01 + 5.228000000000e-10 -3.046638401901e-01 + 5.328000000000e-10 -3.527112223433e-01 + 5.428000000000e-10 -3.880786380631e-01 + 5.528000000000e-10 -3.925506229445e-01 + 5.628000000000e-10 -3.260495799326e-01 + 5.728000000000e-10 -1.729761662154e-01 + 5.828000000000e-10 7.974498187451e-03 + 5.928000000000e-10 1.527311696558e-01 + 6.028000000000e-10 2.356760074325e-01 + 6.128000000000e-10 2.668297167568e-01 + 6.228000000000e-10 3.046702367069e-01 + 6.328000000000e-10 3.526500635637e-01 + 6.428000000000e-10 3.880902250634e-01 + 6.528000000000e-10 3.925010528185e-01 + 6.628000000000e-10 3.260730653917e-01 + 6.728000000000e-10 1.729410953112e-01 + 6.828000000000e-10 -7.941970684065e-03 + 6.928000000000e-10 -1.527585341072e-01 + 7.028000000000e-10 -2.356430884825e-01 + 7.128000000000e-10 -2.668569558480e-01 + 7.228000000000e-10 -3.046384985761e-01 + 7.328000000000e-10 -3.526798341051e-01 + 7.428000000000e-10 -3.880593641809e-01 + 7.528000000000e-10 -3.925295324367e-01 + 7.628000000000e-10 -3.260427874257e-01 + 7.728000000000e-10 -1.729689796013e-01 + 7.828000000000e-10 7.970639231343e-03 + 7.928000000000e-10 1.527324506408e-01 + 8.028000000000e-10 2.356706370408e-01 + 8.128000000000e-10 2.668314718812e-01 + 8.228000000000e-10 3.046665550415e-01 + 8.328000000000e-10 3.526529348742e-01 + 8.428000000000e-10 3.880863283995e-01 + 8.528000000000e-10 3.925032166540e-01 + 8.628000000000e-10 3.260684590033e-01 + 8.728000000000e-10 1.729436324779e-01 + 8.828000000000e-10 -7.945691115533e-03 + 8.928000000000e-10 -1.527560420249e-01 + 9.028000000000e-10 -2.356465048672e-01 + 9.128000000000e-10 -2.668543449819e-01 + 9.228000000000e-10 -3.046422495200e-01 + 9.328000000000e-10 -3.526772110923e-01 + 9.428000000000e-10 -3.880628732866e-01 + 9.528000000000e-10 -3.925266759429e-01 + 9.628000000000e-10 -3.260456785141e-01 + 9.728000000000e-10 -1.729665660062e-01 + 9.828000000000e-10 7.967487161613e-03 + 9.928000000000e-10 1.527347010769e-01 + 1.000000000000e-09 2.198236907112e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/conditions.yaml new file mode 100644 index 00000000..056e114c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 22 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_22 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/CML_core_tb.sch new file mode 100644 index 00000000..aacf6b64 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/CML_core_tb_23.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/CML_core_tb_23.data new file mode 100644 index 00000000..7b2e7ab2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/CML_core_tb_23.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.957054612407e-01 + 1.728000000000e-10 -1.475216919691e-01 + 1.828000000000e-10 3.196996632833e-02 + 1.928000000000e-10 1.773696584526e-01 + 2.028000000000e-10 2.602670445343e-01 + 2.128000000000e-10 2.919684489720e-01 + 2.228000000000e-10 3.273690981683e-01 + 2.328000000000e-10 3.736661732429e-01 + 2.428000000000e-10 4.086769482098e-01 + 2.528000000000e-10 4.113258498473e-01 + 2.628000000000e-10 3.414272197123e-01 + 2.728000000000e-10 1.833836328070e-01 + 2.828000000000e-10 -4.501363849837e-03 + 2.928000000000e-10 -1.562318489881e-01 + 3.028000000000e-10 -2.435570784568e-01 + 3.128000000000e-10 -2.775386220390e-01 + 3.228000000000e-10 -3.142878056355e-01 + 3.328000000000e-10 -3.618442790176e-01 + 3.428000000000e-10 -3.986028140213e-01 + 3.528000000000e-10 -4.040381865127e-01 + 3.628000000000e-10 -3.369104214062e-01 + 3.728000000000e-10 -1.811830752063e-01 + 3.828000000000e-10 5.355128083595e-03 + 3.928000000000e-10 1.563630270676e-01 + 4.028000000000e-10 2.436522664355e-01 + 4.128000000000e-10 2.777202130414e-01 + 4.228000000000e-10 3.146716935396e-01 + 4.328000000000e-10 3.621309165835e-01 + 4.428000000000e-10 3.988648293319e-01 + 4.528000000000e-10 4.040567761896e-01 + 4.628000000000e-10 3.368362274946e-01 + 4.728000000000e-10 1.809052635954e-01 + 4.828000000000e-10 -5.606347307292e-03 + 4.928000000000e-10 -1.566747533637e-01 + 5.028000000000e-10 -2.438438929936e-01 + 5.128000000000e-10 -2.779365198916e-01 + 5.228000000000e-10 -3.147868656031e-01 + 5.328000000000e-10 -3.623069078218e-01 + 5.428000000000e-10 -3.989546307961e-01 + 5.528000000000e-10 -4.041975741324e-01 + 5.628000000000e-10 -3.368831845243e-01 + 5.728000000000e-10 -1.810020824460e-01 + 5.828000000000e-10 5.593858826262e-03 + 5.928000000000e-10 1.566090374935e-01 + 6.028000000000e-10 2.438493522755e-01 + 6.128000000000e-10 2.778818285943e-01 + 6.228000000000e-10 3.147972496077e-01 + 6.328000000000e-10 3.622530927659e-01 + 6.428000000000e-10 3.989689895438e-01 + 6.528000000000e-10 4.041528360847e-01 + 6.628000000000e-10 3.369065350765e-01 + 6.728000000000e-10 1.809679655825e-01 + 6.828000000000e-10 -5.565139497590e-03 + 6.928000000000e-10 -1.566366178225e-01 + 7.028000000000e-10 -2.438204188033e-01 + 7.128000000000e-10 -2.779089356335e-01 + 7.228000000000e-10 -3.147686522157e-01 + 7.328000000000e-10 -3.622826637804e-01 + 7.428000000000e-10 -3.989411843085e-01 + 7.528000000000e-10 -4.041807678845e-01 + 7.628000000000e-10 -3.368790616195e-01 + 7.728000000000e-10 -1.809947630224e-01 + 7.828000000000e-10 5.591512634984e-03 + 7.928000000000e-10 1.566120178189e-01 + 8.028000000000e-10 2.438458933358e-01 + 8.128000000000e-10 2.778849719194e-01 + 8.228000000000e-10 3.147945034671e-01 + 8.328000000000e-10 3.622568751046e-01 + 8.428000000000e-10 3.989662140554e-01 + 8.528000000000e-10 4.041558823701e-01 + 8.628000000000e-10 3.369030769235e-01 + 8.728000000000e-10 1.809706945647e-01 + 8.828000000000e-10 -5.568483515763e-03 + 8.928000000000e-10 -1.566340912711e-01 + 9.028000000000e-10 -2.438236181184e-01 + 9.128000000000e-10 -2.779064153414e-01 + 9.228000000000e-10 -3.147718720666e-01 + 9.328000000000e-10 -3.622798572716e-01 + 9.428000000000e-10 -3.989444036153e-01 + 9.528000000000e-10 -4.041778978449e-01 + 9.628000000000e-10 -3.368819513246e-01 + 9.728000000000e-10 -1.809921012276e-01 + 9.828000000000e-10 5.588724287086e-03 + 9.928000000000e-10 1.566143682128e-01 + 1.000000000000e-09 2.267750497136e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/conditions.yaml new file mode 100644 index 00000000..64e9af11 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 23 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_23 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/CML_core_tb.sch new file mode 100644 index 00000000..f736930d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/CML_core_tb_24.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/CML_core_tb_24.data new file mode 100644 index 00000000..a01deb89 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/CML_core_tb_24.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.908985659112e-01 + 1.728000000000e-10 -9.049079150817e-02 + 1.828000000000e-10 3.945873683219e-02 + 1.928000000000e-10 1.521437177417e-01 + 2.028000000000e-10 2.220068772324e-01 + 2.128000000000e-10 2.535092334052e-01 + 2.228000000000e-10 2.861973397174e-01 + 2.328000000000e-10 3.239843013312e-01 + 2.428000000000e-10 3.520113017607e-01 + 2.528000000000e-10 3.540468115658e-01 + 2.628000000000e-10 2.949447709683e-01 + 2.728000000000e-10 1.587983397866e-01 + 2.828000000000e-10 -6.865354773069e-03 + 2.928000000000e-10 -1.448078480843e-01 + 3.028000000000e-10 -2.275605338030e-01 + 3.128000000000e-10 -2.625604064747e-01 + 3.228000000000e-10 -2.958552078644e-01 + 3.328000000000e-10 -3.351711406638e-01 + 3.428000000000e-10 -3.644984224381e-01 + 3.528000000000e-10 -3.669950471097e-01 + 3.628000000000e-10 -3.072796408874e-01 + 3.728000000000e-10 -1.699866077827e-01 + 3.828000000000e-10 -2.842045316933e-03 + 3.928000000000e-10 1.365086891956e-01 + 4.028000000000e-10 2.207869920157e-01 + 4.128000000000e-10 2.567713461579e-01 + 4.228000000000e-10 2.907030026757e-01 + 4.328000000000e-10 3.302687598301e-01 + 4.428000000000e-10 3.600803190405e-01 + 4.528000000000e-10 3.632331450943e-01 + 4.628000000000e-10 3.045482678871e-01 + 4.728000000000e-10 1.682698274629e-01 + 4.828000000000e-10 2.058504292284e-03 + 4.928000000000e-10 -1.367871396964e-01 + 5.028000000000e-10 -2.207717990252e-01 + 5.128000000000e-10 -2.567684885934e-01 + 5.228000000000e-10 -2.906651825463e-01 + 5.328000000000e-10 -3.302494358660e-01 + 5.428000000000e-10 -3.599712284157e-01 + 5.528000000000e-10 -3.631239508150e-01 + 5.628000000000e-10 -3.043584109358e-01 + 5.728000000000e-10 -1.680958385636e-01 + 5.828000000000e-10 -1.834034512727e-03 + 5.928000000000e-10 1.369613450439e-01 + 6.028000000000e-10 2.209618957221e-01 + 6.128000000000e-10 2.568952536478e-01 + 6.228000000000e-10 2.908171185353e-01 + 6.328000000000e-10 3.303549214919e-01 + 6.428000000000e-10 3.601082390759e-01 + 6.528000000000e-10 3.632059905221e-01 + 6.628000000000e-10 3.044557238628e-01 + 6.728000000000e-10 1.681292777859e-01 + 6.828000000000e-10 1.882442241730e-03 + 6.928000000000e-10 -1.369637862409e-01 + 7.028000000000e-10 -2.209363992802e-01 + 7.128000000000e-10 -2.569065829626e-01 + 7.228000000000e-10 -2.907936706940e-01 + 7.328000000000e-10 -3.303682701482e-01 + 7.428000000000e-10 -3.600879594395e-01 + 7.528000000000e-10 -3.632220959958e-01 + 7.628000000000e-10 -3.044401007882e-01 + 7.728000000000e-10 -1.681486407544e-01 + 7.828000000000e-10 -1.870004957548e-03 + 7.928000000000e-10 1.369437070838e-01 + 8.028000000000e-10 2.209481957039e-01 + 8.128000000000e-10 2.568879030180e-01 + 8.228000000000e-10 2.908064848389e-01 + 8.328000000000e-10 3.303493303219e-01 + 8.428000000000e-10 3.601006147126e-01 + 8.528000000000e-10 3.632041339109e-01 + 8.628000000000e-10 3.044528281549e-01 + 8.728000000000e-10 1.681322760827e-01 + 8.828000000000e-10 1.883536763259e-03 + 8.928000000000e-10 -1.369582535540e-01 + 9.028000000000e-10 -2.209346296842e-01 + 9.128000000000e-10 -2.569016830366e-01 + 9.228000000000e-10 -2.907925936742e-01 + 9.328000000000e-10 -3.303636164667e-01 + 9.428000000000e-10 -3.600871302257e-01 + 9.528000000000e-10 -3.632178492939e-01 + 9.628000000000e-10 -3.044398392752e-01 + 9.728000000000e-10 -1.681454261603e-01 + 9.828000000000e-10 -1.870628705438e-03 + 9.928000000000e-10 1.369459433541e-01 + 1.000000000000e-09 2.037746084522e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/conditions.yaml new file mode 100644 index 00000000..9a8754c0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 24 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_24 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/CML_core_tb.sch new file mode 100644 index 00000000..1118b097 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/CML_core_tb_25.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/CML_core_tb_25.data new file mode 100644 index 00000000..182746dc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/CML_core_tb_25.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.878715792581e-01 + 1.728000000000e-10 -8.812036120597e-02 + 1.828000000000e-10 4.046526586524e-02 + 1.928000000000e-10 1.515705626527e-01 + 2.028000000000e-10 2.200566198342e-01 + 2.128000000000e-10 2.503583455541e-01 + 2.228000000000e-10 2.832914205797e-01 + 2.328000000000e-10 3.216696186231e-01 + 2.428000000000e-10 3.500303926946e-01 + 2.528000000000e-10 3.524815741411e-01 + 2.628000000000e-10 2.936462106779e-01 + 2.728000000000e-10 1.576219496242e-01 + 2.828000000000e-10 -7.121462127754e-03 + 2.928000000000e-10 -1.436071598858e-01 + 3.028000000000e-10 -2.249496922999e-01 + 3.128000000000e-10 -2.586592240194e-01 + 3.228000000000e-10 -2.922419569702e-01 + 3.328000000000e-10 -3.321983211521e-01 + 3.428000000000e-10 -3.618684381611e-01 + 3.528000000000e-10 -3.648249016007e-01 + 3.628000000000e-10 -3.055379959953e-01 + 3.728000000000e-10 -1.686105488568e-01 + 3.828000000000e-10 -2.582643774162e-03 + 3.928000000000e-10 1.352182085241e-01 + 4.028000000000e-10 2.180702244722e-01 + 4.128000000000e-10 2.527783389641e-01 + 4.228000000000e-10 2.869845016096e-01 + 4.328000000000e-10 3.271697550530e-01 + 4.428000000000e-10 3.573213651505e-01 + 4.528000000000e-10 3.609341509143e-01 + 4.628000000000e-10 3.026708512688e-01 + 4.728000000000e-10 1.667591862946e-01 + 4.828000000000e-10 1.676053368052e-03 + 4.928000000000e-10 -1.356064331336e-01 + 5.028000000000e-10 -2.181494577446e-01 + 5.128000000000e-10 -2.528581012316e-01 + 5.228000000000e-10 -2.870203472690e-01 + 5.328000000000e-10 -3.272198972187e-01 + 5.428000000000e-10 -3.572767955086e-01 + 5.528000000000e-10 -3.608816832152e-01 + 5.628000000000e-10 -3.025243774497e-01 + 5.728000000000e-10 -1.666129730216e-01 + 5.828000000000e-10 -1.465204057357e-03 + 5.928000000000e-10 1.357749931272e-01 + 6.028000000000e-10 2.183376260095e-01 + 6.128000000000e-10 2.529831758691e-01 + 6.228000000000e-10 2.871716452249e-01 + 6.328000000000e-10 3.273254918206e-01 + 6.428000000000e-10 3.574148326524e-01 + 6.528000000000e-10 3.609652866209e-01 + 6.628000000000e-10 3.026246199120e-01 + 6.728000000000e-10 1.666502220733e-01 + 6.828000000000e-10 1.518129196282e-03 + 6.928000000000e-10 -1.357732099566e-01 + 7.028000000000e-10 -2.183080403425e-01 + 7.128000000000e-10 -2.529912058397e-01 + 7.228000000000e-10 -2.871450109118e-01 + 7.328000000000e-10 -3.273360198503e-01 + 7.428000000000e-10 -3.573916245859e-01 + 7.528000000000e-10 -3.609790664977e-01 + 7.628000000000e-10 -3.026068066478e-01 + 7.728000000000e-10 -1.666683959674e-01 + 7.828000000000e-10 -1.504711775466e-03 + 7.928000000000e-10 1.357534602326e-01 + 8.028000000000e-10 2.183202914392e-01 + 8.128000000000e-10 2.529726082081e-01 + 8.228000000000e-10 2.871582302084e-01 + 8.328000000000e-10 3.273171284192e-01 + 8.428000000000e-10 3.574045685766e-01 + 8.528000000000e-10 3.609610284998e-01 + 8.628000000000e-10 3.026196909841e-01 + 8.728000000000e-10 1.666518528053e-01 + 8.828000000000e-10 1.518315117290e-03 + 8.928000000000e-10 -1.357682747942e-01 + 9.028000000000e-10 -2.183066580359e-01 + 9.128000000000e-10 -2.529866332266e-01 + 9.228000000000e-10 -2.871442829871e-01 + 9.328000000000e-10 -3.273316607928e-01 + 9.428000000000e-10 -3.573910212469e-01 + 9.528000000000e-10 -3.609749965926e-01 + 9.628000000000e-10 -3.026065830591e-01 + 9.728000000000e-10 -1.666652414066e-01 + 9.828000000000e-10 -1.505286118034e-03 + 9.928000000000e-10 1.357557668798e-01 + 1.000000000000e-09 2.016242513907e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/conditions.yaml new file mode 100644 index 00000000..5d3e544c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 25 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_25 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/CML_core_tb.sch new file mode 100644 index 00000000..28e06605 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/CML_core_tb_26.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/CML_core_tb_26.data new file mode 100644 index 00000000..c21b093d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/CML_core_tb_26.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.135873679018e-01 + 1.728000000000e-10 -1.054229355639e-01 + 1.828000000000e-10 3.485798650969e-02 + 1.928000000000e-10 1.569675139767e-01 + 2.028000000000e-10 2.330635404696e-01 + 2.128000000000e-10 2.680443549179e-01 + 2.228000000000e-10 3.014044829899e-01 + 2.328000000000e-10 3.394080314353e-01 + 2.428000000000e-10 3.679529618424e-01 + 2.528000000000e-10 3.700593040123e-01 + 2.628000000000e-10 3.097824620429e-01 + 2.728000000000e-10 1.706514675999e-01 + 2.828000000000e-10 3.558070014658e-04 + 2.928000000000e-10 -1.428409974599e-01 + 3.028000000000e-10 -2.298289579719e-01 + 3.128000000000e-10 -2.678794741753e-01 + 3.228000000000e-10 -3.017454056957e-01 + 3.328000000000e-10 -3.410620518407e-01 + 3.428000000000e-10 -3.712405389398e-01 + 3.528000000000e-10 -3.749327973471e-01 + 3.628000000000e-10 -3.157484466493e-01 + 3.728000000000e-10 -1.773087198166e-01 + 3.828000000000e-10 -7.070252178339e-03 + 3.928000000000e-10 1.364462941621e-01 + 4.028000000000e-10 2.243241068758e-01 + 4.128000000000e-10 2.631279769125e-01 + 4.228000000000e-10 2.976097246349e-01 + 4.328000000000e-10 3.371159716785e-01 + 4.428000000000e-10 3.676405775058e-01 + 4.528000000000e-10 3.717787254056e-01 + 4.628000000000e-10 3.133854979421e-01 + 4.728000000000e-10 1.756870158595e-01 + 4.828000000000e-10 6.171257018760e-03 + 4.928000000000e-10 -1.369680995621e-01 + 5.028000000000e-10 -2.245781248931e-01 + 5.128000000000e-10 -2.633829468620e-01 + 5.228000000000e-10 -2.978042748481e-01 + 5.328000000000e-10 -3.373348877854e-01 + 5.428000000000e-10 -3.677584906255e-01 + 5.528000000000e-10 -3.718812762918e-01 + 5.628000000000e-10 -3.133649557524e-01 + 5.728000000000e-10 -1.756479312047e-01 + 5.828000000000e-10 -6.040608056278e-03 + 5.928000000000e-10 1.370690415770e-01 + 6.028000000000e-10 2.247181767783e-01 + 6.128000000000e-10 2.634617265965e-01 + 6.228000000000e-10 2.979157296699e-01 + 6.328000000000e-10 3.373958940353e-01 + 6.428000000000e-10 3.678612954525e-01 + 6.528000000000e-10 3.719309221475e-01 + 6.628000000000e-10 3.134447453066e-01 + 6.728000000000e-10 1.756687688086e-01 + 6.828000000000e-10 6.090200135509e-03 + 6.928000000000e-10 -1.370702307281e-01 + 7.028000000000e-10 -2.246847420648e-01 + 7.128000000000e-10 -2.634701196121e-01 + 7.228000000000e-10 -2.978849158722e-01 + 7.328000000000e-10 -3.374068878437e-01 + 7.428000000000e-10 -3.678336110941e-01 + 7.528000000000e-10 -3.719446503824e-01 + 7.628000000000e-10 -3.134227431793e-01 + 7.728000000000e-10 -1.756868885858e-01 + 7.828000000000e-10 -6.072676723321e-03 + 7.928000000000e-10 1.370503070743e-01 + 8.028000000000e-10 2.247004966695e-01 + 8.128000000000e-10 2.634509722982e-01 + 8.228000000000e-10 2.979013793804e-01 + 8.328000000000e-10 3.373870921905e-01 + 8.428000000000e-10 3.678495602861e-01 + 8.528000000000e-10 3.719256264749e-01 + 8.628000000000e-10 3.134381864470e-01 + 8.728000000000e-10 1.756688935561e-01 + 8.828000000000e-10 6.088345643719e-03 + 8.928000000000e-10 -1.370666831053e-01 + 9.028000000000e-10 -2.246851372638e-01 + 9.128000000000e-10 -2.634666121684e-01 + 9.228000000000e-10 -2.978856025968e-01 + 9.328000000000e-10 -3.374033621769e-01 + 9.428000000000e-10 -3.678342837151e-01 + 9.528000000000e-10 -3.719412125322e-01 + 9.628000000000e-10 -3.134235677100e-01 + 9.728000000000e-10 -1.756838495744e-01 + 9.828000000000e-10 -6.073781243164e-03 + 9.928000000000e-10 1.370527135588e-01 + 1.000000000000e-09 2.065229990524e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/conditions.yaml new file mode 100644 index 00000000..10bb7cbc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 26 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/run_26 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/simulation_summary.csv new file mode 100644 index 00000000..df931bcf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/simulation_summary.csv @@ -0,0 +1,28 @@ +run,corner,temperature,vdd,time,vo_diff,voltage_swing +run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.111e-01, -1.870e-01, -3.563e-02, …]",0.763 +run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.099e-01, -1.895e-01, -4.060e-02, …]",0.754 +run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.876e-01, -3.217e-02, …]",0.780 +run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.915e-01, -1.780e-01, -3.803e-02, …]",0.715 +run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.909e-01, -1.806e-01, -4.276e-02, …]",0.706 +run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.959e-01, -1.792e-01, -3.599e-02, …]",0.732 +run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.689e-01, -1.692e-01, -4.423e-02, …]",0.639 +run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.694e-01, -1.722e-01, -4.907e-02, …]",0.629 +run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.723e-01, -1.701e-01, -4.252e-02, …]",0.659 +run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.623e-01, -1.963e-01, -5.713e-03, …]",0.843 +run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.622e-01, -1.984e-01, -1.024e-02, …]",0.836 +run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.669e-01, -1.979e-01, -3.070e-03, …]",0.857 +run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",0.803 +run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.407e-01, -1.880e-01, -9.263e-03, …]",0.796 +run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.446e-01, -1.889e-01, -5.355e-03, …]",0.817 +run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.832e-01, -1.548e-01, 2.955e-03, …]",0.743 +run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.908e-01, -1.609e-01, -2.321e-03, …]",0.736 +run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.858e-01, -1.573e-01, 2.540e-03, …]",0.758 +run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.214e-01, -1.558e-01, 3.477e-02, …]",0.836 +run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.529e-01, 3.475e-02, …]",0.830 +run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.365e-01, -1.657e-01, 3.100e-02, …]",0.853 +run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.748e-01, -1.328e-01, 3.931e-02, …]",0.799 +run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.701e-01, -1.295e-01, 4.028e-02, …]",0.793 +run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.957e-01, -1.475e-01, 3.197e-02, …]",0.816 +run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.909e-01, -9.049e-02, 3.946e-02, …]",0.730 +run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.879e-01, -8.812e-02, 4.047e-02, …]",0.726 +run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.136e-01, -1.054e-01, 3.486e-02, …]",0.747 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/simulation_summary.md new file mode 100644 index 00000000..718ef066 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/parameters/VoltageSwing/simulation_summary.md @@ -0,0 +1,31 @@ +# Simulation Summary for Vpp + +| run | corner | temperature | vdd | time | vo_diff | voltage_swing | +| :-- | -----: | ----------: | --: | ---: | ------: | ------------: | +| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.111e-01, -1.870e-01, -3.563e-02, …] | 0.763 | +| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.099e-01, -1.895e-01, -4.060e-02, …] | 0.754 | +| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.876e-01, -3.217e-02, …] | 0.780 | +| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.915e-01, -1.780e-01, -3.803e-02, …] | 0.715 | +| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.909e-01, -1.806e-01, -4.276e-02, …] | 0.706 | +| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.959e-01, -1.792e-01, -3.599e-02, …] | 0.732 | +| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.689e-01, -1.692e-01, -4.423e-02, …] | 0.639 | +| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.694e-01, -1.722e-01, -4.907e-02, …] | 0.629 | +| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.723e-01, -1.701e-01, -4.252e-02, …] | 0.659 | +| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.623e-01, -1.963e-01, -5.713e-03, …] | 0.843 | +| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.622e-01, -1.984e-01, -1.024e-02, …] | 0.836 | +| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.669e-01, -1.979e-01, -3.070e-03, …] | 0.857 | +| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 0.803 | +| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.407e-01, -1.880e-01, -9.263e-03, …] | 0.796 | +| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.446e-01, -1.889e-01, -5.355e-03, …] | 0.817 | +| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.832e-01, -1.548e-01, 2.955e-03, …] | 0.743 | +| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.908e-01, -1.609e-01, -2.321e-03, …] | 0.736 | +| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.858e-01, -1.573e-01, 2.540e-03, …] | 0.758 | +| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.214e-01, -1.558e-01, 3.477e-02, …] | 0.836 | +| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.529e-01, 3.475e-02, …] | 0.830 | +| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.365e-01, -1.657e-01, 3.100e-02, …] | 0.853 | +| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.748e-01, -1.328e-01, 3.931e-02, …] | 0.799 | +| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.701e-01, -1.295e-01, 4.028e-02, …] | 0.793 | +| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.957e-01, -1.475e-01, 3.197e-02, …] | 0.816 | +| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.909e-01, -9.049e-02, 3.946e-02, …] | 0.730 | +| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.879e-01, -8.812e-02, 4.047e-02, …] | 0.726 | +| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.136e-01, -1.054e-01, 3.486e-02, …] | 0.747 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/summary.md new file mode 100644 index 00000000..c88c2771 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-57-35/summary.md @@ -0,0 +1,11 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.3 GHz | 4.722 GHz | 5.0 GHz | 4.722 GHz | 5.2 GHz | 4.722 GHz | Pass ✅ | +| Amplitude | ngspice | amplitude | 0.2 V | 0.315 V | 0.4 V | 0.382 V | 0.6 V | 0.429 V | Pass ✅ | +| Vpp | ngspice | voltage_swing | 0.4 V | 0.629 V | 0.8 V | 0.763 V | 1.2 V | 0.857 V | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/CML_core_tb.sch new file mode 100644 index 00000000..48f6f0bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/CML_core_tb.sch new file mode 100644 index 00000000..5d22316b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/CML_core_tb_0.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/CML_core_tb_0.data new file mode 100644 index 00000000..4cb5b399 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/CML_core_tb_0.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.110742996065e-01 + 1.728000000000e-10 -1.869505717284e-01 + 1.828000000000e-10 -3.563037101706e-02 + 1.928000000000e-10 1.056708524540e-01 + 2.028000000000e-10 2.100393804445e-01 + 2.128000000000e-10 2.784249297688e-01 + 2.228000000000e-10 3.224310579067e-01 + 2.328000000000e-10 3.548600651170e-01 + 2.428000000000e-10 3.792482005271e-01 + 2.528000000000e-10 3.740820324036e-01 + 2.628000000000e-10 3.079440308227e-01 + 2.728000000000e-10 1.813826171807e-01 + 2.828000000000e-10 2.923027813912e-02 + 2.928000000000e-10 -1.118282325615e-01 + 3.028000000000e-10 -2.157337068367e-01 + 3.128000000000e-10 -2.829033176767e-01 + 3.228000000000e-10 -3.260714502323e-01 + 3.328000000000e-10 -3.577361248183e-01 + 3.428000000000e-10 -3.819104006606e-01 + 3.528000000000e-10 -3.764730474160e-01 + 3.628000000000e-10 -3.102968359246e-01 + 3.728000000000e-10 -1.832608913655e-01 + 3.828000000000e-10 -3.084931437320e-02 + 3.928000000000e-10 1.106163095990e-01 + 4.028000000000e-10 2.145714971977e-01 + 4.128000000000e-10 2.819937231053e-01 + 4.228000000000e-10 3.251740998910e-01 + 4.328000000000e-10 3.570946969464e-01 + 4.428000000000e-10 3.813004444382e-01 + 4.528000000000e-10 3.761230596147e-01 + 4.628000000000e-10 3.099646053412e-01 + 4.728000000000e-10 1.831473345022e-01 + 4.828000000000e-10 3.069401022130e-02 + 4.928000000000e-10 -1.106258411343e-01 + 5.028000000000e-10 -2.146793601179e-01 + 5.128000000000e-10 -2.820035552799e-01 + 5.228000000000e-10 -3.252909243829e-01 + 5.328000000000e-10 -3.570986338553e-01 + 5.428000000000e-10 -3.813904658256e-01 + 5.528000000000e-10 -3.760889514061e-01 + 5.628000000000e-10 -3.100114096943e-01 + 5.728000000000e-10 -1.830827247194e-01 + 5.828000000000e-10 -3.072480545922e-02 + 5.928000000000e-10 1.106906463094e-01 + 6.028000000000e-10 2.146493837568e-01 + 6.128000000000e-10 2.820610673881e-01 + 6.228000000000e-10 3.252525482967e-01 + 6.328000000000e-10 3.571504708749e-01 + 6.428000000000e-10 3.813516648295e-01 + 6.528000000000e-10 3.761390656738e-01 + 6.628000000000e-10 3.099742259389e-01 + 6.728000000000e-10 1.831331110808e-01 + 6.828000000000e-10 3.068765829312e-02 + 6.928000000000e-10 -1.106445812930e-01 + 7.028000000000e-10 -2.146859050297e-01 + 7.128000000000e-10 -2.820172231683e-01 + 7.228000000000e-10 -3.252905125649e-01 + 7.328000000000e-10 -3.571078709926e-01 + 7.428000000000e-10 -3.813893177320e-01 + 7.528000000000e-10 -3.760986555866e-01 + 7.628000000000e-10 -3.100117776476e-01 + 7.728000000000e-10 -1.830935153198e-01 + 7.828000000000e-10 -3.072484475908e-02 + 7.928000000000e-10 1.106810594907e-01 + 8.028000000000e-10 2.146507312123e-01 + 8.128000000000e-10 2.820530370402e-01 + 8.228000000000e-10 3.252547871433e-01 + 8.328000000000e-10 3.571432636036e-01 + 8.428000000000e-10 3.813547544577e-01 + 8.528000000000e-10 3.761324372121e-01 + 8.628000000000e-10 3.099775475493e-01 + 8.728000000000e-10 1.831274535707e-01 + 8.828000000000e-10 3.069175078476e-02 + 8.928000000000e-10 -1.106491559136e-01 + 9.028000000000e-10 -2.146821655528e-01 + 9.128000000000e-10 -2.820218639330e-01 + 9.228000000000e-10 -3.252864642203e-01 + 9.328000000000e-10 -3.571122611941e-01 + 9.428000000000e-10 -3.813854215351e-01 + 9.528000000000e-10 -3.761024723822e-01 + 9.628000000000e-10 -3.100075395903e-01 + 9.728000000000e-10 -1.830975404653e-01 + 9.828000000000e-10 -3.072097080048e-02 + 9.928000000000e-10 1.106770531472e-01 + 1.000000000000e-09 1.895325033433e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/conditions.yaml new file mode 100644 index 00000000..900e683e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_00 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/CML_core_tb.sch new file mode 100644 index 00000000..69c98925 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/CML_core_tb_1.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/CML_core_tb_1.data new file mode 100644 index 00000000..2b8492c0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/CML_core_tb_1.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.098686002716e-01 + 1.728000000000e-10 -1.894560696460e-01 + 1.828000000000e-10 -4.059695742871e-02 + 1.928000000000e-10 9.940964501315e-02 + 2.028000000000e-10 2.033133834097e-01 + 2.128000000000e-10 2.719620830710e-01 + 2.228000000000e-10 3.163098950569e-01 + 2.328000000000e-10 3.491513279687e-01 + 2.428000000000e-10 3.741332087119e-01 + 2.528000000000e-10 3.700254590965e-01 + 2.628000000000e-10 3.062168938694e-01 + 2.728000000000e-10 1.827341653261e-01 + 2.828000000000e-10 3.280764574542e-02 + 2.928000000000e-10 -1.069769977212e-01 + 3.028000000000e-10 -2.102924295592e-01 + 3.128000000000e-10 -2.774748738503e-01 + 3.228000000000e-10 -3.207751929169e-01 + 3.328000000000e-10 -3.527202709264e-01 + 3.428000000000e-10 -3.774342269369e-01 + 3.528000000000e-10 -3.730540733905e-01 + 3.628000000000e-10 -3.091949741363e-01 + 3.728000000000e-10 -1.851642002832e-01 + 3.828000000000e-10 -3.487935842603e-02 + 3.928000000000e-10 1.053970083053e-01 + 4.028000000000e-10 2.088131472734e-01 + 4.128000000000e-10 2.762908135843e-01 + 4.228000000000e-10 3.196385089100e-01 + 4.328000000000e-10 3.518763575372e-01 + 4.428000000000e-10 3.766558038448e-01 + 4.528000000000e-10 3.725714207051e-01 + 4.628000000000e-10 3.087619830708e-01 + 4.728000000000e-10 1.849833837695e-01 + 4.828000000000e-10 3.467977975354e-02 + 4.928000000000e-10 -1.054340839288e-01 + 5.028000000000e-10 -2.089448612506e-01 + 5.128000000000e-10 -2.763231704068e-01 + 5.228000000000e-10 -3.197791718821e-01 + 5.328000000000e-10 -3.518998659973e-01 + 5.428000000000e-10 -3.767613178326e-01 + 5.528000000000e-10 -3.725445308461e-01 + 5.628000000000e-10 -3.088109693961e-01 + 5.728000000000e-10 -1.849155432321e-01 + 5.828000000000e-10 -3.470667341543e-02 + 5.928000000000e-10 1.055048847061e-01 + 6.028000000000e-10 2.089187592091e-01 + 6.128000000000e-10 2.763849186823e-01 + 6.228000000000e-10 3.197425041182e-01 + 6.328000000000e-10 3.519544114659e-01 + 6.428000000000e-10 3.767237647599e-01 + 6.528000000000e-10 3.725977061828e-01 + 6.628000000000e-10 3.087755728399e-01 + 6.728000000000e-10 1.849692271918e-01 + 6.828000000000e-10 3.467099374312e-02 + 6.928000000000e-10 -1.054562384013e-01 + 7.028000000000e-10 -2.089544093361e-01 + 7.128000000000e-10 -2.763388509076e-01 + 7.228000000000e-10 -3.197800091948e-01 + 7.328000000000e-10 -3.519101110125e-01 + 7.428000000000e-10 -3.767612419697e-01 + 7.528000000000e-10 -3.725558598664e-01 + 7.628000000000e-10 -3.088133010441e-01 + 7.728000000000e-10 -1.849285593480e-01 + 7.828000000000e-10 -3.470862903587e-02 + 7.928000000000e-10 1.054936381918e-01 + 8.028000000000e-10 2.089186129636e-01 + 8.128000000000e-10 2.763755879874e-01 + 8.228000000000e-10 3.197437164625e-01 + 8.328000000000e-10 3.519463479929e-01 + 8.428000000000e-10 3.767260853907e-01 + 8.528000000000e-10 3.725904126785e-01 + 8.628000000000e-10 3.087783440951e-01 + 8.728000000000e-10 1.849632167070e-01 + 8.828000000000e-10 3.467482549783e-02 + 8.928000000000e-10 -1.054610682584e-01 + 9.028000000000e-10 -2.089507846182e-01 + 9.128000000000e-10 -2.763436586770e-01 + 9.228000000000e-10 -3.197760754687e-01 + 9.328000000000e-10 -3.519146615050e-01 + 9.428000000000e-10 -3.767573997120e-01 + 9.528000000000e-10 -3.725597535055e-01 + 9.628000000000e-10 -3.088090609970e-01 + 9.728000000000e-10 -1.849326628321e-01 + 9.828000000000e-10 -3.470475490247e-02 + 9.928000000000e-10 1.054896146910e-01 + 1.000000000000e-09 1.838520001242e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/conditions.yaml new file mode 100644 index 00000000..898d6529 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 1 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_01 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/CML_core_tb.sch new file mode 100644 index 00000000..cc7c424c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/CML_core_tb_2.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/CML_core_tb_2.data new file mode 100644 index 00000000..b332ca2c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/CML_core_tb_2.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162797108708e-01 + 1.728000000000e-10 -1.875883768906e-01 + 1.828000000000e-10 -3.217177564589e-02 + 1.928000000000e-10 1.118453904517e-01 + 2.028000000000e-10 2.178869753922e-01 + 2.128000000000e-10 2.869187499571e-01 + 2.228000000000e-10 3.311831063176e-01 + 2.328000000000e-10 3.637965093552e-01 + 2.428000000000e-10 3.884475585753e-01 + 2.528000000000e-10 3.831703446637e-01 + 2.628000000000e-10 3.149426000366e-01 + 2.728000000000e-10 1.840825734866e-01 + 2.828000000000e-10 2.786370536806e-02 + 2.928000000000e-10 -1.159899232258e-01 + 3.028000000000e-10 -2.217323928122e-01 + 3.128000000000e-10 -2.897841810826e-01 + 3.228000000000e-10 -3.334256487170e-01 + 3.328000000000e-10 -3.654508602495e-01 + 3.428000000000e-10 -3.900407544937e-01 + 3.528000000000e-10 -3.846189534315e-01 + 3.628000000000e-10 -3.164922452622e-01 + 3.728000000000e-10 -1.853182634851e-01 + 3.828000000000e-10 -2.898615964086e-02 + 3.928000000000e-10 1.151710782521e-01 + 4.028000000000e-10 2.209054309263e-01 + 4.128000000000e-10 2.891817322742e-01 + 4.228000000000e-10 3.328077516782e-01 + 4.328000000000e-10 3.650515838921e-01 + 4.428000000000e-10 3.896233583948e-01 + 4.528000000000e-10 3.844074302627e-01 + 4.628000000000e-10 3.162448842688e-01 + 4.728000000000e-10 1.852475068120e-01 + 4.828000000000e-10 2.884623360652e-02 + 4.928000000000e-10 -1.151788252337e-01 + 5.028000000000e-10 -2.210147130581e-01 + 5.128000000000e-10 -2.891872658193e-01 + 5.228000000000e-10 -3.329167168088e-01 + 5.328000000000e-10 -3.650471930963e-01 + 5.428000000000e-10 -3.897100874545e-01 + 5.528000000000e-10 -3.843762306477e-01 + 5.628000000000e-10 -3.163013912188e-01 + 5.728000000000e-10 -1.851950213487e-01 + 5.828000000000e-10 -2.889036873678e-02 + 5.928000000000e-10 1.152312899162e-01 + 6.028000000000e-10 2.209735588305e-01 + 6.128000000000e-10 2.892357416511e-01 + 6.228000000000e-10 3.328707955285e-01 + 6.328000000000e-10 3.650931065031e-01 + 6.428000000000e-10 3.896657987149e-01 + 6.528000000000e-10 3.844215105032e-01 + 6.628000000000e-10 3.162596917265e-01 + 6.728000000000e-10 1.852417351036e-01 + 6.828000000000e-10 2.884992827621e-02 + 6.928000000000e-10 -1.151876679011e-01 + 7.028000000000e-10 -2.210123101756e-01 + 7.128000000000e-10 -2.891938845816e-01 + 7.228000000000e-10 -3.329106389600e-01 + 7.328000000000e-10 -3.650518039465e-01 + 7.428000000000e-10 -3.897047407363e-01 + 7.528000000000e-10 -3.843819858648e-01 + 7.628000000000e-10 -3.162978744015e-01 + 7.728000000000e-10 -1.852023753321e-01 + 7.828000000000e-10 -2.888743165850e-02 + 7.928000000000e-10 1.152240030808e-01 + 8.028000000000e-10 2.209771419031e-01 + 8.128000000000e-10 2.892295361788e-01 + 8.228000000000e-10 3.328747680971e-01 + 8.328000000000e-10 3.650871456099e-01 + 8.428000000000e-10 3.896701175780e-01 + 8.528000000000e-10 3.844156912621e-01 + 8.628000000000e-10 3.162637401476e-01 + 8.728000000000e-10 1.852363586492e-01 + 8.828000000000e-10 2.885434112124e-02 + 8.928000000000e-10 -1.151920978903e-01 + 9.028000000000e-10 -2.210084087345e-01 + 9.128000000000e-10 -2.891984388712e-01 + 9.228000000000e-10 -3.329064027155e-01 + 9.328000000000e-10 -3.650560988894e-01 + 9.428000000000e-10 -3.897007143418e-01 + 9.528000000000e-10 -3.843858173814e-01 + 9.628000000000e-10 -3.162935974835e-01 + 9.728000000000e-10 -1.852064424274e-01 + 9.828000000000e-10 -2.888350905479e-02 + 9.928000000000e-10 1.152199079204e-01 + 1.000000000000e-09 1.954791142410e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/conditions.yaml new file mode 100644 index 00000000..137f4e77 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 2 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_02 +temperature: '-40' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/CML_core_tb.sch new file mode 100644 index 00000000..57438f7c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/CML_core_tb_3.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/CML_core_tb_3.data new file mode 100644 index 00000000..6dccbfd6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/CML_core_tb_3.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.914571027454e-01 + 1.728000000000e-10 -1.780117263272e-01 + 1.828000000000e-10 -3.802564096594e-02 + 1.928000000000e-10 9.479025580261e-02 + 2.028000000000e-10 1.961220444980e-01 + 2.128000000000e-10 2.643669322964e-01 + 2.228000000000e-10 3.071498875260e-01 + 2.328000000000e-10 3.351667250191e-01 + 2.428000000000e-10 3.529478733093e-01 + 2.528000000000e-10 3.439767079911e-01 + 2.628000000000e-10 2.827109934029e-01 + 2.728000000000e-10 1.683025534555e-01 + 2.828000000000e-10 2.843266655337e-02 + 2.928000000000e-10 -1.036223502576e-01 + 3.028000000000e-10 -2.042863713809e-01 + 3.128000000000e-10 -2.713818104821e-01 + 3.228000000000e-10 -3.132717880322e-01 + 3.328000000000e-10 -3.402903477971e-01 + 3.428000000000e-10 -3.574262556597e-01 + 3.528000000000e-10 -3.476240566503e-01 + 3.628000000000e-10 -2.857203755187e-01 + 3.728000000000e-10 -1.703849236420e-01 + 3.828000000000e-10 -2.994825869373e-02 + 3.928000000000e-10 1.026817167876e-01 + 4.028000000000e-10 2.034750084544e-01 + 4.128000000000e-10 2.707812081585e-01 + 4.228000000000e-10 3.126503625184e-01 + 4.328000000000e-10 3.399043734480e-01 + 4.428000000000e-10 3.571021595385e-01 + 4.528000000000e-10 3.475896983741e-01 + 4.628000000000e-10 2.857411927694e-01 + 4.728000000000e-10 1.706053611761e-01 + 4.828000000000e-10 3.010795594348e-02 + 4.928000000000e-10 -1.024135388755e-01 + 5.028000000000e-10 -2.033190471438e-01 + 5.128000000000e-10 -2.705615444577e-01 + 5.228000000000e-10 -3.125558523975e-01 + 5.328000000000e-10 -3.397330193449e-01 + 5.428000000000e-10 -3.570354300338e-01 + 5.528000000000e-10 -3.474353611027e-01 + 5.628000000000e-10 -2.856876769732e-01 + 5.728000000000e-10 -1.704760895977e-01 + 5.828000000000e-10 -3.008641427314e-02 + 5.928000000000e-10 1.025087996136e-01 + 6.028000000000e-10 2.033209986443e-01 + 6.128000000000e-10 2.706412375819e-01 + 6.228000000000e-10 3.125457575810e-01 + 6.328000000000e-10 3.398008382665e-01 + 6.428000000000e-10 3.570145583479e-01 + 6.528000000000e-10 3.474888598072e-01 + 6.628000000000e-10 2.856551852535e-01 + 6.728000000000e-10 1.705188293935e-01 + 6.828000000000e-10 3.004736925580e-02 + 6.928000000000e-10 -1.024728514478e-01 + 7.028000000000e-10 -2.033602328622e-01 + 7.128000000000e-10 -2.706061106716e-01 + 7.228000000000e-10 -3.125843283316e-01 + 7.328000000000e-10 -3.397655433228e-01 + 7.428000000000e-10 -3.570523646632e-01 + 7.528000000000e-10 -3.474554820929e-01 + 7.628000000000e-10 -2.856929985560e-01 + 7.728000000000e-10 -1.704859799650e-01 + 7.828000000000e-10 -3.008383757896e-02 + 7.928000000000e-10 1.025039608177e-01 + 8.028000000000e-10 2.033261442763e-01 + 8.128000000000e-10 2.706371082838e-01 + 8.228000000000e-10 3.125504649737e-01 + 8.328000000000e-10 3.397966066528e-01 + 8.428000000000e-10 3.570198965640e-01 + 8.528000000000e-10 3.474857187206e-01 + 8.628000000000e-10 2.856614378232e-01 + 8.728000000000e-10 1.705164607562e-01 + 8.828000000000e-10 3.005354621749e-02 + 8.928000000000e-10 -1.024749769036e-01 + 9.028000000000e-10 -2.033548454455e-01 + 9.128000000000e-10 -2.706087008930e-01 + 9.228000000000e-10 -3.125792630790e-01 + 9.328000000000e-10 -3.397683901773e-01 + 9.428000000000e-10 -3.570478314069e-01 + 9.528000000000e-10 -3.474583427153e-01 + 9.628000000000e-10 -2.856887110961e-01 + 9.728000000000e-10 -1.704892548593e-01 + 9.828000000000e-10 -3.008001356704e-02 + 9.928000000000e-10 1.025005080892e-01 + 1.000000000000e-09 1.786649040194e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/conditions.yaml new file mode 100644 index 00000000..5d8e903b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 3 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_03 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/CML_core_tb.sch new file mode 100644 index 00000000..076f35a1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/CML_core_tb_4.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/CML_core_tb_4.data new file mode 100644 index 00000000..3efc8a54 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/CML_core_tb_4.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908886906683e-01 + 1.728000000000e-10 -1.805890382926e-01 + 1.828000000000e-10 -4.276329247682e-02 + 1.928000000000e-10 8.882407595099e-02 + 2.028000000000e-10 1.894983505466e-01 + 2.128000000000e-10 2.576242567207e-01 + 2.228000000000e-10 3.005212718886e-01 + 2.328000000000e-10 3.289546768723e-01 + 2.428000000000e-10 3.474240530436e-01 + 2.528000000000e-10 3.394794629215e-01 + 2.628000000000e-10 2.802266193594e-01 + 2.728000000000e-10 1.685520573893e-01 + 2.828000000000e-10 3.081792474830e-02 + 2.928000000000e-10 -9.985913249602e-02 + 3.028000000000e-10 -1.996535082954e-01 + 3.128000000000e-10 -2.663519845580e-01 + 3.228000000000e-10 -3.081166100610e-01 + 3.328000000000e-10 -3.353557582557e-01 + 3.428000000000e-10 -3.530339682910e-01 + 3.528000000000e-10 -3.441234226063e-01 + 3.628000000000e-10 -2.840838930007e-01 + 3.728000000000e-10 -1.712890179908e-01 + 3.828000000000e-10 -3.280692441870e-02 + 3.928000000000e-10 9.858702888345e-02 + 4.028000000000e-10 1.985844458095e-01 + 4.128000000000e-10 2.655374220709e-01 + 4.228000000000e-10 3.073092043222e-01 + 4.328000000000e-10 3.348254361967e-01 + 4.428000000000e-10 3.526065806553e-01 + 4.528000000000e-10 3.440384505411e-01 + 4.628000000000e-10 2.840943593119e-01 + 4.728000000000e-10 1.715352376725e-01 + 4.828000000000e-10 3.300625747524e-02 + 4.928000000000e-10 -9.826793525126e-02 + 5.028000000000e-10 -1.983826392696e-01 + 5.128000000000e-10 -2.652748957302e-01 + 5.228000000000e-10 -3.071819372703e-01 + 5.328000000000e-10 -3.346211766496e-01 + 5.428000000000e-10 -3.525115401756e-01 + 5.528000000000e-10 -3.438520776438e-01 + 5.628000000000e-10 -2.840132934403e-01 + 5.728000000000e-10 -1.713783534881e-01 + 5.828000000000e-10 -3.296528839742e-02 + 5.928000000000e-10 9.838210726041e-02 + 6.028000000000e-10 1.983970962128e-01 + 6.128000000000e-10 2.653685996210e-01 + 6.228000000000e-10 3.071805271474e-01 + 6.328000000000e-10 3.346994451143e-01 + 6.428000000000e-10 3.524959527178e-01 + 6.528000000000e-10 3.439124816552e-01 + 6.628000000000e-10 2.839825148385e-01 + 6.728000000000e-10 1.714247364616e-01 + 6.828000000000e-10 3.292536702304e-02 + 6.928000000000e-10 -9.834444145178e-02 + 7.028000000000e-10 -1.984381153623e-01 + 7.128000000000e-10 -2.653318964793e-01 + 7.228000000000e-10 -3.072207693265e-01 + 7.328000000000e-10 -3.346627011511e-01 + 7.428000000000e-10 -3.525355719541e-01 + 7.528000000000e-10 -3.438780517049e-01 + 7.628000000000e-10 -2.840226095914e-01 + 7.728000000000e-10 -1.713910964736e-01 + 7.828000000000e-10 -3.296406429130e-02 + 7.928000000000e-10 9.837645950128e-02 + 8.028000000000e-10 1.984019833998e-01 + 8.128000000000e-10 2.653640104122e-01 + 8.228000000000e-10 3.071850636337e-01 + 8.328000000000e-10 3.346949515146e-01 + 8.428000000000e-10 3.525014052751e-01 + 8.528000000000e-10 3.439095067618e-01 + 8.628000000000e-10 2.839893402731e-01 + 8.728000000000e-10 1.714228569780e-01 + 8.828000000000e-10 3.293222880403e-02 + 8.928000000000e-10 -9.834616516704e-02 + 9.028000000000e-10 -1.984321208293e-01 + 9.128000000000e-10 -2.653341991167e-01 + 9.228000000000e-10 -3.072152380466e-01 + 9.328000000000e-10 -3.346653803170e-01 + 9.428000000000e-10 -3.525306496503e-01 + 9.528000000000e-10 -3.438807929682e-01 + 9.628000000000e-10 -2.840179937834e-01 + 9.728000000000e-10 -1.713943425416e-01 + 9.828000000000e-10 -3.296001530074e-02 + 9.928000000000e-10 9.837298926970e-02 + 1.000000000000e-09 1.738955459088e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/conditions.yaml new file mode 100644 index 00000000..fcc26cda --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 4 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_04 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/CML_core_tb.sch new file mode 100644 index 00000000..402e88ce --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/CML_core_tb_5.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/CML_core_tb_5.data new file mode 100644 index 00000000..0cc77d23 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/CML_core_tb_5.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.958574299710e-01 + 1.728000000000e-10 -1.791897212785e-01 + 1.828000000000e-10 -3.599075048614e-02 + 1.928000000000e-10 9.946703268478e-02 + 2.028000000000e-10 2.032502871016e-01 + 2.128000000000e-10 2.733994094958e-01 + 2.228000000000e-10 3.172845988123e-01 + 2.328000000000e-10 3.455609123691e-01 + 2.428000000000e-10 3.630923957132e-01 + 2.528000000000e-10 3.534419450967e-01 + 2.628000000000e-10 2.903663934708e-01 + 2.728000000000e-10 1.726743312860e-01 + 2.828000000000e-10 2.930291139472e-02 + 2.928000000000e-10 -1.057514312075e-01 + 3.028000000000e-10 -2.091913834589e-01 + 3.128000000000e-10 -2.784696434768e-01 + 3.228000000000e-10 -3.216873931074e-01 + 3.328000000000e-10 -3.491870426412e-01 + 3.428000000000e-10 -3.662894191498e-01 + 3.528000000000e-10 -3.560374131806e-01 + 3.628000000000e-10 -2.925719059469e-01 + 3.728000000000e-10 -1.742159787839e-01 + 3.828000000000e-10 -3.049391935212e-02 + 3.928000000000e-10 1.049756016137e-01 + 4.028000000000e-10 2.084672065617e-01 + 4.128000000000e-10 2.779301238417e-01 + 4.228000000000e-10 3.211180618030e-01 + 4.328000000000e-10 3.488255023686e-01 + 4.428000000000e-10 3.659572542624e-01 + 4.528000000000e-10 3.559493947967e-01 + 4.628000000000e-10 2.925058094407e-01 + 4.728000000000e-10 1.743267017008e-01 + 4.828000000000e-10 3.054314172764e-02 + 4.928000000000e-10 -1.048175245910e-01 + 5.028000000000e-10 -2.084096499031e-01 + 5.128000000000e-10 -2.777998408986e-01 + 5.228000000000e-10 -3.210985617265e-01 + 5.328000000000e-10 -3.487226120056e-01 + 5.428000000000e-10 -3.659481451181e-01 + 5.528000000000e-10 -3.558482598240e-01 + 5.628000000000e-10 -2.924942070749e-01 + 5.728000000000e-10 -1.742324941843e-01 + 5.828000000000e-10 -3.054486718364e-02 + 5.928000000000e-10 1.048934295445e-01 + 6.028000000000e-10 2.083991544976e-01 + 6.128000000000e-10 2.778660140822e-01 + 6.228000000000e-10 3.210794561497e-01 + 6.328000000000e-10 3.487805773205e-01 + 6.428000000000e-10 3.659226785140e-01 + 6.528000000000e-10 3.558970058340e-01 + 6.628000000000e-10 2.924624137185e-01 + 6.728000000000e-10 1.742748110039e-01 + 6.828000000000e-10 3.050920657876e-02 + 6.928000000000e-10 -1.048562048812e-01 + 7.028000000000e-10 -2.084343791218e-01 + 7.128000000000e-10 -2.778299623633e-01 + 7.228000000000e-10 -3.211147582115e-01 + 7.328000000000e-10 -3.487447461690e-01 + 7.428000000000e-10 -3.659575085549e-01 + 7.528000000000e-10 -3.558632428052e-01 + 7.628000000000e-10 -2.924972481137e-01 + 7.728000000000e-10 -1.742418088753e-01 + 7.828000000000e-10 -3.054328720193e-02 + 7.928000000000e-10 1.048870377838e-01 + 8.028000000000e-10 2.084024115537e-01 + 8.128000000000e-10 2.778603942564e-01 + 8.228000000000e-10 3.210827582845e-01 + 8.328000000000e-10 3.487751488045e-01 + 8.428000000000e-10 3.659266824704e-01 + 8.528000000000e-10 3.558925702991e-01 + 8.628000000000e-10 2.924671830422e-01 + 8.728000000000e-10 1.742711856894e-01 + 8.828000000000e-10 3.051417003050e-02 + 8.928000000000e-10 -1.048591994973e-01 + 9.028000000000e-10 -2.084299430076e-01 + 9.128000000000e-10 -2.778331783696e-01 + 9.228000000000e-10 -3.211104359655e-01 + 9.328000000000e-10 -3.487480244246e-01 + 9.428000000000e-10 -3.659535267111e-01 + 9.528000000000e-10 -3.558663548813e-01 + 9.628000000000e-10 -2.924933270906e-01 + 9.728000000000e-10 -1.742451324195e-01 + 9.828000000000e-10 -3.053963678018e-02 + 9.928000000000e-10 1.048836196344e-01 + 1.000000000000e-09 1.830293824662e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/conditions.yaml new file mode 100644 index 00000000..e376bd3e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 5 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_05 +temperature: '27' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/CML_core_tb.sch new file mode 100644 index 00000000..9b63c1e2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/CML_core_tb_6.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/CML_core_tb_6.data new file mode 100644 index 00000000..38ffd8bf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/CML_core_tb_6.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.689355033953e-01 + 1.728000000000e-10 -1.691728954892e-01 + 1.828000000000e-10 -4.423302134033e-02 + 1.928000000000e-10 7.663444207075e-02 + 2.028000000000e-10 1.714764750752e-01 + 2.128000000000e-10 2.368219567798e-01 + 2.228000000000e-10 2.772768132445e-01 + 2.328000000000e-10 3.013675537348e-01 + 2.428000000000e-10 3.140706479520e-01 + 2.528000000000e-10 3.038549886105e-01 + 2.628000000000e-10 2.508404086347e-01 + 2.728000000000e-10 1.528360605683e-01 + 2.828000000000e-10 3.040034809293e-02 + 2.928000000000e-10 -8.785381094258e-02 + 3.028000000000e-10 -1.808734961109e-01 + 3.128000000000e-10 -2.445795528199e-01 + 3.228000000000e-10 -2.838354337528e-01 + 3.328000000000e-10 -3.065800962400e-01 + 3.428000000000e-10 -3.181767360109e-01 + 3.528000000000e-10 -3.065752663659e-01 + 3.628000000000e-10 -2.523878800401e-01 + 3.728000000000e-10 -1.531173668737e-01 + 3.828000000000e-10 -2.992055538556e-02 + 3.928000000000e-10 8.900435641641e-02 + 4.028000000000e-10 1.821756238512e-01 + 4.128000000000e-10 2.460123650690e-01 + 4.228000000000e-10 2.851182310100e-01 + 4.328000000000e-10 3.079291995556e-01 + 4.428000000000e-10 3.194129911462e-01 + 4.528000000000e-10 3.078915366323e-01 + 4.628000000000e-10 2.535144344421e-01 + 4.728000000000e-10 1.541542026196e-01 + 4.828000000000e-10 3.063651583090e-02 + 4.928000000000e-10 -8.839161491074e-02 + 5.028000000000e-10 -1.817999659778e-01 + 5.128000000000e-10 -2.456456661989e-01 + 5.228000000000e-10 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7.728000000000e-10 -1.541282589474e-01 + 7.828000000000e-10 -3.072672689244e-02 + 7.928000000000e-10 8.835148526653e-02 + 8.028000000000e-10 1.816795669555e-01 + 8.128000000000e-10 2.455984246601e-01 + 8.228000000000e-10 2.848062931006e-01 + 8.328000000000e-10 3.076705916890e-01 + 8.428000000000e-10 3.192450073559e-01 + 8.528000000000e-10 3.077736319697e-01 + 8.628000000000e-10 2.534831121829e-01 + 8.728000000000e-10 1.541590953584e-01 + 8.828000000000e-10 3.069946612700e-02 + 8.928000000000e-10 -8.832341199891e-02 + 9.028000000000e-10 -1.817063952021e-01 + 9.128000000000e-10 -2.455714256322e-01 + 9.228000000000e-10 -2.848333922463e-01 + 9.328000000000e-10 -3.076440936715e-01 + 9.428000000000e-10 -3.192716274515e-01 + 9.528000000000e-10 -3.077481608676e-01 + 9.628000000000e-10 -2.535093614867e-01 + 9.728000000000e-10 -1.541340765567e-01 + 9.828000000000e-10 -3.072486745089e-02 + 9.928000000000e-10 8.834711873249e-02 + 1.000000000000e-09 1.586239577417e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/conditions.yaml new file mode 100644 index 00000000..b41d16dd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 6 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_06 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/CML_core_tb.sch new file mode 100644 index 00000000..c7eefa4e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/CML_core_tb_7.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/CML_core_tb_7.data new file mode 100644 index 00000000..1cfe87b5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/CML_core_tb_7.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.694477874818e-01 + 1.728000000000e-10 -1.721829739194e-01 + 1.828000000000e-10 -4.906833766415e-02 + 1.928000000000e-10 7.069743134728e-02 + 2.028000000000e-10 1.648418946330e-01 + 2.128000000000e-10 2.298765389610e-01 + 2.228000000000e-10 2.702802052070e-01 + 2.328000000000e-10 2.947129455777e-01 + 2.428000000000e-10 3.081296602318e-01 + 2.528000000000e-10 2.990063012040e-01 + 2.628000000000e-10 2.478884705263e-01 + 2.728000000000e-10 1.524230846398e-01 + 2.828000000000e-10 3.216725009037e-02 + 2.928000000000e-10 -8.452884553171e-02 + 3.028000000000e-10 -1.764495371150e-01 + 3.128000000000e-10 -2.394951663999e-01 + 3.228000000000e-10 -2.784178156025e-01 + 3.328000000000e-10 -3.012580547427e-01 + 3.428000000000e-10 -3.133510931360e-01 + 3.528000000000e-10 -3.026055002423e-01 + 3.628000000000e-10 -2.500554574282e-01 + 3.728000000000e-10 -1.530444893437e-01 + 3.828000000000e-10 -3.179895766292e-02 + 3.928000000000e-10 8.573594509971e-02 + 4.028000000000e-10 1.778922744476e-01 + 4.128000000000e-10 2.411102030583e-01 + 4.228000000000e-10 2.798967112063e-01 + 4.328000000000e-10 3.028156837380e-01 + 4.428000000000e-10 3.148075876296e-01 + 4.528000000000e-10 3.041758344829e-01 + 4.628000000000e-10 2.514478797306e-01 + 4.728000000000e-10 1.543354303295e-01 + 4.828000000000e-10 3.272908827542e-02 + 4.928000000000e-10 -8.494488064942e-02 + 5.028000000000e-10 -1.773750790235e-01 + 5.128000000000e-10 -2.406241070550e-01 + 5.228000000000e-10 -2.796032327906e-01 + 5.328000000000e-10 -3.025154625175e-01 + 5.428000000000e-10 -3.146850050735e-01 + 5.528000000000e-10 -3.040456856306e-01 + 5.628000000000e-10 -2.514865398019e-01 + 5.728000000000e-10 -1.543455010081e-01 + 5.828000000000e-10 -3.286780649422e-02 + 5.928000000000e-10 8.487071769529e-02 + 6.028000000000e-10 1.772120847555e-01 + 6.128000000000e-10 2.405506532865e-01 + 6.228000000000e-10 2.794557736074e-01 + 6.328000000000e-10 3.024581955274e-01 + 6.428000000000e-10 3.145521515255e-01 + 6.528000000000e-10 3.039990633934e-01 + 6.628000000000e-10 2.513709142203e-01 + 6.728000000000e-10 1.543241408079e-01 + 6.828000000000e-10 3.278555364704e-02 + 6.928000000000e-10 -8.486327141666e-02 + 7.028000000000e-10 -1.772689800248e-01 + 7.128000000000e-10 -2.405282060865e-01 + 7.228000000000e-10 -2.795021370136e-01 + 7.328000000000e-10 -3.024278022377e-01 + 7.428000000000e-10 -3.145896170200e-01 + 7.528000000000e-10 -3.039617953787e-01 + 7.628000000000e-10 -2.514004690324e-01 + 7.728000000000e-10 -1.542820043229e-01 + 7.828000000000e-10 -3.281110337775e-02 + 7.928000000000e-10 8.490436306023e-02 + 8.028000000000e-10 1.772446330839e-01 + 8.128000000000e-10 2.405674335146e-01 + 8.228000000000e-10 2.794761963085e-01 + 8.328000000000e-10 3.024650976088e-01 + 8.428000000000e-10 3.145632644585e-01 + 8.528000000000e-10 3.039968961590e-01 + 8.628000000000e-10 2.513733111446e-01 + 8.728000000000e-10 1.543150179356e-01 + 8.828000000000e-10 3.278304586331e-02 + 8.928000000000e-10 -8.487456857602e-02 + 9.028000000000e-10 -1.772725618584e-01 + 9.128000000000e-10 -2.405389250041e-01 + 9.228000000000e-10 -2.795045102279e-01 + 9.328000000000e-10 -3.024372521320e-01 + 9.428000000000e-10 -3.145911572553e-01 + 9.528000000000e-10 -3.039701598993e-01 + 9.628000000000e-10 -2.514009218164e-01 + 9.728000000000e-10 -1.542887967264e-01 + 9.828000000000e-10 -3.280979517783e-02 + 9.928000000000e-10 8.489941508642e-02 + 1.000000000000e-09 1.544118489485e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/conditions.yaml new file mode 100644 index 00000000..cc95717e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 7 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_07 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/CML_core_tb.sch new file mode 100644 index 00000000..e7e6745f --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/CML_core_tb_8.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/CML_core_tb_8.data new file mode 100644 index 00000000..b4ed17dd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/CML_core_tb_8.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.722799425151e-01 + 1.728000000000e-10 -1.701277707773e-01 + 1.828000000000e-10 -4.252496989706e-02 + 1.928000000000e-10 8.092536896213e-02 + 2.028000000000e-10 1.785199933375e-01 + 2.128000000000e-10 2.463984181452e-01 + 2.228000000000e-10 2.885755113271e-01 + 2.328000000000e-10 3.131967480955e-01 + 2.428000000000e-10 3.255285716483e-01 + 2.528000000000e-10 3.143820454109e-01 + 2.628000000000e-10 2.595824958850e-01 + 2.728000000000e-10 1.585585813323e-01 + 2.828000000000e-10 3.254606172598e-02 + 2.928000000000e-10 -8.921916265210e-02 + 3.028000000000e-10 -1.857143058967e-01 + 3.128000000000e-10 -2.524588707093e-01 + 3.228000000000e-10 -2.937876617757e-01 + 3.328000000000e-10 -3.173655773168e-01 + 3.428000000000e-10 -3.288566343508e-01 + 3.528000000000e-10 -3.166123605828e-01 + 3.628000000000e-10 -2.609360611345e-01 + 3.728000000000e-10 -1.589355414621e-01 + 3.828000000000e-10 -3.237621747627e-02 + 3.928000000000e-10 8.990939637816e-02 + 4.028000000000e-10 1.864994737191e-01 + 4.128000000000e-10 2.533636311879e-01 + 4.228000000000e-10 2.945633129641e-01 + 4.328000000000e-10 3.182197832362e-01 + 4.428000000000e-10 3.296245618008e-01 + 4.528000000000e-10 3.174841059207e-01 + 4.628000000000e-10 2.616780558587e-01 + 4.728000000000e-10 1.596622360522e-01 + 4.828000000000e-10 3.287681921596e-02 + 4.928000000000e-10 -8.943999963453e-02 + 5.028000000000e-10 -1.862066308093e-01 + 5.128000000000e-10 -2.530527908612e-01 + 5.228000000000e-10 -2.943931136832e-01 + 5.328000000000e-10 -3.180152021024e-01 + 5.428000000000e-10 -3.295545667130e-01 + 5.528000000000e-10 -3.173812952412e-01 + 5.628000000000e-10 -2.617027726155e-01 + 5.728000000000e-10 -1.596411992093e-01 + 5.828000000000e-10 -3.295895028258e-02 + 5.928000000000e-10 8.942267434718e-02 + 6.028000000000e-10 1.861105403656e-01 + 6.128000000000e-10 2.530344325895e-01 + 6.228000000000e-10 2.943051008579e-01 + 6.328000000000e-10 3.180051485103e-01 + 6.428000000000e-10 3.294737915539e-01 + 6.528000000000e-10 3.173744791022e-01 + 6.628000000000e-10 2.616291881364e-01 + 6.728000000000e-10 1.596450333001e-01 + 6.828000000000e-10 3.290088244348e-02 + 6.928000000000e-10 -8.940659470005e-02 + 7.028000000000e-10 -1.861562133447e-01 + 7.128000000000e-10 -2.530116656482e-01 + 7.228000000000e-10 -2.943454309811e-01 + 7.328000000000e-10 -3.179780561670e-01 + 7.428000000000e-10 -3.295087969733e-01 + 7.528000000000e-10 -3.173438661274e-01 + 7.628000000000e-10 -2.616591955397e-01 + 7.728000000000e-10 -1.596115565426e-01 + 7.828000000000e-10 -3.292790237402e-02 + 7.928000000000e-10 8.943927261705e-02 + 8.028000000000e-10 1.861310420114e-01 + 8.128000000000e-10 2.530433655174e-01 + 8.228000000000e-10 2.943195630770e-01 + 8.328000000000e-10 3.180088285378e-01 + 8.428000000000e-10 3.294832118435e-01 + 8.528000000000e-10 3.173732295072e-01 + 8.628000000000e-10 2.616337486722e-01 + 8.728000000000e-10 1.596399004289e-01 + 8.828000000000e-10 3.290244884503e-02 + 8.928000000000e-10 -8.941301350766e-02 + 9.028000000000e-10 -1.861557185261e-01 + 9.128000000000e-10 -2.530180139920e-01 + 9.228000000000e-10 -2.943444772306e-01 + 9.328000000000e-10 -3.179838696148e-01 + 9.428000000000e-10 -3.295076633013e-01 + 9.528000000000e-10 -3.173492560727e-01 + 9.628000000000e-10 -2.616577755083e-01 + 9.728000000000e-10 -1.596163947717e-01 + 9.828000000000e-10 -3.292583900074e-02 + 9.928000000000e-10 8.943518431692e-02 + 1.000000000000e-09 1.621529465729e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/conditions.yaml new file mode 100644 index 00000000..a062e45e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 8 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_08 +temperature: '80' +vdd: '0.8' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/CML_core_tb.sch new file mode 100644 index 00000000..ea3a2f93 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/CML_core_tb_9.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/CML_core_tb_9.data new file mode 100644 index 00000000..6b24d1d6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/CML_core_tb_9.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.622644182692e-01 + 1.728000000000e-10 -1.962653738736e-01 + 1.828000000000e-10 -5.712895575235e-03 + 1.928000000000e-10 1.510345047594e-01 + 2.028000000000e-10 2.432775412534e-01 + 2.128000000000e-10 2.772000132926e-01 + 2.228000000000e-10 3.161630086256e-01 + 2.328000000000e-10 3.654121904616e-01 + 2.428000000000e-10 4.070200809677e-01 + 2.528000000000e-10 4.211809118313e-01 + 2.628000000000e-10 3.552666659990e-01 + 2.728000000000e-10 1.954111420719e-01 + 2.828000000000e-10 7.499275151763e-03 + 2.928000000000e-10 -1.488912332472e-01 + 3.028000000000e-10 -2.420325529570e-01 + 3.128000000000e-10 -2.768171400503e-01 + 3.228000000000e-10 -3.164103191401e-01 + 3.328000000000e-10 -3.656815561297e-01 + 3.428000000000e-10 -4.072561733660e-01 + 3.528000000000e-10 -4.210637971044e-01 + 3.628000000000e-10 -3.548415521036e-01 + 3.728000000000e-10 -1.946286859654e-01 + 3.828000000000e-10 -6.746438981043e-03 + 3.928000000000e-10 1.496127957227e-01 + 4.028000000000e-10 2.425057762271e-01 + 4.128000000000e-10 2.772590268750e-01 + 4.228000000000e-10 3.167075169816e-01 + 4.328000000000e-10 3.660182242119e-01 + 4.428000000000e-10 4.074726111052e-01 + 4.528000000000e-10 4.212975956202e-01 + 4.628000000000e-10 3.549573822535e-01 + 4.728000000000e-10 1.947835560361e-01 + 4.828000000000e-10 6.801482567115e-03 + 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9.828000000000e-10 -6.823236278537e-03 + 9.928000000000e-10 1.495363177485e-01 + 1.000000000000e-09 2.250264100511e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/conditions.yaml new file mode 100644 index 00000000..8d006303 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 9 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_09 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/CML_core_tb.sch new file mode 100644 index 00000000..20c807f5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/CML_core_tb_10.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/CML_core_tb_10.data new file mode 100644 index 00000000..f64d27bb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/CML_core_tb_10.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.621881537650e-01 + 1.728000000000e-10 -1.984429143572e-01 + 1.828000000000e-10 -1.024381876325e-02 + 1.928000000000e-10 1.456486678579e-01 + 2.028000000000e-10 2.379497773075e-01 + 2.128000000000e-10 2.714724605336e-01 + 2.228000000000e-10 3.108042897090e-01 + 2.328000000000e-10 3.600441003378e-01 + 2.428000000000e-10 4.020596908788e-01 + 2.528000000000e-10 4.176332246346e-01 + 2.628000000000e-10 3.534480183483e-01 + 2.728000000000e-10 1.957884716864e-01 + 2.828000000000e-10 1.048070619246e-02 + 2.928000000000e-10 -1.446967472000e-01 + 3.028000000000e-10 -2.375576326508e-01 + 3.128000000000e-10 -2.717915022579e-01 + 3.228000000000e-10 -3.116603869888e-01 + 3.328000000000e-10 -3.608573425706e-01 + 3.428000000000e-10 -4.027490548925e-01 + 3.528000000000e-10 -4.178578104758e-01 + 3.628000000000e-10 -3.532507313188e-01 + 3.728000000000e-10 -1.951536666098e-01 + 3.828000000000e-10 -9.813336101525e-03 + 3.928000000000e-10 1.453604720604e-01 + 4.028000000000e-10 2.379857130154e-01 + 4.128000000000e-10 2.721818635676e-01 + 4.228000000000e-10 3.119088225778e-01 + 4.328000000000e-10 3.611475798924e-01 + 4.428000000000e-10 4.029304727738e-01 + 4.528000000000e-10 4.180700216423e-01 + 4.628000000000e-10 3.533627988360e-01 + 4.728000000000e-10 1.953149158213e-01 + 4.828000000000e-10 9.881134950277e-03 + 4.928000000000e-10 -1.452466419838e-01 + 5.028000000000e-10 -2.379576224969e-01 + 5.128000000000e-10 -2.720935242692e-01 + 5.228000000000e-10 -3.118909714313e-01 + 5.328000000000e-10 -3.610674239906e-01 + 5.428000000000e-10 -4.029229661263e-01 + 5.528000000000e-10 -4.180098057029e-01 + 5.628000000000e-10 -3.533753449283e-01 + 5.728000000000e-10 -1.952727841385e-01 + 5.828000000000e-10 -9.906008920915e-03 + 5.928000000000e-10 1.452800172029e-01 + 6.028000000000e-10 2.379306740359e-01 + 6.128000000000e-10 2.721261300904e-01 + 6.228000000000e-10 3.118646486801e-01 + 6.328000000000e-10 3.611003417151e-01 + 6.428000000000e-10 4.028972890619e-01 + 6.528000000000e-10 4.180401129989e-01 + 6.628000000000e-10 3.533488930459e-01 + 6.728000000000e-10 1.953007885397e-01 + 6.828000000000e-10 9.878072761317e-03 + 6.928000000000e-10 -1.452545395230e-01 + 7.028000000000e-10 -2.379578117562e-01 + 7.128000000000e-10 -2.721008877684e-01 + 7.228000000000e-10 -3.118914026492e-01 + 7.328000000000e-10 -3.610744602697e-01 + 7.428000000000e-10 -4.029226014194e-01 + 7.528000000000e-10 -4.180151483436e-01 + 7.628000000000e-10 -3.533732531474e-01 + 7.728000000000e-10 -1.952759500525e-01 + 7.828000000000e-10 -9.902411226855e-03 + 7.928000000000e-10 1.452776462046e-01 + 8.028000000000e-10 2.379341379884e-01 + 8.128000000000e-10 2.721234101956e-01 + 8.228000000000e-10 3.118677116052e-01 + 8.328000000000e-10 3.610975209728e-01 + 8.428000000000e-10 4.029000595077e-01 + 8.528000000000e-10 4.180375331400e-01 + 8.628000000000e-10 3.533517750284e-01 + 8.728000000000e-10 1.952981248182e-01 + 8.828000000000e-10 9.880873061622e-03 + 8.928000000000e-10 -1.452571579233e-01 + 9.028000000000e-10 -2.379551078725e-01 + 9.128000000000e-10 -2.721034614056e-01 + 9.228000000000e-10 -3.118886463518e-01 + 9.328000000000e-10 -3.610770519544e-01 + 9.428000000000e-10 -4.029199107687e-01 + 9.528000000000e-10 -4.180177452829e-01 + 9.628000000000e-10 -3.533708821878e-01 + 9.728000000000e-10 -1.952784134813e-01 + 9.828000000000e-10 -9.899898542678e-03 + 9.928000000000e-10 1.452754037376e-01 + 1.000000000000e-09 2.207322871295e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/conditions.yaml new file mode 100644 index 00000000..222dc9c0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 10 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_10 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/CML_core_tb.sch new file mode 100644 index 00000000..42c7f15e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/CML_core_tb_11.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/CML_core_tb_11.data new file mode 100644 index 00000000..1453012b --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/CML_core_tb_11.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.668500025046e-01 + 1.728000000000e-10 -1.978704758130e-01 + 1.828000000000e-10 -3.069550951996e-03 + 1.928000000000e-10 1.561389387989e-01 + 2.028000000000e-10 2.488697408913e-01 + 2.128000000000e-10 2.833379270136e-01 + 2.228000000000e-10 3.221467647695e-01 + 2.328000000000e-10 3.723176028273e-01 + 2.428000000000e-10 4.147931582649e-01 + 2.528000000000e-10 4.286646301121e-01 + 2.628000000000e-10 3.614677855799e-01 + 2.728000000000e-10 1.982726052647e-01 + 2.828000000000e-10 5.580533140739e-03 + 2.928000000000e-10 -1.536551403474e-01 + 3.028000000000e-10 -2.474729097395e-01 + 3.128000000000e-10 -2.827981749211e-01 + 3.228000000000e-10 -3.222400643179e-01 + 3.328000000000e-10 -3.724510578191e-01 + 3.428000000000e-10 -4.149487937489e-01 + 3.528000000000e-10 -4.285094572794e-01 + 3.628000000000e-10 -3.610716711123e-01 + 3.728000000000e-10 -1.975613483211e-01 + 3.828000000000e-10 -4.936396792217e-03 + 3.928000000000e-10 1.542720670721e-01 + 4.028000000000e-10 2.478554934965e-01 + 4.128000000000e-10 2.831768205427e-01 + 4.228000000000e-10 3.224764565266e-01 + 4.328000000000e-10 3.727376628527e-01 + 4.428000000000e-10 4.151128450004e-01 + 4.528000000000e-10 4.287030398326e-01 + 4.628000000000e-10 3.611465460996e-01 + 4.728000000000e-10 1.976871290976e-01 + 4.828000000000e-10 4.962067120498e-03 + 4.928000000000e-10 -1.541857483448e-01 + 5.028000000000e-10 -2.478549856990e-01 + 5.128000000000e-10 -2.831031432303e-01 + 5.228000000000e-10 -3.224786212940e-01 + 5.328000000000e-10 -3.726675199031e-01 + 5.428000000000e-10 -4.151222726988e-01 + 5.528000000000e-10 -4.286496175832e-01 + 5.628000000000e-10 -3.611719348809e-01 + 5.728000000000e-10 -1.976471175954e-01 + 5.828000000000e-10 -4.995016715658e-03 + 5.928000000000e-10 1.542195273485e-01 + 6.028000000000e-10 2.478226151197e-01 + 6.128000000000e-10 2.831371441394e-01 + 6.228000000000e-10 3.224465270882e-01 + 6.328000000000e-10 3.727020829784e-01 + 6.428000000000e-10 4.150919188021e-01 + 6.528000000000e-10 4.286821395136e-01 + 6.628000000000e-10 3.611419365066e-01 + 6.728000000000e-10 1.976777927703e-01 + 6.828000000000e-10 4.963507878799e-03 + 6.928000000000e-10 -1.541913949207e-01 + 7.028000000000e-10 -2.478529800499e-01 + 7.128000000000e-10 -2.831092109235e-01 + 7.228000000000e-10 -3.224762894768e-01 + 7.328000000000e-10 -3.726728668334e-01 + 7.428000000000e-10 -4.151201370880e-01 + 7.528000000000e-10 -4.286543531433e-01 + 7.628000000000e-10 -3.611692599178e-01 + 7.728000000000e-10 -1.976499135935e-01 + 7.828000000000e-10 -4.990471824028e-03 + 7.928000000000e-10 1.542171227717e-01 + 8.028000000000e-10 2.478269854332e-01 + 8.128000000000e-10 2.831343470853e-01 + 8.228000000000e-10 3.224500362551e-01 + 8.328000000000e-10 3.726987138014e-01 + 8.428000000000e-10 4.150953468135e-01 + 8.528000000000e-10 4.286792233560e-01 + 8.628000000000e-10 3.611455588852e-01 + 8.728000000000e-10 1.976743961081e-01 + 8.828000000000e-10 4.966432661841e-03 + 8.928000000000e-10 -1.541946484524e-01 + 9.028000000000e-10 -2.478502288236e-01 + 9.128000000000e-10 -2.831123474050e-01 + 9.228000000000e-10 -3.224731331421e-01 + 9.328000000000e-10 -3.726757720747e-01 + 9.428000000000e-10 -4.151172388981e-01 + 9.528000000000e-10 -4.286573581279e-01 + 9.628000000000e-10 -3.611667698498e-01 + 9.728000000000e-10 -1.976525646923e-01 + 9.828000000000e-10 -4.987471597641e-03 + 9.928000000000e-10 1.542147143463e-01 + 1.000000000000e-09 2.301006397866e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/conditions.yaml new file mode 100644 index 00000000..dbc7a355 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 11 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_11 +temperature: '-40' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/CML_core_tb.sch new file mode 100644 index 00000000..aa6c02de --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/CML_core_tb_12.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/CML_core_tb_12.data new file mode 100644 index 00000000..3b0782c6 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/CML_core_tb_12.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.388323931118e-01 + 1.728000000000e-10 -1.851651732117e-01 + 1.828000000000e-10 -4.985209728467e-03 + 1.928000000000e-10 1.464303664236e-01 + 2.028000000000e-10 2.390890865534e-01 + 2.128000000000e-10 2.778147857521e-01 + 2.228000000000e-10 3.140298283994e-01 + 2.328000000000e-10 3.564486269316e-01 + 2.428000000000e-10 3.920777300126e-01 + 2.528000000000e-10 4.026431485981e-01 + 2.628000000000e-10 3.407818057760e-01 + 2.728000000000e-10 1.919413521399e-01 + 2.828000000000e-10 1.380608162301e-02 + 2.928000000000e-10 -1.377275777470e-01 + 3.028000000000e-10 -2.320727525709e-01 + 3.128000000000e-10 -2.723718882130e-01 + 3.228000000000e-10 -3.097195919600e-01 + 3.328000000000e-10 -3.525356430610e-01 + 3.428000000000e-10 -3.885938438581e-01 + 3.528000000000e-10 -3.995683250409e-01 + 3.628000000000e-10 -3.382392747069e-01 + 3.728000000000e-10 -1.897685835172e-01 + 3.828000000000e-10 -1.211190537496e-02 + 3.928000000000e-10 1.391365825109e-01 + 4.028000000000e-10 2.331433172305e-01 + 4.128000000000e-10 2.733678679410e-01 + 4.228000000000e-10 3.105714733021e-01 + 4.328000000000e-10 3.533708758772e-01 + 4.428000000000e-10 3.892622592719e-01 + 4.528000000000e-10 4.001272859757e-01 + 4.628000000000e-10 3.385642563623e-01 + 4.728000000000e-10 1.899916781684e-01 + 4.828000000000e-10 1.218033620775e-02 + 4.928000000000e-10 -1.390656421002e-01 + 5.028000000000e-10 -2.331398693887e-01 + 5.128000000000e-10 -2.733037181082e-01 + 5.228000000000e-10 -3.105518491305e-01 + 5.328000000000e-10 -3.533032068815e-01 + 5.428000000000e-10 -3.892531494066e-01 + 5.528000000000e-10 -4.000849100741e-01 + 5.628000000000e-10 -3.385845178207e-01 + 5.728000000000e-10 -1.899774211598e-01 + 5.828000000000e-10 -1.221996984529e-02 + 5.928000000000e-10 1.390720456320e-01 + 6.028000000000e-10 2.331027694491e-01 + 6.128000000000e-10 2.733156842718e-01 + 6.228000000000e-10 3.105197170718e-01 + 6.328000000000e-10 3.533171034352e-01 + 6.428000000000e-10 3.892243222051e-01 + 6.528000000000e-10 4.000997182403e-01 + 6.628000000000e-10 3.385594083538e-01 + 6.728000000000e-10 1.899934277570e-01 + 6.828000000000e-10 1.219466050150e-02 + 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-3.533012749995e-01 + 9.428000000000e-10 -3.892430673555e-01 + 9.528000000000e-10 -4.000844420176e-01 + 9.628000000000e-10 -3.385768441038e-01 + 9.728000000000e-10 -1.899764612955e-01 + 9.828000000000e-10 -1.221122328152e-02 + 9.928000000000e-10 1.390717643268e-01 + 1.000000000000e-09 2.142511381663e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/conditions.yaml new file mode 100644 index 00000000..5f8f23e4 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 12 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_12 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/CML_core_tb.sch new file mode 100644 index 00000000..e15707be --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/CML_core_tb_13.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/CML_core_tb_13.data new file mode 100644 index 00000000..36de6040 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/CML_core_tb_13.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.406999838743e-01 + 1.728000000000e-10 -1.879936990253e-01 + 1.828000000000e-10 -9.262901303246e-03 + 1.928000000000e-10 1.413611635485e-01 + 2.028000000000e-10 2.336775345801e-01 + 2.128000000000e-10 2.717294842894e-01 + 2.228000000000e-10 3.082620487639e-01 + 2.328000000000e-10 3.509422339502e-01 + 2.428000000000e-10 3.871053596645e-01 + 2.528000000000e-10 3.988940820744e-01 + 2.628000000000e-10 3.384312270542e-01 + 2.728000000000e-10 1.913281233779e-01 + 2.828000000000e-10 1.537343295661e-02 + 2.928000000000e-10 -1.347916275204e-01 + 3.028000000000e-10 -2.283419665374e-01 + 3.128000000000e-10 -2.677291408127e-01 + 3.228000000000e-10 -3.052231075401e-01 + 3.328000000000e-10 -3.481601477547e-01 + 3.428000000000e-10 -3.845854123080e-01 + 3.528000000000e-10 -3.965379624605e-01 + 3.628000000000e-10 -3.363314255870e-01 + 3.728000000000e-10 -1.893723794407e-01 + 3.828000000000e-10 -1.375643865463e-02 + 3.928000000000e-10 1.361849816757e-01 + 4.028000000000e-10 2.294005939140e-01 + 4.128000000000e-10 2.686949729273e-01 + 4.228000000000e-10 3.060328157788e-01 + 4.328000000000e-10 3.489590274886e-01 + 4.428000000000e-10 3.852266672724e-01 + 4.528000000000e-10 3.970921187630e-01 + 4.628000000000e-10 3.366736237881e-01 + 4.728000000000e-10 1.896320772426e-01 + 4.828000000000e-10 1.386475371506e-02 + 4.928000000000e-10 -1.360753156283e-01 + 5.028000000000e-10 -2.293675908871e-01 + 5.128000000000e-10 -2.686062530832e-01 + 5.228000000000e-10 -3.059945800423e-01 + 5.328000000000e-10 -3.488729675224e-01 + 5.428000000000e-10 -3.852026785029e-01 + 5.528000000000e-10 -3.970350594993e-01 + 5.628000000000e-10 -3.366834486256e-01 + 5.728000000000e-10 -1.896077423819e-01 + 5.828000000000e-10 -1.389840122586e-02 + 5.928000000000e-10 1.360876217327e-01 + 6.028000000000e-10 2.293336021557e-01 + 6.128000000000e-10 2.686225622920e-01 + 6.228000000000e-10 3.059648098566e-01 + 6.328000000000e-10 3.488907093130e-01 + 6.428000000000e-10 3.851753633828e-01 + 6.528000000000e-10 3.970526526302e-01 + 6.628000000000e-10 3.366583891048e-01 + 6.728000000000e-10 1.896251667832e-01 + 6.828000000000e-10 1.387242911077e-02 + 6.928000000000e-10 -1.360702314024e-01 + 7.028000000000e-10 -2.293580006158e-01 + 7.128000000000e-10 -2.686047945045e-01 + 7.228000000000e-10 -3.059879182353e-01 + 7.328000000000e-10 -3.488722408399e-01 + 7.428000000000e-10 -3.851969589401e-01 + 7.528000000000e-10 -3.970345404264e-01 + 7.628000000000e-10 -3.366782708831e-01 + 7.728000000000e-10 -1.896058621860e-01 + 7.828000000000e-10 -1.389192450355e-02 + 7.928000000000e-10 1.360888260036e-01 + 8.028000000000e-10 2.293391038565e-01 + 8.128000000000e-10 2.686227634282e-01 + 8.228000000000e-10 3.059688096850e-01 + 8.328000000000e-10 3.488900661997e-01 + 8.428000000000e-10 3.851789257250e-01 + 8.528000000000e-10 3.970519764807e-01 + 8.628000000000e-10 3.366616134215e-01 + 8.728000000000e-10 1.896231972496e-01 + 8.828000000000e-10 1.387461571983e-02 + 8.928000000000e-10 -1.360724758723e-01 + 9.028000000000e-10 -2.293560182270e-01 + 9.128000000000e-10 -2.686070528237e-01 + 9.228000000000e-10 -3.059854790954e-01 + 9.328000000000e-10 -3.488740842624e-01 + 9.428000000000e-10 -3.851947329758e-01 + 9.528000000000e-10 -3.970365843841e-01 + 9.628000000000e-10 -3.366766115599e-01 + 9.728000000000e-10 -1.896075309897e-01 + 9.828000000000e-10 -1.388973786858e-02 + 9.928000000000e-10 1.360872156510e-01 + 1.000000000000e-09 2.108297225004e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/conditions.yaml new file mode 100644 index 00000000..1d24dad2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 13 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_13 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/CML_core_tb.sch new file mode 100644 index 00000000..ff1a3bda --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/CML_core_tb_14.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/CML_core_tb_14.data new file mode 100644 index 00000000..73c31d13 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/CML_core_tb_14.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.445927026449e-01 + 1.728000000000e-10 -1.889320969581e-01 + 1.828000000000e-10 -5.355234564888e-03 + 1.928000000000e-10 1.489911128277e-01 + 2.028000000000e-10 2.434822449071e-01 + 2.128000000000e-10 2.838702060450e-01 + 2.228000000000e-10 3.202156401988e-01 + 2.328000000000e-10 3.629401474789e-01 + 2.428000000000e-10 3.990998051164e-01 + 2.528000000000e-10 4.099063275401e-01 + 2.628000000000e-10 3.477923521709e-01 + 2.728000000000e-10 1.968519788675e-01 + 2.828000000000e-10 1.493750763318e-02 + 2.928000000000e-10 -1.398437743336e-01 + 3.028000000000e-10 -2.362338093992e-01 + 3.128000000000e-10 -2.782887085314e-01 + 3.228000000000e-10 -3.158910292643e-01 + 3.328000000000e-10 -3.590893499920e-01 + 3.428000000000e-10 -3.957248346768e-01 + 3.528000000000e-10 -4.069627998073e-01 + 3.628000000000e-10 -3.454070734708e-01 + 3.728000000000e-10 -1.948243362004e-01 + 3.828000000000e-10 -1.337926088934e-02 + 3.928000000000e-10 1.411472162204e-01 + 4.028000000000e-10 2.372231231196e-01 + 4.128000000000e-10 2.792284454069e-01 + 4.228000000000e-10 3.166817589057e-01 + 4.328000000000e-10 3.598702175634e-01 + 4.428000000000e-10 3.963375250752e-01 + 4.528000000000e-10 4.074753309124e-01 + 4.628000000000e-10 3.456854225481e-01 + 4.728000000000e-10 1.950177434222e-01 + 4.828000000000e-10 1.342430394201e-02 + 4.928000000000e-10 -1.410850608466e-01 + 5.028000000000e-10 -2.372286880899e-01 + 5.128000000000e-10 -2.791659662153e-01 + 5.228000000000e-10 -3.166689293508e-01 + 5.328000000000e-10 -3.598026374101e-01 + 5.428000000000e-10 -3.963331138013e-01 + 5.528000000000e-10 -4.074316676804e-01 + 5.628000000000e-10 -3.457088001737e-01 + 5.728000000000e-10 -1.950000158899e-01 + 5.828000000000e-10 -1.346504722293e-02 + 5.928000000000e-10 1.410957635246e-01 + 6.028000000000e-10 2.371909425038e-01 + 6.128000000000e-10 2.791817404178e-01 + 6.228000000000e-10 3.166356138828e-01 + 6.328000000000e-10 3.598203377806e-01 + 6.428000000000e-10 3.963033609435e-01 + 6.528000000000e-10 4.074499160221e-01 + 6.628000000000e-10 3.456826167292e-01 + 6.728000000000e-10 1.950190841630e-01 + 6.828000000000e-10 1.343803454206e-02 + 6.928000000000e-10 -1.410764950259e-01 + 7.028000000000e-10 -2.372163265848e-01 + 7.128000000000e-10 -2.791624229651e-01 + 7.228000000000e-10 -3.166599225368e-01 + 7.328000000000e-10 -3.598002455584e-01 + 7.428000000000e-10 -3.963259615583e-01 + 7.528000000000e-10 -4.074304662079e-01 + 7.628000000000e-10 -3.457033629648e-01 + 7.728000000000e-10 -1.949983704767e-01 + 7.828000000000e-10 -1.345872104163e-02 + 7.928000000000e-10 1.410962716693e-01 + 8.028000000000e-10 2.371963808526e-01 + 8.128000000000e-10 2.791814500218e-01 + 8.228000000000e-10 3.166396456569e-01 + 8.328000000000e-10 3.598191409746e-01 + 8.428000000000e-10 3.963069790813e-01 + 8.528000000000e-10 4.074488078929e-01 + 8.628000000000e-10 3.456858987705e-01 + 8.728000000000e-10 1.950166421641e-01 + 8.828000000000e-10 1.344025602045e-02 + 8.928000000000e-10 -1.410790665154e-01 + 9.028000000000e-10 -2.372142995262e-01 + 9.128000000000e-10 -2.791649325552e-01 + 9.228000000000e-10 -3.166573514474e-01 + 9.328000000000e-10 -3.598022359716e-01 + 9.428000000000e-10 -3.963236588924e-01 + 9.528000000000e-10 -4.074326778223e-01 + 9.628000000000e-10 -3.457016440453e-01 + 9.728000000000e-10 -1.950001702792e-01 + 9.828000000000e-10 -1.345633761364e-02 + 9.928000000000e-10 1.410945129066e-01 + 1.000000000000e-09 2.176807579100e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/conditions.yaml new file mode 100644 index 00000000..c8e12cf0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 14 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_14 +temperature: '27' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/CML_core_tb.sch new file mode 100644 index 00000000..6f66df42 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/CML_core_tb_15.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/CML_core_tb_15.data new file mode 100644 index 00000000..6f87c434 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/CML_core_tb_15.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.831577979118e-01 + 1.728000000000e-10 -1.548331321524e-01 + 1.828000000000e-10 2.954507991941e-03 + 1.928000000000e-10 1.412083661187e-01 + 2.028000000000e-10 2.303947789211e-01 + 2.128000000000e-10 2.725788032239e-01 + 2.228000000000e-10 3.064646814943e-01 + 2.328000000000e-10 3.412898568956e-01 + 2.428000000000e-10 3.692979025942e-01 + 2.528000000000e-10 3.751979264520e-01 + 2.628000000000e-10 3.186495551608e-01 + 2.728000000000e-10 1.849115684226e-01 + 2.828000000000e-10 2.146912258403e-02 + 2.928000000000e-10 -1.215319416200e-01 + 3.028000000000e-10 -2.147336364713e-01 + 3.128000000000e-10 -2.593628319189e-01 + 3.228000000000e-10 -2.947919001104e-01 + 3.328000000000e-10 -3.306034656465e-01 + 3.428000000000e-10 -3.598903423599e-01 + 3.528000000000e-10 -3.674806029527e-01 + 3.628000000000e-10 -3.131864519443e-01 + 3.728000000000e-10 -1.816607205648e-01 + 3.828000000000e-10 -2.002885045896e-02 + 3.928000000000e-10 1.219326732879e-01 + 4.028000000000e-10 2.146583452252e-01 + 4.128000000000e-10 2.593288859790e-01 + 4.228000000000e-10 2.947836961551e-01 + 4.328000000000e-10 3.305873089453e-01 + 4.428000000000e-10 3.597520160348e-01 + 4.528000000000e-10 3.672634041173e-01 + 4.628000000000e-10 3.128292575731e-01 + 4.728000000000e-10 1.812525079401e-01 + 4.828000000000e-10 1.956255085056e-02 + 4.928000000000e-10 -1.223539241893e-01 + 5.028000000000e-10 -2.150587893921e-01 + 5.128000000000e-10 -2.596440912838e-01 + 5.228000000000e-10 -2.950896959018e-01 + 5.328000000000e-10 -3.308452440946e-01 + 5.428000000000e-10 -3.600168265621e-01 + 5.528000000000e-10 -3.674687038170e-01 + 5.628000000000e-10 -3.130140501398e-01 + 5.728000000000e-10 -1.813584327872e-01 + 5.828000000000e-10 -1.965159115909e-02 + 5.928000000000e-10 1.223212864923e-01 + 6.028000000000e-10 2.150157103205e-01 + 6.128000000000e-10 2.596318060931e-01 + 6.228000000000e-10 2.950524078153e-01 + 6.328000000000e-10 3.308363963911e-01 + 6.428000000000e-10 3.599874022300e-01 + 6.528000000000e-10 3.674690181116e-01 + 6.628000000000e-10 3.129980588961e-01 + 6.728000000000e-10 1.813712653368e-01 + 6.828000000000e-10 1.964491680526e-02 + 6.928000000000e-10 -1.223023112353e-01 + 7.028000000000e-10 -2.150202483004e-01 + 7.128000000000e-10 -2.596144309164e-01 + 7.228000000000e-10 -2.950582886643e-01 + 7.328000000000e-10 -3.308199600200e-01 + 7.428000000000e-10 -3.599931640339e-01 + 7.528000000000e-10 -3.674538095645e-01 + 7.628000000000e-10 -3.130042913922e-01 + 7.728000000000e-10 -1.813570925598e-01 + 7.828000000000e-10 -1.965290666609e-02 + 7.928000000000e-10 1.223145971689e-01 + 8.028000000000e-10 2.150114430495e-01 + 8.128000000000e-10 2.596256780136e-01 + 8.228000000000e-10 2.950490452158e-01 + 8.328000000000e-10 3.308307530718e-01 + 8.428000000000e-10 3.599842799802e-01 + 8.528000000000e-10 3.674639698479e-01 + 8.628000000000e-10 3.129957925611e-01 + 8.728000000000e-10 1.813666711568e-01 + 8.828000000000e-10 1.964348030724e-02 + 8.928000000000e-10 -1.223056361887e-01 + 9.028000000000e-10 -2.150207890100e-01 + 9.128000000000e-10 -2.596171721225e-01 + 9.228000000000e-10 -2.950581404305e-01 + 9.328000000000e-10 -3.308221104591e-01 + 9.428000000000e-10 -3.599929167296e-01 + 9.528000000000e-10 -3.674557320782e-01 + 9.628000000000e-10 -3.130039671541e-01 + 9.728000000000e-10 -1.813582011282e-01 + 9.828000000000e-10 -1.965175786777e-02 + 9.928000000000e-10 1.223137237372e-01 + 1.000000000000e-09 1.953703252853e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/conditions.yaml new file mode 100644 index 00000000..e829ebf8 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 15 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_15 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/CML_core_tb.sch new file mode 100644 index 00000000..7ae2f531 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/CML_core_tb_16.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/CML_core_tb_16.data new file mode 100644 index 00000000..c0c44c66 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/CML_core_tb_16.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.908214410229e-01 + 1.728000000000e-10 -1.609006026552e-01 + 1.828000000000e-10 -2.321243117629e-03 + 1.928000000000e-10 1.363185315112e-01 + 2.028000000000e-10 2.253864999197e-01 + 2.128000000000e-10 2.667546328680e-01 + 2.228000000000e-10 3.007016001191e-01 + 2.328000000000e-10 3.359037685855e-01 + 2.428000000000e-10 3.646369081917e-01 + 2.528000000000e-10 3.717564842409e-01 + 2.628000000000e-10 3.164681086559e-01 + 2.728000000000e-10 1.842122200319e-01 + 2.828000000000e-10 2.261788955655e-02 + 2.928000000000e-10 -1.190364341005e-01 + 3.028000000000e-10 -2.112326750882e-01 + 3.128000000000e-10 -2.547832728498e-01 + 3.228000000000e-10 -2.901354995194e-01 + 3.328000000000e-10 -3.261256516764e-01 + 3.428000000000e-10 -3.558916364396e-01 + 3.528000000000e-10 -3.643768878587e-01 + 3.628000000000e-10 -3.109660871267e-01 + 3.728000000000e-10 -1.806005122430e-01 + 3.828000000000e-10 -2.063463882859e-02 + 3.928000000000e-10 1.200417121301e-01 + 4.028000000000e-10 2.117115066678e-01 + 4.128000000000e-10 2.552245954862e-01 + 4.228000000000e-10 2.905358174314e-01 + 4.328000000000e-10 3.264964127076e-01 + 4.428000000000e-10 3.561164409890e-01 + 4.528000000000e-10 3.644937527082e-01 + 4.628000000000e-10 3.108863598347e-01 + 4.728000000000e-10 1.804066968471e-01 + 4.828000000000e-10 2.031749353463e-02 + 4.928000000000e-10 -1.203543467152e-01 + 5.028000000000e-10 -2.120338656010e-01 + 5.128000000000e-10 -2.554694201182e-01 + 5.228000000000e-10 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7.728000000000e-10 -1.804978632753e-01 + 7.828000000000e-10 -2.040852410596e-02 + 7.928000000000e-10 1.203110667878e-01 + 8.028000000000e-10 2.119781439274e-01 + 8.128000000000e-10 2.554465105638e-01 + 8.228000000000e-10 2.907345088651e-01 + 8.328000000000e-10 3.266793442083e-01 + 8.428000000000e-10 3.562962712815e-01 + 8.528000000000e-10 3.646525269207e-01 + 8.628000000000e-10 3.110264147595e-01 + 8.728000000000e-10 1.805087495738e-01 + 8.828000000000e-10 2.039807927138e-02 + 8.928000000000e-10 -1.203008828088e-01 + 9.028000000000e-10 -2.119885143169e-01 + 9.128000000000e-10 -2.554368509477e-01 + 9.228000000000e-10 -2.907446372900e-01 + 9.328000000000e-10 -3.266695427412e-01 + 9.428000000000e-10 -3.563059183968e-01 + 9.528000000000e-10 -3.646431522847e-01 + 9.628000000000e-10 -3.110356032735e-01 + 9.728000000000e-10 -1.804991631480e-01 + 9.828000000000e-10 -2.040735001275e-02 + 9.928000000000e-10 1.203099974113e-01 + 1.000000000000e-09 1.927324868168e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/conditions.yaml new file mode 100644 index 00000000..88e4213c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 16 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_16 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/CML_core_tb.sch new file mode 100644 index 00000000..047a1eaf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/CML_core_tb_17.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/CML_core_tb_17.data new file mode 100644 index 00000000..1e62d263 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/CML_core_tb_17.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.857852225245e-01 + 1.728000000000e-10 -1.572533595452e-01 + 1.828000000000e-10 2.540381659783e-03 + 1.928000000000e-10 1.434374080790e-01 + 2.028000000000e-10 2.351272809546e-01 + 2.128000000000e-10 2.797956268783e-01 + 2.228000000000e-10 3.144243918962e-01 + 2.328000000000e-10 3.493618787392e-01 + 2.428000000000e-10 3.773715695689e-01 + 2.528000000000e-10 3.831823569325e-01 + 2.628000000000e-10 3.264482498061e-01 + 2.728000000000e-10 1.910530045686e-01 + 2.828000000000e-10 2.436059711742e-02 + 2.928000000000e-10 -1.220220612332e-01 + 3.028000000000e-10 -2.180809390746e-01 + 3.128000000000e-10 -2.653775774444e-01 + 3.228000000000e-10 -3.017848824321e-01 + 3.328000000000e-10 -3.379021858146e-01 + 3.428000000000e-10 -3.673696540777e-01 + 3.528000000000e-10 -3.751149757425e-01 + 3.628000000000e-10 -3.209083740174e-01 + 3.728000000000e-10 -1.878979131572e-01 + 3.828000000000e-10 -2.307531260616e-02 + 3.928000000000e-10 1.222703025101e-01 + 4.028000000000e-10 2.179003509445e-01 + 4.128000000000e-10 2.652908784701e-01 + 4.228000000000e-10 3.017672646237e-01 + 4.328000000000e-10 3.378931599738e-01 + 4.428000000000e-10 3.672390198172e-01 + 4.528000000000e-10 3.748903812400e-01 + 4.628000000000e-10 3.205316331029e-01 + 4.728000000000e-10 1.874647700937e-01 + 4.828000000000e-10 2.258819957166e-02 + 4.928000000000e-10 -1.227112688171e-01 + 5.028000000000e-10 -2.183172764214e-01 + 5.128000000000e-10 -2.656203742551e-01 + 5.228000000000e-10 -3.020800906145e-01 + 5.328000000000e-10 -3.381553362553e-01 + 5.428000000000e-10 -3.675051891202e-01 + 5.528000000000e-10 -3.750972240389e-01 + 5.628000000000e-10 -3.207148935088e-01 + 5.728000000000e-10 -1.875700292984e-01 + 5.828000000000e-10 -2.267596999196e-02 + 5.928000000000e-10 1.226776663562e-01 + 6.028000000000e-10 2.182733434309e-01 + 6.128000000000e-10 2.656053081095e-01 + 6.228000000000e-10 3.020411985396e-01 + 6.328000000000e-10 3.381435634392e-01 + 6.428000000000e-10 3.674743818406e-01 + 6.528000000000e-10 3.750952532513e-01 + 6.628000000000e-10 3.206986438750e-01 + 6.728000000000e-10 1.875816736609e-01 + 6.828000000000e-10 2.266940437016e-02 + 6.928000000000e-10 -1.226596158426e-01 + 7.028000000000e-10 -2.182776851932e-01 + 7.128000000000e-10 -2.655888997029e-01 + 7.228000000000e-10 -3.020470638059e-01 + 7.328000000000e-10 -3.381282771084e-01 + 7.428000000000e-10 -3.674800981492e-01 + 7.528000000000e-10 -3.750811166601e-01 + 7.628000000000e-10 -3.207046174850e-01 + 7.728000000000e-10 -1.875682790354e-01 + 7.828000000000e-10 -2.267703281628e-02 + 7.928000000000e-10 1.226713327530e-01 + 8.028000000000e-10 2.182693863135e-01 + 8.128000000000e-10 2.655996099454e-01 + 8.228000000000e-10 3.020383466326e-01 + 8.328000000000e-10 3.381385294735e-01 + 8.428000000000e-10 3.674717742910e-01 + 8.528000000000e-10 3.750907045119e-01 + 8.628000000000e-10 3.206966644115e-01 + 8.728000000000e-10 1.875773616331e-01 + 8.828000000000e-10 2.266807684955e-02 + 8.928000000000e-10 -1.226628120211e-01 + 9.028000000000e-10 -2.182782381400e-01 + 9.128000000000e-10 -2.655915506047e-01 + 9.228000000000e-10 -3.020469590318e-01 + 9.328000000000e-10 -3.381303351991e-01 + 9.428000000000e-10 -3.674798958779e-01 + 9.528000000000e-10 -3.750829516380e-01 + 9.628000000000e-10 -3.207043265993e-01 + 9.728000000000e-10 -1.875693454762e-01 + 9.828000000000e-10 -2.267594148777e-02 + 9.928000000000e-10 1.226704651969e-01 + 1.000000000000e-09 1.977257563344e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/conditions.yaml new file mode 100644 index 00000000..69338d4c --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 17 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_17 +temperature: '80' +vdd: '1.2' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/CML_core_tb.sch new file mode 100644 index 00000000..31f675ce --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/CML_core_tb_18.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/CML_core_tb_18.data new file mode 100644 index 00000000..16422ca1 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/CML_core_tb_18.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.213526702696e-01 + 1.728000000000e-10 -1.557909441213e-01 + 1.828000000000e-10 3.476956205809e-02 + 1.928000000000e-10 1.811250151598e-01 + 2.028000000000e-10 2.596166993269e-01 + 2.128000000000e-10 2.853727091731e-01 + 2.228000000000e-10 3.254453264627e-01 + 2.328000000000e-10 3.792799604087e-01 + 2.428000000000e-10 4.176388066249e-01 + 2.528000000000e-10 4.205544301124e-01 + 2.628000000000e-10 3.463528198985e-01 + 2.728000000000e-10 1.792096076204e-01 + 2.828000000000e-10 -1.442396833933e-02 + 2.928000000000e-10 -1.649237711275e-01 + 3.028000000000e-10 -2.471596975948e-01 + 3.128000000000e-10 -2.748735614517e-01 + 3.228000000000e-10 -3.160128767795e-01 + 3.328000000000e-10 -3.707930594343e-01 + 3.428000000000e-10 -4.104823651943e-01 + 3.528000000000e-10 -4.153692056047e-01 + 3.628000000000e-10 -3.427931169871e-01 + 3.728000000000e-10 -1.769552164151e-01 + 3.828000000000e-10 1.590673093360e-02 + 3.928000000000e-10 1.658834812043e-01 + 4.028000000000e-10 2.479775600913e-01 + 4.128000000000e-10 2.756409688001e-01 + 4.228000000000e-10 3.168596600790e-01 + 4.328000000000e-10 3.715133147191e-01 + 4.428000000000e-10 4.111218222953e-01 + 4.528000000000e-10 4.157229971644e-01 + 4.628000000000e-10 3.430019798682e-01 + 4.728000000000e-10 1.769456026445e-01 + 4.828000000000e-10 -1.592886494610e-02 + 4.928000000000e-10 -1.659782283296e-01 + 5.028000000000e-10 -2.479947853664e-01 + 5.128000000000e-10 -2.756931315881e-01 + 5.228000000000e-10 -3.168416717549e-01 + 5.328000000000e-10 -3.715547211919e-01 + 5.428000000000e-10 -4.111034138799e-01 + 5.528000000000e-10 -4.157691346087e-01 + 5.628000000000e-10 -3.429925568898e-01 + 5.728000000000e-10 -1.770024985869e-01 + 5.828000000000e-10 1.592938202906e-02 + 5.928000000000e-10 1.659292038608e-01 + 6.028000000000e-10 2.480043512000e-01 + 6.128000000000e-10 2.756533285421e-01 + 6.228000000000e-10 3.168576585763e-01 + 6.328000000000e-10 3.715156583068e-01 + 6.428000000000e-10 4.111207690964e-01 + 6.528000000000e-10 4.157343976531e-01 + 6.628000000000e-10 3.430135347581e-01 + 6.728000000000e-10 1.769734665185e-01 + 6.828000000000e-10 -1.590652763180e-02 + 6.928000000000e-10 -1.659537152419e-01 + 7.028000000000e-10 -2.479812550746e-01 + 7.128000000000e-10 -2.756768834918e-01 + 7.228000000000e-10 -3.168350969677e-01 + 7.328000000000e-10 -3.715419152243e-01 + 7.428000000000e-10 -4.110983779981e-01 + 7.528000000000e-10 -4.157587194411e-01 + 7.628000000000e-10 -3.429901444601e-01 + 7.728000000000e-10 -1.769973775521e-01 + 7.828000000000e-10 1.592723735432e-02 + 7.928000000000e-10 1.659318535084e-01 + 8.028000000000e-10 2.480017799848e-01 + 8.128000000000e-10 2.756559811492e-01 + 8.228000000000e-10 3.168566227283e-01 + 8.328000000000e-10 3.715195500188e-01 + 8.428000000000e-10 4.111190536097e-01 + 8.528000000000e-10 4.157370668569e-01 + 8.628000000000e-10 3.430103710665e-01 + 8.728000000000e-10 1.769771675859e-01 + 8.828000000000e-10 -1.590770493918e-02 + 8.928000000000e-10 -1.659501582149e-01 + 9.028000000000e-10 -2.479827571068e-01 + 9.128000000000e-10 -2.756738772283e-01 + 9.228000000000e-10 -3.168377001445e-01 + 9.328000000000e-10 -3.715391180409e-01 + 9.428000000000e-10 -4.111007797151e-01 + 9.528000000000e-10 -4.157556639381e-01 + 9.628000000000e-10 -3.429919881202e-01 + 9.728000000000e-10 -1.769955652012e-01 + 9.828000000000e-10 1.592430721908e-02 + 9.928000000000e-10 1.659331850974e-01 + 1.000000000000e-09 2.332140069758e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/conditions.yaml new file mode 100644 index 00000000..a140860e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 18 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_18 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/CML_core_tb.sch new file mode 100644 index 00000000..b3d13ecf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/CML_core_tb_19.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/CML_core_tb_19.data new file mode 100644 index 00000000..6e384890 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/CML_core_tb_19.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.162777317791e-01 + 1.728000000000e-10 -1.528661974147e-01 + 1.828000000000e-10 3.474832458294e-02 + 1.928000000000e-10 1.787124308466e-01 + 2.028000000000e-10 2.559986610902e-01 + 2.128000000000e-10 2.810767408313e-01 + 2.228000000000e-10 3.219404824571e-01 + 2.328000000000e-10 3.760375868322e-01 + 2.428000000000e-10 4.141294975409e-01 + 2.528000000000e-10 4.175370858756e-01 + 2.628000000000e-10 3.443891646085e-01 + 2.728000000000e-10 1.786024667409e-01 + 2.828000000000e-10 -1.272368439666e-02 + 2.928000000000e-10 -1.612661145276e-01 + 3.028000000000e-10 -2.425558656005e-01 + 3.128000000000e-10 -2.696709375544e-01 + 3.228000000000e-10 -3.115976016931e-01 + 3.328000000000e-10 -3.666762080522e-01 + 3.428000000000e-10 -4.062269757432e-01 + 3.528000000000e-10 -4.117682170104e-01 + 3.628000000000e-10 -3.403932990270e-01 + 3.728000000000e-10 -1.760595961534e-01 + 3.828000000000e-10 1.438676142530e-02 + 3.928000000000e-10 1.623380571180e-01 + 4.028000000000e-10 2.434588647096e-01 + 4.128000000000e-10 2.705169080514e-01 + 4.228000000000e-10 3.125303134845e-01 + 4.328000000000e-10 3.674735521527e-01 + 4.428000000000e-10 4.069324770669e-01 + 4.528000000000e-10 4.121668816011e-01 + 4.628000000000e-10 3.406314536055e-01 + 4.728000000000e-10 1.760592839129e-01 + 4.828000000000e-10 -1.440702618479e-02 + 4.928000000000e-10 -1.624387020945e-01 + 5.028000000000e-10 -2.434775787799e-01 + 5.128000000000e-10 -2.705727170369e-01 + 5.228000000000e-10 -3.125119373252e-01 + 5.328000000000e-10 -3.675184828947e-01 + 5.428000000000e-10 -4.069140356329e-01 + 5.528000000000e-10 -4.122173977207e-01 + 5.628000000000e-10 -3.406230488723e-01 + 5.728000000000e-10 -1.761225643375e-01 + 5.828000000000e-10 1.440482600394e-02 + 5.928000000000e-10 1.623840500109e-01 + 6.028000000000e-10 2.434858819416e-01 + 6.128000000000e-10 2.705285901327e-01 + 6.228000000000e-10 3.125279242462e-01 + 6.328000000000e-10 3.674758375852e-01 + 6.428000000000e-10 4.069313048189e-01 + 6.528000000000e-10 4.121794941223e-01 + 6.628000000000e-10 3.406442721772e-01 + 6.728000000000e-10 1.760913923029e-01 + 6.828000000000e-10 -1.438048626859e-02 + 6.928000000000e-10 -1.624102913298e-01 + 7.028000000000e-10 -2.434611919520e-01 + 7.128000000000e-10 -2.705537859875e-01 + 7.228000000000e-10 -3.125040211699e-01 + 7.328000000000e-10 -3.675038904367e-01 + 7.428000000000e-10 -4.069074652851e-01 + 7.528000000000e-10 -4.122054838885e-01 + 7.628000000000e-10 -3.406192567768e-01 + 7.728000000000e-10 -1.761170868219e-01 + 7.828000000000e-10 1.440247036537e-02 + 7.928000000000e-10 1.623867436405e-01 + 8.028000000000e-10 2.434830143217e-01 + 8.128000000000e-10 2.705312548291e-01 + 8.228000000000e-10 3.125271394700e-01 + 8.328000000000e-10 3.674800931307e-01 + 8.428000000000e-10 4.069295144266e-01 + 8.528000000000e-10 4.121823557439e-01 + 8.628000000000e-10 3.406407407456e-01 + 8.728000000000e-10 1.760956573916e-01 + 8.828000000000e-10 -1.438135361500e-02 + 8.928000000000e-10 -1.624062315135e-01 + 9.028000000000e-10 -2.434625084707e-01 + 9.128000000000e-10 -2.705503455528e-01 + 9.228000000000e-10 -3.125068466958e-01 + 9.328000000000e-10 -3.675009271833e-01 + 9.428000000000e-10 -4.069098943042e-01 + 9.528000000000e-10 -4.122022218921e-01 + 9.628000000000e-10 -3.406210058100e-01 + 9.728000000000e-10 -1.761154015725e-01 + 9.828000000000e-10 1.439913133121e-02 + 9.928000000000e-10 1.623879640093e-01 + 1.000000000000e-09 2.290402036537e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/conditions.yaml new file mode 100644 index 00000000..81fac9cf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 19 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_19 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/CML_core_tb.sch new file mode 100644 index 00000000..0c1eba16 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/CML_core_tb_20.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp -40 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/CML_core_tb_20.data new file mode 100644 index 00000000..3dfcf241 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/CML_core_tb_20.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -3.365386572536e-01 + 1.728000000000e-10 -1.657072094068e-01 + 1.828000000000e-10 3.099865584261e-02 + 1.928000000000e-10 1.820426436768e-01 + 2.028000000000e-10 2.627018214462e-01 + 2.128000000000e-10 2.893736945719e-01 + 2.228000000000e-10 3.287984169352e-01 + 2.328000000000e-10 3.833334317825e-01 + 2.428000000000e-10 4.238785365972e-01 + 2.528000000000e-10 4.280322768716e-01 + 2.628000000000e-10 3.532409470363e-01 + 2.728000000000e-10 1.834641899168e-01 + 2.828000000000e-10 -1.474496205711e-02 + 2.928000000000e-10 -1.691349612478e-01 + 3.028000000000e-10 -2.530204867896e-01 + 3.128000000000e-10 -2.814070764654e-01 + 3.228000000000e-10 -3.218416847899e-01 + 3.328000000000e-10 -3.771799136100e-01 + 3.428000000000e-10 -4.187055626636e-01 + 3.528000000000e-10 -4.243036771430e-01 + 3.628000000000e-10 -3.506062035467e-01 + 3.728000000000e-10 -1.816763297909e-01 + 3.828000000000e-10 1.601938741723e-02 + 3.928000000000e-10 1.700087907901e-01 + 4.028000000000e-10 2.537596951165e-01 + 4.128000000000e-10 2.820887501770e-01 + 4.228000000000e-10 3.225625541805e-01 + 4.328000000000e-10 3.777928583784e-01 + 4.428000000000e-10 4.192485534625e-01 + 4.528000000000e-10 4.246080285894e-01 + 4.628000000000e-10 3.507916132015e-01 + 4.728000000000e-10 1.816929452641e-01 + 4.828000000000e-10 -1.601075067965e-02 + 4.928000000000e-10 -1.700562644838e-01 + 5.028000000000e-10 -2.537513990380e-01 + 5.128000000000e-10 -2.821086741965e-01 + 5.228000000000e-10 -3.225309737549e-01 + 5.328000000000e-10 -3.778081660132e-01 + 5.428000000000e-10 -4.192196231589e-01 + 5.528000000000e-10 -4.246325132019e-01 + 5.628000000000e-10 -3.507765562578e-01 + 5.728000000000e-10 -1.817315603141e-01 + 5.828000000000e-10 1.601468821266e-02 + 5.928000000000e-10 1.700220210141e-01 + 6.028000000000e-10 2.537612841477e-01 + 6.128000000000e-10 2.820810469197e-01 + 6.228000000000e-10 3.225454957468e-01 + 6.328000000000e-10 3.777800822765e-01 + 6.428000000000e-10 4.192350742948e-01 + 6.528000000000e-10 4.246071005326e-01 + 6.628000000000e-10 3.507940665347e-01 + 6.728000000000e-10 1.817094337521e-01 + 6.828000000000e-10 -1.599736953115e-02 + 6.928000000000e-10 -1.700405869499e-01 + 7.028000000000e-10 -2.537437685408e-01 + 7.128000000000e-10 -2.820988428465e-01 + 7.228000000000e-10 -3.225283133162e-01 + 7.328000000000e-10 -3.778004844844e-01 + 7.428000000000e-10 -4.192180216890e-01 + 7.528000000000e-10 -4.246257635725e-01 + 7.628000000000e-10 -3.507760422929e-01 + 7.728000000000e-10 -1.817278922025e-01 + 7.828000000000e-10 1.601285231965e-02 + 7.928000000000e-10 1.700238629540e-01 + 8.028000000000e-10 2.537592487741e-01 + 8.128000000000e-10 2.820829438407e-01 + 8.228000000000e-10 3.225445511573e-01 + 8.328000000000e-10 3.777829985044e-01 + 8.428000000000e-10 4.192337708379e-01 + 8.528000000000e-10 4.246090234999e-01 + 8.628000000000e-10 3.507916632731e-01 + 8.728000000000e-10 1.817122417436e-01 + 8.828000000000e-10 -1.599824136343e-02 + 8.928000000000e-10 -1.700377849177e-01 + 9.028000000000e-10 -2.537449127629e-01 + 9.128000000000e-10 -2.820965585668e-01 + 9.228000000000e-10 -3.225302446360e-01 + 9.328000000000e-10 -3.777982010874e-01 + 9.428000000000e-10 -4.192199753705e-01 + 9.528000000000e-10 -4.246232587341e-01 + 9.628000000000e-10 -3.507775800865e-01 + 9.728000000000e-10 -1.817263367247e-01 + 9.828000000000e-10 1.601066647660e-02 + 9.928000000000e-10 1.700248857455e-01 + 1.000000000000e-09 2.385375784000e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/conditions.yaml new file mode 100644 index 00000000..c3c068cd --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 20 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_20 +temperature: '-40' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/CML_core_tb.sch new file mode 100644 index 00000000..39e95ccf --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/CML_core_tb_21.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/CML_core_tb_21.data new file mode 100644 index 00000000..86f9b023 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/CML_core_tb_21.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.747912795524e-01 + 1.728000000000e-10 -1.327955908449e-01 + 1.828000000000e-10 3.931332790349e-02 + 1.928000000000e-10 1.782957289495e-01 + 2.028000000000e-10 2.573194188668e-01 + 2.128000000000e-10 2.870254911902e-01 + 2.228000000000e-10 3.228650321442e-01 + 2.328000000000e-10 3.690575149088e-01 + 2.428000000000e-10 4.023791308175e-01 + 2.528000000000e-10 4.034409994944e-01 + 2.628000000000e-10 3.332295993533e-01 + 2.728000000000e-10 1.767123870243e-01 + 2.828000000000e-10 -7.574880255958e-03 + 2.928000000000e-10 -1.550892096227e-01 + 3.028000000000e-10 -2.394679486139e-01 + 3.128000000000e-10 -2.715465054757e-01 + 3.228000000000e-10 -3.085580168164e-01 + 3.328000000000e-10 -3.560821219044e-01 + 3.428000000000e-10 -3.914831036325e-01 + 3.528000000000e-10 -3.956717314322e-01 + 3.628000000000e-10 -3.285929470428e-01 + 3.728000000000e-10 -1.747908753666e-01 + 3.828000000000e-10 7.882784627431e-03 + 3.928000000000e-10 1.545893087045e-01 + 4.028000000000e-10 2.389887597051e-01 + 4.128000000000e-10 2.712307710628e-01 + 4.228000000000e-10 3.085047043395e-01 + 4.328000000000e-10 3.559448484744e-01 + 4.428000000000e-10 3.913507819782e-01 + 4.528000000000e-10 3.953547803018e-01 + 4.628000000000e-10 3.282585464854e-01 + 4.728000000000e-10 1.743078825018e-01 + 4.828000000000e-10 -8.291328068348e-03 + 4.928000000000e-10 -1.550293895867e-01 + 5.028000000000e-10 -2.392804293874e-01 + 5.128000000000e-10 -2.715405217782e-01 + 5.228000000000e-10 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a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/conditions.yaml new file mode 100644 index 00000000..1443a18f --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 21 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_21 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/CML_core_tb.sch new file mode 100644 index 00000000..579cefeb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/CML_core_tb_22.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/CML_core_tb_22.data new file mode 100644 index 00000000..ef0e6c8e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/CML_core_tb_22.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.701426652476e-01 + 1.728000000000e-10 -1.295079168872e-01 + 1.828000000000e-10 4.028305902420e-02 + 1.928000000000e-10 1.769160181627e-01 + 2.028000000000e-10 2.543038782058e-01 + 2.128000000000e-10 2.828787064062e-01 + 2.228000000000e-10 3.193333275112e-01 + 2.328000000000e-10 3.660596632426e-01 + 2.428000000000e-10 3.993599084345e-01 + 2.528000000000e-10 4.007883413226e-01 + 2.628000000000e-10 3.312419521143e-01 + 2.728000000000e-10 1.754810620333e-01 + 2.828000000000e-10 -7.142746942805e-03 + 2.928000000000e-10 -1.527779354444e-01 + 3.028000000000e-10 -2.358001938178e-01 + 3.128000000000e-10 -2.668485168237e-01 + 3.228000000000e-10 -3.044746718514e-01 + 3.328000000000e-10 -3.525545062341e-01 + 3.428000000000e-10 -3.880254364838e-01 + 3.528000000000e-10 -3.926522183008e-01 + 3.628000000000e-10 -3.262954780243e-01 + 3.728000000000e-10 -1.733443838482e-01 + 3.828000000000e-10 7.573790689709e-03 + 3.928000000000e-10 1.523487073311e-01 + 4.028000000000e-10 2.353677758316e-01 + 4.128000000000e-10 2.665695097895e-01 + 4.228000000000e-10 3.044490522149e-01 + 4.328000000000e-10 3.524353166192e-01 + 4.428000000000e-10 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6.928000000000e-10 -1.527585341072e-01 + 7.028000000000e-10 -2.356430884825e-01 + 7.128000000000e-10 -2.668569558480e-01 + 7.228000000000e-10 -3.046384985761e-01 + 7.328000000000e-10 -3.526798341051e-01 + 7.428000000000e-10 -3.880593641809e-01 + 7.528000000000e-10 -3.925295324367e-01 + 7.628000000000e-10 -3.260427874257e-01 + 7.728000000000e-10 -1.729689796013e-01 + 7.828000000000e-10 7.970639231343e-03 + 7.928000000000e-10 1.527324506408e-01 + 8.028000000000e-10 2.356706370408e-01 + 8.128000000000e-10 2.668314718812e-01 + 8.228000000000e-10 3.046665550415e-01 + 8.328000000000e-10 3.526529348742e-01 + 8.428000000000e-10 3.880863283995e-01 + 8.528000000000e-10 3.925032166540e-01 + 8.628000000000e-10 3.260684590033e-01 + 8.728000000000e-10 1.729436324779e-01 + 8.828000000000e-10 -7.945691115533e-03 + 8.928000000000e-10 -1.527560420249e-01 + 9.028000000000e-10 -2.356465048672e-01 + 9.128000000000e-10 -2.668543449819e-01 + 9.228000000000e-10 -3.046422495200e-01 + 9.328000000000e-10 -3.526772110923e-01 + 9.428000000000e-10 -3.880628732866e-01 + 9.528000000000e-10 -3.925266759429e-01 + 9.628000000000e-10 -3.260456785141e-01 + 9.728000000000e-10 -1.729665660062e-01 + 9.828000000000e-10 7.967487161613e-03 + 9.928000000000e-10 1.527347010769e-01 + 1.000000000000e-09 2.198236907112e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/conditions.yaml new file mode 100644 index 00000000..cfd32067 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 22 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_22 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/CML_core_tb.sch new file mode 100644 index 00000000..f3078de4 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/CML_core_tb_23.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 27 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/CML_core_tb_23.data new file mode 100644 index 00000000..7b2e7ab2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/CML_core_tb_23.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.957054612407e-01 + 1.728000000000e-10 -1.475216919691e-01 + 1.828000000000e-10 3.196996632833e-02 + 1.928000000000e-10 1.773696584526e-01 + 2.028000000000e-10 2.602670445343e-01 + 2.128000000000e-10 2.919684489720e-01 + 2.228000000000e-10 3.273690981683e-01 + 2.328000000000e-10 3.736661732429e-01 + 2.428000000000e-10 4.086769482098e-01 + 2.528000000000e-10 4.113258498473e-01 + 2.628000000000e-10 3.414272197123e-01 + 2.728000000000e-10 1.833836328070e-01 + 2.828000000000e-10 -4.501363849837e-03 + 2.928000000000e-10 -1.562318489881e-01 + 3.028000000000e-10 -2.435570784568e-01 + 3.128000000000e-10 -2.775386220390e-01 + 3.228000000000e-10 -3.142878056355e-01 + 3.328000000000e-10 -3.618442790176e-01 + 3.428000000000e-10 -3.986028140213e-01 + 3.528000000000e-10 -4.040381865127e-01 + 3.628000000000e-10 -3.369104214062e-01 + 3.728000000000e-10 -1.811830752063e-01 + 3.828000000000e-10 5.355128083595e-03 + 3.928000000000e-10 1.563630270676e-01 + 4.028000000000e-10 2.436522664355e-01 + 4.128000000000e-10 2.777202130414e-01 + 4.228000000000e-10 3.146716935396e-01 + 4.328000000000e-10 3.621309165835e-01 + 4.428000000000e-10 3.988648293319e-01 + 4.528000000000e-10 4.040567761896e-01 + 4.628000000000e-10 3.368362274946e-01 + 4.728000000000e-10 1.809052635954e-01 + 4.828000000000e-10 -5.606347307292e-03 + 4.928000000000e-10 -1.566747533637e-01 + 5.028000000000e-10 -2.438438929936e-01 + 5.128000000000e-10 -2.779365198916e-01 + 5.228000000000e-10 -3.147868656031e-01 + 5.328000000000e-10 -3.623069078218e-01 + 5.428000000000e-10 -3.989546307961e-01 + 5.528000000000e-10 -4.041975741324e-01 + 5.628000000000e-10 -3.368831845243e-01 + 5.728000000000e-10 -1.810020824460e-01 + 5.828000000000e-10 5.593858826262e-03 + 5.928000000000e-10 1.566090374935e-01 + 6.028000000000e-10 2.438493522755e-01 + 6.128000000000e-10 2.778818285943e-01 + 6.228000000000e-10 3.147972496077e-01 + 6.328000000000e-10 3.622530927659e-01 + 6.428000000000e-10 3.989689895438e-01 + 6.528000000000e-10 4.041528360847e-01 + 6.628000000000e-10 3.369065350765e-01 + 6.728000000000e-10 1.809679655825e-01 + 6.828000000000e-10 -5.565139497590e-03 + 6.928000000000e-10 -1.566366178225e-01 + 7.028000000000e-10 -2.438204188033e-01 + 7.128000000000e-10 -2.779089356335e-01 + 7.228000000000e-10 -3.147686522157e-01 + 7.328000000000e-10 -3.622826637804e-01 + 7.428000000000e-10 -3.989411843085e-01 + 7.528000000000e-10 -4.041807678845e-01 + 7.628000000000e-10 -3.368790616195e-01 + 7.728000000000e-10 -1.809947630224e-01 + 7.828000000000e-10 5.591512634984e-03 + 7.928000000000e-10 1.566120178189e-01 + 8.028000000000e-10 2.438458933358e-01 + 8.128000000000e-10 2.778849719194e-01 + 8.228000000000e-10 3.147945034671e-01 + 8.328000000000e-10 3.622568751046e-01 + 8.428000000000e-10 3.989662140554e-01 + 8.528000000000e-10 4.041558823701e-01 + 8.628000000000e-10 3.369030769235e-01 + 8.728000000000e-10 1.809706945647e-01 + 8.828000000000e-10 -5.568483515763e-03 + 8.928000000000e-10 -1.566340912711e-01 + 9.028000000000e-10 -2.438236181184e-01 + 9.128000000000e-10 -2.779064153414e-01 + 9.228000000000e-10 -3.147718720666e-01 + 9.328000000000e-10 -3.622798572716e-01 + 9.428000000000e-10 -3.989444036153e-01 + 9.528000000000e-10 -4.041778978449e-01 + 9.628000000000e-10 -3.368819513246e-01 + 9.728000000000e-10 -1.809921012276e-01 + 9.828000000000e-10 5.588724287086e-03 + 9.928000000000e-10 1.566143682128e-01 + 1.000000000000e-09 2.267750497136e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/conditions.yaml new file mode 100644 index 00000000..25af9d3e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 23 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_23 +temperature: '27' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/CML_core_tb.sch new file mode 100644 index 00000000..7c483691 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/CML_core_tb_24.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/CML_core_tb_24.data new file mode 100644 index 00000000..a01deb89 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/CML_core_tb_24.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.908985659112e-01 + 1.728000000000e-10 -9.049079150817e-02 + 1.828000000000e-10 3.945873683219e-02 + 1.928000000000e-10 1.521437177417e-01 + 2.028000000000e-10 2.220068772324e-01 + 2.128000000000e-10 2.535092334052e-01 + 2.228000000000e-10 2.861973397174e-01 + 2.328000000000e-10 3.239843013312e-01 + 2.428000000000e-10 3.520113017607e-01 + 2.528000000000e-10 3.540468115658e-01 + 2.628000000000e-10 2.949447709683e-01 + 2.728000000000e-10 1.587983397866e-01 + 2.828000000000e-10 -6.865354773069e-03 + 2.928000000000e-10 -1.448078480843e-01 + 3.028000000000e-10 -2.275605338030e-01 + 3.128000000000e-10 -2.625604064747e-01 + 3.228000000000e-10 -2.958552078644e-01 + 3.328000000000e-10 -3.351711406638e-01 + 3.428000000000e-10 -3.644984224381e-01 + 3.528000000000e-10 -3.669950471097e-01 + 3.628000000000e-10 -3.072796408874e-01 + 3.728000000000e-10 -1.699866077827e-01 + 3.828000000000e-10 -2.842045316933e-03 + 3.928000000000e-10 1.365086891956e-01 + 4.028000000000e-10 2.207869920157e-01 + 4.128000000000e-10 2.567713461579e-01 + 4.228000000000e-10 2.907030026757e-01 + 4.328000000000e-10 3.302687598301e-01 + 4.428000000000e-10 3.600803190405e-01 + 4.528000000000e-10 3.632331450943e-01 + 4.628000000000e-10 3.045482678871e-01 + 4.728000000000e-10 1.682698274629e-01 + 4.828000000000e-10 2.058504292284e-03 + 4.928000000000e-10 -1.367871396964e-01 + 5.028000000000e-10 -2.207717990252e-01 + 5.128000000000e-10 -2.567684885934e-01 + 5.228000000000e-10 -2.906651825463e-01 + 5.328000000000e-10 -3.302494358660e-01 + 5.428000000000e-10 -3.599712284157e-01 + 5.528000000000e-10 -3.631239508150e-01 + 5.628000000000e-10 -3.043584109358e-01 + 5.728000000000e-10 -1.680958385636e-01 + 5.828000000000e-10 -1.834034512727e-03 + 5.928000000000e-10 1.369613450439e-01 + 6.028000000000e-10 2.209618957221e-01 + 6.128000000000e-10 2.568952536478e-01 + 6.228000000000e-10 2.908171185353e-01 + 6.328000000000e-10 3.303549214919e-01 + 6.428000000000e-10 3.601082390759e-01 + 6.528000000000e-10 3.632059905221e-01 + 6.628000000000e-10 3.044557238628e-01 + 6.728000000000e-10 1.681292777859e-01 + 6.828000000000e-10 1.882442241730e-03 + 6.928000000000e-10 -1.369637862409e-01 + 7.028000000000e-10 -2.209363992802e-01 + 7.128000000000e-10 -2.569065829626e-01 + 7.228000000000e-10 -2.907936706940e-01 + 7.328000000000e-10 -3.303682701482e-01 + 7.428000000000e-10 -3.600879594395e-01 + 7.528000000000e-10 -3.632220959958e-01 + 7.628000000000e-10 -3.044401007882e-01 + 7.728000000000e-10 -1.681486407544e-01 + 7.828000000000e-10 -1.870004957548e-03 + 7.928000000000e-10 1.369437070838e-01 + 8.028000000000e-10 2.209481957039e-01 + 8.128000000000e-10 2.568879030180e-01 + 8.228000000000e-10 2.908064848389e-01 + 8.328000000000e-10 3.303493303219e-01 + 8.428000000000e-10 3.601006147126e-01 + 8.528000000000e-10 3.632041339109e-01 + 8.628000000000e-10 3.044528281549e-01 + 8.728000000000e-10 1.681322760827e-01 + 8.828000000000e-10 1.883536763259e-03 + 8.928000000000e-10 -1.369582535540e-01 + 9.028000000000e-10 -2.209346296842e-01 + 9.128000000000e-10 -2.569016830366e-01 + 9.228000000000e-10 -2.907925936742e-01 + 9.328000000000e-10 -3.303636164667e-01 + 9.428000000000e-10 -3.600871302257e-01 + 9.528000000000e-10 -3.632178492939e-01 + 9.628000000000e-10 -3.044398392752e-01 + 9.728000000000e-10 -1.681454261603e-01 + 9.828000000000e-10 -1.870628705438e-03 + 9.928000000000e-10 1.369459433541e-01 + 1.000000000000e-09 2.037746084522e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/conditions.yaml new file mode 100644 index 00000000..98b082aa --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 24 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_24 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/CML_core_tb.sch new file mode 100644 index 00000000..48d7a9a7 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/CML_core_tb_25.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/CML_core_tb_25.data new file mode 100644 index 00000000..182746dc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/CML_core_tb_25.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -1.878715792581e-01 + 1.728000000000e-10 -8.812036120597e-02 + 1.828000000000e-10 4.046526586524e-02 + 1.928000000000e-10 1.515705626527e-01 + 2.028000000000e-10 2.200566198342e-01 + 2.128000000000e-10 2.503583455541e-01 + 2.228000000000e-10 2.832914205797e-01 + 2.328000000000e-10 3.216696186231e-01 + 2.428000000000e-10 3.500303926946e-01 + 2.528000000000e-10 3.524815741411e-01 + 2.628000000000e-10 2.936462106779e-01 + 2.728000000000e-10 1.576219496242e-01 + 2.828000000000e-10 -7.121462127754e-03 + 2.928000000000e-10 -1.436071598858e-01 + 3.028000000000e-10 -2.249496922999e-01 + 3.128000000000e-10 -2.586592240194e-01 + 3.228000000000e-10 -2.922419569702e-01 + 3.328000000000e-10 -3.321983211521e-01 + 3.428000000000e-10 -3.618684381611e-01 + 3.528000000000e-10 -3.648249016007e-01 + 3.628000000000e-10 -3.055379959953e-01 + 3.728000000000e-10 -1.686105488568e-01 + 3.828000000000e-10 -2.582643774162e-03 + 3.928000000000e-10 1.352182085241e-01 + 4.028000000000e-10 2.180702244722e-01 + 4.128000000000e-10 2.527783389641e-01 + 4.228000000000e-10 2.869845016096e-01 + 4.328000000000e-10 3.271697550530e-01 + 4.428000000000e-10 3.573213651505e-01 + 4.528000000000e-10 3.609341509143e-01 + 4.628000000000e-10 3.026708512688e-01 + 4.728000000000e-10 1.667591862946e-01 + 4.828000000000e-10 1.676053368052e-03 + 4.928000000000e-10 -1.356064331336e-01 + 5.028000000000e-10 -2.181494577446e-01 + 5.128000000000e-10 -2.528581012316e-01 + 5.228000000000e-10 -2.870203472690e-01 + 5.328000000000e-10 -3.272198972187e-01 + 5.428000000000e-10 -3.572767955086e-01 + 5.528000000000e-10 -3.608816832152e-01 + 5.628000000000e-10 -3.025243774497e-01 + 5.728000000000e-10 -1.666129730216e-01 + 5.828000000000e-10 -1.465204057357e-03 + 5.928000000000e-10 1.357749931272e-01 + 6.028000000000e-10 2.183376260095e-01 + 6.128000000000e-10 2.529831758691e-01 + 6.228000000000e-10 2.871716452249e-01 + 6.328000000000e-10 3.273254918206e-01 + 6.428000000000e-10 3.574148326524e-01 + 6.528000000000e-10 3.609652866209e-01 + 6.628000000000e-10 3.026246199120e-01 + 6.728000000000e-10 1.666502220733e-01 + 6.828000000000e-10 1.518129196282e-03 + 6.928000000000e-10 -1.357732099566e-01 + 7.028000000000e-10 -2.183080403425e-01 + 7.128000000000e-10 -2.529912058397e-01 + 7.228000000000e-10 -2.871450109118e-01 + 7.328000000000e-10 -3.273360198503e-01 + 7.428000000000e-10 -3.573916245859e-01 + 7.528000000000e-10 -3.609790664977e-01 + 7.628000000000e-10 -3.026068066478e-01 + 7.728000000000e-10 -1.666683959674e-01 + 7.828000000000e-10 -1.504711775466e-03 + 7.928000000000e-10 1.357534602326e-01 + 8.028000000000e-10 2.183202914392e-01 + 8.128000000000e-10 2.529726082081e-01 + 8.228000000000e-10 2.871582302084e-01 + 8.328000000000e-10 3.273171284192e-01 + 8.428000000000e-10 3.574045685766e-01 + 8.528000000000e-10 3.609610284998e-01 + 8.628000000000e-10 3.026196909841e-01 + 8.728000000000e-10 1.666518528053e-01 + 8.828000000000e-10 1.518315117290e-03 + 8.928000000000e-10 -1.357682747942e-01 + 9.028000000000e-10 -2.183066580359e-01 + 9.128000000000e-10 -2.529866332266e-01 + 9.228000000000e-10 -2.871442829871e-01 + 9.328000000000e-10 -3.273316607928e-01 + 9.428000000000e-10 -3.573910212469e-01 + 9.528000000000e-10 -3.609749965926e-01 + 9.628000000000e-10 -3.026065830591e-01 + 9.728000000000e-10 -1.666652414066e-01 + 9.828000000000e-10 -1.505286118034e-03 + 9.928000000000e-10 1.357557668798e-01 + 1.000000000000e-09 2.016242513907e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/conditions.yaml new file mode 100644 index 00000000..efe12cb2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 25 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ff +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_25 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/CML_core_tb.sch new file mode 100644 index 00000000..77437bd5 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/CML_core_tb.sch @@ -0,0 +1,71 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 740 -940 740 -920 {lab=GND} +N 740 -1090 740 -1060 {lab=VDD} +N 600 -1020 620 -1020 {lab=Vinplus} +N 600 -980 620 -980 {lab=Vinminus} +N 860 -1020 880 -1020 {lab=Voplus} +N 860 -980 880 -980 {lab=Vominus} +N 1150 -850 1150 -820 {lab=VDD} +N 1150 -760 1150 -730 {lab=GND} +N 930 -850 930 -820 {lab=Vinminus} +N 930 -760 930 -730 {lab=GND} +N 720 -850 720 -820 {lab=Vinplus} +N 720 -760 720 -730 {lab=GND} +C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false +value=" +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/CML_core_tb_26.data vo_diff +quit + +.endc +"} +C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus} +C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus} +C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice + +.temp 80 +" +} +C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD} +C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus} +C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus} +C {CML_divider.sym} 740 -1000 0 1 {name=x1} +C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false} +C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD} +C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false} +C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/CML_core_tb_26.data new file mode 100644 index 00000000..c21b093d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/CML_core_tb_26.data @@ -0,0 +1,85 @@ + 1.628000000000e-10 -2.135873679018e-01 + 1.728000000000e-10 -1.054229355639e-01 + 1.828000000000e-10 3.485798650969e-02 + 1.928000000000e-10 1.569675139767e-01 + 2.028000000000e-10 2.330635404696e-01 + 2.128000000000e-10 2.680443549179e-01 + 2.228000000000e-10 3.014044829899e-01 + 2.328000000000e-10 3.394080314353e-01 + 2.428000000000e-10 3.679529618424e-01 + 2.528000000000e-10 3.700593040123e-01 + 2.628000000000e-10 3.097824620429e-01 + 2.728000000000e-10 1.706514675999e-01 + 2.828000000000e-10 3.558070014658e-04 + 2.928000000000e-10 -1.428409974599e-01 + 3.028000000000e-10 -2.298289579719e-01 + 3.128000000000e-10 -2.678794741753e-01 + 3.228000000000e-10 -3.017454056957e-01 + 3.328000000000e-10 -3.410620518407e-01 + 3.428000000000e-10 -3.712405389398e-01 + 3.528000000000e-10 -3.749327973471e-01 + 3.628000000000e-10 -3.157484466493e-01 + 3.728000000000e-10 -1.773087198166e-01 + 3.828000000000e-10 -7.070252178339e-03 + 3.928000000000e-10 1.364462941621e-01 + 4.028000000000e-10 2.243241068758e-01 + 4.128000000000e-10 2.631279769125e-01 + 4.228000000000e-10 2.976097246349e-01 + 4.328000000000e-10 3.371159716785e-01 + 4.428000000000e-10 3.676405775058e-01 + 4.528000000000e-10 3.717787254056e-01 + 4.628000000000e-10 3.133854979421e-01 + 4.728000000000e-10 1.756870158595e-01 + 4.828000000000e-10 6.171257018760e-03 + 4.928000000000e-10 -1.369680995621e-01 + 5.028000000000e-10 -2.245781248931e-01 + 5.128000000000e-10 -2.633829468620e-01 + 5.228000000000e-10 -2.978042748481e-01 + 5.328000000000e-10 -3.373348877854e-01 + 5.428000000000e-10 -3.677584906255e-01 + 5.528000000000e-10 -3.718812762918e-01 + 5.628000000000e-10 -3.133649557524e-01 + 5.728000000000e-10 -1.756479312047e-01 + 5.828000000000e-10 -6.040608056278e-03 + 5.928000000000e-10 1.370690415770e-01 + 6.028000000000e-10 2.247181767783e-01 + 6.128000000000e-10 2.634617265965e-01 + 6.228000000000e-10 2.979157296699e-01 + 6.328000000000e-10 3.373958940353e-01 + 6.428000000000e-10 3.678612954525e-01 + 6.528000000000e-10 3.719309221475e-01 + 6.628000000000e-10 3.134447453066e-01 + 6.728000000000e-10 1.756687688086e-01 + 6.828000000000e-10 6.090200135509e-03 + 6.928000000000e-10 -1.370702307281e-01 + 7.028000000000e-10 -2.246847420648e-01 + 7.128000000000e-10 -2.634701196121e-01 + 7.228000000000e-10 -2.978849158722e-01 + 7.328000000000e-10 -3.374068878437e-01 + 7.428000000000e-10 -3.678336110941e-01 + 7.528000000000e-10 -3.719446503824e-01 + 7.628000000000e-10 -3.134227431793e-01 + 7.728000000000e-10 -1.756868885858e-01 + 7.828000000000e-10 -6.072676723321e-03 + 7.928000000000e-10 1.370503070743e-01 + 8.028000000000e-10 2.247004966695e-01 + 8.128000000000e-10 2.634509722982e-01 + 8.228000000000e-10 2.979013793804e-01 + 8.328000000000e-10 3.373870921905e-01 + 8.428000000000e-10 3.678495602861e-01 + 8.528000000000e-10 3.719256264749e-01 + 8.628000000000e-10 3.134381864470e-01 + 8.728000000000e-10 1.756688935561e-01 + 8.828000000000e-10 6.088345643719e-03 + 8.928000000000e-10 -1.370666831053e-01 + 9.028000000000e-10 -2.246851372638e-01 + 9.128000000000e-10 -2.634666121684e-01 + 9.228000000000e-10 -2.978856025968e-01 + 9.328000000000e-10 -3.374033621769e-01 + 9.428000000000e-10 -3.678342837151e-01 + 9.528000000000e-10 -3.719412125322e-01 + 9.628000000000e-10 -3.134235677100e-01 + 9.728000000000e-10 -1.756838495744e-01 + 9.828000000000e-10 -6.073781243164e-03 + 9.928000000000e-10 1.370527135588e-01 + 1.000000000000e-09 2.065229990524e-01 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/CML_divider.sym new file mode 100644 index 00000000..e46eb233 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/conditions.yaml new file mode 100644 index 00000000..bb398631 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26/conditions.yaml @@ -0,0 +1,9 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice +N: 26 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: ss +filename: CML_core_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/run_26 +temperature: '80' +vdd: '1.6' diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/simulation_summary.csv new file mode 100644 index 00000000..1422d52e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/simulation_summary.csv @@ -0,0 +1,28 @@ +run,corner,temperature,vdd,time,vo_diff,frequency,amplitude,voltage_swing +run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.111e-01, -1.870e-01, -3.563e-02, …]",4.722e+09,0.382,0.763 +run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.099e-01, -1.895e-01, -4.060e-02, …]",4.722e+09,0.377,0.754 +run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.876e-01, -3.217e-02, …]",4.722e+09,0.390,0.780 +run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.915e-01, -1.780e-01, -3.803e-02, …]",4.722e+09,0.357,0.715 +run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.909e-01, -1.806e-01, -4.276e-02, …]",4.722e+09,0.353,0.706 +run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.959e-01, -1.792e-01, -3.599e-02, …]",4.722e+09,0.366,0.732 +run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.689e-01, -1.692e-01, -4.423e-02, …]",4.722e+09,0.319,0.639 +run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.694e-01, -1.722e-01, -4.907e-02, …]",4.722e+09,0.315,0.629 +run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.723e-01, -1.701e-01, -4.252e-02, …]",4.722e+09,0.330,0.659 +run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.623e-01, -1.963e-01, -5.713e-03, …]",4.722e+09,0.421,0.843 +run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.622e-01, -1.984e-01, -1.024e-02, …]",4.722e+09,0.418,0.836 +run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.669e-01, -1.979e-01, -3.070e-03, …]",4.722e+09,0.429,0.857 +run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.388e-01, -1.852e-01, -4.985e-03, …]",4.722e+09,0.401,0.803 +run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.407e-01, -1.880e-01, -9.263e-03, …]",4.722e+09,0.398,0.796 +run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.446e-01, -1.889e-01, -5.355e-03, …]",4.722e+09,0.409,0.817 +run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.832e-01, -1.548e-01, 2.955e-03, …]",4.722e+09,0.371,0.743 +run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.908e-01, -1.609e-01, -2.321e-03, …]",4.722e+09,0.368,0.736 +run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.858e-01, -1.573e-01, 2.540e-03, …]",4.722e+09,0.379,0.758 +run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.214e-01, -1.558e-01, 3.477e-02, …]",4.722e+09,0.418,0.836 +run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.163e-01, -1.529e-01, 3.475e-02, …]",4.722e+09,0.415,0.830 +run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.365e-01, -1.657e-01, 3.100e-02, …]",4.722e+09,0.426,0.853 +run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.748e-01, -1.328e-01, 3.931e-02, …]",4.722e+09,0.400,0.799 +run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.701e-01, -1.295e-01, 4.028e-02, …]",4.722e+09,0.397,0.793 +run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.957e-01, -1.475e-01, 3.197e-02, …]",4.722e+09,0.408,0.816 +run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.909e-01, -9.049e-02, 3.946e-02, …]",4.722e+09,0.365,0.730 +run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-1.879e-01, -8.812e-02, 4.047e-02, …]",4.722e+09,0.363,0.726 +run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.136e-01, -1.054e-01, 3.486e-02, …]",4.722e+09,0.373,0.747 diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/simulation_summary.md new file mode 100644 index 00000000..014379b0 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/simulation_summary.md @@ -0,0 +1,31 @@ +# Simulation Summary for CML divider frequency response + +| run | corner | temperature | vdd | time | vo_diff | frequency | amplitude | voltage_swing | +| :-- | -----: | ----------: | --: | ---: | ------: | --------: | --------: | ------------: | +| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.111e-01, -1.870e-01, -3.563e-02, …] | 4.722e+09 | 0.382 | 0.763 | +| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.099e-01, -1.895e-01, -4.060e-02, …] | 4.722e+09 | 0.377 | 0.754 | +| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.876e-01, -3.217e-02, …] | 4.722e+09 | 0.390 | 0.780 | +| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.915e-01, -1.780e-01, -3.803e-02, …] | 4.722e+09 | 0.357 | 0.715 | +| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.909e-01, -1.806e-01, -4.276e-02, …] | 4.722e+09 | 0.353 | 0.706 | +| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.959e-01, -1.792e-01, -3.599e-02, …] | 4.722e+09 | 0.366 | 0.732 | +| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.689e-01, -1.692e-01, -4.423e-02, …] | 4.722e+09 | 0.319 | 0.639 | +| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.694e-01, -1.722e-01, -4.907e-02, …] | 4.722e+09 | 0.315 | 0.629 | +| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.723e-01, -1.701e-01, -4.252e-02, …] | 4.722e+09 | 0.330 | 0.659 | +| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.623e-01, -1.963e-01, -5.713e-03, …] | 4.722e+09 | 0.421 | 0.843 | +| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.622e-01, -1.984e-01, -1.024e-02, …] | 4.722e+09 | 0.418 | 0.836 | +| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.669e-01, -1.979e-01, -3.070e-03, …] | 4.722e+09 | 0.429 | 0.857 | +| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.388e-01, -1.852e-01, -4.985e-03, …] | 4.722e+09 | 0.401 | 0.803 | +| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.407e-01, -1.880e-01, -9.263e-03, …] | 4.722e+09 | 0.398 | 0.796 | +| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.446e-01, -1.889e-01, -5.355e-03, …] | 4.722e+09 | 0.409 | 0.817 | +| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.832e-01, -1.548e-01, 2.955e-03, …] | 4.722e+09 | 0.371 | 0.743 | +| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.908e-01, -1.609e-01, -2.321e-03, …] | 4.722e+09 | 0.368 | 0.736 | +| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.858e-01, -1.573e-01, 2.540e-03, …] | 4.722e+09 | 0.379 | 0.758 | +| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.214e-01, -1.558e-01, 3.477e-02, …] | 4.722e+09 | 0.418 | 0.836 | +| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.163e-01, -1.529e-01, 3.475e-02, …] | 4.722e+09 | 0.415 | 0.830 | +| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.365e-01, -1.657e-01, 3.100e-02, …] | 4.722e+09 | 0.426 | 0.853 | +| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.748e-01, -1.328e-01, 3.931e-02, …] | 4.722e+09 | 0.400 | 0.799 | +| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.701e-01, -1.295e-01, 4.028e-02, …] | 4.722e+09 | 0.397 | 0.793 | +| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.957e-01, -1.475e-01, 3.197e-02, …] | 4.722e+09 | 0.408 | 0.816 | +| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.909e-01, -9.049e-02, 3.946e-02, …] | 4.722e+09 | 0.365 | 0.730 | +| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-1.879e-01, -8.812e-02, 4.047e-02, …] | 4.722e+09 | 0.363 | 0.726 | +| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.136e-01, -1.054e-01, 3.486e-02, …] | 4.722e+09 | 0.373 | 0.747 | diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/vo_diff_vs_time.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/vo_diff_vs_time.png new file mode 100644 index 00000000..b3049fae Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/parameters/ac_params/vo_diff_vs_time.png differ diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/summary.md new file mode 100644 index 00000000..682fed03 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-11_17-59-49/summary.md @@ -0,0 +1,11 @@ + +# CACE Summary for CML_divider + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Frequency | ngspice | frequency | 4.3 GHz | 4.722 GHz | 5.0 GHz | 4.722 GHz | 5.2 GHz | 4.722 GHz | Pass ✅ | +| Amplitude | ngspice | amplitude | 0.2 V | 0.315 V | 0.4 V | 0.382 V | 0.6 V | 0.429 V | Pass ✅ | +| Voltage swing | ngspice | voltage_swing | 0.4 V | 0.629 V | 0.8 V | 0.763 V | 1.2 V | 0.857 V | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/CML_divider/testbench/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/testbench/CML_core_tb.sch new file mode 100644 index 00000000..0fc8ac25 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/testbench/CML_core_tb.sch @@ -0,0 +1,171 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +B 2 1110 -700 1910 -300 {flags=graph +y1=0.72 +y2=1.2 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=2.9974739e-10 +x2=5.9578291e-10 +divx=5 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 +dataset=-1 +unitx=1 +logx=0 +logy=0 +color="4 7" +node="vo_m +vo_p"} +B 2 1110 -1120 1910 -720 {flags=graph +y1=0.17956962 +y2=0.4801486 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=2.9974739e-10 +x2=5.9578291e-10 +divx=5 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 +dataset=-1 +unitx=1 +logx=0 +logy=0 +color="4 7" +node="vinplus +vinminus" +} +B 2 1930 -1120 2730 -720 {flags=graph +y1=-0.41 +y2=0.41 +ypos1=0 +ypos2=2 +divy=5 +subdivy=1 +unity=1 +x1=2.9974739e-10 +x2=5.9578291e-10 +divx=5 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 +dataset=-1 +unitx=1 +logx=0 +logy=0 +color=4 +node=vo_diff} +N 420 -290 420 -260 {lab=vdd} +N 420 -200 420 -170 {lab=GND} +N 690 -280 690 -260 {lab=GND} +N 690 -430 690 -400 {lab=vdd} +N 810 -360 830 -360 {lab=Vinplus} +N 810 -320 830 -320 {lab=Vinminus} +N 550 -360 570 -360 {lab=Voplus} +N 550 -320 570 -320 {lab=Vominus} +N 210 -300 210 -270 {lab=Vinminus} +N 210 -210 210 -180 {lab=GND} +N 0 -300 0 -270 {lab=Vinplus} +N 0 -210 0 -180 {lab=GND} +C {code_shown.sym} 10 -1150 0 0 {name=transient_tb only_toplevel=false +value=" +.include CML_core_tb.save +.param temp=100 +.param A = 0.3 +.ic V(Voplus)=1.2 +.control +set noaskquit +set numdgt=12 + +* Save & simulate +save all +op +write CML_core_tb.raw +set appendwrite +tran 10p 1n 160p +save all + +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m +* --- Main output (mimic CACE naming, just to compare) --- +set wr_singlescale +wrdata differential_output.txt vo_diff + +* --- Extra debug (like we did for CACE) --- +set wr_vecnames +wrdata manual_debug.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write CML_core_tb.raw +.endc +"} +C {devices/code_shown.sym} 10 -460 0 0 {name=MODEL only_toplevel=true +format="tcleval( @value )" +value=".lib cornerMOSlv.lib mos_ss +" +} +C {devices/launcher.sym} 1190 -250 0 0 {name=h1 +descr="OP annotate" +tclcommand="xschem annotate_op" +} +C {launcher.sym} 1190 -170 0 0 {name=h5 +descr="load waves" +tclcommand="xschem raw_read $netlist_dir/CML_core_tb.raw tran" +} +C {vsource.sym} 420 -230 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 420 -170 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 420 -290 0 0 {name=p2 sig_type=std_logic lab=vdd} +C {opin.sym} 550 -360 2 0 {name=p6 lab=Voplus} +C {gnd.sym} 690 -260 0 0 {name=l3 lab=GND} +C {lab_pin.sym} 690 -430 0 1 {name=p7 sig_type=std_logic lab=vdd} +C {gnd.sym} 210 -180 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 210 -300 0 0 {name=p4 sig_type=std_logic lab=Vinminus} +C {vsource.sym} 0 -240 0 0 {name=V3 value="dc 0 ac 0 SIN(0.6 A 10G 0 0 0)" savecurrent=false} +C {gnd.sym} 0 -180 0 0 {name=l4 lab=GND +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {lab_pin.sym} 0 -300 0 0 {name=p8 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {launcher.sym} 1190 -210 0 0 {name=h2 +descr=SimulateNGSPICE +tclcommand=" +# Setup the default simulation commands if not already set up +# for example by already launched simulations. +set_sim_defaults +puts $sim(spice,1,cmd) + +# Change the Xyce command. In the spice category there are currently +# 5 commands (0, 1, 2, 3, 4). Command 3 is the Xyce batch +# you can get the number by querying $sim(spice,n) +set sim(spice,1,cmd) \{ngspice \\"$N\\" -a\} + +# change the simulator to be used (Xyce) +set sim(spice,default) 0 + +# Create FET and BIP .save file +mkdir -p $netlist_dir +write_data [save_params] $netlist_dir/[file rootname [file tail [xschem get current_name]]].save + +# run netlist and simulation +xschem netlist +simulate +"} +C {vsource.sym} 210 -240 0 0 {name=V2 value="dc 0 ac 0 SIN(0.6 A 10G 0 0 180)" savecurrent=false} +C {opin.sym} 550 -320 0 1 {name=p9 lab=Vominus} +C {lab_pin.sym} 830 -320 2 0 {name=p1 sig_type=std_logic lab=Vinminus} +C {lab_pin.sym} 830 -360 2 0 {name=p3 sig_type=std_logic lab=Vinplus +value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"} +C {CML_divider.sym} 690 -340 0 0 {name=x1} diff --git a/modules/module_4_type_2_PLL/CML_divider/testbench/simulations/CML_core_tb.save b/modules/module_4_type_2_PLL/CML_divider/testbench/simulations/CML_core_tb.save new file mode 100644 index 00000000..bf475e1e --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/testbench/simulations/CML_core_tb.save @@ -0,0 +1,122 @@ +* Place this .save file with a .include line in your testbench + +.save @n.x1.xm1.nsg13_lv_nmos[ids] +.save @n.x1.xm1.nsg13_lv_nmos[gm] +.save @n.x1.xm1.nsg13_lv_nmos[gds] +.save @n.x1.xm1.nsg13_lv_nmos[vth] +.save @n.x1.xm1.nsg13_lv_nmos[vgs] +.save @n.x1.xm1.nsg13_lv_nmos[vdss] +.save @n.x1.xm1.nsg13_lv_nmos[vds] +.save @n.x1.xm1.nsg13_lv_nmos[cgg] +.save @n.x1.xm1.nsg13_lv_nmos[cgsol] +.save @n.x1.xm1.nsg13_lv_nmos[cgdol] +.save @n.x1.xm2.nsg13_lv_nmos[ids] +.save @n.x1.xm2.nsg13_lv_nmos[gm] +.save @n.x1.xm2.nsg13_lv_nmos[gds] +.save @n.x1.xm2.nsg13_lv_nmos[vth] +.save @n.x1.xm2.nsg13_lv_nmos[vgs] +.save @n.x1.xm2.nsg13_lv_nmos[vdss] +.save @n.x1.xm2.nsg13_lv_nmos[vds] +.save @n.x1.xm2.nsg13_lv_nmos[cgg] +.save @n.x1.xm2.nsg13_lv_nmos[cgsol] +.save @n.x1.xm2.nsg13_lv_nmos[cgdol] +.save @n.x1.xm3.nsg13_lv_nmos[ids] +.save @n.x1.xm3.nsg13_lv_nmos[gm] +.save @n.x1.xm3.nsg13_lv_nmos[gds] +.save @n.x1.xm3.nsg13_lv_nmos[vth] +.save @n.x1.xm3.nsg13_lv_nmos[vgs] +.save @n.x1.xm3.nsg13_lv_nmos[vdss] +.save @n.x1.xm3.nsg13_lv_nmos[vds] +.save @n.x1.xm3.nsg13_lv_nmos[cgg] +.save @n.x1.xm3.nsg13_lv_nmos[cgsol] +.save @n.x1.xm3.nsg13_lv_nmos[cgdol] +.save @n.x1.xm4.nsg13_lv_nmos[ids] +.save @n.x1.xm4.nsg13_lv_nmos[gm] +.save @n.x1.xm4.nsg13_lv_nmos[gds] +.save @n.x1.xm4.nsg13_lv_nmos[vth] +.save @n.x1.xm4.nsg13_lv_nmos[vgs] +.save @n.x1.xm4.nsg13_lv_nmos[vdss] +.save @n.x1.xm4.nsg13_lv_nmos[vds] +.save @n.x1.xm4.nsg13_lv_nmos[cgg] +.save @n.x1.xm4.nsg13_lv_nmos[cgsol] +.save @n.x1.xm4.nsg13_lv_nmos[cgdol] +.save @n.x1.xm5.nsg13_lv_nmos[ids] +.save @n.x1.xm5.nsg13_lv_nmos[gm] +.save @n.x1.xm5.nsg13_lv_nmos[gds] +.save @n.x1.xm5.nsg13_lv_nmos[vth] +.save @n.x1.xm5.nsg13_lv_nmos[vgs] +.save @n.x1.xm5.nsg13_lv_nmos[vdss] +.save @n.x1.xm5.nsg13_lv_nmos[vds] +.save @n.x1.xm5.nsg13_lv_nmos[cgg] +.save @n.x1.xm5.nsg13_lv_nmos[cgsol] +.save @n.x1.xm5.nsg13_lv_nmos[cgdol] +.save @n.x1.xm6.nsg13_lv_nmos[ids] +.save @n.x1.xm6.nsg13_lv_nmos[gm] +.save @n.x1.xm6.nsg13_lv_nmos[gds] +.save @n.x1.xm6.nsg13_lv_nmos[vth] +.save @n.x1.xm6.nsg13_lv_nmos[vgs] +.save @n.x1.xm6.nsg13_lv_nmos[vdss] +.save @n.x1.xm6.nsg13_lv_nmos[vds] +.save @n.x1.xm6.nsg13_lv_nmos[cgg] +.save @n.x1.xm6.nsg13_lv_nmos[cgsol] +.save @n.x1.xm6.nsg13_lv_nmos[cgdol] +.save @n.x1.xm7.nsg13_lv_nmos[ids] +.save @n.x1.xm7.nsg13_lv_nmos[gm] +.save @n.x1.xm7.nsg13_lv_nmos[gds] +.save @n.x1.xm7.nsg13_lv_nmos[vth] +.save @n.x1.xm7.nsg13_lv_nmos[vgs] +.save @n.x1.xm7.nsg13_lv_nmos[vdss] +.save @n.x1.xm7.nsg13_lv_nmos[vds] +.save @n.x1.xm7.nsg13_lv_nmos[cgg] +.save @n.x1.xm7.nsg13_lv_nmos[cgsol] +.save @n.x1.xm7.nsg13_lv_nmos[cgdol] +.save @n.x1.xm8.nsg13_lv_nmos[ids] +.save @n.x1.xm8.nsg13_lv_nmos[gm] +.save @n.x1.xm8.nsg13_lv_nmos[gds] +.save @n.x1.xm8.nsg13_lv_nmos[vth] +.save @n.x1.xm8.nsg13_lv_nmos[vgs] +.save @n.x1.xm8.nsg13_lv_nmos[vdss] +.save @n.x1.xm8.nsg13_lv_nmos[vds] +.save @n.x1.xm8.nsg13_lv_nmos[cgg] +.save @n.x1.xm8.nsg13_lv_nmos[cgsol] +.save @n.x1.xm8.nsg13_lv_nmos[cgdol] +.save @n.x1.xm9.nsg13_lv_nmos[ids] +.save @n.x1.xm9.nsg13_lv_nmos[gm] +.save @n.x1.xm9.nsg13_lv_nmos[gds] +.save @n.x1.xm9.nsg13_lv_nmos[vth] +.save @n.x1.xm9.nsg13_lv_nmos[vgs] +.save @n.x1.xm9.nsg13_lv_nmos[vdss] +.save @n.x1.xm9.nsg13_lv_nmos[vds] +.save @n.x1.xm9.nsg13_lv_nmos[cgg] +.save @n.x1.xm9.nsg13_lv_nmos[cgsol] +.save @n.x1.xm9.nsg13_lv_nmos[cgdol] +.save @n.x1.xm10.nsg13_lv_nmos[ids] +.save @n.x1.xm10.nsg13_lv_nmos[gm] +.save @n.x1.xm10.nsg13_lv_nmos[gds] +.save @n.x1.xm10.nsg13_lv_nmos[vth] +.save @n.x1.xm10.nsg13_lv_nmos[vgs] +.save @n.x1.xm10.nsg13_lv_nmos[vdss] +.save @n.x1.xm10.nsg13_lv_nmos[vds] +.save @n.x1.xm10.nsg13_lv_nmos[cgg] +.save @n.x1.xm10.nsg13_lv_nmos[cgsol] +.save @n.x1.xm10.nsg13_lv_nmos[cgdol] +.save @n.x1.xm11.nsg13_lv_nmos[ids] +.save @n.x1.xm11.nsg13_lv_nmos[gm] +.save @n.x1.xm11.nsg13_lv_nmos[gds] +.save @n.x1.xm11.nsg13_lv_nmos[vth] +.save @n.x1.xm11.nsg13_lv_nmos[vgs] +.save @n.x1.xm11.nsg13_lv_nmos[vdss] +.save @n.x1.xm11.nsg13_lv_nmos[vds] +.save @n.x1.xm11.nsg13_lv_nmos[cgg] +.save @n.x1.xm11.nsg13_lv_nmos[cgsol] +.save @n.x1.xm11.nsg13_lv_nmos[cgdol] +.save @n.x1.xm12.nsg13_lv_nmos[ids] +.save @n.x1.xm12.nsg13_lv_nmos[gm] +.save @n.x1.xm12.nsg13_lv_nmos[gds] +.save @n.x1.xm12.nsg13_lv_nmos[vth] +.save @n.x1.xm12.nsg13_lv_nmos[vgs] +.save @n.x1.xm12.nsg13_lv_nmos[vdss] +.save @n.x1.xm12.nsg13_lv_nmos[vds] +.save @n.x1.xm12.nsg13_lv_nmos[cgg] +.save @n.x1.xm12.nsg13_lv_nmos[cgsol] +.save @n.x1.xm12.nsg13_lv_nmos[cgdol] diff --git a/modules/module_4_type_2_PLL/CML_divider/testbench/xschemrc b/modules/module_4_type_2_PLL/CML_divider/testbench/xschemrc new file mode 100644 index 00000000..34b6db6d --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/testbench/xschemrc @@ -0,0 +1,18 @@ +# xschemrc - Custom configuration file for xschem +# This file sources another xschemrc file from a known location + +# Source the base configuration from a known location +source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc + +# (Optional) Add any custom overrides or extensions below +# set xschem_library_path /home/user/my_libs +# set xschem_gui_font "Monospace 10" + +#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here. +###only if you dont have this setup already ### +###append XSCHEM_LIBRARY_PATH :[file dirname [info script]] + + +#### Add custom libraries (directories with .lib files) +append XSCHEM_LIBRARY_PATH :../xschem/ + diff --git a/modules/module_4_type_2_PLL/CML_divider/xschem/CML_divider.sch b/modules/module_4_type_2_PLL/CML_divider/xschem/CML_divider.sch new file mode 100644 index 00000000..ad08aabc --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/xschem/CML_divider.sch @@ -0,0 +1,263 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 310 -500 310 -440 {lab=#net1} +N 420 -440 530 -440 {lab=#net1} +N 530 -500 530 -440 {lab=#net1} +N 420 -530 530 -530 {lab=gnd} +N 310 -620 310 -560 {lab=#net2} +N 530 -590 530 -560 {lab=#net3} +N 310 -720 310 -690 {lab=vdd} +N 420 -720 530 -720 {lab=vdd} +N 530 -720 530 -690 {lab=vdd} +N 420 -440 420 -410 {lab=#net1} +N 310 -440 420 -440 {lab=#net1} +N 420 -350 420 -320 {lab=#net4} +N 420 -320 730 -320 {lab=#net4} +N 730 -320 730 -280 {lab=#net4} +N 730 -320 1040 -320 {lab=#net4} +N 1040 -350 1040 -320 {lab=#net4} +N 1040 -460 1100 -460 {lab=#net5} +N 1100 -500 1100 -460 {lab=#net5} +N 980 -500 980 -460 {lab=#net5} +N 1040 -460 1040 -410 {lab=#net5} +N 980 -460 1040 -460 {lab=#net5} +N 980 -580 980 -560 {lab=#net3} +N 530 -590 980 -590 {lab=#net3} +N 530 -630 530 -590 {lab=#net3} +N 980 -560 1060 -530 {lab=#net3} +N 1020 -530 1100 -560 {lab=#net2} +N 310 -620 1100 -620 {lab=#net2} +N 310 -630 310 -620 {lab=#net2} +N 1100 -620 1100 -560 {lab=#net2} +N 730 -380 1040 -380 {lab=gnd} +N 730 -380 730 -360 {lab=gnd} +N 420 -380 730 -380 {lab=gnd} +N 420 -530 420 -510 {lab=gnd} +N 310 -530 420 -530 {lab=gnd} +N 360 -380 380 -380 {lab=Vi+} +N 1080 -380 1100 -380 {lab=Vi-} +N 730 -220 730 -180 {lab=gnd} +N 910 -530 980 -530 {lab=gnd} +N 1100 -530 1170 -530 {lab=gnd} +N 420 -740 420 -720 {lab=vdd} +N 310 -720 420 -720 {lab=vdd} +N 1270 -500 1270 -440 {lab=#net6} +N 1380 -440 1490 -440 {lab=#net6} +N 1490 -500 1490 -440 {lab=#net6} +N 1380 -530 1490 -530 {lab=gnd} +N 1270 -620 1270 -560 {lab=Vo-} +N 1490 -590 1490 -560 {lab=Vo+} +N 1270 -720 1270 -690 {lab=vdd} +N 1380 -720 1490 -720 {lab=vdd} +N 1490 -720 1490 -690 {lab=vdd} +N 1380 -440 1380 -410 {lab=#net6} +N 1270 -440 1380 -440 {lab=#net6} +N 1380 -350 1380 -320 {lab=#net7} +N 1380 -320 1690 -320 {lab=#net7} +N 1690 -320 1690 -280 {lab=#net7} +N 1690 -320 2000 -320 {lab=#net7} +N 2000 -350 2000 -320 {lab=#net7} +N 2000 -460 2060 -460 {lab=#net8} +N 2060 -500 2060 -460 {lab=#net8} +N 1940 -500 1940 -460 {lab=#net8} +N 2000 -460 2000 -410 {lab=#net8} +N 1940 -460 2000 -460 {lab=#net8} +N 1490 -590 1940 -590 {lab=Vo+} +N 1490 -630 1490 -590 {lab=Vo+} +N 1940 -560 2020 -530 {lab=Vo+} +N 1980 -530 2060 -560 {lab=Vo-} +N 1270 -620 2060 -620 {lab=Vo-} +N 1270 -630 1270 -620 {lab=Vo-} +N 2060 -620 2060 -560 {lab=Vo-} +N 1690 -380 2000 -380 {lab=gnd} +N 1690 -380 1690 -360 {lab=gnd} +N 1380 -380 1690 -380 {lab=gnd} +N 1380 -530 1380 -510 {lab=gnd} +N 1270 -530 1380 -530 {lab=gnd} +N 1320 -380 1340 -380 {lab=Vi-} +N 2040 -380 2060 -380 {lab=Vi+} +N 1690 -220 1690 -180 {lab=gnd} +N 1870 -530 1940 -530 {lab=gnd} +N 2060 -530 2130 -530 {lab=gnd} +N 1380 -740 1380 -720 {lab=vdd} +N 1270 -720 1380 -720 {lab=vdd} +N 2060 -790 2060 -620 {lab=Vo-} +N 250 -790 2060 -790 {lab=Vo-} +N 250 -460 620 -460 {lab=Vo-} +N 250 -790 250 -460 {lab=Vo-} +N 620 -530 620 -460 {lab=Vo-} +N 570 -530 620 -530 {lab=Vo-} +N 210 -530 270 -530 {lab=Vo+} +N 210 -850 210 -530 {lab=Vo+} +N 210 -850 1940 -850 {lab=Vo+} +N 1940 -590 1940 -560 {lab=Vo+} +N 1940 -850 1940 -590 {lab=Vo+} +N 1100 -620 1230 -620 {lab=#net2} +N 1230 -620 1230 -530 {lab=#net2} +N 980 -580 1530 -580 {lab=#net3} +N 980 -590 980 -580 {lab=#net3} +N 1530 -580 1530 -530 {lab=#net3} +C {sg13g2_pr/sg13_lv_nmos.sym} 290 -530 0 0 {name=M1 +l=0.13u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_nmos.sym} 550 -530 0 1 {name=M2 +l=0.13u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {res.sym} 310 -660 0 0 {name=R1 +value=2.5k +footprint=1206 +device=resistor +m=1} +C {res.sym} 530 -660 0 0 {name=R2 +value=2.5k +footprint=1206 +device=resistor +m=1} +C {sg13g2_pr/sg13_lv_nmos.sym} 400 -380 0 0 {name=M3 +l=0.2u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {isource.sym} 730 -250 0 0 {name=I0 value=200u} +C {sg13g2_pr/sg13_lv_nmos.sym} 1060 -380 0 1 {name=M4 +l=0.2u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_nmos.sym} 1000 -530 0 1 {name=M5 +l=0.13u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_nmos.sym} 1080 -530 0 0 {name=M6 +l=0.13u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {lab_pin.sym} 420 -510 2 0 {name=p1 sig_type=std_logic lab=gnd +} +C {lab_pin.sym} 730 -180 2 0 {name=p3 sig_type=std_logic lab=gnd +} +C {lab_pin.sym} 1170 -530 2 0 {name=p4 sig_type=std_logic lab=gnd +} +C {lab_pin.sym} 910 -530 0 0 {name=p5 sig_type=std_logic lab=gnd +} +C {lab_pin.sym} 360 -380 0 0 {name=p6 sig_type=std_logic lab=Vi+ +} +C {lab_pin.sym} 1100 -380 2 0 {name=p7 sig_type=std_logic lab=Vi- +} +C {lab_pin.sym} 730 -360 2 0 {name=p8 sig_type=std_logic lab=gnd +} +C {lab_pin.sym} 420 -740 2 0 {name=p9 sig_type=std_logic lab=vdd +} +C {sg13g2_pr/sg13_lv_nmos.sym} 1250 -530 0 0 {name=M7 +l=0.13u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_nmos.sym} 1510 -530 0 1 {name=M8 +l=0.13u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {res.sym} 1270 -660 0 0 {name=R3 +value=2.5k +footprint=1206 +device=resistor +m=1} +C {res.sym} 1490 -660 0 0 {name=R4 +value=2.5k +footprint=1206 +device=resistor +m=1} +C {sg13g2_pr/sg13_lv_nmos.sym} 1360 -380 0 0 {name=M9 +l=0.2u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {isource.sym} 1690 -250 0 0 {name=I1 value=200u} +C {sg13g2_pr/sg13_lv_nmos.sym} 2020 -380 0 1 {name=M10 +l=0.2u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_nmos.sym} 1960 -530 0 1 {name=M11 +l=0.13u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {sg13g2_pr/sg13_lv_nmos.sym} 2040 -530 0 0 {name=M12 +l=0.13u +w=2u +ng=1 +m=1 +model=sg13_lv_nmos +spiceprefix=X +} +C {lab_pin.sym} 1380 -510 2 0 {name=p10 sig_type=std_logic lab=gnd +} +C {lab_pin.sym} 1690 -180 2 0 {name=p12 sig_type=std_logic lab=gnd +} +C {lab_pin.sym} 2130 -530 2 0 {name=p13 sig_type=std_logic lab=gnd +} +C {lab_pin.sym} 1870 -530 0 0 {name=p14 sig_type=std_logic lab=gnd +} +C {lab_pin.sym} 1690 -360 2 0 {name=p17 sig_type=std_logic lab=gnd +} +C {lab_pin.sym} 1380 -740 2 0 {name=p18 sig_type=std_logic lab=vdd +} +C {lab_pin.sym} 1320 -380 0 0 {name=p15 sig_type=std_logic lab=Vi- +} +C {lab_pin.sym} 2060 -380 0 1 {name=p16 sig_type=std_logic lab=Vi+ +} +C {lab_pin.sym} 1940 -850 2 0 {name=p19 sig_type=std_logic lab=Vo+ +} +C {lab_pin.sym} 2060 -790 2 0 {name=p20 sig_type=std_logic lab=Vo- +} +C {ipin.sym} 230 -410 0 0 {name=p21 lab=Vi+} +C {ipin.sym} 230 -390 0 0 {name=p22 lab=Vi-} +C {opin.sym} 230 -430 2 0 {name=p23 lab=Vo-} +C {iopin.sym} 230 -370 2 0 {name=p24 lab=vdd} +C {iopin.sym} 230 -350 2 0 {name=p25 lab=gnd} +C {opin.sym} 230 -450 2 0 {name=p26 lab=Vo+} diff --git a/modules/module_4_type_2_PLL/CML_divider/xschem/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/xschem/CML_divider.sym new file mode 100644 index 00000000..f8b5f449 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/xschem/CML_divider.sym @@ -0,0 +1,30 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -20 -100 -20 {} +L 4 -120 20 -100 20 {} +L 4 100 -20 120 -20 {} +L 4 100 20 120 20 {} +L 7 0 -60 0 -40 {} +L 7 0 40 0 60 {} +B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out} +B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out} +B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in} +B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in} +B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout} +B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout} +P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {} +T {@symname} -44 -6 0 0 0.3 0.3 {} +T {@name} 45 -52 0 0 0.2 0.2 {} +T {Vo+} -95 -24 0 0 0.2 0.2 {} +T {Vo-} -95 16 0 0 0.2 0.2 {} +T {Vi+} 95 -16 2 0 0.2 0.2 {} +T {Vi-} 95 24 2 0 0.2 0.2 {} +T {vdd} 10 -39 0 1 0.2 0.2 {} +T {gnd} -10 34 2 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/CML_divider/xschem/xschemrc b/modules/module_4_type_2_PLL/CML_divider/xschem/xschemrc new file mode 100644 index 00000000..14a1e9f2 --- /dev/null +++ b/modules/module_4_type_2_PLL/CML_divider/xschem/xschemrc @@ -0,0 +1,12 @@ +# Source the base configuration from a known location +source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc + +# Add current directory to xschem library path +append XSCHEM_LIBRARY_PATH :[file dirname [info script]] + +# Source the dependencies xschemrc files +foreach rcfile [glob -nocomplain ../ip/*/xschem/xschemrc] { + puts "sourcing $rcfile" + source $rcfile +} + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/cace/differential_oscillator.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/cace/differential_oscillator.yaml new file mode 100644 index 00000000..579a7f72 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/cace/differential_oscillator.yaml @@ -0,0 +1,85 @@ +#-------------------------------------------------------------- +# CACE circuit characterization file +#-------------------------------------------------------------- + +name: diff_ring_oscillator +description: Differential Ring oscillator testbench +PDK: ihp-sg13g2 + +cace_format: 5.2 + +authorship: + designer: + company: + creation_date: + license: Apache 2.0 + +paths: + root: .. + schematic: xschem/ + netlist: xschem/simulations + documentation: docs + +pins: + vdd: + description: Positive analog power supply + type: power + direction: inout + Vmin: 0.8 + Vmax: 1.8 + gnd: + description: Analog ground + type: ground + direction: inout + +default_conditions: + vdd: + description: Analog power supply voltage + display: Vdd + unit: V + typical: 1.2 + corner: + description: Process corner + display: Corner + typical: tt + temperature: + description: Ambient temperature + display: Temp + unit: °C + typical: 27 + +parameters: + Frequency: + description: Analysing the frequency of the oscillator + display: Freq + unit: GHz + spec: + frequency: + minimum: + value: 4.2 + typical: + value: 5.4 + maximum: + value: 7.1 + tool: + ngspice: + template: diff_oscillator_tb.sch + format: ascii + suffix: .data + variables: [time_axis, vo_diff] + script: freq.py + script_variables: [frequency] + + plot: + frequency: + xaxis: time_axis + yaxis: vo_diff + conditions: + vdd: + typical: 1.2 + temperature: + typical: 27 + corner: + typical: tt + + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/cace/scripts/__pycache__/freq.cpython-310.pyc b/modules/module_4_type_2_PLL/diff_Roscillator/cace/scripts/__pycache__/freq.cpython-310.pyc new file mode 100644 index 00000000..c822efd5 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/cace/scripts/__pycache__/freq.cpython-310.pyc differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/cace/scripts/freq.py b/modules/module_4_type_2_PLL/diff_Roscillator/cace/scripts/freq.py new file mode 100644 index 00000000..1014da4a --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/cace/scripts/freq.py @@ -0,0 +1,30 @@ +from typing import Any +import numpy as np + +def postprocess(results: dict[str, list], conditions: dict[str, Any]) -> dict[str, list]: + # Extract waveform + t = np.array(results['time_axis']) + y = np.array(results['vo_diff']) + + if len(y) == 0: + # Fallback if waveform is empty + return {'frequency': [0.0]} + + dt = np.mean(np.diff(t)) + fs = 1 / dt + + # FFT + Y = np.fft.fft(y - np.mean(y)) # remove DC + freqs = np.fft.fftfreq(len(Y), d=dt) + + # Only positive frequencies + mask = freqs > 0 + freqs = freqs[mask] + Y = np.abs(Y[mask]) + + # Find frequency with maximum magnitude + freq_peak = freqs[np.argmax(Y)] # convert to GHz + + + # Return as a list for compatibility with sweep/postprocessing tools + return {'frequency': [freq_peak]} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/cace/templates/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/cace/templates/diff_oscillator_tb.sch new file mode 100644 index 00000000..8b2e4f89 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/cace/templates/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n 160p + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/cace/templates/xschemrc b/modules/module_4_type_2_PLL/diff_Roscillator/cace/templates/xschemrc new file mode 100644 index 00000000..88fd1465 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/cace/templates/xschemrc @@ -0,0 +1,18 @@ +# xschemrc - Custom configuration file for xschem +# This file sources another xschemrc file from a known location + +# Source the base configuration from a known location +source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc + +# (Optional) Add any custom overrides or extensions below +# set xschem_library_path /home/user/my_libs +# set xschem_gui_font "Monospace 10" + +#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here. +###only if you dont have this setup already ### +###append XSCHEM_LIBRARY_PATH :[file dirname [info script]] + + +#### Add custom libraries (directories with .lib files) +append XSCHEM_LIBRARY_PATH :../../xschem/ + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator.md b/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator.md new file mode 100644 index 00000000..43b5c6fd --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator.md @@ -0,0 +1,50 @@ +# diff_ring_oscillator + +- Description: Differential Ring oscillator testbench +- PDK: ihp-sg13g2 + +## Authorship + +- Designer: None +- Company: None +- Created: None +- License: Apache 2.0 +- Last modified: None + +## Pins + +- vdd + + Description: Positive analog power supply + + Type: power + + Direction: inout + + Vmin: 0.8 + + Vmax: 1.8 +- gnd + + Description: Analog ground + + Type: ground + + Direction: inout + +## Default Conditions + +- vdd + + Description: Analog power supply voltage + + Display: Vdd + + Unit: V + + Typical: 1.2 +- corner + + Description: Process corner + + Display: Corner + + Typical: tt +- temperature + + Description: Ambient temperature + + Display: Temp + + Unit: °C + + Typical: 27 + +## Symbol + +![Symbol of diff_ring_oscillator](diff_ring_oscillator_symbol.svg) + +## Schematic + +![Schematic of diff_ring_oscillator](diff_ring_oscillator_schematic.svg) diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator/schematic/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator/schematic/frequency.png new file mode 100644 index 00000000..d2bd4121 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator/schematic/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator_schematic.md b/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator_schematic.md new file mode 100644 index 00000000..b83728f3 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator_schematic.md @@ -0,0 +1,15 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.2 GHz | 5.414 GHz | 5.4 GHz | 5.414 GHz | 7.1 GHz | 5.414 GHz | Pass ✅ | + + +## Plots + +## frequency + +![frequency](./diff_ring_oscillator/schematic/frequency.png) diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator_schematic.svg b/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator_schematic.svg new file mode 100644 index 00000000..5de9a6fa --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator_schematic.svg @@ -0,0 +1,160 @@ + + + + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator_symbol.svg b/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator_symbol.svg new file mode 100644 index 00000000..5de9a6fa --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/docs/diff_ring_oscillator_symbol.svg @@ -0,0 +1,160 @@ + + + + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..8007d3ee --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,42 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=#net1} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 0 -840 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +.ic V(Voplus)=1.2 +.control +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n +save all +let vo_diff = v(Voplus) - v(Vominus) +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data V(vo_diff) +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/frequency.png new file mode 100644 index 00000000..f8b9f9a1 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..8eb2ce14 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..36d01301 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,42 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=#net1} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 0 -840 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +.ic V(Voplus)=1.2 +.control +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n +save all +let vo_diff = v(Voplus) - v(Vominus) +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/diff_oscillator_tb_0.data V(vo_diff) +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..fbaae6a4 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,208 @@ + 0.00000000e+00 1.50149049e+00 + 1.00000000e-13 1.49305933e+00 + 2.00000000e-13 1.48762993e+00 + 4.00000000e-13 1.47835377e+00 + 8.00000000e-13 1.46164680e+00 + 1.60000000e-12 1.42856559e+00 + 3.20000000e-12 1.36698463e+00 + 6.40000000e-12 1.25782460e+00 + 1.28000000e-11 1.08329184e+00 + 2.28000000e-11 8.71035493e-01 + 3.28000000e-11 7.01254834e-01 + 4.28000000e-11 5.69268666e-01 + 5.28000000e-11 4.67472873e-01 + 6.28000000e-11 3.88133688e-01 + 7.28000000e-11 3.25963336e-01 + 8.28000000e-11 2.75833402e-01 + 9.28000000e-11 2.35272475e-01 + 1.02800000e-10 2.01449017e-01 + 1.12800000e-10 1.72976489e-01 + 1.22800000e-10 1.48257979e-01 + 1.32800000e-10 1.26851615e-01 + 1.42800000e-10 1.07852737e-01 + 1.52800000e-10 9.13049778e-02 + 1.62800000e-10 7.66490286e-02 + 1.72800000e-10 6.40805814e-02 + 1.82800000e-10 5.31111453e-02 + 1.92800000e-10 4.39141630e-02 + 2.02800000e-10 3.59896484e-02 + 2.12800000e-10 2.94857246e-02 + 2.22800000e-10 2.39196602e-02 + 2.32800000e-10 1.94468223e-02 + 2.42800000e-10 1.56224285e-02 + 2.52800000e-10 1.26211750e-02 + 2.62800000e-10 1.00396496e-02 + 2.72800000e-10 8.07228591e-03 + 2.82800000e-10 6.35363179e-03 + 2.92800000e-10 5.09412630e-03 + 3.02800000e-10 3.96077425e-03 + 3.12800000e-10 3.17515852e-03 + 3.22800000e-10 2.43103839e-03 + 3.32800000e-10 1.95645853e-03 + 3.42800000e-10 1.46686012e-03 + 3.52800000e-10 1.19281616e-03 + 3.62800000e-10 8.67310196e-04 + 3.72800000e-10 7.20419269e-04 + 3.82800000e-10 4.99475012e-04 + 3.92800000e-10 4.31886194e-04 + 4.02800000e-10 2.76956531e-04 + 4.12800000e-10 2.57956889e-04 + 4.22800000e-10 1.44433763e-04 + 4.32800000e-10 1.54585536e-04 + 4.42800000e-10 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-4.21690894e-06 + 1.67280000e-09 4.15604313e-06 + 1.68280000e-09 -4.09729707e-06 + 1.69280000e-09 4.03823423e-06 + 1.70280000e-09 -3.98120084e-06 + 1.71280000e-09 3.92388436e-06 + 1.72280000e-09 -3.86851124e-06 + 1.73280000e-09 3.81288648e-06 + 1.74280000e-09 -3.75912291e-06 + 1.75280000e-09 3.70513701e-06 + 1.76280000e-09 -3.65293401e-06 + 1.77280000e-09 3.60053592e-06 + 1.78280000e-09 -3.54984600e-06 + 1.79280000e-09 3.49898643e-06 + 1.80280000e-09 -3.44976368e-06 + 1.81280000e-09 3.40039490e-06 + 1.82280000e-09 -3.35259493e-06 + 1.83280000e-09 3.30467088e-06 + 1.84280000e-09 -3.25825066e-06 + 1.85280000e-09 3.21172679e-06 + 1.86280000e-09 -3.16664472e-06 + 1.87280000e-09 3.12147793e-06 + 1.88280000e-09 -3.07769371e-06 + 1.89280000e-09 3.03384239e-06 + 1.90280000e-09 -2.99131704e-06 + 1.91280000e-09 2.94874091e-06 + 1.92280000e-09 -2.90743663e-06 + 1.93280000e-09 2.86609674e-06 + 1.94280000e-09 -2.82597704e-06 + 1.95280000e-09 2.78583567e-06 + 1.96280000e-09 -2.74686516e-06 + 1.97280000e-09 2.70788585e-06 + 1.98280000e-09 -2.67003028e-06 + 1.99280000e-09 2.63217780e-06 + 2.00000000e-09 -2.57652890e-06 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..f0e1ddca --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[0.000, 1.000e-13, 2.000e-13, …]","[1.501, 1.493, 1.488, …]",4.976e+08 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..fba78079 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [0.000, 1.000e-13, 2.000e-13, …] | [1.501, 1.493, 1.488, …] | 4.976e+08 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/summary.md new file mode 100644 index 00000000..13a3fa51 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-36-06/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | any | 0.498 GHz | any | 0.498 GHz | any | 0.498 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..35552a14 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,42 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 0 -840 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +.ic V(Voplus)=1.2 +.control +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n +save all +let vo_diff = v(Voplus) - v(Vominus) +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/frequency.png new file mode 100644 index 00000000..f8b9f9a1 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..e9db1781 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..94bdb520 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,42 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 0 -840 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +.ic V(Voplus)=1.2 +.control +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n +save all +let vo_diff = v(Voplus) - v(Vominus) +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..fbaae6a4 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,208 @@ + 0.00000000e+00 1.50149049e+00 + 1.00000000e-13 1.49305933e+00 + 2.00000000e-13 1.48762993e+00 + 4.00000000e-13 1.47835377e+00 + 8.00000000e-13 1.46164680e+00 + 1.60000000e-12 1.42856559e+00 + 3.20000000e-12 1.36698463e+00 + 6.40000000e-12 1.25782460e+00 + 1.28000000e-11 1.08329184e+00 + 2.28000000e-11 8.71035493e-01 + 3.28000000e-11 7.01254834e-01 + 4.28000000e-11 5.69268666e-01 + 5.28000000e-11 4.67472873e-01 + 6.28000000e-11 3.88133688e-01 + 7.28000000e-11 3.25963336e-01 + 8.28000000e-11 2.75833402e-01 + 9.28000000e-11 2.35272475e-01 + 1.02800000e-10 2.01449017e-01 + 1.12800000e-10 1.72976489e-01 + 1.22800000e-10 1.48257979e-01 + 1.32800000e-10 1.26851615e-01 + 1.42800000e-10 1.07852737e-01 + 1.52800000e-10 9.13049778e-02 + 1.62800000e-10 7.66490286e-02 + 1.72800000e-10 6.40805814e-02 + 1.82800000e-10 5.31111453e-02 + 1.92800000e-10 4.39141630e-02 + 2.02800000e-10 3.59896484e-02 + 2.12800000e-10 2.94857246e-02 + 2.22800000e-10 2.39196602e-02 + 2.32800000e-10 1.94468223e-02 + 2.42800000e-10 1.56224285e-02 + 2.52800000e-10 1.26211750e-02 + 2.62800000e-10 1.00396496e-02 + 2.72800000e-10 8.07228591e-03 + 2.82800000e-10 6.35363179e-03 + 2.92800000e-10 5.09412630e-03 + 3.02800000e-10 3.96077425e-03 + 3.12800000e-10 3.17515852e-03 + 3.22800000e-10 2.43103839e-03 + 3.32800000e-10 1.95645853e-03 + 3.42800000e-10 1.46686012e-03 + 3.52800000e-10 1.19281616e-03 + 3.62800000e-10 8.67310196e-04 + 3.72800000e-10 7.20419269e-04 + 3.82800000e-10 4.99475012e-04 + 3.92800000e-10 4.31886194e-04 + 4.02800000e-10 2.76956531e-04 + 4.12800000e-10 2.57956889e-04 + 4.22800000e-10 1.44433763e-04 + 4.32800000e-10 1.54585536e-04 + 4.42800000e-10 6.69535287e-05 + 4.52800000e-10 9.41142808e-05 + 4.62800000e-10 2.26996257e-05 + 4.72800000e-10 5.93807102e-05 + 4.82800000e-10 -1.78612241e-06 + 4.92800000e-10 3.98585351e-05 + 5.02800000e-10 -1.47083610e-05 + 5.12800000e-10 2.91690709e-05 + 5.22800000e-10 -2.10064243e-05 + 5.32800000e-10 2.34975240e-05 + 5.42800000e-10 -2.36122120e-05 + 5.52800000e-10 2.05966110e-05 + 5.62800000e-10 -2.42373428e-05 + 5.72800000e-10 1.91662809e-05 + 5.82800000e-10 -2.38606720e-05 + 5.92800000e-10 1.84715158e-05 + 6.02800000e-10 -2.30271287e-05 + 6.12800000e-10 1.81092938e-05 + 6.22800000e-10 -2.20289175e-05 + 6.32800000e-10 1.78681053e-05 + 6.42800000e-10 -2.10140792e-05 + 6.52800000e-10 1.76443427e-05 + 6.62800000e-10 -2.00506354e-05 + 6.72800000e-10 1.73932875e-05 + 6.82800000e-10 -1.91638592e-05 + 6.92800000e-10 1.71009105e-05 + 7.02800000e-10 -1.83574797e-05 + 7.12800000e-10 1.67680328e-05 + 7.22800000e-10 -1.76254120e-05 + 7.32800000e-10 1.64017176e-05 + 7.42800000e-10 -1.69579955e-05 + 7.52800000e-10 1.60108123e-05 + 7.62800000e-10 -1.63451157e-05 + 7.72800000e-10 1.56038138e-05 + 7.82800000e-10 -1.57776080e-05 + 7.92800000e-10 1.51879916e-05 + 8.02800000e-10 -1.52477524e-05 + 8.12800000e-10 1.47691590e-05 + 8.22800000e-10 -1.47493166e-05 + 8.32800000e-10 1.43517499e-05 + 8.42800000e-10 -1.42773992e-05 + 8.52800000e-10 1.39390192e-05 + 8.62800000e-10 -1.38282052e-05 + 8.72800000e-10 1.35332720e-05 + 8.82800000e-10 -1.33988187e-05 + 8.92800000e-10 1.31360780e-05 + 9.02800000e-10 -1.29870020e-05 + 9.12800000e-10 1.27484537e-05 + 9.22800000e-10 -1.25910299e-05 + 9.32800000e-10 1.23710090e-05 + 9.42800000e-10 -1.22095585e-05 + 9.52800000e-10 1.20040604e-05 + 9.62800000e-10 -1.18415246e-05 + 9.72800000e-10 1.16477172e-05 + 9.82800000e-10 -1.14860712e-05 + 9.92800000e-10 1.13019442e-05 + 1.00280000e-09 -1.11424911e-05 + 1.01280000e-09 1.09666084e-05 + 1.02280000e-09 -1.08101874e-05 + 1.03280000e-09 1.06415116e-05 + 1.04280000e-09 -1.04886439e-05 + 1.05280000e-09 1.03264143e-05 + 1.06280000e-09 -1.01774042e-05 + 1.07280000e-09 1.00210517e-05 + 1.08280000e-09 -9.87605735e-06 + 1.09280000e-09 9.72514526e-06 + 1.10280000e-09 -9.58422695e-06 + 1.11280000e-09 9.43841071e-06 + 1.12280000e-09 -9.30156383e-06 + 1.13280000e-09 9.16056303e-06 + 1.14280000e-09 -9.02774079e-06 + 1.15280000e-09 8.89132013e-06 + 1.16280000e-09 -8.76244881e-06 + 1.17280000e-09 8.63040506e-06 + 1.18280000e-09 -8.50539433e-06 + 1.19280000e-09 8.37754749e-06 + 1.20280000e-09 -8.25629736e-06 + 1.21280000e-09 8.13248451e-06 + 1.22280000e-09 -8.01488990e-06 + 1.23280000e-09 7.89496117e-06 + 1.24280000e-09 -7.78091494e-06 + 1.25280000e-09 7.66473063e-06 + 1.26280000e-09 -7.55412554e-06 + 1.27280000e-09 7.44155422e-06 + 1.28280000e-09 -7.33428425e-06 + 1.29280000e-09 7.22520127e-06 + 1.30280000e-09 -7.12116247e-06 + 1.31280000e-09 7.01544909e-06 + 1.32280000e-09 -6.91453993e-06 + 1.33280000e-09 6.81208267e-06 + 1.34280000e-09 -6.71420446e-06 + 1.35280000e-09 6.61489446e-06 + 1.36280000e-09 -6.51995139e-06 + 1.37280000e-09 6.42368417e-06 + 1.38280000e-09 -6.33158344e-06 + 1.39280000e-09 6.23825850e-06 + 1.40280000e-09 -6.14891024e-06 + 1.41280000e-09 6.05843085e-06 + 1.42280000e-09 -5.97174817e-06 + 1.43280000e-09 5.88402118e-06 + 1.44280000e-09 -5.79992000e-06 + 1.45280000e-09 5.71485565e-06 + 1.46280000e-09 -5.63325474e-06 + 1.47280000e-09 5.55076647e-06 + 1.48280000e-09 -5.47158728e-06 + 1.49280000e-09 5.39159165e-06 + 1.50280000e-09 -5.31475827e-06 + 1.51280000e-09 5.23717479e-06 + 1.52280000e-09 -5.16261385e-06 + 1.53280000e-09 5.08736485e-06 + 1.54280000e-09 -5.01500544e-06 + 1.55280000e-09 4.94201599e-06 + 1.56280000e-09 -4.87178954e-06 + 1.57280000e-09 4.80098734e-06 + 1.58280000e-09 -4.73282758e-06 + 1.59280000e-09 4.66414285e-06 + 1.60280000e-09 -4.59798569e-06 + 1.61280000e-09 4.53135104e-06 + 1.62280000e-09 -4.46713454e-06 + 1.63280000e-09 4.40248494e-06 + 1.64280000e-09 -4.34014921e-06 + 1.65280000e-09 4.27742183e-06 + 1.66280000e-09 -4.21690894e-06 + 1.67280000e-09 4.15604313e-06 + 1.68280000e-09 -4.09729707e-06 + 1.69280000e-09 4.03823423e-06 + 1.70280000e-09 -3.98120084e-06 + 1.71280000e-09 3.92388436e-06 + 1.72280000e-09 -3.86851124e-06 + 1.73280000e-09 3.81288648e-06 + 1.74280000e-09 -3.75912291e-06 + 1.75280000e-09 3.70513701e-06 + 1.76280000e-09 -3.65293401e-06 + 1.77280000e-09 3.60053592e-06 + 1.78280000e-09 -3.54984600e-06 + 1.79280000e-09 3.49898643e-06 + 1.80280000e-09 -3.44976368e-06 + 1.81280000e-09 3.40039490e-06 + 1.82280000e-09 -3.35259493e-06 + 1.83280000e-09 3.30467088e-06 + 1.84280000e-09 -3.25825066e-06 + 1.85280000e-09 3.21172679e-06 + 1.86280000e-09 -3.16664472e-06 + 1.87280000e-09 3.12147793e-06 + 1.88280000e-09 -3.07769371e-06 + 1.89280000e-09 3.03384239e-06 + 1.90280000e-09 -2.99131704e-06 + 1.91280000e-09 2.94874091e-06 + 1.92280000e-09 -2.90743663e-06 + 1.93280000e-09 2.86609674e-06 + 1.94280000e-09 -2.82597704e-06 + 1.95280000e-09 2.78583567e-06 + 1.96280000e-09 -2.74686516e-06 + 1.97280000e-09 2.70788585e-06 + 1.98280000e-09 -2.67003028e-06 + 1.99280000e-09 2.63217780e-06 + 2.00000000e-09 -2.57652890e-06 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..f0e1ddca --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[0.000, 1.000e-13, 2.000e-13, …]","[1.501, 1.493, 1.488, …]",4.976e+08 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..fba78079 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [0.000, 1.000e-13, 2.000e-13, …] | [1.501, 1.493, 1.488, …] | 4.976e+08 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/summary.md new file mode 100644 index 00000000..13a3fa51 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-53-50/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | any | 0.498 GHz | any | 0.498 GHz | any | 0.498 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..7a5b911e --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,42 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 0 -840 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +.ic V(Voplus)=1.2 +.control +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n +save all +let vo_diff = v(Vominus) +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/frequency.png new file mode 100644 index 00000000..98cf514e Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..8b95e613 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..b9a76f33 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,42 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 0 -840 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +.ic V(Voplus)=1.2 +.control +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n +save all +let vo_diff = v(Vominus) +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..94a10bb1 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,208 @@ + 0.00000000e+00 -3.01490490e-01 + 1.00000000e-13 -3.02202826e-01 + 2.00000000e-13 -3.03217377e-01 + 4.00000000e-13 -3.05487354e-01 + 8.00000000e-13 -3.10275218e-01 + 1.60000000e-12 -3.19403583e-01 + 3.20000000e-12 -3.36524442e-01 + 6.40000000e-12 -3.64521958e-01 + 1.28000000e-11 -3.98981227e-01 + 2.28000000e-11 -4.43228477e-01 + 3.28000000e-11 -4.93037785e-01 + 4.28000000e-11 -5.39656031e-01 + 5.28000000e-11 -5.82569960e-01 + 6.28000000e-11 -6.19247599e-01 + 7.28000000e-11 -6.50724716e-01 + 8.28000000e-11 -6.75840014e-01 + 9.28000000e-11 -6.95891563e-01 + 1.02800000e-10 -7.11431033e-01 + 1.12800000e-10 -7.23499559e-01 + 1.22800000e-10 -7.32486459e-01 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1.93280000e-09 -7.68904599e-01 + 1.94280000e-09 -7.68905596e-01 + 1.95280000e-09 -7.68904602e-01 + 1.96280000e-09 -7.68905593e-01 + 1.97280000e-09 -7.68904606e-01 + 1.98280000e-09 -7.68905590e-01 + 1.99280000e-09 -7.68904609e-01 + 2.00000000e-09 -7.68905584e-01 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..acee6e8f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[0.000, 1.000e-13, 2.000e-13, …]","[-3.015e-01, -3.022e-01, -3.032e-01, …]",4.976e+08 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..dc805474 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [0.000, 1.000e-13, 2.000e-13, …] | [-3.015e-01, -3.022e-01, -3.032e-01, …] | 4.976e+08 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/summary.md new file mode 100644 index 00000000..13a3fa51 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_14-54-56/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | any | 0.498 GHz | any | 0.498 GHz | any | 0.498 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..8fa9c421 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,61 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 50 -1230 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters +.include diff_oscillator_tb.save + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..ae3cb591 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..8070d016 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,61 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 50 -1230 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters +.include diff_oscillator_tb.save + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/debug_0.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/summary.md new file mode 100644 index 00000000..6072c5cc --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-40/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | any | ​ | any | ​ | any | ​ | Error ❗ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..5c9d54d2 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,60 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 50 -1230 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/frequency.png new file mode 100644 index 00000000..f8b9f9a1 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..f855aa1f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..a8e9d5b2 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,60 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 50 -1230 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/debug_0.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..4a0b5ac2 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,208 @@ + 0.000000000000e+00 1.501490489952e+00 + 1.000000000000e-13 1.493059332822e+00 + 2.000000000000e-13 1.487629932209e+00 + 4.000000000000e-13 1.478353768016e+00 + 8.000000000000e-13 1.461646802601e+00 + 1.600000000000e-12 1.428565592219e+00 + 3.200000000000e-12 1.366984627607e+00 + 6.400000000000e-12 1.257824602026e+00 + 1.280000000000e-11 1.083291838740e+00 + 2.280000000000e-11 8.710354931983e-01 + 3.280000000000e-11 7.012548342612e-01 + 4.280000000000e-11 5.692686657539e-01 + 5.280000000000e-11 4.674728734214e-01 + 6.280000000000e-11 3.881336879207e-01 + 7.280000000000e-11 3.259633362701e-01 + 8.280000000000e-11 2.758334023214e-01 + 9.280000000000e-11 2.352724747795e-01 + 1.028000000000e-10 2.014490165507e-01 + 1.128000000000e-10 1.729764887031e-01 + 1.228000000000e-10 1.482579790988e-01 + 1.328000000000e-10 1.268516151810e-01 + 1.428000000000e-10 1.078527366224e-01 + 1.528000000000e-10 9.130497780307e-02 + 1.628000000000e-10 7.664902855206e-02 + 1.728000000000e-10 6.408058136449e-02 + 1.828000000000e-10 5.311114526166e-02 + 1.928000000000e-10 4.391416298544e-02 + 2.028000000000e-10 3.598964843066e-02 + 2.128000000000e-10 2.948572457647e-02 + 2.228000000000e-10 2.391966019122e-02 + 2.328000000000e-10 1.944682229659e-02 + 2.428000000000e-10 1.562242854644e-02 + 2.528000000000e-10 1.262117501377e-02 + 2.628000000000e-10 1.003964957631e-02 + 2.728000000000e-10 8.072285909579e-03 + 2.828000000000e-10 6.353631794527e-03 + 2.928000000000e-10 5.094126301006e-03 + 3.028000000000e-10 3.960774252123e-03 + 3.128000000000e-10 3.175158522702e-03 + 3.228000000000e-10 2.431038392751e-03 + 3.328000000000e-10 1.956458525826e-03 + 3.428000000000e-10 1.466860117281e-03 + 3.528000000000e-10 1.192816155690e-03 + 3.628000000000e-10 8.673101959982e-04 + 3.728000000000e-10 7.204192692291e-04 + 3.828000000000e-10 4.994750120545e-04 + 3.928000000000e-10 4.318861942222e-04 + 4.028000000000e-10 2.769565308169e-04 + 4.128000000000e-10 2.579568886254e-04 + 4.228000000000e-10 1.444337625361e-04 + 4.328000000000e-10 1.545855356601e-04 + 4.428000000000e-10 6.695352871566e-05 + 4.528000000000e-10 9.411428076378e-05 + 4.628000000000e-10 2.269962569268e-05 + 4.728000000000e-10 5.938071020783e-05 + 4.828000000000e-10 -1.786122408753e-06 + 4.928000000000e-10 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7.428000000000e-10 -1.695799551626e-05 + 7.528000000000e-10 1.601081233293e-05 + 7.628000000000e-10 -1.634511571857e-05 + 7.728000000000e-10 1.560381375043e-05 + 7.828000000000e-10 -1.577760799520e-05 + 7.928000000000e-10 1.518799157274e-05 + 8.028000000000e-10 -1.524775235184e-05 + 8.128000000000e-10 1.476915897591e-05 + 8.228000000000e-10 -1.474931656797e-05 + 8.328000000000e-10 1.435174987197e-05 + 8.428000000000e-10 -1.427739921545e-05 + 8.528000000000e-10 1.393901916680e-05 + 8.628000000000e-10 -1.382820520168e-05 + 8.728000000000e-10 1.353327195985e-05 + 8.828000000000e-10 -1.339881866980e-05 + 8.928000000000e-10 1.313607799325e-05 + 9.028000000000e-10 -1.298700201535e-05 + 9.128000000000e-10 1.274845373045e-05 + 9.228000000000e-10 -1.259102994633e-05 + 9.328000000000e-10 1.237100900031e-05 + 9.428000000000e-10 -1.220955849468e-05 + 9.528000000000e-10 1.200406044899e-05 + 9.628000000000e-10 -1.184152464995e-05 + 9.728000000000e-10 1.164771719997e-05 + 9.828000000000e-10 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1.722800000000e-09 -3.868511237570e-06 + 1.732800000000e-09 3.812886476329e-06 + 1.742800000000e-09 -3.759122911395e-06 + 1.752800000000e-09 3.705137014531e-06 + 1.762800000000e-09 -3.652934007503e-06 + 1.772800000000e-09 3.600535924630e-06 + 1.782800000000e-09 -3.549846003148e-06 + 1.792800000000e-09 3.498986428596e-06 + 1.802800000000e-09 -3.449763679053e-06 + 1.812800000000e-09 3.400394904207e-06 + 1.822800000000e-09 -3.352594933781e-06 + 1.832800000000e-09 3.304670882387e-06 + 1.842800000000e-09 -3.258250656057e-06 + 1.852800000000e-09 3.211726785857e-06 + 1.862800000000e-09 -3.166644716113e-06 + 1.872800000000e-09 3.121477931800e-06 + 1.882800000000e-09 -3.077693713549e-06 + 1.892800000000e-09 3.033842391531e-06 + 1.902800000000e-09 -2.991317038625e-06 + 1.912800000000e-09 2.948740905895e-06 + 1.922800000000e-09 -2.907436633337e-06 + 1.932800000000e-09 2.866096736276e-06 + 1.942800000000e-09 -2.825977035048e-06 + 1.952800000000e-09 2.785835670593e-06 + 1.962800000000e-09 -2.746865162440e-06 + 1.972800000000e-09 2.707885854991e-06 + 1.982800000000e-09 -2.670030278207e-06 + 1.992800000000e-09 2.632177803608e-06 + 2.000000000000e-09 -2.576528895126e-06 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..f0e1ddca --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[0.000, 1.000e-13, 2.000e-13, …]","[1.501, 1.493, 1.488, …]",4.976e+08 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..fba78079 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [0.000, 1.000e-13, 2.000e-13, …] | [1.501, 1.493, 1.488, …] | 4.976e+08 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/summary.md new file mode 100644 index 00000000..13a3fa51 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-04-51/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | any | 0.498 GHz | any | 0.498 GHz | any | 0.498 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..2816ca3f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/frequency.png new file mode 100644 index 00000000..50dc9b77 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..db3e0bb8 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..a110c9f0 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/debug_0.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..55aad520 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,208 @@ + 0.000000000000e+00 6.337866790587e-02 + 1.000000000000e-13 5.977070129326e-02 + 2.000000000000e-13 5.737010752555e-02 + 4.000000000000e-13 5.321759247257e-02 + 8.000000000000e-13 4.572726454202e-02 + 1.600000000000e-12 3.110636852241e-02 + 3.200000000000e-12 4.261647382150e-03 + 6.400000000000e-12 -4.367747947467e-02 + 1.280000000000e-11 -1.262652366305e-01 + 2.280000000000e-11 -2.340996284945e-01 + 3.280000000000e-11 -3.130989756157e-01 + 4.280000000000e-11 -3.432505429806e-01 + 5.280000000000e-11 -3.012854887225e-01 + 6.280000000000e-11 -1.904316905848e-01 + 7.280000000000e-11 -4.073682199355e-02 + 8.280000000000e-11 1.139505637115e-01 + 9.280000000000e-11 2.545516769294e-01 + 1.028000000000e-10 3.797066846222e-01 + 1.128000000000e-10 4.904124358963e-01 + 1.228000000000e-10 5.415988913067e-01 + 1.328000000000e-10 4.823039600532e-01 + 1.428000000000e-10 3.286487398132e-01 + 1.528000000000e-10 1.494333187522e-01 + 1.628000000000e-10 -2.292252894521e-02 + 1.728000000000e-10 -1.721878995476e-01 + 1.828000000000e-10 -3.003971530482e-01 + 1.928000000000e-10 -4.209827688535e-01 + 2.028000000000e-10 -5.322027853128e-01 + 2.128000000000e-10 -5.791583227387e-01 + 2.228000000000e-10 -5.110033194175e-01 + 2.328000000000e-10 -3.457576287601e-01 + 2.428000000000e-10 -1.607196798900e-01 + 2.528000000000e-10 1.365547887835e-02 + 2.628000000000e-10 1.638016925338e-01 + 2.728000000000e-10 2.919305498126e-01 + 2.828000000000e-10 4.124239288433e-01 + 2.928000000000e-10 5.263166298848e-01 + 3.028000000000e-10 5.824106149717e-01 + 3.128000000000e-10 5.252174273130e-01 + 3.228000000000e-10 3.651459872532e-01 + 3.328000000000e-10 1.795084214438e-01 + 3.428000000000e-10 3.226267600252e-03 + 3.528000000000e-10 -1.496702035742e-01 + 3.628000000000e-10 -2.792887178681e-01 + 3.728000000000e-10 -4.000019021719e-01 + 3.828000000000e-10 -5.160190704246e-01 + 3.928000000000e-10 -5.816500208715e-01 + 4.028000000000e-10 -5.372846837038e-01 + 4.128000000000e-10 -3.848834507397e-01 + 4.228000000000e-10 -1.993014483184e-01 + 4.328000000000e-10 -2.125168120944e-02 + 4.428000000000e-10 1.345897939599e-01 + 4.528000000000e-10 2.660516467047e-01 + 4.628000000000e-10 3.871267719337e-01 + 4.728000000000e-10 5.047282820024e-01 + 4.828000000000e-10 5.793062880329e-01 + 4.928000000000e-10 5.480670992790e-01 + 5.028000000000e-10 4.046247574272e-01 + 5.128000000000e-10 2.194567139019e-01 + 5.228000000000e-10 3.978854030163e-02 + 5.328000000000e-10 -1.190134240033e-01 + 5.428000000000e-10 -2.525512770557e-01 + 5.528000000000e-10 -3.741228468393e-01 + 5.628000000000e-10 -4.927999203803e-01 + 5.728000000000e-10 -5.755235861382e-01 + 5.828000000000e-10 -5.574109039140e-01 + 5.928000000000e-10 -4.240101965476e-01 + 6.028000000000e-10 -2.397070733991e-01 + 6.128000000000e-10 -5.859311656156e-02 + 6.228000000000e-10 1.031069489747e-01 + 6.328000000000e-10 2.389202178782e-01 + 6.428000000000e-10 3.611164053835e-01 + 6.528000000000e-10 4.804511503358e-01 + 6.628000000000e-10 5.703927182427e-01 + 6.728000000000e-10 5.651995411624e-01 + 6.828000000000e-10 4.426884649777e-01 + 6.928000000000e-10 2.598493744117e-01 + 7.028000000000e-10 7.747657769560e-02 + 7.128000000000e-10 -8.699618736653e-02 + 7.228000000000e-10 -2.252447884331e-01 + 7.328000000000e-10 -3.481970680463e-01 + 7.428000000000e-10 -4.678842164117e-01 + 7.528000000000e-10 -5.640875390474e-01 + 7.628000000000e-10 -5.714336476059e-01 + 7.728000000000e-10 -4.604185473907e-01 + 7.828000000000e-10 -2.797750138125e-01 + 7.928000000000e-10 -9.633858138806e-02 + 8.028000000000e-10 7.073777814255e-02 + 8.128000000000e-10 2.115493094061e-01 + 8.228000000000e-10 3.353876046363e-01 + 8.328000000000e-10 4.552524923411e-01 + 8.428000000000e-10 5.567938616314e-01 + 8.528000000000e-10 5.762058661922e-01 + 8.628000000000e-10 4.770908355033e-01 + 8.728000000000e-10 2.994880974607e-01 + 8.828000000000e-10 1.151828864331e-01 + 8.928000000000e-10 -5.431208395594e-02 + 9.028000000000e-10 -1.977861602727e-01 + 9.128000000000e-10 -3.226531529049e-01 + 9.228000000000e-10 -4.427347421602e-01 + 9.328000000000e-10 -5.488327643130e-01 + 9.428000000000e-10 -5.797041909504e-01 + 9.528000000000e-10 -4.927265308101e-01 + 9.628000000000e-10 -3.191097454976e-01 + 9.728000000000e-10 -1.342181141771e-01 + 9.828000000000e-10 3.744993884902e-02 + 9.928000000000e-10 1.836370942174e-01 + 1.002800000000e-09 3.096940812427e-01 + 1.012800000000e-09 4.298817640101e-01 + 1.022800000000e-09 5.397599749883e-01 + 1.032800000000e-09 5.817861936754e-01 + 1.042800000000e-09 5.074041226008e-01 + 1.052800000000e-09 3.388664774534e-01 + 1.062800000000e-09 1.535104608579e-01 + 1.072800000000e-09 -2.024845785028e-02 + 1.082800000000e-09 -1.692491421902e-01 + 1.092800000000e-09 -2.967013757932e-01 + 1.102800000000e-09 -4.171073443425e-01 + 1.112800000000e-09 -5.301213512093e-01 + 1.122800000000e-09 -5.826820342472e-01 + 1.132800000000e-09 -5.208927839223e-01 + 1.142800000000e-09 -3.582851623030e-01 + 1.152800000000e-09 -1.726179318326e-01 + 1.162800000000e-09 3.001935102304e-03 + 1.172800000000e-09 1.548738889534e-01 + 1.182800000000e-09 2.838707642593e-01 + 1.192800000000e-09 4.044922095117e-01 + 1.202800000000e-09 5.198180562761e-01 + 1.212800000000e-09 5.821632166084e-01 + 1.222800000000e-09 5.332184734218e-01 + 1.232800000000e-09 3.779624918474e-01 + 1.242800000000e-09 1.922988577092e-01 + 1.252800000000e-09 1.486703325848e-02 + 1.262800000000e-09 -1.399496932386e-01 + 1.272800000000e-09 -2.707197504860e-01 + 1.282800000000e-09 -3.916660474216e-01 + 1.292800000000e-09 -5.087606367752e-01 + 1.302800000000e-09 -5.803016232270e-01 + 1.312800000000e-09 -5.444413186477e-01 + 1.322800000000e-09 -3.977418947932e-01 + 1.332800000000e-09 -2.123689566689e-01 + 1.342800000000e-09 -3.326433605185e-02 + 1.352800000000e-09 1.245198660865e-01 + 1.362800000000e-09 2.572914801001e-01 + 1.372800000000e-09 3.786884397038e-01 + 1.382800000000e-09 4.970287842619e-01 + 1.392800000000e-09 5.770140673465e-01 + 1.402800000000e-09 5.543068732670e-01 + 1.412800000000e-09 4.172944393038e-01 + 1.422800000000e-09 2.326135914048e-01 + 1.432800000000e-09 5.200031629165e-02 + 1.442800000000e-09 -1.087117173734e-01 + 1.452800000000e-09 -2.436934942172e-01 + 1.462800000000e-09 -3.656702152799e-01 + 1.472800000000e-09 -4.848025482630e-01 + 1.482800000000e-09 -5.723385369588e-01 + 1.492800000000e-09 -5.626458033125e-01 + 1.502800000000e-09 -4.362543636943e-01 + 1.512800000000e-09 -2.528118155371e-01 + 1.522800000000e-09 -7.087265053387e-02 + 1.532800000000e-09 9.266186071927e-02 + 1.542800000000e-09 2.300274395412e-01 + 1.552800000000e-09 3.527140919248e-01 + 1.562800000000e-09 4.722911338649e-01 + 1.572800000000e-09 5.664223472519e-01 + 1.582800000000e-09 5.694169369289e-01 + 1.592800000000e-09 4.543351006071e-01 + 1.602800000000e-09 2.728185799251e-01 + 1.612800000000e-09 8.974653097500e-02 + 1.622800000000e-09 -7.645342918533e-02 + 1.632800000000e-09 -2.163412758022e-01 + 1.642800000000e-09 -3.398672125281e-01 + 1.652800000000e-09 -4.596702740436e-01 + 1.662800000000e-09 -5.594547917655e-01 + 1.672800000000e-09 -5.746885318592e-01 + 1.682800000000e-09 -4.713817902736e-01 + 1.692800000000e-09 -2.925998303757e-01 + 1.702800000000e-09 -1.085902848019e-01 + 1.712800000000e-09 6.009271011551e-02 + 1.722800000000e-09 2.026110402562e-01 + 1.732800000000e-09 3.271137583800e-01 + 1.742800000000e-09 4.470366757261e-01 + 1.752800000000e-09 5.516024260258e-01 + 1.762800000000e-09 5.785682691472e-01 + 1.772800000000e-09 4.872997263391e-01 + 1.782800000000e-09 3.121706971956e-01 + 1.792800000000e-09 1.275093354174e-01 + 1.802800000000e-09 -4.339966691138e-02 + 1.812800000000e-09 -1.885914489076e-01 + 1.822800000000e-09 -3.142192224600e-01 + 1.832800000000e-09 -4.343522534326e-01 + 1.842800000000e-09 -5.430041650422e-01 + 1.852800000000e-09 -5.811837349212e-01 + 1.862800000000e-09 -5.023856761573e-01 + 1.872800000000e-09 -3.319418855515e-01 + 1.882800000000e-09 -1.467398868003e-01 + 1.892800000000e-09 2.631801497144e-02 + 1.902800000000e-09 1.743391836774e-01 + 1.912800000000e-09 3.012879943958e-01 + 1.922800000000e-09 4.215592295324e-01 + 1.932800000000e-09 5.336096259357e-01 + 1.942800000000e-09 5.825911854269e-01 + 1.952800000000e-09 5.163685478590e-01 + 1.962800000000e-09 3.514506166310e-01 + 1.972800000000e-09 1.658449567189e-01 + 1.982800000000e-09 -9.123570295392e-03 + 1.992800000000e-09 -1.599641527363e-01 + 2.000000000000e-09 -2.536669268561e-01 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..116f997d --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[0.000, 1.000e-13, 2.000e-13, …]","[6.338e-02, 5.977e-02, 5.737e-02, …]",5.474e+09 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..84d31e27 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [0.000, 1.000e-13, 2.000e-13, …] | [6.338e-02, 5.977e-02, 5.737e-02, …] | 5.474e+09 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/summary.md new file mode 100644 index 00000000..e2473f45 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-27-09/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | any | 5.474 GHz | any | 5.474 GHz | any | 5.474 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..2816ca3f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/frequency.png new file mode 100644 index 00000000..50dc9b77 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..6e9b7331 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..af42fa86 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/debug_0.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..55aad520 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,208 @@ + 0.000000000000e+00 6.337866790587e-02 + 1.000000000000e-13 5.977070129326e-02 + 2.000000000000e-13 5.737010752555e-02 + 4.000000000000e-13 5.321759247257e-02 + 8.000000000000e-13 4.572726454202e-02 + 1.600000000000e-12 3.110636852241e-02 + 3.200000000000e-12 4.261647382150e-03 + 6.400000000000e-12 -4.367747947467e-02 + 1.280000000000e-11 -1.262652366305e-01 + 2.280000000000e-11 -2.340996284945e-01 + 3.280000000000e-11 -3.130989756157e-01 + 4.280000000000e-11 -3.432505429806e-01 + 5.280000000000e-11 -3.012854887225e-01 + 6.280000000000e-11 -1.904316905848e-01 + 7.280000000000e-11 -4.073682199355e-02 + 8.280000000000e-11 1.139505637115e-01 + 9.280000000000e-11 2.545516769294e-01 + 1.028000000000e-10 3.797066846222e-01 + 1.128000000000e-10 4.904124358963e-01 + 1.228000000000e-10 5.415988913067e-01 + 1.328000000000e-10 4.823039600532e-01 + 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-5.811837349212e-01 + 1.862800000000e-09 -5.023856761573e-01 + 1.872800000000e-09 -3.319418855515e-01 + 1.882800000000e-09 -1.467398868003e-01 + 1.892800000000e-09 2.631801497144e-02 + 1.902800000000e-09 1.743391836774e-01 + 1.912800000000e-09 3.012879943958e-01 + 1.922800000000e-09 4.215592295324e-01 + 1.932800000000e-09 5.336096259357e-01 + 1.942800000000e-09 5.825911854269e-01 + 1.952800000000e-09 5.163685478590e-01 + 1.962800000000e-09 3.514506166310e-01 + 1.972800000000e-09 1.658449567189e-01 + 1.982800000000e-09 -9.123570295392e-03 + 1.992800000000e-09 -1.599641527363e-01 + 2.000000000000e-09 -2.536669268561e-01 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..116f997d --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[0.000, 1.000e-13, 2.000e-13, …]","[6.338e-02, 5.977e-02, 5.737e-02, …]",5.474e+09 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..84d31e27 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [0.000, 1.000e-13, 2.000e-13, …] | [6.338e-02, 5.977e-02, 5.737e-02, …] | 5.474e+09 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/summary.md new file mode 100644 index 00000000..a758e068 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-28-35/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.2GHz GHz | 5.474 GHz | 5.4GHz GHz | 5.474 GHz | 7.1GHz GHz | 5.474 GHz | Fail ❌ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..2816ca3f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/frequency.png new file mode 100644 index 00000000..50dc9b77 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..f52afc19 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..7b5840c0 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/debug_0.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..55aad520 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,208 @@ + 0.000000000000e+00 6.337866790587e-02 + 1.000000000000e-13 5.977070129326e-02 + 2.000000000000e-13 5.737010752555e-02 + 4.000000000000e-13 5.321759247257e-02 + 8.000000000000e-13 4.572726454202e-02 + 1.600000000000e-12 3.110636852241e-02 + 3.200000000000e-12 4.261647382150e-03 + 6.400000000000e-12 -4.367747947467e-02 + 1.280000000000e-11 -1.262652366305e-01 + 2.280000000000e-11 -2.340996284945e-01 + 3.280000000000e-11 -3.130989756157e-01 + 4.280000000000e-11 -3.432505429806e-01 + 5.280000000000e-11 -3.012854887225e-01 + 6.280000000000e-11 -1.904316905848e-01 + 7.280000000000e-11 -4.073682199355e-02 + 8.280000000000e-11 1.139505637115e-01 + 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-4.339966691138e-02 + 1.812800000000e-09 -1.885914489076e-01 + 1.822800000000e-09 -3.142192224600e-01 + 1.832800000000e-09 -4.343522534326e-01 + 1.842800000000e-09 -5.430041650422e-01 + 1.852800000000e-09 -5.811837349212e-01 + 1.862800000000e-09 -5.023856761573e-01 + 1.872800000000e-09 -3.319418855515e-01 + 1.882800000000e-09 -1.467398868003e-01 + 1.892800000000e-09 2.631801497144e-02 + 1.902800000000e-09 1.743391836774e-01 + 1.912800000000e-09 3.012879943958e-01 + 1.922800000000e-09 4.215592295324e-01 + 1.932800000000e-09 5.336096259357e-01 + 1.942800000000e-09 5.825911854269e-01 + 1.952800000000e-09 5.163685478590e-01 + 1.962800000000e-09 3.514506166310e-01 + 1.972800000000e-09 1.658449567189e-01 + 1.982800000000e-09 -9.123570295392e-03 + 1.992800000000e-09 -1.599641527363e-01 + 2.000000000000e-09 -2.536669268561e-01 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..116f997d --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[0.000, 1.000e-13, 2.000e-13, …]","[6.338e-02, 5.977e-02, 5.737e-02, …]",5.474e+09 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..84d31e27 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [0.000, 1.000e-13, 2.000e-13, …] | [6.338e-02, 5.977e-02, 5.737e-02, …] | 5.474e+09 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/summary.md new file mode 100644 index 00000000..8f601475 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_15-29-02/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.2 GHz | 5.474 GHz | 5.4 GHz | 5.474 GHz | 7.1 GHz | 5.474 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..2816ca3f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/frequency.png new file mode 100644 index 00000000..50dc9b77 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..9635501f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..406a891f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/debug_0.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..55aad520 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,208 @@ + 0.000000000000e+00 6.337866790587e-02 + 1.000000000000e-13 5.977070129326e-02 + 2.000000000000e-13 5.737010752555e-02 + 4.000000000000e-13 5.321759247257e-02 + 8.000000000000e-13 4.572726454202e-02 + 1.600000000000e-12 3.110636852241e-02 + 3.200000000000e-12 4.261647382150e-03 + 6.400000000000e-12 -4.367747947467e-02 + 1.280000000000e-11 -1.262652366305e-01 + 2.280000000000e-11 -2.340996284945e-01 + 3.280000000000e-11 -3.130989756157e-01 + 4.280000000000e-11 -3.432505429806e-01 + 5.280000000000e-11 -3.012854887225e-01 + 6.280000000000e-11 -1.904316905848e-01 + 7.280000000000e-11 -4.073682199355e-02 + 8.280000000000e-11 1.139505637115e-01 + 9.280000000000e-11 2.545516769294e-01 + 1.028000000000e-10 3.797066846222e-01 + 1.128000000000e-10 4.904124358963e-01 + 1.228000000000e-10 5.415988913067e-01 + 1.328000000000e-10 4.823039600532e-01 + 1.428000000000e-10 3.286487398132e-01 + 1.528000000000e-10 1.494333187522e-01 + 1.628000000000e-10 -2.292252894521e-02 + 1.728000000000e-10 -1.721878995476e-01 + 1.828000000000e-10 -3.003971530482e-01 + 1.928000000000e-10 -4.209827688535e-01 + 2.028000000000e-10 -5.322027853128e-01 + 2.128000000000e-10 -5.791583227387e-01 + 2.228000000000e-10 -5.110033194175e-01 + 2.328000000000e-10 -3.457576287601e-01 + 2.428000000000e-10 -1.607196798900e-01 + 2.528000000000e-10 1.365547887835e-02 + 2.628000000000e-10 1.638016925338e-01 + 2.728000000000e-10 2.919305498126e-01 + 2.828000000000e-10 4.124239288433e-01 + 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-2.536669268561e-01 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..116f997d --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[0.000, 1.000e-13, 2.000e-13, …]","[6.338e-02, 5.977e-02, 5.737e-02, …]",5.474e+09 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..84d31e27 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [0.000, 1.000e-13, 2.000e-13, …] | [6.338e-02, 5.977e-02, 5.737e-02, …] | 5.474e+09 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/summary.md new file mode 100644 index 00000000..8f601475 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-20_17-00-02/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.2 GHz | 5.474 GHz | 5.4 GHz | 5.474 GHz | 7.1 GHz | 5.474 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..8b2e4f89 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n 160p + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/frequency.png new file mode 100644 index 00000000..c624000f Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..04ec32c2 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..8f8f4675 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n 160p + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/debug_0.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..b960892f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,185 @@ + 1.628000000000e-10 -2.292252894521e-02 + 1.728000000000e-10 -1.721878995476e-01 + 1.828000000000e-10 -3.003971530482e-01 + 1.928000000000e-10 -4.209827688535e-01 + 2.028000000000e-10 -5.322027853128e-01 + 2.128000000000e-10 -5.791583227387e-01 + 2.228000000000e-10 -5.110033194175e-01 + 2.328000000000e-10 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1.952800000000e-09 5.163685478590e-01 + 1.962800000000e-09 3.514506166310e-01 + 1.972800000000e-09 1.658449567189e-01 + 1.982800000000e-09 -9.123570295392e-03 + 1.992800000000e-09 -1.599641527363e-01 + 2.000000000000e-09 -2.536669268561e-01 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..8f65c459 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.292e-02, -1.722e-01, -3.004e-01, …]",5.414e+09 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..a45b7af4 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.292e-02, -1.722e-01, -3.004e-01, …] | 5.414e+09 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/summary.md new file mode 100644 index 00000000..a5320ec1 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-03-04/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.2 GHz | 5.414 GHz | 5.4 GHz | 5.414 GHz | 7.1 GHz | 5.414 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..8b2e4f89 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n 160p + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/frequency.png new file mode 100644 index 00000000..c624000f Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..7a0b728f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..e18d29c4 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n 160p + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/debug_0.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..b960892f --- /dev/null +++ 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1.842800000000e-09 -5.430041650422e-01 + 1.852800000000e-09 -5.811837349212e-01 + 1.862800000000e-09 -5.023856761573e-01 + 1.872800000000e-09 -3.319418855515e-01 + 1.882800000000e-09 -1.467398868003e-01 + 1.892800000000e-09 2.631801497144e-02 + 1.902800000000e-09 1.743391836774e-01 + 1.912800000000e-09 3.012879943958e-01 + 1.922800000000e-09 4.215592295324e-01 + 1.932800000000e-09 5.336096259357e-01 + 1.942800000000e-09 5.825911854269e-01 + 1.952800000000e-09 5.163685478590e-01 + 1.962800000000e-09 3.514506166310e-01 + 1.972800000000e-09 1.658449567189e-01 + 1.982800000000e-09 -9.123570295392e-03 + 1.992800000000e-09 -1.599641527363e-01 + 2.000000000000e-09 -2.536669268561e-01 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..8f65c459 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.292e-02, -1.722e-01, -3.004e-01, …]",5.414e+09 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..a45b7af4 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.292e-02, -1.722e-01, -3.004e-01, …] | 5.414e+09 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/summary.md new file mode 100644 index 00000000..a5320ec1 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-08-28_13-08-46/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.2 GHz | 5.414 GHz | 5.4 GHz | 5.414 GHz | 7.1 GHz | 5.414 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..8b2e4f89 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n 160p + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/frequency.png new file mode 100644 index 00000000..d2bd4121 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..c9e97c56 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..e297ca60 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n 160p + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/debug_0.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..b960892f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,185 @@ + 1.628000000000e-10 -2.292252894521e-02 + 1.728000000000e-10 -1.721878995476e-01 + 1.828000000000e-10 -3.003971530482e-01 + 1.928000000000e-10 -4.209827688535e-01 + 2.028000000000e-10 -5.322027853128e-01 + 2.128000000000e-10 -5.791583227387e-01 + 2.228000000000e-10 -5.110033194175e-01 + 2.328000000000e-10 -3.457576287601e-01 + 2.428000000000e-10 -1.607196798900e-01 + 2.528000000000e-10 1.365547887835e-02 + 2.628000000000e-10 1.638016925338e-01 + 2.728000000000e-10 2.919305498126e-01 + 2.828000000000e-10 4.124239288433e-01 + 2.928000000000e-10 5.263166298848e-01 + 3.028000000000e-10 5.824106149717e-01 + 3.128000000000e-10 5.252174273130e-01 + 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a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..8f65c459 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.292e-02, -1.722e-01, -3.004e-01, …]",5.414e+09 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..a45b7af4 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.292e-02, -1.722e-01, -3.004e-01, …] | 5.414e+09 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/summary.md new file mode 100644 index 00000000..a5320ec1 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_14-28-29/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.2 GHz | 5.414 GHz | 5.4 GHz | 5.414 GHz | 7.1 GHz | 5.414 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/diff_oscillator_tb.sch new file mode 100644 index 00000000..8b2e4f89 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n 160p + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata CACE\{simpath\}/debug_CACE\{N\}.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\} + +.include CACE\{DUT_path\} + +.temp CACE\{temperature\} +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/frequency.png b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/frequency.png new file mode 100644 index 00000000..d2bd4121 Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/frequency.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/.spiceinit b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/.spiceinit new file mode 100644 index 00000000..02b902fb --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/.spiceinit @@ -0,0 +1,30 @@ +* a custom spiceinit file for IHP-Open-PDK + +* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc +* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK +* export PDK=ihp-sg13g2 + +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice ) +setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice ) +*echo $sourcepath + +*option tnom=28 +*option list + +* KLU solver still do not work correctly for every simulation +*option klu + +*option node +*option opts +*option warn=1 +*option maxwarns=10 +*option savecurrents + +*set ngbehavior=hsa +*set noinit + +* add OSDI +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi' +osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi' + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/conditions.yaml b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/conditions.yaml new file mode 100644 index 00000000..111ef545 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/conditions.yaml @@ -0,0 +1,8 @@ +DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice +N: 0 +PDK: ihp-sg13g2 +PDK_ROOT: /home/pedersen/IHP-Open-PDK +corner: tt +filename: diff_oscillator_tb +simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0 +temperature: '27' diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/diff_oscillator_tb.sch new file mode 100644 index 00000000..94d8601e --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/diff_oscillator_tb.sch @@ -0,0 +1,65 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 760 -230 760 -210 {lab=vdd} +N 720 -230 720 -210 {lab=gnd} +N 830 -340 850 -340 {lab=Voplus} +N 830 -300 850 -300 {lab=Vominus} +N 390 -280 390 -250 {lab=GND} +N 390 -370 390 -340 {lab=vdd} +C {opin.sym} 850 -340 0 0 {name=p3 lab=Voplus} +C {opin.sym} 850 -300 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1170 0 0 {name=transient_tb only_toplevel=false +value=" +.param temp=27 +* Keep this if your manual run has it — parity matters + +.ic V(Voplus)=1.2 +.control +* Stability & parity options +set noaskquit +set numdgt=12 + +* Save vectors and run +save all +op +write diff_oscillator_tb.raw +set appendwrite +tran 10p 2n 160p + +* Define explicit vectors (avoid V(...) on calculated vectors) +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main file that CACE reads: 2 columns (time, vo_diff) --- +set wr_singlescale +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/diff_oscillator_tb_0.data vo_diff + +* --- Extra debug file (CACE ignores): 4 columns w/ names --- +set wr_vecnames +wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/debug_0.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw +.endc +"} +C {iopin.sym} 760 -210 0 0 {name=p1 lab=vdd} +C {devices/code_shown.sym} 10 -510 0 0 {name=MODEL1 only_toplevel=true +format="tcleval( @value )" +value=" +.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt + +.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/diff_Roscillator/xschem/simulations/schematic/diff_ring_oscillator.spice + +.temp 27 +" +} +C {diff_ring_oscillator.sym} 740 -320 0 0 {name=x1} +C {iopin.sym} 720 -210 2 0 {name=p2 lab=gnd} +C {vsource.sym} 390 -310 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 390 -250 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 390 -370 2 0 {name=p5 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/diff_oscillator_tb_0.data b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/diff_oscillator_tb_0.data new file mode 100644 index 00000000..b960892f --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/diff_oscillator_tb_0.data @@ -0,0 +1,185 @@ + 1.628000000000e-10 -2.292252894521e-02 + 1.728000000000e-10 -1.721878995476e-01 + 1.828000000000e-10 -3.003971530482e-01 + 1.928000000000e-10 -4.209827688535e-01 + 2.028000000000e-10 -5.322027853128e-01 + 2.128000000000e-10 -5.791583227387e-01 + 2.228000000000e-10 -5.110033194175e-01 + 2.328000000000e-10 -3.457576287601e-01 + 2.428000000000e-10 -1.607196798900e-01 + 2.528000000000e-10 1.365547887835e-02 + 2.628000000000e-10 1.638016925338e-01 + 2.728000000000e-10 2.919305498126e-01 + 2.828000000000e-10 4.124239288433e-01 + 2.928000000000e-10 5.263166298848e-01 + 3.028000000000e-10 5.824106149717e-01 + 3.128000000000e-10 5.252174273130e-01 + 3.228000000000e-10 3.651459872532e-01 + 3.328000000000e-10 1.795084214438e-01 + 3.428000000000e-10 3.226267600252e-03 + 3.528000000000e-10 -1.496702035742e-01 + 3.628000000000e-10 -2.792887178681e-01 + 3.728000000000e-10 -4.000019021719e-01 + 3.828000000000e-10 -5.160190704246e-01 + 3.928000000000e-10 -5.816500208715e-01 + 4.028000000000e-10 -5.372846837038e-01 + 4.128000000000e-10 -3.848834507397e-01 + 4.228000000000e-10 -1.993014483184e-01 + 4.328000000000e-10 -2.125168120944e-02 + 4.428000000000e-10 1.345897939599e-01 + 4.528000000000e-10 2.660516467047e-01 + 4.628000000000e-10 3.871267719337e-01 + 4.728000000000e-10 5.047282820024e-01 + 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-1.085902848019e-01 + 1.712800000000e-09 6.009271011551e-02 + 1.722800000000e-09 2.026110402562e-01 + 1.732800000000e-09 3.271137583800e-01 + 1.742800000000e-09 4.470366757261e-01 + 1.752800000000e-09 5.516024260258e-01 + 1.762800000000e-09 5.785682691472e-01 + 1.772800000000e-09 4.872997263391e-01 + 1.782800000000e-09 3.121706971956e-01 + 1.792800000000e-09 1.275093354174e-01 + 1.802800000000e-09 -4.339966691138e-02 + 1.812800000000e-09 -1.885914489076e-01 + 1.822800000000e-09 -3.142192224600e-01 + 1.832800000000e-09 -4.343522534326e-01 + 1.842800000000e-09 -5.430041650422e-01 + 1.852800000000e-09 -5.811837349212e-01 + 1.862800000000e-09 -5.023856761573e-01 + 1.872800000000e-09 -3.319418855515e-01 + 1.882800000000e-09 -1.467398868003e-01 + 1.892800000000e-09 2.631801497144e-02 + 1.902800000000e-09 1.743391836774e-01 + 1.912800000000e-09 3.012879943958e-01 + 1.922800000000e-09 4.215592295324e-01 + 1.932800000000e-09 5.336096259357e-01 + 1.942800000000e-09 5.825911854269e-01 + 1.952800000000e-09 5.163685478590e-01 + 1.962800000000e-09 3.514506166310e-01 + 1.972800000000e-09 1.658449567189e-01 + 1.982800000000e-09 -9.123570295392e-03 + 1.992800000000e-09 -1.599641527363e-01 + 2.000000000000e-09 -2.536669268561e-01 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/diff_ring_oscillator.sym new file mode 100644 index 00000000..e632b156 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/run_0/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/simulation_summary.csv b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/simulation_summary.csv new file mode 100644 index 00000000..8f65c459 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/simulation_summary.csv @@ -0,0 +1,2 @@ +run,time_axis,vo_diff,frequency +run_0,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.292e-02, -1.722e-01, -3.004e-01, …]",5.414e+09 diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/simulation_summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/simulation_summary.md new file mode 100644 index 00000000..a45b7af4 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/parameters/Frequency/simulation_summary.md @@ -0,0 +1,5 @@ +# Simulation Summary for Freq + +| run | time_axis | vo_diff | frequency | +| :-- | --------: | ------: | --------: | +| run_0 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.292e-02, -1.722e-01, -3.004e-01, …] | 5.414e+09 | diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/summary.md b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/summary.md new file mode 100644 index 00000000..a5320ec1 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/runs/RUN_2025-11-11_17-40-06/summary.md @@ -0,0 +1,9 @@ + +# CACE Summary for diff_ring_oscillator + +**netlist source**: schematic + +| Parameter | Tool | Result | Min Limit | Min Value | Typ Target | Typ Value | Max Limit | Max Value | Status | +| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: | +| Freq | ngspice | frequency | 4.2 GHz | 5.414 GHz | 5.4 GHz | 5.414 GHz | 7.1 GHz | 5.414 GHz | Pass ✅ | + diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/testbench/diff_oscillator_tb.sch b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/diff_oscillator_tb.sch index 96a4c078..40030ac1 100644 --- a/modules/module_4_type_2_PLL/diff_Roscillator/testbench/diff_oscillator_tb.sch +++ b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/diff_oscillator_tb.sch @@ -4,16 +4,16 @@ K {} V {} S {} E {} -B 2 1250 -560 2050 -160 {flags=graph -y1=-0.59 -y2=1.3 +B 2 1060 -700 1860 -300 {flags=graph +y1=-0.023 +y2=0.7 ypos1=0 ypos2=2 divy=5 subdivy=1 unity=1 -x1=0 -x2=2e-09 +x1=2.2231151e-07 +x2=2.2291988e-07 divx=5 subdivx=1 xlabmag=1.0 @@ -26,64 +26,54 @@ color="4 7 12" node="voplus vominus vo_diff"} -N 650 -240 700 -240 {lab=#net1} -N 650 -160 700 -160 {lab=#net2} -N 850 -240 900 -240 {lab=#net3} -N 850 -160 900 -160 {lab=#net4} -N 550 -290 550 -270 {lab=vdd} -N 750 -290 950 -290 {lab=vdd} -N 950 -290 950 -270 {lab=vdd} -N 750 -290 750 -270 {lab=vdd} -N 550 -290 750 -290 {lab=vdd} -N 550 -130 550 -110 {lab=GND} -N 550 -110 750 -110 {lab=GND} -N 750 -130 750 -110 {lab=GND} -N 750 -110 950 -110 {lab=GND} -N 950 -130 950 -110 {lab=GND} -N 480 -240 500 -240 {lab=Voplus} -N 480 -330 1070 -330 {lab=Voplus} -N 1050 -240 1070 -240 {lab=Voplus} -N 480 -330 480 -240 {lab=Voplus} -N 1070 -330 1070 -240 {lab=Voplus} -N 1070 -160 1070 -70 {lab=Vominus} -N 1050 -160 1070 -160 {lab=Vominus} -N 480 -160 500 -160 {lab=Vominus} -N 480 -160 480 -70 {lab=Vominus} -N 400 -130 400 -90 {lab=GND} -N 480 -70 1070 -70 {lab=Vominus} -N 400 -230 400 -190 {lab=vdd} -C {differential_core.sym} 650 -200 0 0 {name=x1} -C {differential_core.sym} 850 -200 0 0 {name=x2} -C {differential_core.sym} 1050 -200 0 0 {name=x3} -C {lab_pin.sym} 950 -290 2 0 {name=p1 sig_type=std_logic lab=vdd} -C {vsource.sym} 400 -160 0 0 {name=V1 value=1.2 savecurrent=false} -C {gnd.sym} 950 -110 0 0 {name=l1 lab=GND} -C {gnd.sym} 400 -90 0 0 {name=l2 lab=GND} -C {lab_pin.sym} 400 -230 2 0 {name=p2 sig_type=std_logic lab=vdd} -C {opin.sym} 1070 -330 0 0 {name=p3 lab=Voplus} -C {opin.sym} 1070 -70 2 1 {name=p4 lab=Vominus} -C {code_shown.sym} 0 -450 0 0 {name=transient_tb only_toplevel=false +N 350 -300 350 -270 {lab=vdd} +N 350 -210 350 -180 {lab=GND} +N 600 -290 600 -270 {lab=GND} +N 640 -290 640 -270 {lab=vdd} +N 710 -400 740 -400 {lab=Voplus} +N 710 -360 740 -360 {lab=Vominus} +C {opin.sym} 740 -400 0 0 {name=p3 lab=Voplus} +C {opin.sym} 740 -360 2 1 {name=p4 lab=Vominus} +C {code_shown.sym} 10 -1120 0 0 {name=transient_tb only_toplevel=false value=" .include diff_oscillator_tb.save .param temp=27 .ic V(Voplus)=1.2 .control -save all +set noaskquit +set numdgt=12 + +* Save & simulate +save all op write diff_oscillator_tb.raw set appendwrite -tran 10p 2n +tran 10p 1u 160p save all -let vo_diff = v(Voplus) - v(Vominus) -write diff_oscillator_tb.raw +* Explicit vectors +let vo_p = v(Voplus) +let vo_m = v(Vominus) +let vo_diff = vo_p - vo_m + +* --- Main output (mimic CACE naming, just to compare) --- +set wr_singlescale +wrdata differential_output.txt vo_diff + +* --- Extra debug (like we did for CACE) --- +set wr_vecnames +wrdata manual_debug.dat time vo_p vo_m vo_diff +unset wr_vecnames + +write diff_oscillator_tb.raw .endc "} -C {devices/code_shown.sym} 0 -110 0 0 {name=MODEL only_toplevel=true +C {devices/code_shown.sym} 10 -460 0 0 {name=MODEL only_toplevel=true format="tcleval( @value )" value=".lib cornerMOSlv.lib mos_tt -"} -C {launcher.sym} 1310 -70 0 0 {name=h3 +" +} +C {launcher.sym} 1120 -240 0 0 {name=h3 descr=SimulateNGSPICE tclcommand=" # Setup the default simulation commands if not already set up @@ -107,11 +97,17 @@ write_data [save_params] $netlist_dir/[file rootname [file tail [xschem get curr xschem netlist simulate "} -C {devices/launcher.sym} 1310 -110 0 0 {name=h1 +C {devices/launcher.sym} 1120 -280 0 0 {name=h1 descr="OP annotate" tclcommand="xschem annotate_op" } -C {launcher.sym} 1310 -30 0 0 {name=h5 +C {launcher.sym} 1120 -190 0 0 {name=h5 descr="load waves" tclcommand="xschem raw_read $netlist_dir/diff_oscillator_tb.raw tran" } +C {vsource.sym} 350 -240 0 0 {name=V1 value=1.2 savecurrent=false} +C {gnd.sym} 350 -180 0 0 {name=l2 lab=GND} +C {lab_pin.sym} 350 -300 0 0 {name=p2 sig_type=std_logic lab=vdd} +C {diff_ring_oscillator.sym} 620 -380 0 0 {name=x1} +C {gnd.sym} 600 -270 0 0 {name=l1 lab=GND} +C {lab_pin.sym} 640 -270 0 1 {name=p1 sig_type=std_logic lab=vdd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/testbench/diff_oscillator_tb.sym b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/diff_oscillator_tb.sym new file mode 100644 index 00000000..35d2073e --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/diff_oscillator_tb.sym @@ -0,0 +1,14 @@ +v {xschem version=3.4.6 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +T {@symname} -99 -6 0 0 0.3 0.3 {} +T {@name} 135 -32 0 0 0.2 0.2 {} +P 4 5 130 -20 -130 -20 -130 20 130 20 130 -20 {} +B 5 147.5 -12.5 152.5 -7.5 {name=Voplus dir=out} +L 4 130 -10 150 -10 {} +T {Voplus} 125 -14 0 1 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=Vominus dir=out} +L 4 130 10 150 10 {} +T {Vominus} 125 6 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/testbench/python/freq.py b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/python/freq.py new file mode 100644 index 00000000..5fe904f3 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/python/freq.py @@ -0,0 +1,54 @@ +#!/usr/bin/env python3 +import sys +import numpy as np +import matplotlib +matplotlib.use("Agg") # Use non-GUI backend for batch plotting +import matplotlib.pyplot as plt + +def main(): + if len(sys.argv) < 2: + print("Usage: python plot_diffout.py data.txt") + sys.exit(1) + + filename = sys.argv[1] + + # Load data (two columns: time, differential output) + data = np.loadtxt(filename) + t = data[:, 0] + y = data[:, 1] + + # Plot + plt.figure(figsize=(8,5)) + plt.plot(t, y, label="Differential Output") + plt.xlabel("Time (s)") + plt.ylabel("Differential Output (V)") + plt.title("Differential Output vs Time") + plt.legend() + plt.grid(True) + + # Save plot as PNG + outname = filename.replace(".txt", ".png") + plt.savefig(outname, dpi=300) + plt.close() + print(f"Saved plot as {outname}") + + # Estimate frequency using FFT + # Compute sampling interval + dt = np.mean(np.diff(t)) + fs = 1/dt # sampling frequency + + # FFT + Y = np.fft.fft(y - np.mean(y)) # remove DC component + freqs = np.fft.fftfreq(len(Y), d=dt) + + # Only positive frequencies + mask = freqs > 0 + freqs = freqs[mask] + Y = np.abs(Y[mask]) + + # Find frequency with maximum magnitude + freq_peak = freqs[np.argmax(Y)] + print(f"Estimated frequency: {freq_peak:.3e} Hz") + +if __name__ == "__main__": + main() diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/testbench/python/pn_spectrum.py b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/python/pn_spectrum.py new file mode 100644 index 00000000..203f4622 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/python/pn_spectrum.py @@ -0,0 +1,186 @@ +#!/usr/bin/env python3 +""" +pn_batch.py + +Usage: + python pn_batch.py data1.txt data2.txt ... + +Input format: + - Two columns: time[s] v[t] + - Three columns: time[s] vp[t] vn[t] (script will use vp - vn) + +Outputs: + - ./spectrum/_phase_noise.png + - printed summary: carrier freq estimate, fs (after resample), record length, samples +""" + +import sys +from pathlib import Path +import numpy as np +import matplotlib.pyplot as plt +from scipy.signal import welch, butter, filtfilt +from scipy.interpolate import interp1d + +# --------- Parameters you can tweak ---------- +RESAMPLE = True # resample to uniform grid if input isn't uniform +TARGET_SAMPLES = 200000 # target samples when resampling (tradeoff mem / res) +LPF_BW = None # if None, autopick based on carrier (see code). Bandwidth for baseband LPF (Hz) +NPERSEG = None # if None, will choose based on record length (see code) +OVERLAP = 0.5 # fraction for Welch overlap +# ------------------------------------------------ + +def load_data(fname): + data = np.loadtxt(fname) + if data.ndim == 1 or data.shape[1] == 1: + raise ValueError("File must have 2 or 3 columns (time, v) or (time, vp, vn)") + t = data[:,0] + if data.shape[1] == 2: + v = data[:,1] + else: + v = data[:,1] - data[:,2] + return t, v + +def uniform_resample(t, v, target_samples=200000): + # build uniform grid from min->max with target_samples (bounded) + t0, t1 = float(t[0]), float(t[-1]) + dt_median = np.median(np.diff(t)) + if dt_median == 0: + raise ValueError("Median dt is zero: check the input file for repeated timestamps.") + N = min(target_samples, max(1024, int((t1 - t0) / dt_median))) + tu = np.linspace(t0, t1, N) + interp = interp1d(t, v, kind='cubic', bounds_error=False, fill_value="extrapolate") + vu = interp(tu) + return tu, vu + +def estimate_carrier_freq(t, v, fs_est=None): + # Quick FFT-based estimate (uses zero-padding for better resolution) + N = len(t) + i0, i1 = N//4, 3*N//4 + x = v[i0:i1] * np.hanning(i1-i0) + nfft = 1 << (int(np.ceil(np.log2(len(x)))) + 3) + X = np.fft.rfft(x, n=nfft) + freqs = np.fft.rfftfreq(nfft, d=(t[1]-t[0])) + mag = np.abs(X) + idx = np.argmax(mag) + # parabolic refine around peak + if 1 <= idx < len(mag)-1: + alpha = mag[idx-1] + beta = mag[idx] + gamma = mag[idx+1] + p = 0.5*(alpha - gamma)/(alpha - 2*beta + gamma) + peak_freq = (freqs[idx] + p*(freqs[1]-freqs[0])) + else: + peak_freq = freqs[idx] + return peak_freq + +def lowpass_iq(t, v, fc, fs_bb): + # Mix down to baseband using the estimated fc, then lowpass to fs_bb/2 + t = np.asarray(t) + carrier = 2*np.pi*fc*t + I = v * np.cos(carrier) + Q = -v * np.sin(carrier) + + nyq = 0.5 * (1.0/(t[1]-t[0])) + cutoff = min(0.5*fs_bb, nyq*0.9) + b, a = butter(4, cutoff/nyq) + I_f = filtfilt(b, a, I) + Q_f = filtfilt(b, a, Q) + + t_start, t_end = t[0], t[-1] + num = int(np.floor((t_end - t_start) * fs_bb)) + if num < 16: + raise ValueError("fs_bb too high or record too short for downsampling. Decrease fs_bb.") + tb = np.linspace(t_start, t_end, num) + I_interp = interp1d(t, I_f, kind='cubic')(tb) + Q_interp = interp1d(t, Q_f, kind='cubic')(tb) + return tb, I_interp, Q_interp + +def compute_phase_from_iq(I, Q): + phase = np.unwrap(np.arctan2(Q, I)) + return phase + +def phase_to_LdBcHz(phase, fs_bb, nperseg=None, overlap=0.5): + if nperseg is None: + nperseg = min(len(phase), 2**14) + noverlap = int(nperseg * overlap) + f, Pphi = welch(phase, fs=fs_bb, nperseg=nperseg, noverlap=noverlap, scaling='density', window='hann') + L = 10*np.log10(0.5 * Pphi) + return f, L + +def process_file(fname): + fname = Path(fname) + t, v = load_data(fname) + sort_idx = np.argsort(t) + t = t[sort_idx] + v = v[sort_idx] + + if RESAMPLE: + t_u, v_u = uniform_resample(t, v, target_samples=TARGET_SAMPLES) + else: + dt = np.diff(t) + if np.max(dt) - np.min(dt) > 1e-12: + t_u, v_u = uniform_resample(t, v, target_samples=TARGET_SAMPLES) + else: + t_u, v_u = t, v + + dt = t_u[1] - t_u[0] + fs = 1.0 / dt + T = t_u[-1] - t_u[0] + + fc = estimate_carrier_freq(t_u, v_u, fs_est=fs) + + if LPF_BW is None: + fs_bb = min(1e6, max(200000.0, fs/20)) + else: + fs_bb = max(1000.0, LPF_BW*4) + + nyq_orig = 0.5*fs + if fs_bb > nyq_orig*0.9: + fs_bb = nyq_orig*0.9 + + try: + tb, Ibb, Qbb = lowpass_iq(t_u, v_u, fc, fs_bb) + except Exception as e: + raise RuntimeError("IQ demod failed: " + str(e)) + + phase = compute_phase_from_iq(Ibb, Qbb) + p = np.polyfit(tb, phase, 1) + phase_dev = phase - np.polyval(p, tb) + + if NPERSEG is None: + nperseg = int(max(256, min(len(phase_dev), int(fs_bb * (T/8.0))))) + nperseg = 1 << int(np.floor(np.log2(nperseg))) + else: + nperseg = NPERSEG + + f, L = phase_to_LdBcHz(phase_dev, fs_bb, nperseg=nperseg, overlap=OVERLAP) + + outdir = Path("spectrum") + outdir.mkdir(parents=True, exist_ok=True) + out_png = outdir / (fname.stem + "_phase_noise.png") + + plt.figure(figsize=(6.5,4)) + plt.semilogx(f, L) + plt.xlim(max(1.0, f[1]), f[-1]) + plt.xlabel("Offset frequency [Hz]") + plt.ylabel("Phase noise [dBc/Hz]") + plt.title(f"{fname.name} fc~{fc/1e6:.6f} MHz fs_bb={fs_bb/1e3:.1f} kHz T={T*1e6:.3f} µs") + plt.grid(True, which='both', ls=':', alpha=0.6) + plt.tight_layout() + plt.savefig(out_png, dpi=150) + plt.close() + + print(f"{fname.name}: fc={fc:.3f} Hz, fs={fs:.1f} Hz, T={T:.6f} s, samples={len(t_u)}") + +def main(): + if len(sys.argv) < 2: + print("Usage: python pn_batch.py data1.txt data2.txt ...") + sys.exit(1) + for f in sys.argv[1:]: + try: + process_file(f) + except Exception as e: + print(f"Error processing {f}: {e}") + +if __name__ == "__main__": + main() diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/testbench/simulations/diff_oscillator_tb.save b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/simulations/diff_oscillator_tb.save index 50debb58..235abce2 100644 --- a/modules/module_4_type_2_PLL/diff_Roscillator/testbench/simulations/diff_oscillator_tb.save +++ b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/simulations/diff_oscillator_tb.save @@ -1,62 +1,62 @@ * Place this .save file with a .include line in your testbench -.save @n.x1.xm1.nsg13_lv_nmos[ids] -.save @n.x1.xm1.nsg13_lv_nmos[gm] -.save @n.x1.xm1.nsg13_lv_nmos[gds] -.save @n.x1.xm1.nsg13_lv_nmos[vth] -.save @n.x1.xm1.nsg13_lv_nmos[vgs] -.save @n.x1.xm1.nsg13_lv_nmos[vdss] -.save @n.x1.xm1.nsg13_lv_nmos[vds] -.save @n.x1.xm1.nsg13_lv_nmos[cgg] -.save @n.x1.xm1.nsg13_lv_nmos[cgsol] -.save @n.x1.xm1.nsg13_lv_nmos[cgdol] -.save @n.x1.xm2.nsg13_lv_nmos[ids] -.save @n.x1.xm2.nsg13_lv_nmos[gm] -.save @n.x1.xm2.nsg13_lv_nmos[gds] -.save @n.x1.xm2.nsg13_lv_nmos[vth] -.save @n.x1.xm2.nsg13_lv_nmos[vgs] -.save @n.x1.xm2.nsg13_lv_nmos[vdss] -.save @n.x1.xm2.nsg13_lv_nmos[vds] -.save @n.x1.xm2.nsg13_lv_nmos[cgg] -.save @n.x1.xm2.nsg13_lv_nmos[cgsol] -.save @n.x1.xm2.nsg13_lv_nmos[cgdol] -.save @n.x2.xm1.nsg13_lv_nmos[ids] -.save @n.x2.xm1.nsg13_lv_nmos[gm] -.save @n.x2.xm1.nsg13_lv_nmos[gds] -.save @n.x2.xm1.nsg13_lv_nmos[vth] -.save @n.x2.xm1.nsg13_lv_nmos[vgs] -.save @n.x2.xm1.nsg13_lv_nmos[vdss] -.save @n.x2.xm1.nsg13_lv_nmos[vds] -.save @n.x2.xm1.nsg13_lv_nmos[cgg] -.save @n.x2.xm1.nsg13_lv_nmos[cgsol] -.save @n.x2.xm1.nsg13_lv_nmos[cgdol] -.save @n.x2.xm2.nsg13_lv_nmos[ids] -.save @n.x2.xm2.nsg13_lv_nmos[gm] -.save @n.x2.xm2.nsg13_lv_nmos[gds] -.save @n.x2.xm2.nsg13_lv_nmos[vth] -.save @n.x2.xm2.nsg13_lv_nmos[vgs] -.save @n.x2.xm2.nsg13_lv_nmos[vdss] -.save @n.x2.xm2.nsg13_lv_nmos[vds] -.save @n.x2.xm2.nsg13_lv_nmos[cgg] -.save @n.x2.xm2.nsg13_lv_nmos[cgsol] -.save @n.x2.xm2.nsg13_lv_nmos[cgdol] -.save @n.x3.xm1.nsg13_lv_nmos[ids] -.save @n.x3.xm1.nsg13_lv_nmos[gm] -.save @n.x3.xm1.nsg13_lv_nmos[gds] -.save @n.x3.xm1.nsg13_lv_nmos[vth] -.save @n.x3.xm1.nsg13_lv_nmos[vgs] -.save @n.x3.xm1.nsg13_lv_nmos[vdss] -.save @n.x3.xm1.nsg13_lv_nmos[vds] -.save @n.x3.xm1.nsg13_lv_nmos[cgg] -.save @n.x3.xm1.nsg13_lv_nmos[cgsol] -.save @n.x3.xm1.nsg13_lv_nmos[cgdol] -.save @n.x3.xm2.nsg13_lv_nmos[ids] -.save @n.x3.xm2.nsg13_lv_nmos[gm] -.save @n.x3.xm2.nsg13_lv_nmos[gds] -.save @n.x3.xm2.nsg13_lv_nmos[vth] -.save @n.x3.xm2.nsg13_lv_nmos[vgs] -.save @n.x3.xm2.nsg13_lv_nmos[vdss] -.save @n.x3.xm2.nsg13_lv_nmos[vds] -.save @n.x3.xm2.nsg13_lv_nmos[cgg] -.save @n.x3.xm2.nsg13_lv_nmos[cgsol] -.save @n.x3.xm2.nsg13_lv_nmos[cgdol] +.save @n.x1.x1.xm1.nsg13_lv_nmos[ids] +.save @n.x1.x1.xm1.nsg13_lv_nmos[gm] +.save @n.x1.x1.xm1.nsg13_lv_nmos[gds] +.save @n.x1.x1.xm1.nsg13_lv_nmos[vth] +.save @n.x1.x1.xm1.nsg13_lv_nmos[vgs] +.save @n.x1.x1.xm1.nsg13_lv_nmos[vdss] +.save @n.x1.x1.xm1.nsg13_lv_nmos[vds] +.save @n.x1.x1.xm1.nsg13_lv_nmos[cgg] +.save @n.x1.x1.xm1.nsg13_lv_nmos[cgsol] +.save @n.x1.x1.xm1.nsg13_lv_nmos[cgdol] +.save @n.x1.x1.xm2.nsg13_lv_nmos[ids] +.save @n.x1.x1.xm2.nsg13_lv_nmos[gm] +.save @n.x1.x1.xm2.nsg13_lv_nmos[gds] +.save @n.x1.x1.xm2.nsg13_lv_nmos[vth] +.save @n.x1.x1.xm2.nsg13_lv_nmos[vgs] +.save @n.x1.x1.xm2.nsg13_lv_nmos[vdss] +.save @n.x1.x1.xm2.nsg13_lv_nmos[vds] +.save @n.x1.x1.xm2.nsg13_lv_nmos[cgg] +.save @n.x1.x1.xm2.nsg13_lv_nmos[cgsol] +.save @n.x1.x1.xm2.nsg13_lv_nmos[cgdol] +.save @n.x1.x2.xm1.nsg13_lv_nmos[ids] +.save @n.x1.x2.xm1.nsg13_lv_nmos[gm] +.save @n.x1.x2.xm1.nsg13_lv_nmos[gds] +.save @n.x1.x2.xm1.nsg13_lv_nmos[vth] +.save @n.x1.x2.xm1.nsg13_lv_nmos[vgs] +.save @n.x1.x2.xm1.nsg13_lv_nmos[vdss] +.save @n.x1.x2.xm1.nsg13_lv_nmos[vds] +.save @n.x1.x2.xm1.nsg13_lv_nmos[cgg] +.save @n.x1.x2.xm1.nsg13_lv_nmos[cgsol] +.save @n.x1.x2.xm1.nsg13_lv_nmos[cgdol] +.save @n.x1.x2.xm2.nsg13_lv_nmos[ids] +.save @n.x1.x2.xm2.nsg13_lv_nmos[gm] +.save @n.x1.x2.xm2.nsg13_lv_nmos[gds] +.save @n.x1.x2.xm2.nsg13_lv_nmos[vth] +.save @n.x1.x2.xm2.nsg13_lv_nmos[vgs] +.save @n.x1.x2.xm2.nsg13_lv_nmos[vdss] +.save @n.x1.x2.xm2.nsg13_lv_nmos[vds] +.save @n.x1.x2.xm2.nsg13_lv_nmos[cgg] +.save @n.x1.x2.xm2.nsg13_lv_nmos[cgsol] +.save @n.x1.x2.xm2.nsg13_lv_nmos[cgdol] +.save @n.x1.x3.xm1.nsg13_lv_nmos[ids] +.save @n.x1.x3.xm1.nsg13_lv_nmos[gm] +.save @n.x1.x3.xm1.nsg13_lv_nmos[gds] +.save @n.x1.x3.xm1.nsg13_lv_nmos[vth] +.save @n.x1.x3.xm1.nsg13_lv_nmos[vgs] +.save @n.x1.x3.xm1.nsg13_lv_nmos[vdss] +.save @n.x1.x3.xm1.nsg13_lv_nmos[vds] +.save @n.x1.x3.xm1.nsg13_lv_nmos[cgg] +.save @n.x1.x3.xm1.nsg13_lv_nmos[cgsol] +.save @n.x1.x3.xm1.nsg13_lv_nmos[cgdol] +.save @n.x1.x3.xm2.nsg13_lv_nmos[ids] +.save @n.x1.x3.xm2.nsg13_lv_nmos[gm] +.save @n.x1.x3.xm2.nsg13_lv_nmos[gds] +.save @n.x1.x3.xm2.nsg13_lv_nmos[vth] +.save @n.x1.x3.xm2.nsg13_lv_nmos[vgs] +.save @n.x1.x3.xm2.nsg13_lv_nmos[vdss] +.save @n.x1.x3.xm2.nsg13_lv_nmos[vds] +.save @n.x1.x3.xm2.nsg13_lv_nmos[cgg] +.save @n.x1.x3.xm2.nsg13_lv_nmos[cgsol] +.save @n.x1.x3.xm2.nsg13_lv_nmos[cgdol] diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/testbench/spectrum/differential_output_phase_noise.png b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/spectrum/differential_output_phase_noise.png new file mode 100644 index 00000000..e6a42d1b Binary files /dev/null and b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/spectrum/differential_output_phase_noise.png differ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/testbench/xschemrc b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/xschemrc index 795ca780..34b6db6d 100644 --- a/modules/module_4_type_2_PLL/diff_Roscillator/testbench/xschemrc +++ b/modules/module_4_type_2_PLL/diff_Roscillator/testbench/xschemrc @@ -14,5 +14,5 @@ source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc #### Add custom libraries (directories with .lib files) -append XSCHEM_LIBRARY_PATH :../schematic/ +append XSCHEM_LIBRARY_PATH :../xschem/ diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/xschem/diff_ring_oscillator.sch b/modules/module_4_type_2_PLL/diff_Roscillator/xschem/diff_ring_oscillator.sch new file mode 100644 index 00000000..f52c0e30 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/xschem/diff_ring_oscillator.sch @@ -0,0 +1,37 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {} +V {} +S {} +E {} +N 560 -430 610 -430 {lab=#net1} +N 560 -350 610 -350 {lab=#net2} +N 760 -430 810 -430 {lab=#net3} +N 760 -350 810 -350 {lab=#net4} +N 460 -480 460 -460 {lab=vdd} +N 660 -480 860 -480 {lab=vdd} +N 860 -480 860 -460 {lab=vdd} +N 660 -480 660 -460 {lab=vdd} +N 460 -480 660 -480 {lab=vdd} +N 460 -320 460 -300 {lab=gnd} +N 460 -300 660 -300 {lab=gnd} +N 660 -320 660 -300 {lab=gnd} +N 660 -300 860 -300 {lab=gnd} +N 860 -320 860 -300 {lab=gnd} +N 390 -430 410 -430 {lab=#net5} +N 390 -520 980 -520 {lab=#net5} +N 960 -430 980 -430 {lab=#net5} +N 390 -520 390 -430 {lab=#net5} +N 980 -520 980 -430 {lab=#net5} +N 980 -350 980 -260 {lab=Voplus} +N 960 -350 980 -350 {lab=Voplus} +N 390 -350 410 -350 {lab=Voplus} +N 390 -350 390 -260 {lab=Voplus} +N 390 -260 980 -260 {lab=Voplus} +C {differential_core.sym} 560 -390 0 0 {name=x1} +C {differential_core.sym} 760 -390 0 0 {name=x2} +C {differential_core.sym} 960 -390 0 0 {name=x3} +C {opin.sym} 980 -260 0 0 {name=p3 lab=Voplus} +C {opin.sym} 980 -510 2 1 {name=p4 lab=Vominus} +C {iopin.sym} 860 -480 0 0 {name=p1 lab=vdd} +C {iopin.sym} 860 -300 0 0 {name=p2 lab=gnd} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/xschem/diff_ring_oscillator.sym b/modules/module_4_type_2_PLL/diff_Roscillator/xschem/diff_ring_oscillator.sym new file mode 100644 index 00000000..b9399769 --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/xschem/diff_ring_oscillator.sym @@ -0,0 +1,27 @@ +v {xschem version=3.4.6 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 70 -20 90 -20 {} +L 4 70 20 90 20 {} +L 7 20 70 20 90 {} +L 7 -20 70 -20 90 {} +B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out} +B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout} +B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout} +B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out} +A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {} +A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {} +A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {} +T {@symname} -40.5 -56 0 0 0.1 0.1 {} +T {@name} -40 -47 0 0 0.1 0.1 { +} +T {Voplus} 65 -24 0 1 0.2 0.2 {} +T {vdd} 5 64 2 1 0.2 0.2 {} +T {gnd} -35 64 2 1 0.2 0.2 {} +T {Vominus} 65 16 0 1 0.2 0.2 {} diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/schematic/differential_core.sch b/modules/module_4_type_2_PLL/diff_Roscillator/xschem/differential_core.sch similarity index 100% rename from modules/module_4_type_2_PLL/diff_Roscillator/schematic/differential_core.sch rename to modules/module_4_type_2_PLL/diff_Roscillator/xschem/differential_core.sch diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/schematic/differential_core.sym b/modules/module_4_type_2_PLL/diff_Roscillator/xschem/differential_core.sym similarity index 100% rename from modules/module_4_type_2_PLL/diff_Roscillator/schematic/differential_core.sym rename to modules/module_4_type_2_PLL/diff_Roscillator/xschem/differential_core.sym diff --git a/modules/module_4_type_2_PLL/diff_Roscillator/xschem/xschemrc b/modules/module_4_type_2_PLL/diff_Roscillator/xschem/xschemrc new file mode 100644 index 00000000..34b6db6d --- /dev/null +++ b/modules/module_4_type_2_PLL/diff_Roscillator/xschem/xschemrc @@ -0,0 +1,18 @@ +# xschemrc - Custom configuration file for xschem +# This file sources another xschemrc file from a known location + +# Source the base configuration from a known location +source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc + +# (Optional) Add any custom overrides or extensions below +# set xschem_library_path /home/user/my_libs +# set xschem_gui_font "Monospace 10" + +#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here. +###only if you dont have this setup already ### +###append XSCHEM_LIBRARY_PATH :[file dirname [info script]] + + +#### Add custom libraries (directories with .lib files) +append XSCHEM_LIBRARY_PATH :../xschem/ +